CFET Power Delivery Network for Buried Power Rails

Abstract

A semiconductor device includes a first power rail, a first power input structure, a circuit, and a first mid-section rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to be connected to a first terminal of a power source external to the semiconductor device to receive power from the power source. The circuit is formed on the substrate by layers between the first power rail and the first power input structure. The first mid-section rail is formed by one or more of the layers forming the circuit. The first mid-section rail is configured to deliver power from the first power input structure to the first power rail, and the first power rail provides power to the circuit for operation.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Non-Provisional Application No. 16 / 659,251, filed on October 21, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments described in this disclosure relate generally to semiconductor devices and fabrication processes. Background Art

[0004] Historically, in the semiconductor industry, transistors have been created on one plane, with wiring / metallization formed above, and thus, this has been characterized as two-dimensional (2D) circuits or 2D manufacturing. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits. As traditional 2D scaling shows a rapidly decreasing return on investment, the semiconductor industry is looking for a 3rd dimension to maintain improvements in power-performance-area-cost (PPAC) from node to node. A very promising approach to increase transistor density using the vertical axis is a new device architecture known as complementary FET (CFET). In the CFET approach, a logic cell with an N-type device and a P-type device is essentially folded so that one of the two devices (such as the P-type device) is placed above the other of the two devices (such as the N-type device), while the two devices share a common gate. Summary of the invention

[0005] Placing two complementary devices on top of each other and eliminating the large amount of lateral space required between N-type and P-type devices puts standard cell logic design into a domain where the cell height is limited by the cumulative width of the required routing tracks rather than the device width. Under scaling constraints, the cell height must accommodate 4 routing tracks and a robust power rail. This results in a minimum cell height of 6 routing tracks (6T) when assuming that the width of the twice-wide power rail is sufficient to prevent voltage drops or electromagnetic coupling issues on power delivery.

[0006] To further shrink cell height while maintaining robust power delivery, the semiconductor industry is looking to buried power rails (BPRs). Moving the power rails below the device plane allows the cell height to be reduced to 5T (i.e., 4 routing tracks for signal transmission plus one routing track for absorbing line end extensions and end-to-end spacing in compact packaging cells).

[0007] While buried power rails (BPRs) play a critical role in leveraging 3D’s transistor-on-transistor stacking to open a new path forward at the end of 2D scaling, they also present a new challenge: how to get power into the BPRs. Connecting the power rails, now located below the device plane, to the power delivery network (PDN) located above the device plane requires a high-power connection. This power connection cannot be too small at the risk of creating a current pinch, nor too large at the risk of interfering with dense cell placement.

[0008] Recognizing the advantages of CFETs and BPRs as described above, and further recognizing the need for a robust, low resistance device to deliver power into a BPR, the present disclosure provides a unique mid-stage power delivery network approach.

[0009] Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes a first power rail, a first power input structure, a circuit, and a first mid-section rail. The first power rail is formed in a first rail opening within a first isolation trench on a substrate. The first power input structure is configured to be connected to a first terminal of a power source external to the semiconductor device to receive power from the power source. The circuit is formed on the substrate by layers between the first power rail and the first power input structure. The first mid-section rail is formed by one or more of the layers forming the circuit. The first mid-section rail is configured to deliver power from the first power input structure to the first power rail, and the first power rail provides power to the circuit for operation.

[0010] Further, in some embodiments, the semiconductor device includes a second power rail, a second power input structure, and a second mid-section rail. The second power rail is formed in a second rail opening within a second isolation trench on the substrate. The second power rail is parallel to the first power rail. The second power input structure is configured to be connected to a second terminal of a power source and receive power from the power source using the first power input structure. The second mid-section rail is formed by one or more of the layers forming the circuit. The second mid-section rail is parallel to the first mid-section rail, and the first mid-section rail and the second mid-section rail are configured to deliver power from the first input structure and the second input structure to the first power rail and the second power rail. The first power rail and the second power rail provide power to the circuit for operation.

[0011] In some embodiments, the circuit includes a cell row of cell circuits having the same cell height. The first mid-rail includes a portion of power tap cells disposed in the cell row, the power tap cells having the same cell height as the cell circuits.

[0012] In some examples, the first mid-section rail is formed from at least one layer used to form a connection within the unit circuit.

[0013] In an embodiment, the circuit comprises a plurality of cell rows of the cell circuit, and the first mid-section rail is formed by portions of power tap cells respectively arranged in the plurality of cell rows.

[0014] In some examples, the power tap units are arranged in a column, and the portions in the respective power tap units are conductively connected to form a first mid-rail.

[0015] In an example, each of these parts in a respective power tap unit is connected to the first power rail by at least one power via and to the metal rail by at least one contact.

[0016] In some embodiments, the first mid-rail and the second mid-rail are perpendicular to the first power rail and the second power rail.

[0017] In some examples, the circuit includes a first transistor disposed above a second transistor in a vertical direction perpendicular to a surface of the substrate. Then, in an example, the first mid-section rail includes a first layer for forming a local interconnect in the first transistor, a second layer for forming a local interconnect in the second transistor, and a strap layer for merging the first layer and the second layer.

[0018] Aspects of the present disclosure also provide a method for manufacturing a semiconductor device. For example, a buried power rail is formed in a rail opening within an isolation trench on a substrate. In an example, the buried power rail forms a BPR power delivery network. Then, an active device and a MOL power delivery network are formed. In some examples, the MOL power delivery network includes a MIL rail and an M0 rail. In an example, the MIL rail includes a top LI structure, a bottom LI structure, and a band structure merging the top LI structure and the bottom LI structure. The MIL rail is connected to the BPR through a short power via, and the MIL rail and the M0 rail are connected through a top CD structure. Further, an upper metal layer is formed, and a via structure connecting wires in different metal layers is also formed. The UML power delivery network is formed in the upper metal layer. In an example, a power input pad is formed in the top metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] When with Figure 1 The aspects of the present disclosure are best understood from the following detailed description when read together. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0020] Figure 1 A simplified diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0021] Figure 2A top view of a semiconductor device according to some embodiments of the present disclosure is shown.

[0022] Figure 3 A top view and a cross-sectional view of a power tap unit according to some embodiments of the present disclosure are shown.

[0023] Figure 4 A top view and a cross-sectional view of a power tap unit according to some embodiments of the present disclosure are shown.

[0024] Figure 5 A top view and a cross-sectional view of a logic cell according to some embodiments of the present disclosure are shown.

[0025] Figure 6 A flow chart outlining an example of a process according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0026] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0027] Further, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to one or more other elements or features as illustrated in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the accompanying drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted in a similar manner accordingly.

[0028] Various aspects of the present disclosure provide a semiconductor device that uses a buried power rail (BPR) to reduce the height of a standard cell of a circuit, thereby reducing the area occupied by the standard cell and the circuit. These BPRs form a BPR power delivery network to provide power to circuits in the semiconductor device, such as logic circuits, analog circuits, memory circuits, etc. The semiconductor device further includes a plurality of power tap cells that are arranged in a plane for active devices together with the standard cells. The power tap cells form a mid-stage (MOL) power delivery network (PDN) in the semiconductor device. The MOL power delivery network is arranged between the BPR power delivery network and the upper metal layer (UML) power delivery network.

[0029] Typically, a semiconductor device includes multiple metal layers, such as eight metal layers referred to as M0 to M7. In some examples, metal layer M0 is typically used for connections within a standard cell, and metal layers M1 to M7 are located above metal layer M0 and can be used for connections between different cells. In some embodiments, the MOL power delivery network is implemented using one or more layers of standard cells (such as local interconnects, M0, etc.) used to form the MOL power delivery network. The UML power delivery network is formed by the upper metal layers (such as metal layers M1 to M7). The MOL power delivery network interconnects the BPR power delivery network and the UML power delivery network.

[0030] The MOL power delivery network helps inject power from the UML power delivery network into the BPR power delivery network. For example, power is distributed from the UML power delivery network to the MOL power delivery network, and from the MOL power delivery network to the BPR power delivery network. According to some aspects of the present disclosure, the MOL power delivery network is configured to minimize current crowding and voltage drops due to excessive resistance during power delivery. In one aspect of the present disclosure, the MOL power delivery network is configured to maximize the number of redundant connections between the UML power delivery network and the BPR power delivery network. In another aspect of the present disclosure, the MOL power delivery network forms an intermediate power delivery rail arranged perpendicular to the BPR.

[0031] Figure 1A simplified diagram showing a semiconductor device 100 according to some embodiments of the present disclosure is shown. The semiconductor device 100 includes power input structures 101 and 102, a UML power delivery network 110, a MOL power delivery network 120, and a BPR power delivery network 190 coupled together. The MOL power delivery network 120 is formed in a layer where active devices (such as logic circuits, memory cells, etc.) are formed, and is configured to help inject power from the UML power delivery network 110 to the BPR power delivery network 190. The BPR power delivery network 190 is configured to provide power to the active devices. In some embodiments, the logic circuit is implemented using standard cells, and the MOL power delivery network 120 is formed by a plurality of power tap cells. During circuit and layout design, the power tap cells can be set together with the standard cells in the layout.

[0032] Note that the semiconductor device 100 can be any suitable device, such as a semiconductor chip (or bare die), a semiconductor wafer (having multiple semiconductor bare dies formed on the semiconductor wafer), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips assembled on a packaging substrate, etc.

[0033] According to some aspects of the present disclosure, the semiconductor device 100 includes active devices such as logic circuits, analog circuits, memory circuits, etc. The active devices are formed in layers that are appropriately deposited and patterned. In some embodiments, standard cells from a standard cell library (such as inverter cells, NAND cells, NOR cells, etc.) are used to implement logic circuits. Each standard cell is configured to perform one or more operations. In an example, the inverter cell is configured to perform a logic inversion operation, so that the output generated by the inverter cell has a logic value that is inverted from the input. For example, when the input is a binary logic value "0", the output is a binary logic value "1"; and when the input is a binary logic value "1", the output is a binary logic value "0". In some examples, in the standard cells, the inverter cell is the smallest logic cell and occupies the smallest area in the example. In some embodiments, the power tap cell is configured to have the same size as the inverter cell or smaller than the size of the inverter cell.

[0034] In some examples, power input structures 101 and 102 are input pads configured to receive power from a power source (not shown) external to the semiconductor device. For example, the external power source has V DD Terminals and V SS Terminal. V DD Used to indicate the high voltage level side of the power supply, such as 5V, 3V, 1.5V, etc., while V SS The power input structure 101 is electrically coupled to the VDD terminal, and the power input structure 102 is electrically coupled to the power source V SS Terminals. In some examples, power input structures 101 and 102 are formed from a top metal layer.

[0035] The UML power delivery network 110 includes electrical connections in upper metal layers that are coupled to form the power delivery network. For example, when the semiconductor device 100 includes metal layers M0 to M7 above active devices, the UML power delivery network 110 includes some wires formed in metal layers M7 to M1 and includes via connections connecting wires in different metal layers.

[0036] The buried power rails of the BPR power delivery network 190 are formed below the physical devices (e.g., active devices, transistors) to allow for a reduction in cell length (footprint). For example, standard cells in a standard cell library are typically implemented as cells with a fixed height and variable width. The fixed height enables these cells to be placed in rows and simplifies the process of automatic layout design. In some examples, the row direction is an orientation referred to as an east-west orientation, while the direction perpendicular to the east-west orientation is referred to as a north-south orientation. According to this naming convention, M0 will typically include lines extending in an east-west orientation, while M1 will have lines extending in a north-south orientation. In some examples, subsequent metal layers will extend perpendicularly relative to the previous metal layers.

[0037] Burying the power rails underneath the physical device allows the cell height of the standard cell to be defined by the number of routing tracks or signal lines, rather than by the combination of power rails and routing tracks. In some examples, by introducing this concept, the cell height can be easily scaled from a cell height of 6.0 to 6.5 routing tracks (6.5T) (assuming the width of the power rail is equal to 2 or 3 times the width of the routing track line) to a cell height of 5.0 routing tracks, even if the actual number of routing tracks is the same.

[0038] exist Figure 1 In the example, for V DD and V SS The buried power rails are arranged in parallel and alternately and extend in an east-west direction respectively. In some embodiments, shallow trench isolation (STI) is used to isolate active devices. The buried power rails can be encapsulated in STI or encapsulated in both bulk silicon and STI, and the buried power rails are buried below the plane of the layer forming the active device. In some embodiments, the rail opening can be formed in STI and extend downward into the bulk silicon, and then the rail opening can be filled with a conductive metal material (such as copper, cobalt or aluminum, ruthenium, etc.), as disclosed in the applicant's co-pending application No. 16 / 011,377 filed on June 18, 2018, which is incorporated herein by reference in its entirety.

[0039] In some embodiments, the rows of standard cells are also in an east-west orientation. The power rails can have a relatively wider width than conventional routing rails, such as about 2 or 3 times the width of the routing rails. In some examples, adjacent rows of standard cells can be arranged in opposite orientations to share a power rail. For example, the standard cells in the first row are oriented north-south (e.g., V DD In the north, V SS in the south), while the standard cells in the second row are oriented north-south (e.g., V DD In the south, V SS When the first row is north of the second row, V SS The power rail can provide V to the standard cells in the first and second rows at the same time. SS .

[0040] exist Figure 1 In the example of FIG. 1 , the power tap unit 120 is arranged in a cell row together with the standard cells. Note that in some examples, multiple power tap units 120 may be arranged in a cell row.

[0041] According to some aspects of the present disclosure, a power tap unit 120 is formed in a device plane with active devices and includes redundant connections for interfacing a UML power delivery network 110 above the device plane with a BPR power delivery network 190 located below the device plane. Further, the power tap unit 120 uses a continuously merged local interconnect to help redistribute current loads while highly redundant connections reduce overall resistance.

[0042] Specifically, the power tap unit 120 includes a rail 150 formed of merged local interconnects, and the rail 150 is referred to as a merged local interconnect (MLI) rail 150. In an example, the MLI rail 150 is formed of a top local interconnect (LI), a bottom LI, and a tape layer connecting the top LI with the bottom LI to continuously merge the top LI with the bottom LI.

[0043] The MLI rail 150 is connected to the buried power rail using a low profile power via structure 160. Figure 1 In the example of FIG. 1 , the buried power rail 190 is in an east-west orientation and the MLI rail 150 is in a north-south orientation.

[0044] Further, the power tap unit 120 includes a track 130 formed in the metal layer M0, and the track 130 is referred to as the M0 track 130. The M0 track 130 is in an east-west orientation. The M0 track 130 is connected to a wire in, for example, the metal layer M1 using a via referred to as V0, and is connected to the MLI track 150 using a top contact diffusion (CD) structure 140.

[0045] According to some aspects of the present disclosure, the components used in the power tap cell 120 are similar to some components used to implement the standard cell, so the power tap cell 120 can be manufactured using the same manufacturing process as the active device. In an embodiment using the CFET method, the logic standard cell has an N-type device (e.g., an N-type metal oxide semiconductor transistor or NMOS transistor) and a P-type device (a P-type metal oxide semiconductor transistor or PMOS transistor), and the N-type device is arranged above the P-type device while sharing a common gate. In some examples, the MLI rail 150 is formed in a manner similar to the drain connection of the inverter cell. For the inverter cell, the drain of the N-type device and the P-type device are connected. In an example, the drain connection of the inverter cell includes a top LI to the drain of the N-type device, a bottom LI to the drain of the P-type device, and a band connection of the top LI and the bottom LI. Similarly, each MLI rail 150 is formed by a top LI, a bottom LI, and a band connection merging the top LI and the bottom LI.

[0046] Note that in some embodiments, additional mask(s) and processes may be used to form the strap connections of the top LI and bottom LI to form the MIL rail 150 .

[0047] The top LI, bottom LI, and strap connections of the MIL rail 150 may each be formed of any suitable conductive material or combination of conductive materials, such as copper, cobalt or aluminum, ruthenium, titanium, doped polysilicon, or the like.

[0048] Note that the standard cell may use some other components. For example, the standard cell also includes a high power via structure and a bottom CD structure. In some examples of CFETs, a power via structure is used to provide power to the active device from the BPR 190. In the example, the N-type device is arranged above the P-type device in a vertical direction perpendicular to the main surface of the substrate, and the buried power rail (e.g., V SS ) are connected to N-type devices using high power via structures, and buried power rails (e.g., V DD ) is connected to a P-type device using a short power via structure. In some examples of CFETs, the metal layer M0 is connected to the active device using a contact diffusion (CD) structure. In an example, the metal layer M0 can be connected to an N-type device using a top CD structure and can be connected to a P-type device using a bottom CD structure. Typically, a tall power via structure has a higher resistance than a short power via structure, and a bottom CD structure has a higher resistance than a top CD structure. Using a short power via structure and a top CD structure in the MOL power delivery network 120 can reduce the voltage drop of power delivery.

[0049] Figure 2FIG. 2 shows a top view of a semiconductor device 200 according to some embodiments of the present disclosure. The semiconductor device 200 is formed by patterns in various layers. Note that for convenience and clarity, Figure 2 Some layers are omitted, such as polysilicon layers.

[0050] exist Figure 2 In the example of , the semiconductor device 200 includes three cell rows, referred to as cell row A, cell row B, and cell row C. The cell rows are oriented east-west and have the same height H. Each cell row includes a plurality of cells, such as logic standard cells, power tap cells, etc. For example, cell row A includes an inverter cell 201, a power tap cell 221, and other logic cells 281 and 282; cell row B includes an inverter cell 202, a power tap cell 222, and other logic cells 283 and 284; and cell row C includes an inverter cell 203, a power tap cell 223, and other logic cells 285 and 286. The power tap cells 221-223 occupy approximately the same footprint as the inverter cells.

[0051] exist Figure 2 In the example of FIG. 1 , the power tap cells 221-223 are aligned in a north-south orientation, and each power tap cell 221-223 includes a portion of a mid-section rail, and the portions are connected to the rails. For example, the two MLI rails 250 and 255 are formed by connecting portions of each power tap cell 221-223. Further, the cells in the cell rows are appropriately oriented, and cell row A and cell row B share (e.g., for V SS ) BPR 292, and cell row B and cell row C share (eg, for V DD Note that cell row A may be shared with an adjacent row in the north direction (not shown) (e.g., for V DD ) BPR 291, and cell row C may be shared with an adjacent row in the south direction (not shown) (e.g., for V SS (d) BPR 294.

[0052] exist Figure 2 In the example of FIG. 1 , the height of the standard unit can support four M0 rails. In the power tap units 221-223, the M0 rail 230 can form multiple redundant connections with the two MLI rails 250 and 255, respectively, and couple the two MLI rails 250 and 255 to the UML power delivery network ( Figure 2 ). Figures 3 to 5 Details of the semiconductor device 200 are described.

[0053] Figure 3A top view 300A and a cross-sectional view 300B are shown of the power tap unit 222 and the power tap unit 223 according to some embodiments of the present disclosure. The cross-sectional view 300B is taken along the line BB' in the top view 300A.

[0054] exist Figure 3 In the example of FIG. 4 , the BPRs 292 - 294 are arranged to extend in an east-west orientation, while the MLI rails 250 and 255 are arranged in a north-south orientation perpendicular to the BPRs 292 - 294 .

[0055] MLI rail 250 is formed by top LI structure 251, strap structure 252, and bottom LI structure 253. MLI rail 250 is connected to BPR 293 through short via structure 261. MLI rail 250 is connected to V through top CD structure 241. DD The M0 track 231.

[0056] exist Figure 3 In the example, each power tap cell includes a power rail from M0 to V DD When setting the power tap units in the unit row as Figure 2 When connected as shown, the power tap unit can redistribute the current load on the BPR, and the redundant connections can reduce the overall resistance.

[0057] Figure 4 A top view 400A and a cross-sectional view 400B are shown of the power tap unit 221 and the power tap unit 222 according to some embodiments of the present disclosure. The cross-sectional view 400B is taken along the line CC' in the top view 400A.

[0058] exist Figure 4 In the example of FIG. 1 , the BPRs 291 - 293 are arranged to extend in an east-west orientation, while the MLI rails 250 and 255 are arranged in a north-south orientation perpendicular to the BPRs 291 - 293 .

[0059] MLI rail 255 is formed by top LI structure 256, strap structure 257, and bottom LI structure 258. MLI rail 255 is connected to BPR 292 through shorty via structure 262. MLI rail 255 is connected to V through top CD structure 242. SS The M0 track 232.

[0060] exist Figure 4 In the example, each power tap cell includes a power rail from M0 to V SS When setting the power tap unit in the unit row as Figure 2When connected as shown, the power tap unit can redistribute the current load on the BPR, and the redundant connection can reduce the overall resistance.

[0061] Figure 5 A top view 500A and two cross-sectional views 500B and 500C of logic cell 286 according to some embodiments of the present disclosure are shown. Cross-sectional view 500B is taken along line DD' in the source / drain region of the CFET, and cross-sectional view 500C is taken along line EE' in the gate region of the CFET.

[0062] exist Figure 5 In the example of FIG. 5 , an N-type device is formed above a P-type device in active structure 599. The source of the N-type device is connected to the V pin through top LI structure 259 and high power via 265. SS of the BPR 294, and the drain of the P-type device is connected to the M0 rail 233 through the bottom LI structure 254 and the bottom CD 245.

[0063] Figure 6 A flow chart outlining an example of a process for manufacturing a semiconductor device, such as semiconductor device 100 , semiconductor device 200 , etc. is shown. The process starts at S601 and proceeds to S610 .

[0064] At S610, a buried power rail is formed in a rail opening within an isolation trench on a substrate. In an example, the buried power rail forms a BPR power delivery network.

[0065] At S620, active devices and a MOL power delivery network are formed. In some examples, the MOL power delivery network includes a MIL rail and an M0 rail. In an example, the MIL rail includes a top LI structure, a bottom LI structure, and a band structure merging the top LI structure and the bottom LI structure. The MIL rail is connected to the BPR through a short power via, and the MIL rail and the M0 rail are connected through a top CD structure.

[0066] At S630, an upper metal layer is formed, and a via structure is also formed to connect the wires in different metal layers. The UML power delivery network is formed in the upper metal layer. In an example, a power input pad is formed in the top metal layer. Then, the process proceeds to S699 and terminates.

[0067] In the foregoing description, specific details have been set forth, such as the specific geometry of the processing system and the description of the various components and processes used therein. However, it should be understood that the technology herein can be practiced in other embodiments that depart from these specific details, and such details are for the purpose of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for the purpose of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. However, embodiments can be practiced without such specific details. Components having substantially the same functional configuration are represented by similar reference numerals, and any redundant description can therefore be omitted.

[0068] Various techniques have been described as multiple discrete operations to help understand various embodiments. The order of description should not be interpreted as meaning that these operations must be dependent on the order. In fact, these operations do not need to be performed in the order presented. The described operations can be performed in an order different from the described embodiments. In additional embodiments, various additional operations can be performed and / or the described operations can be omitted.

[0069] As used herein, "substrate" or "target substrate" generally refers to an object to be processed according to the present invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor wafer, a mask), or a layer (such as a thin film) on or overlying a base substrate structure. Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. The description may refer to a specific type of substrate, but this is for illustrative purposes only.

[0070] Those skilled in the art will also appreciate that many changes may be made to the operation of the above-mentioned techniques while still achieving the same purpose of the present invention. The scope of this disclosure is intended to include these changes. Therefore, the foregoing description of the embodiments of the present invention is not intended to be restrictive. On the contrary, any limitation to the embodiments of the present invention is presented in the appended claims.

Claims

1. A semiconductor device, comprising: a first power rail formed in a first rail opening within a first isolation trench on the substrate; a first power input structure configured to be connected to a first terminal of a power source external to the semiconductor device to receive power from the power source; an active device formed between the first power rail and the first power input structure; as well as a first middle rail, the first middle rail being formed by a plurality of layers arranged along a first direction, the first middle rail being configured to deliver power from the first power input structure to the first power rail, the first power rail providing the power to the active device for operation, and, in the first direction, The bottom surface of the topmost layer of the plurality of layers of the first middle track is higher than and adjacent to the top surface of the active device, and The bottom surface of the lowest layer among the multiple layers of the first middle track is higher than and adjacent to the bottom surface of the active device.

2. The semiconductor device according to claim 1, further comprising: a second power rail formed in a second rail opening in a second isolation trench on the substrate, the second power rail being parallel to the first power rail; a second power input structure configured to be connected to a second terminal of the power source and to receive power from the power source using the first power input structure; as well as A second mid-section rail is formed of a plurality of layers, the second mid-section rail is parallel to the first mid-section rail, and the first mid-section rail and the second mid-section rail are configured to deliver power from the first input structure and the second input structure to the first power rail and the second power rail, and the first power rail and the second power rail provide the power to the active device for operation.

3. The semiconductor device according to claim 1, wherein: The active device includes a cell row of cell circuits having a same cell height; and The first mid-rail includes a portion of the power tap cells arranged in the cell row, the power tap cells having the same cell height as the cell circuits.

4. The semiconductor device according to claim 3, wherein: The first mid-section rail is formed of at least one layer for forming connections within the unit circuit.

5. The semiconductor device according to claim 3, wherein: The active device includes a plurality of cell rows of cell circuits; and The first middle rail is formed by portions respectively disposed in the power tap units in the plurality of unit rows.

6. The semiconductor device according to claim 5, wherein: The power tap units are arranged in a row, and the parts in the corresponding power tap units are conductively connected to form the first middle rail.

7. The semiconductor device according to claim 5, wherein: Each of the parts in the respective power tap unit is connected to the first power rail by at least one power via and to the metal rail by at least one contact.

8. The semiconductor device according to claim 2, wherein: The first middle rail and the second middle rail are perpendicular to the first power rail and the second power rail.

9. The semiconductor device according to claim 1, wherein: The active device includes a first transistor disposed above a second transistor in a vertical direction perpendicular to a surface of the substrate.

10. The semiconductor device according to claim 9, wherein: The first mid-rail includes a first layer for forming a local interconnect in the first transistor, a second layer for forming a local interconnect in the second transistor, and a strap layer for merging the first layer and the second layer.

11. A method for manufacturing a semiconductor device, the method comprising: forming a first power rail in a first rail opening in a first isolation trench on the substrate; forming a first power input structure for coupling with a first terminal of a power source external to the semiconductor device to receive power from the power source; as well as Active devices and a first mid-section rail are formed in a plurality of layers arranged along a first direction between the first power rail and the first power input structure, the first mid-section rail delivers power from the first power input structure to the first power rail, the first power rail provides the power to the active device for operation, and, in the first direction, The bottom surface of the topmost layer of the plurality of layers of the first middle track is higher than and adjacent to the top surface of the active device, and The bottom surface of the lowest layer among the multiple layers of the first middle track is higher than and adjacent to the bottom surface of the active device.

12. The method of claim 11, further comprising: forming a second power rail parallel to the first power rail in a second rail opening in a second isolation trench on the substrate; forming a second power input structure for coupling with a second terminal of the power source to receive the power from the power source; as well as A second mid-section rail is formed in multiple layers of the active device, the second mid-section rail is parallel to the first mid-section rail, and the first mid-section rail and the second mid-section rail deliver power from the first input structure and the second input structure to the first power rail and the second power rail, and the first power rail and the second power rail provide the power to the active device for operation.

13. The method of claim 11, wherein: Forming the active device and the first mid-rail in a plurality of layers between the first power rail and the first power input structure further comprises: A cell row of cell circuits and at least one power tap cell having the same height as the cell circuits are formed, the power tap cell including a portion of the first mid-section rail.

14. The method of claim 13, further comprising: The first mid-section rail is formed using at least one layer used to form connections within a unit circuit.

15. The method of claim 13, further comprising: forming a plurality of cell rows of a cell circuit, wherein the power tap cells are arranged in the plurality of cell rows; as well as The first mid-rail is formed using corresponding portions of the power tap units.

16. The method of claim 15, further comprising: These power tap units are formed to be arranged in a row.

17. The method of claim 15, wherein: Each of the parts in the respective power tap unit is connected to the first power rail by at least one power via and to the metal rail by at least one contact.

18. The method of claim 12, wherein: The first middle rail and the second middle rail are perpendicular to the first power rail and the second power rail.

19. The method of claim 11, wherein: The active device has a first transistor disposed above a second transistor in a vertical direction perpendicular to a surface of the substrate.

20. The method of claim 19, further comprising: The first mid-section rail is formed in a first layer for forming local interconnects in the first transistor, a second layer for forming local interconnects in the second transistor, and a strap layer for merging the first layer and the second layer.

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