Abnormal power failure recovery method, memory controller and memory storage device

Abstract

The present invention provides a method for recovering from an abnormal power failure, a memory control circuit unit, and a memory storage device. The method is used for a memory storage device including a rewritable non-volatile memory module having multiple super physical units. The super physical unit includes at least two physical erase units, each of which belongs to a different operation unit and includes multiple physical programming units. The method includes: when the memory storage device is powered on again and detects an abnormal power failure, reading data stored in a first super physical unit that does not have a corresponding array error correction code to obtain first data, wherein the first super physical unit is the last super physical unit to which data was written before the abnormal power failure occurred; and copying the first data to a second super physical unit.

Description

Technical Field

[0001] The present invention relates to a data storage technology, and in particular to an abnormal power failure recovery method, a memory control circuit unit, and a memory storage device. Background Art

[0002] The rapid growth of digital cameras, mobile phones, and MP3 players in recent years has led to a surge in consumer demand for storage media. Rewritable non-volatile memory modules (e.g., flash memory) are ideally suited for portable electronic products such as laptops due to their data non-volatility, power efficiency, compact size, lack of mechanical structure, and fast read / write speeds. Solid-state drives (SSDs) are a type of memory storage device that utilizes flash memory as its storage medium. Consequently, the flash memory industry has become a highly sought-after sector in the electronics industry in recent years.

[0003] With technological advancements, the number of physical programming units included in a single super physical erase unit has increased, sometimes exceeding 3,000. Consequently, during sudden power-off recovery (SPOR), processing the interrupted operations and managing the physical units takes a significant amount of time. This increases the power-off recovery time and reduces device restart efficiency. Summary of the Invention

[0004] The present invention provides an abnormal power failure recovery method, a memory control circuit unit and a memory storage device, which can reduce the abnormal power failure recovery time and improve the operation efficiency of the memory storage device.

[0005] An exemplary embodiment of the present invention provides a method for recovering from an abnormal power failure, for use in a memory storage device including a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of super physical units, wherein the super physical unit includes at least two physical erase units, the at least two physical erase units belong to different operation units, and each of the physical erase units includes a plurality of physical programming units. The method for recovering from an abnormal power failure includes: when the memory storage device is powered on again and detects an abnormal power failure, reading data stored in a first super physical unit that does not have a corresponding array error correction code to obtain first data, wherein the first super physical unit is the last super physical unit to which data was written before the abnormal power failure occurred; and copying the first data to a second super physical unit.

[0006] In an exemplary embodiment of the present invention, before the step of reading data stored in the first super physical unit that does not have a corresponding array error correction code to obtain the first data, the method further includes: when the memory storage device is powered on again and detects an abnormal power failure, scanning the first super physical unit to obtain the amount of written data in the first super physical unit; determining whether the amount of written data is greater than a first threshold; in response to the amount of written data being greater than the first threshold, obtaining the first data and copying the first data to the second super physical unit; and in response to the amount of written data being less than the first threshold, reading all data stored in the first super physical unit to obtain second data, and copying the second data to the second super physical unit.

[0007] In an exemplary embodiment of the present invention, the first threshold is determined according to the capacity of the first super-entity unit.

[0008] In an exemplary embodiment of the present invention, the first threshold is 1 / 3 of the capacity of the first super-entity unit.

[0009] In an exemplary embodiment of the present invention, after the step of copying the first data to the second super physical unit, the method further includes: receiving a write instruction from a host system, and writing the data indicated by the write instruction to be written into the second super physical unit following the first data.

[0010] In an exemplary embodiment of the present invention, after the step of copying the first data to the second super-physical unit, the method further includes: determining whether an idle time from the last write to the plurality of super-physical units to the present is greater than a preset time; and in response to the idle time being greater than the preset time, reading data other than the first data in the first super-physical unit to obtain third data, and copying the third data to a third super-physical unit.

[0011] In an exemplary embodiment of the present invention, the above method further includes: determining whether the first super physical erase unit is a first-type physical unit or a second-type physical unit; in response to the first super physical erase unit being the first-type physical unit, reading the first data and copying the first data to the second super physical unit; and in response to the second super physical erase unit being the second-type physical unit, not copying the data stored in the first super physical unit.

[0012] In an exemplary embodiment of the present invention, a first total number of physical programming units in the erased state in the first type of physical cells is different from a second total number of physical programming units in the erased state in the second type of physical cells.

[0013] In an exemplary embodiment of the present invention, the first total number is not zero, and the second total number is zero.

[0014] An exemplary embodiment of the present invention provides a memory control circuit unit for controlling a memory storage device. The memory storage device includes a rewritable non-volatile memory module. The memory control circuit unit includes a host interface, a memory interface, and a memory management circuit. The host interface is coupled to a host system. The memory interface is coupled to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of super physical units, wherein each super physical unit includes at least two physical erase units, each of which belongs to different operation units and each includes a plurality of physical programming units. The memory management circuit is coupled to the host interface and the memory interface. When the memory storage device is powered on again and detects an abnormal power failure, the memory management circuit is configured to read data stored in a first super physical unit that does not have a corresponding array error correction code to obtain first data. The first super physical unit is the last super physical unit to which data was written before the abnormal power failure occurred. The memory management circuit is further configured to copy the first data to a second super physical unit.

[0015] In an exemplary embodiment of the present invention, before reading data stored in the first super physical unit that does not have a corresponding array error correction code to obtain the first data, the memory management circuit is further configured to: when the memory storage device is powered on again and detects an abnormal power failure, scan the first super physical unit to obtain the amount of written data in the first super physical unit; determine whether the amount of written data is greater than a first threshold; in response to the amount of written data being greater than the first threshold, obtain the first data and copy the first data to the second super physical unit; and in response to the amount of written data being less than the first threshold, read all data stored in the first super physical unit to obtain second data and copy the second data to the second super physical unit.

[0016] In an exemplary embodiment of the present invention, the first threshold is determined according to the capacity of the first super-entity unit.

[0017] In an exemplary embodiment of the present invention, the first threshold is 1 / 3 of the capacity of the first super-entity unit.

[0018] In an exemplary embodiment of the present invention, after the operation of copying the first data to the second super physical unit, the memory management circuit is further configured to receive a write instruction from the host system and write the data indicated by the write instruction into the second super physical unit following the first data.

[0019] In an exemplary embodiment of the present invention, after copying the first data to the second super-physical unit, the memory management circuit is further configured to determine whether an idle time period between the last write to the plurality of super-physical units and the present is greater than a predetermined time period. Furthermore, in response to the idle time period being greater than the predetermined time period, the memory management circuit is further configured to read data other than the first data from the first super-physical unit to obtain third data, and copy the third data to a third super-physical unit.

[0020] In an exemplary embodiment of the present invention, the memory management circuit is further configured to determine whether the first super physical erase unit is a first-type physical unit or a second-type physical unit. In response to the first super physical erase unit being the first-type physical unit, the memory management circuit is further configured to read the first data and copy the first data to the second super physical unit. Furthermore, in response to the second super physical erase unit being the second-type physical unit, the memory management circuit is further configured not to copy the data stored in the first super physical unit.

[0021] In an exemplary embodiment of the present invention, a first total number of physical programming units in the erased state in the first type of physical cells is different from a second total number of physical programming units in the erased state in the second type of physical cells.

[0022] In an exemplary embodiment of the present invention, the first total number is not zero, and the second total number is zero.

[0023] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, and a memory control circuit unit. The connection interface unit is used to couple to a host system. The rewritable non-volatile memory module includes a plurality of super physical units, wherein the super physical unit includes at least two physical erase units, the at least two physical erase units belonging to different operation units, and each of the physical erase units includes a plurality of physical programming units. The memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. The memory control circuit unit is used to read data stored in a first super physical unit that does not have a corresponding array error correction code to obtain first data when the memory storage device is powered on again and detects an abnormal power outage. The first super physical unit is the super physical unit to which data was last written before the abnormal power outage occurred. In addition, the memory control circuit unit is further used to copy the first data to a second super physical unit.

[0024] In an exemplary embodiment of the present invention, before reading data stored in the first super-physical unit that does not have a corresponding array error correction code to obtain the first data, the memory control circuit unit is further configured to: when the memory storage device is powered on again and detects an abnormal power failure, scan the first super-physical unit to obtain the amount of written data in the first super-physical unit; determine whether the amount of written data is greater than a first threshold; in response to the amount of written data being greater than the first threshold, obtain the first data and copy the first data to the second super-physical unit; and in response to the amount of written data being less than the first threshold, read all data stored in the first super-physical unit to obtain second data and copy the second data to the second super-physical unit.

[0025] In an exemplary embodiment of the present invention, the first threshold is determined according to the capacity of the first super-entity unit.

[0026] In an exemplary embodiment of the present invention, the first threshold is 1 / 3 of the capacity of the first super-entity unit.

[0027] In an exemplary embodiment of the present invention, after the operation of copying the first data to the second super physical unit, the memory control circuit unit is further configured to receive a write instruction from the host system and write the data indicated by the write instruction into the second super physical unit following the first data.

[0028] In an exemplary embodiment of the present invention, after copying the first data to the second super-physical unit, the memory control circuit unit is further configured to determine whether an idle time period between the last write to the plurality of super-physical units and the present is greater than a predetermined time period. Furthermore, in response to the idle time period being greater than the predetermined time period, the memory control circuit unit is further configured to read data other than the first data from the first super-physical unit to obtain third data, and copy the third data to a third super-physical unit.

[0029] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to determine whether the first super physical erase unit is a first-type physical unit or a second-type physical unit. In response to the first super physical erase unit being the first-type physical unit, the memory control circuit unit is further configured to read the first data and copy the first data to the second super physical unit. Furthermore, in response to the second super physical erase unit being the second-type physical unit, the memory control circuit unit is further configured to not copy the data stored in the first super physical unit.

[0030] In an exemplary embodiment of the present invention, a first total number of physical programming units in the erased state in the first type of physical cells is different from a second total number of physical programming units in the erased state in the second type of physical cells.

[0031] In an exemplary embodiment of the present invention, the first total number is not zero, and the second total number is zero.

[0032] Based on the foregoing, the abnormal power failure recovery method, memory control circuit unit, and memory storage device proposed in embodiments of the present invention can, when a super-physical unit includes an increasing number of physical programming units, copy all or part of the data in a super-physical unit to another super-physical unit based on its characteristics upon power-on after an abnormal power failure. This effectively reduces the recovery time from an abnormal power failure and improves the operating efficiency of the memory storage device.

[0033] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0035] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment;

[0036] Figure 2 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to another exemplary embodiment;

[0037] Figure 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment;

[0038] Figure 4 is a schematic block diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;

[0039] Figure 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

[0040] Figure 6 is a schematic diagram of managing a rewritable non-volatile memory module according to an exemplary embodiment of the present invention;

[0041] Figure 7 is a schematic diagram of a management unit according to an exemplary embodiment of the present invention;

[0042] Figure 8 is a schematic diagram of data writing according to an exemplary embodiment of the present invention;

[0043] Figure 9 is a schematic diagram of data writing according to an exemplary embodiment of the present invention;

[0044] Figures 10 to 12 FIG. 4 is a flow chart of a method for recovering from an abnormal power failure according to an exemplary embodiment. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0046] Generally speaking, a memory storage device (also known as a memory storage system) includes a rewritable non-volatile memory module and a controller (also known as a control circuit unit). The memory storage device is typically used in conjunction with a host system so that the host system can write data to the memory storage device or read data from the memory storage device.

[0047] Figure 1 is a schematic diagram of a host system, a memory storage device, and an input / output (I / O) device according to an exemplary embodiment. Figure 2is a schematic diagram illustrating a host system, a memory storage device, and an input / output (I / O) device according to another exemplary embodiment.

[0048] Please refer to Figure 1 and Figure 2 The host system 11 generally includes a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 , and a data transmission interface 114 . The processor 111 , the RAM 112 , the ROM 113 , and the data transmission interface 114 are all coupled to a system bus 110 .

[0049] In this exemplary embodiment, the host system 11 is coupled to the memory storage device 10 via a data transfer interface 114. For example, the host system 11 can write data to the memory storage device 10 or read data from the memory storage device 10 via the data transfer interface 114. In addition, the host system 11 is coupled to the I / O device 12 via a system bus 110. For example, the host system 11 can transmit output signals to the I / O device 12 or receive input signals from the I / O device 12 via the system bus 110.

[0050] In this exemplary embodiment, the processor 111, random access memory 112, read-only memory 113, and data transmission interface 114 may be disposed on a motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 may be coupled to the memory storage device 10 via a wired or wireless method. The memory storage device 10 may be, for example, a USB flash drive 201, a memory card 202, a solid state drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device, or a low-power Bluetooth memory storage device (e.g., iBeacon), or other memory storage devices based on various wireless communication technologies. Furthermore, the motherboard 20 may also be coupled to various I / O devices such as a Global Positioning System (GPS) module 205, a network adapter 206, a wireless transmission device 207, a keyboard 208, a display 209, and a speaker 210 via the system bus 110. For example, in one exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.

[0051] In one exemplary embodiment, the host system mentioned is any system that can actually cooperate with the memory storage device to store data. Although in the above exemplary embodiment, the host system is described as a computer system, however, Figure 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment. Figure 3 In another exemplary embodiment, the host system 31 may be a digital camera, video camera, communication device, audio player, video player, or tablet computer, and the memory storage device 30 may be a non-volatile memory storage device such as an SD card 32, a CF card 33, or an embedded storage device 34. The embedded storage device 34 includes various types of embedded storage devices that directly couple the memory module to the host system's substrate, such as an embedded Multi-Media Card (eMMC) 341 and / or an embedded Multi-Chip Package (eMCP) 342.

[0052] Figure 4 FIG. 1 is a schematic block diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention.

[0053] Please refer to Figure 4 The memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 , and a rewritable non-volatile memory module 406 .

[0054] In this exemplary embodiment, the connection interface unit 402 is compatible with the Peripheral Component Interconnect Express (PCI Express) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may also comply with the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronic Engineers (IEEE) 1394 standard, the Secure Digital (SD) interface standard, the Universal Serial Bus (USB) standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the Multi-Chip Package (MCP) interface standard, the Multi Media Card (MMC) interface standard, the Embedded Multimedia Card (eMMC) interface standard, the Compact Flash (CF) interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. In this exemplary embodiment, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in one chip, or the connection interface unit 402 may be disposed outside a chip including the memory control circuit unit 404 .

[0055] The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations such as writing, reading, and erasing data in the rewritable non-volatile memory module 406 according to instructions from the host system 11 .

[0056] The rewritable non-volatile memory module 406 is coupled to the memory control circuit unit 404 and is used to store data written by the host system 11. The rewritable non-volatile memory module 406 has physical erase units 410 (0) to 410 (N). For example, the physical erase units 410 (0) to 410 (N) may belong to the same memory die or to different memory dies. Each physical erase unit has a plurality of physical programming units, wherein the physical programming units belonging to the same physical erase unit can be written independently and erased simultaneously. However, it must be understood that the present invention is not limited to this, and each physical erase unit can be composed of 64 physical programming units, 256 physical programming units, or any other number of physical programming units.

[0057] More specifically, a physical erase unit is the smallest unit of erase. That is, each physical erase unit contains a minimum number of erased storage cells. A physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit of data written. Each physical programming unit typically includes a data bit area and a redundancy bit area. The data bit area contains multiple physical access addresses for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as control information and error correction codes). In this exemplary embodiment, the data bit area of each physical programming unit contains 8 physical access addresses, and the size of each physical access address is 512 bytes. However, in other exemplary embodiments, the data bit area may also contain a larger or smaller number of physical access addresses, and the present invention is not limited to the size and number of physical access addresses. For example, in one exemplary embodiment, the physical erase unit is a physical block, and the physical programming unit is a physical page or a physical sector, but the present invention is not limited to this.

[0058] In this exemplary embodiment, the rewritable non-volatile memory module 406 is a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module in which one storage cell can store one data bit). However, the present invention is not limited thereto, and the rewritable non-volatile memory module 406 may also be a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module in which one storage cell can store two data bits), a trinary level cell (TLC) NAND flash memory module (i.e., a flash memory module in which one storage cell can store three data bits), or other memory modules with the same characteristics. Specifically, the storage cells on the same character line can constitute one or more physical programming units. If each storage cell can store more than two bits, the physical programming units on the same character line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programming cell, and the most significant bit (MSB) of a memory cell belongs to the upper physical programming cell. Generally speaking, in MLC NAND flash memory, the write speed of the lower physical programming cell is greater than the write speed of the upper physical programming cell, and / or the reliability of the lower physical programming cell is higher than the reliability of the upper physical programming cell.

[0059] Figure 5 FIG. 4 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

[0060] Please refer to Figure 5 The memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 .

[0061] The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 operates, these control instructions are executed to perform operations such as writing, reading, and erasing data.

[0062] In this exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 includes a microprocessor unit (not shown) and a read-only memory (ROM) (not shown), and these control instructions are burned into the ROM. When the memory storage device 10 is operating, these control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.

[0063] In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 may also be stored in the form of program code in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). Furthermore, the memory management circuit 502 includes a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (RAM) (not shown). Specifically, the ROM includes a driver code. When the memory control circuit unit 404 is enabled, the microprocessor unit first executes this driver code segment to load the control instructions stored in the rewritable non-volatile memory module 406 into the RAM of the memory management circuit 502. The microprocessor unit then executes these control instructions to perform operations such as writing, reading, and erasing data.

[0064] Furthermore, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 502 can also be implemented in hardware. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory write circuit, the memory read circuit, the memory erase circuit, and the data processing circuit are coupled to the microcontroller. Among them, the storage unit management circuit is used to manage the physical erase unit of the rewritable non-volatile memory module 406; the memory write circuit is used to issue a write instruction to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406; the memory read circuit is used to issue a read instruction to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406; the memory erase circuit is used to issue an erase instruction to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406; and the data processing circuit is used to process data to be written to the rewritable non-volatile memory module 406 and data to be read from the rewritable non-volatile memory module 406.

[0065] The host interface 504 is coupled to the memory management circuit 502 and is used to couple to the connection interface unit 402 to receive and identify commands and data transmitted by the host system 11. In other words, the commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In this exemplary embodiment, the host interface 504 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited to this standard. The host interface 504 may also be compatible with the PATA standard, IEEE 1394 standard, SATA standard, USB standard, UHS-I interface standard, UHS-II interface standard, SD standard, MS standard, MMC standard, CF standard, IDE standard, or other suitable data transmission standards.

[0066] The memory interface 506 is coupled to the memory management circuit 502 and is used to access the rewritable non-volatile memory module 406. That is, data to be written to the rewritable non-volatile memory module 406 is converted into a format acceptable to the rewritable non-volatile memory module 406 via the memory interface 506.

[0067] The buffer memory 508 is coupled to the memory management circuit 502 and is used to temporarily store data and commands from the host system 11 or data from the rewritable non-volatile memory module 406 .

[0068] In one exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 508 , a power management circuit 510 , and an error checking and correction circuit 512 .

[0069] The power management circuit 510 is coupled to the memory management circuit 502 and is used to control the power of the memory storage device 10 .

[0070] The ECC circuit 512 is coupled to the memory management circuit 502 and is configured to perform error checking and correction (ECC) procedures to ensure data accuracy. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the ECC circuit 512 generates an ECC code (Error Checking and Correcting Code) for the data corresponding to the write command. The memory management circuit 502 then writes the data corresponding to the write command and the ECC code to the rewritable non-volatile memory module 406. Subsequently, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it simultaneously reads the ECC code corresponding to the data. The ECC circuit 512 then performs an ECC procedure on the read data based on the ECC code.

[0071] The following description of operations performed by the memory management circuit 502 , the host interface 504 , the memory interface 506 , the buffer memory 508 , the power management circuit 510 , and the error checking and correction circuit 512 may also refer to operations performed by the memory control circuit unit 404 .

[0072] In one exemplary embodiment, the basic unit for the ECC circuit 512 to perform encoding / decoding is a frame. A frame includes a plurality of data bits, for example, 256 bits. However, in different exemplary embodiments, a frame may include more or fewer bits.

[0073] In this exemplary embodiment, the ECC circuit 512 can perform single-frame encoding and decoding for data stored in the same physical programming unit, or multi-frame encoding and decoding for data stored in multiple physical programming units. Single-frame encoding and multi-frame encoding can each employ at least one of a coding algorithm such as a low-density parity check code (LDPC code), a BCH code, a convolutional code, or a turbo code. Alternatively, in one exemplary embodiment, multi-frame encoding can employ a Reed-Solomon code (RS code) algorithm. In addition to the aforementioned coding algorithms, more coding algorithms not listed above can also be employed and are not further described here. Based on the employed coding algorithm, the ECC circuit 512 can encode the data to be protected to generate a corresponding ECC code. The ECC code can be a parity checking code, a channel coding, or other types. For the convenience of explanation, the error checking and correction code is referred to as error correction code below.

[0074] In one exemplary embodiment, the error correction code comprises a Redundant Array of Independent Disks (RAID) error correction code, also referred to as a RAID ECC code. For example, the memory management circuit 502 may temporarily store data corresponding to a write command from the host system 11 in the buffer memory 508 and generate a RAID ECC based on the data. This RAID ECC is used to correct data in multiple physical programming units. For example, the memory management circuit 502 performs a logical operation on data programmed into different physical programming units to generate the RAID ECC. Both the data used to generate the RAID ECC and the RAID ECC comply with the encoding rules of the RAID ECC. Therefore, the RAID ECC can correct data in more than two physical programming units. The generated RAID ECC is also programmed into one physical programming unit. In this exemplary embodiment, the RAID ECC is generated by the memory management circuit 502. However, the RAID ECC may also be generated by the error checking and correction circuit 512, and the present invention is not limited thereto.

[0075] In one exemplary embodiment, the memory management circuit 502 may manage and access physical nodes in the rewritable non-volatile memory module 406 based on management units. A management unit is also referred to as a virtual block (VB). A management unit may include multiple physical nodes. For example, a management unit may include multiple physical nodes belonging to one or more planes (also referred to as memory planes) and / or one or more chip enables (CEs) in the rewritable non-volatile memory module 406.

[0076] Figure 6 FIG is a schematic diagram showing a management method of a rewritable non-volatile memory module according to an exemplary embodiment of the present invention. Figure 6 , the rewritable non-volatile memory module 406 includes management units 61(0)~61(n). Each of the management units 61(0)~61(n) includes chip enable (also called chip enable group) CE(0) and CE(1). The chip enable CE(0) and CE(1) each include multiple physical nodes. The memory management circuit 502 can enable the chip enable through the chip enable pin respectively. The memory management circuit 502 can access the management units 61(0)~61(n) through channels 60(0)~60(m). For example, the memory management circuit 502 can access the management units 61(0)~61(1) in parallel (or called interleaved) through at least two channels among the channels 60(0)~60(m). In addition, the chip enable CE(0) and CE(1) can each include multiple planes (for example Figure 7The first plane PL(1), PL(3), PL(5), PL(7) and the second plane PL(2), PL(4), PL(6), PL(8)).

[0077] The planes in management units 61(0) and 61(1) may include multiple physical nodes. These physical nodes may be accessed in parallel (or interleaved) to improve access efficiency. In one exemplary embodiment, multiple consecutive physical nodes in a plane may be referred to as a physical programming unit. Alternatively, in one exemplary embodiment, multiple consecutive physical nodes in a chip enable may be referred to as a physical programming unit. Alternatively, in one exemplary embodiment, multiple consecutive physical nodes in multiple planes may be referred to as a physical programming unit.

[0078] The memory management circuit 502 may also combine multiple physical erase units belonging to different memory planes into a super physical unit (also referred to as a super physical erase unit) to perform operations (e.g., data write operations, data erase operations). A super physical unit includes at least two available physical erase units from all physical erase units. In this exemplary embodiment, the at least two available physical erase units included in a super physical unit belong to different operation units (e.g., planes, interleaves, or channels). Therefore, different physical programming units in the super physical programming units included in the super physical unit can be programmed simultaneously according to the same write instruction.

[0079] Figure 7 is a schematic diagram of a management unit according to an exemplary embodiment of the present invention. Figure 7Taking the management units 61(0) and 61(1) as an example, the first planes PL(1), PL(3), PL(5), PL(7) and the second planes PL(2), PL(4), PL(6), PL(8) may include a plurality of physical nodes. The management unit 61(0) includes chip enable CE(0) and CE(1), and the first planes PL(1), PL(3) and the second planes PL(2), PL(4) in the chip enable CE(0) and CE(1) respectively include physical programming units 701(0) to 701(M), 702(0) to 702(M), 703(0) to 703(M) and 704(0) to 704(M). The management unit 61(1) includes chip enable CE(0) and CE(1). The first plane PL(5), PL(7) and the second plane PL(6), PL(8) in the chip enable CE(0) and CE(1) respectively include physical programming units 705(0)-705(M), 706(0)-706(M), 707(0)-707(M) and 708(0)-708(M). In this exemplary embodiment, the physical programming units 701(0)-708(0), 701(1)-708(1) and 701(M)-708(M) can be configured as super physical programming units.

[0080] In this exemplary embodiment, the memory management circuit 502 can write data into a plurality of physical programming units according to the programming order of planes PL(1) to PL(8). Assuming that all physical programming units are blank, in order to write a write data that can fill 14 physical programming units, the memory management circuit 502 will program the write data into the physical programming units starting from the first blank physical programming unit (e.g., physical programming unit 701(0)) according to a programming order (e.g., physical programming units 701(0), 702(0), 703(0), 704(0), 705(0), 706(0), 707(0), 708(0), 701(1), 702(1), 703(1), 704(1), 705(1), 706(1) will program the write data into the physical programming units according to the programming order), and so on. In another embodiment, the memory management circuit 502 may program data into a single (or more) management unit, for example, it may program data into multiple physical programming units according to the programming order of planes PL(1) to PL(4), but the present invention is not limited thereto.

[0081] Figure 8 Schematic diagram of data writing according to an exemplary embodiment of the present invention. For the sake of simplicity, the corresponding number of each physical programming unit is not directly drawn here. Please refer to Figure 7 The entity programmatic unit in Figure 8The label of the entity programming unit on the left. Figure 8 In the exemplary embodiment, for ease of explanation, it is assumed that a super physical unit includes 48 physical programming units, and the physical programming units 701(0)-708(0), 701(1)-708(1), 701(2)-708(2), 701(3)-708(3), 701(4)-708(4), and 701(5)-708(5) can be configured as a super physical unit 810. That is, each super physical unit includes multiple physical programming units belonging to different operation units (e.g., planes, interlaces, or channels). It should be noted that in different exemplary embodiments, a super physical unit may also include more or fewer physical programming units.

[0082] In this exemplary embodiment, upon receiving a write command from the host system 11, the memory management circuit 502 may store data corresponding to the write command in a plurality of physical programming units. For example, data D0 to D13 are stored in physical programming units 701(0), 702(0), 703(0), 704(0), 705(0), 706(0), 707(0), 708(0), 701(1), 702(1), 703(1), 704(1), 705(1), and 706(1), respectively. After performing multi-frame encoding on the data D0 to D13, array error correction codes P0 and P1 are generated and stored in physical programming units 707(1) and 708(1). In other words, the array ECC codes P0 and P1 can be considered fault-tolerant RAID error correction codes corresponding to data D0-D13. Array ECC codes P0 and P1 are generated by encoding data D0-D13 based on the encoding rules of the fault-tolerant RAID error correction codes. In this exemplary embodiment, data D0-D13 and the array ECC codes P0 and P1 can be combined to form a block code with the array ECC code as the protection unit.

[0083] It is worth noting that the host system 11 may experience an abnormal power loss during operation, causing the memory storage device 10 to suddenly lose power when data is being written. If an abnormal power loss occurs, the written data will not be fully stored in the rewritable non-volatile memory module 406, and the written data may be lost in any physical programming unit.

[0084] Figure 9 FIG. 1 is a schematic diagram of data writing according to an exemplary embodiment of the present invention. Figure 8, assuming that the memory management circuit 502 continues to store data into the super physical unit 810 including the physical programming unit according to the write instruction. For example, data D14 to D17 are stored in the physical programming units 701 (2), 702 (2), 703 (2), and 704 (2), respectively. If the memory storage device 10 loses power while writing data D17 to the physical programming unit 704 (2), the data write operation will be interrupted. At this time, the data D14 to D17 that have not yet been protected by the array error correction code will not be corrected when there is an error in the data.

[0085] In one exemplary embodiment, when the memory storage device 10 is powered on again, the memory management circuit 502 may determine whether the power-off state of the memory storage device 10 is an abnormal power-off state. For example, the memory management circuit 502 may determine whether the memory storage device 10 experienced a normal power-off or an abnormal power-off state based on a power-off instruction. Specifically, when the system is powered off normally, the memory storage device 10 will receive a power-off instruction from the host system 11. If the memory management circuit 502 does not detect the power-off instruction when the memory storage device 10 is powered on again after a power outage, it may be determined that the memory storage device 10 experienced an abnormal power-off during the power-off state and is in an abnormal power-off state. If the memory management circuit 502 detects the power-off instruction when the memory storage device 10 is powered on again after a power outage, it may be determined that the memory storage device 10 experienced a normal power-off during the power-off and is in a normal power-off state.

[0086] In one exemplary embodiment, if a sudden power outage occurs in the memory storage device 10, the memory management circuit 502 may perform a sudden power-off recovery (SPOR) operation. During the SPOR operation, the memory management circuit 502 may scan a specific super unit (also referred to as a first super unit) to obtain the amount of data written to the super unit. Specifically, the first super unit is the last super unit to be written before the sudden power outage.

[0087] In this exemplary embodiment, the memory management circuit 502 determines whether the amount of received write data is greater than a threshold value (also referred to as a first threshold value). The memory management circuit 502 may determine the first threshold value based on the capacity of the super physical unit. For example, the capacity of the super physical unit may be calculated based on the capacity of each physical programming unit in the super physical unit and the number of physical programming units. The first threshold value may be set to 1 / 3 of the capacity of the super physical unit or 1 / 2 of the capacity of the super physical unit, depending on the needs, but the present invention is not limited thereto.

[0088] With technological advancements, the number of physical programming units configured to be included in a super physical unit is increasing, even increasing from over 100 physical programming units to over 3,000 physical programming units. If data is written to a location close to the last physical programming unit in a super physical unit during an abnormal power outage, the amount of data to be copied will be very large. This will result in a very long copying time, affecting the boot time of the host system 11. Therefore, in an exemplary embodiment, in response to the amount of written data being greater than a first threshold value, the memory management circuit 502 reads data stored in the first super physical unit that does not have a corresponding array error correction code to obtain data (also referred to as first data), and copies the read first data to another super physical unit (also referred to as a second super physical unit). The data that does not have a corresponding array error correction code indicates that the data is not protected by the array error correction code.

[0089] For example, see Figure 9 Assume that the first threshold value is 1 / 3 of the capacity of the super physical unit. When the memory storage device 10 experiences an abnormal power outage and is powered on again, the amount of data written to the super physical unit 810 exceeds the first threshold value. The memory management circuit 502 may copy the data D14-D17 in the super physical unit 810 that do not have a corresponding array error correction code to another super physical unit. It is worth noting that in this exemplary embodiment, when performing a power outage recovery operation, the memory management circuit 502 does not read the data stored in the first super physical unit that has a corresponding array error correction code. Instead, it copies the data stored in the first super physical unit that does not have a corresponding array error correction code to another super physical unit.

[0090] After copying the first data to the second super physical unit, the memory management circuit 502 may update the mapping information between the logical address corresponding to the first data and the physical programming unit included in the second super physical unit in the logical-to-physical mapping table. Furthermore, when the memory storage device 10 receives a write command from the host system 11, the memory management circuit 502 may write the data indicated by the write command to the second super physical unit following the first data.

[0091] For example, see Figure 9 Assume that the first threshold is 1 / 3 of the capacity of the super physical unit. When the memory storage device 10 experiences an abnormal power outage and then powers back on, the amount of data written into the super physical unit 810 exceeds the first threshold. The memory management circuit 502 may copy the data D14-D17 in the super physical unit 810 that do not have corresponding array ECCs, as well as the last set of block codes written into the super physical unit 810 (including data D0-D13 and array ECCs P0 and P1) protected by the array ECC, to another super physical unit.

[0092] In one exemplary embodiment, the physical programming units included in the last super-physical unit to which data was written before the abnormal power outage are relatively unstable. If the amount of data written is small and does not exceed a specific amount, all data stored in the super-physical unit may be copied to another super-physical unit to maintain the stability of the stored data. Therefore, in response to the amount of written data being no greater than a first threshold, the memory management circuit 502 may read all data stored in the first super-physical unit to obtain data (also referred to as second data), and copy the read second data to another super-physical unit (also referred to as a second super-physical unit). In this exemplary embodiment, after copying the second data to the second super-physical unit, the memory management circuit 502 may update the mapping information between the logical address corresponding to the second data and the physical programming units included in the second super-physical unit in the logical-to-physical mapping table, and erase the data in the first super-physical unit.

[0093] It is worth noting that when the memory storage device 10 is powered on again and detects an abnormal power failure, the memory management circuit 502 can also directly read the data stored in the first super physical unit that does not have a corresponding array error correction code to obtain the first data without scanning, and copy the first data to the second super physical unit.

[0094] In one exemplary embodiment, the memory management circuit 502 may further determine the type of the first super-physical unit to determine whether to copy the data stored in the first super-physical unit. Specifically, when performing a power-off recovery operation, the memory management circuit 502 may obtain the type of the first super-physical unit. This type includes first-type super-physical units and second-type super-physical units. The first-type super-physical unit refers to the super-physical unit that is currently an open unit (also known as an open block). Once a super-physical unit that is an open unit is full (for example, all physical programming units in this super-physical unit have been programmed and are in a programmed state), this super-physical unit may become a closed unit (also known as a closed block). In one exemplary embodiment, the second-type super-physical unit refers to the super-physical unit that is currently a closed unit.

[0095] In this exemplary embodiment, the memory management circuit 502 can determine whether the first super physical erase unit is a first-type physical unit or a second-type physical unit. In response to the first super physical erase unit being a second-type physical unit, the memory management circuit 502 does not copy the data stored in the first super physical unit. In response to the first super physical erase unit being a first-type physical unit, the memory management circuit 502 copies the data stored in the first super physical unit to the second super physical unit. For example, the memory management circuit 502 can copy all or part of the data stored in the first super physical unit to the second super physical unit. The details of copying data and how to determine whether to copy all or part of the data can be found in the description of the aforementioned exemplary embodiment and will not be repeated here.

[0096] In one exemplary embodiment, the memory management circuit 502 may determine whether the first super physical unit is a first-type physical unit or a second-type physical unit based on the total number of physical programming units in the first super physical unit that are in an erased state (or a programmed state). For example, in response to the total number of physical programming units in the first super physical unit that are in an erased state being non-zero, the memory management circuit 502 may determine that the first super physical unit is a first-type physical unit. On the other hand, in response to the total number of physical programming units in the first super physical unit that are in an erased state being zero, the memory management circuit 502 may determine that the first super physical unit is a second-type physical unit.

[0097] Furthermore, it is worth noting that after the power-off recovery operation is completed and the memory storage device 10 begins normal operation, this exemplary embodiment may further process the first type of physical unit to increase management efficiency. In one exemplary embodiment, the memory management circuit 502 may determine whether the idle time elapsed since the last write to the multiple super physical units included in the rewritable non-volatile memory module 406 is greater than a preset time. If the idle time is not greater than the preset time, the usage time continues to be accumulated. In response to the idle time being greater than the preset time, the memory management circuit 502 may perform a data cleanup operation. During the data cleanup operation, the memory management circuit 502 may read data other than the first data in the first super physical unit to obtain third data, and copy the third data to another super physical unit (also referred to as a third super physical unit). After copying the third data to the third super physical unit, the memory management circuit 502 may update the mapping information between the logical address corresponding to the third data and the physical programming unit included in the third super physical unit in the logical-to-physical mapping table, and erase the data in the first super physical unit.

[0098] Specifically, when performing a power-off recovery operation, the memory management circuit 502 copies the first data stored in the first super physical unit, which does not have a corresponding array error correction code, to the second super physical unit. After a period of inactivity, this exemplary embodiment can copy the remaining third data, other than the first data, to the third super physical unit. This third super physical unit may be identical to the second super physical unit in terms of operation, but the present invention is not limited thereto. In this way, the memory storage device 10 can maintain the second type of physical units in the rewritable non-volatile memory module 406, making them easier to manage than the first type of physical units.

[0099] Figure 10 This is a flow chart illustrating a method for recovering from an abnormal power outage according to an exemplary embodiment. In step S1002, the memory storage device is powered on again and detects an abnormal power outage. In step S1004, data stored in the first super-physical unit that does not have a corresponding array error correction code is read to obtain first data, and the first data is copied to the second super-physical unit.

[0100] Figure 11 This is a flow chart of a method for recovering from an abnormal power failure according to an exemplary embodiment. In step S1102, the memory storage device is powered on again and detects an abnormal power failure. In step S1104, the first super-physical unit is scanned to obtain the amount of written data in the first super-physical unit. In step S1106, it is determined whether the amount of written data is greater than a first threshold. If the amount of written data is greater than the first threshold (i.e., step S1106 determines "yes"), in step S1108, data stored in the first super-physical unit that does not have a corresponding array error correction code is read to obtain first data, and the first data is copied to a second super-physical unit. If the amount of written data is not greater than the first threshold (i.e., step S1106 determines "no"), in step S1110, all data stored in the first super-physical unit is read to obtain second data, and the second data is copied to the second super-physical unit.

[0101] Figure 12 This is a flow chart of a method for recovering from an abnormal power failure according to an exemplary embodiment. In step S1202, the memory storage device is powered on again and detects an abnormal power failure. In step S1204, it is determined whether the first super physical erase unit is a first-type physical unit or a second-type physical unit. In step S1206, in response to the first super physical erase unit being a first-type physical unit, the data stored in the first super physical unit is copied to the second super physical unit. In step S1208, in response to the first super physical erase unit being a second-type physical unit, the data stored in the first super physical unit is not copied.

[0102] However, Figures 10 to 12The steps have been described in detail above and will not be repeated here. Figures 10 to 12 Each step can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figures 10 to 12 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0103] In summary, the abnormal power failure recovery method, memory control circuit unit, and memory storage device proposed in the embodiments of the present invention can, upon power-on after an abnormal power failure, copy all or part of the data in a super-physical unit to another super-physical unit based on the characteristics of the super-physical unit. For example, unstable data stored in a super-physical unit without a corresponding array error correction code can be copied to another super-physical unit for storage. This effectively reduces the recovery time from an abnormal power failure and improves the operating efficiency of the memory storage device.

[0104] Although the present invention has been disclosed above with reference to the embodiments, they are not intended to limit the present invention. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for recovering from an abnormal power outage, characterized in that: A memory storage device comprising a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of super physical units, wherein the super physical unit comprises at least two physical erase units, wherein the at least two physical erase units belong to different operation units and each of the physical erase units comprises a plurality of physical programming units, and wherein the abnormal power failure recovery method comprises: When the memory storage device is powered on again and detects abnormal power failure, data stored in the first super entity unit that does not have a corresponding array error correction code is read to obtain the first data. The first super physical unit is the last super physical unit to be written with data before the abnormal power failure occurs; and copying the first data to a second super entity unit, Before the step of reading data stored in the first super-physical unit that does not have a corresponding array error correction code to obtain the first data, the method further includes: When the memory storage device is powered on again and detects an abnormal power outage, scanning the first super physical unit to obtain the amount of written data in the first super physical unit; Determining whether the amount of written data is greater than a first threshold; and In response to the amount of written data being no greater than the first threshold, all data stored in the first super physical unit is read to obtain second data, and the second data is copied to the second super physical unit.

2. The abnormal power failure recovery method according to claim 1, characterized in that: Before the step of reading data stored in the first super-physical unit that does not have a corresponding array error correction code to obtain the first data, the method further includes: In response to the amount of written data being greater than the first threshold, the first data is obtained and copied to the second super physical unit.

3. The abnormal power failure recovery method according to claim 2, characterized in that: The first threshold value is determined according to the capacity of the first super entity unit.

4. The abnormal power failure recovery method according to claim 2, characterized in that: The first threshold value is 1 / 3 of the capacity of the first super-entity unit.

5. The abnormal power failure recovery method according to claim 1, characterized in that: After the step of copying the first data to the second super entity unit, the method further comprises: A write instruction from a host system is received, and the data indicated by the write instruction is written into the second super physical unit following the first data.

6. The abnormal power failure recovery method according to claim 1, characterized in that: After the step of copying the first data to the second super entity unit, the method further comprises: Determining whether the idle time from the last writing to the present in the plurality of super entity units is greater than a preset time; and In response to the idle time being greater than the preset time, data other than the first data in the first super physical unit is read to obtain third data, and the third data is copied to a third super physical unit.

7. The abnormal power failure recovery method according to claim 1, characterized in that: The method further comprises: determining whether the first super entity element is a first-type entity element or a second-type entity element; In response to the first super entity unit being a first type entity unit, reading the first data and copying the first data to the second super entity unit; and In response to the first super entity unit being the second type entity unit, the data stored in the first super entity unit is not copied.

8. The abnormal power failure recovery method according to claim 7, characterized in that: A first total number of physical programming units in the first type of physical units in an erased state is different from a second total number of physical programming units in the second type of physical units in the erased state.

9. The abnormal power failure recovery method according to claim 8, characterized in that: The first total is non-zero, and the second total is zero.

10. A memory control circuit unit for controlling a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module, characterized in that: The memory control circuit unit includes: A host interface for coupling to a host system; a memory interface for coupling to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of super physical units, wherein the super physical unit includes at least two physical erase units, the at least two physical erase units belong to different operation units, and each of the physical erase units includes a plurality of physical programming units; and A memory management circuit coupled to the host interface and the memory interface, wherein the memory management circuit is configured to read data stored in the first super-physical unit that does not have a corresponding array error correction code to obtain the first data when the memory storage device is powered on again and detects an abnormal power outage; The first super entity unit is the last super entity unit to be written with data before the abnormal power failure occurs, and The memory management circuit is further configured to copy the first data to a second super physical unit. Before reading data stored in the first super physical unit that does not have a corresponding array error correction code to obtain the first data, the memory management circuit is further configured to: When the memory storage device is powered on again and detects an abnormal power outage, scanning the first super physical unit to obtain the amount of written data in the first super physical unit; Determining whether the amount of written data is greater than a first threshold; and In response to the amount of written data being no greater than the first threshold, all data stored in the first super physical unit is read to obtain second data, and the second data is copied to the second super physical unit.

11. The memory control circuit unit according to claim 10, wherein: Before reading data stored in the first super physical unit that does not have a corresponding array error correction code to obtain the first data, the memory management circuit is further configured to: In response to the amount of written data being greater than the first threshold, the first data is obtained and copied to the second super physical unit.

12. The memory control circuit unit according to claim 11, wherein: The first threshold value is determined according to the capacity of the first super entity unit.

13. The memory control circuit unit according to claim 11, wherein: The first threshold value is 1 / 3 of the capacity of the first super-entity unit.

14. The memory control circuit unit according to claim 10, wherein: After copying the first data to the second super physical unit, the memory management circuit is further configured to receive a write instruction from the host system and write the data indicated by the write instruction into the second super physical unit following the first data.

15. The memory control circuit unit according to claim 10, wherein: After the operation of copying the first data to the second super physical unit, the memory management circuit is further configured to determine whether the idle time from the last writing to the present in the plurality of super physical units is greater than a preset time, and The memory management circuit is further configured to read data other than the first data in the first super physical unit to obtain third data in response to the idle time being greater than the preset time, and copy the third data to a third super physical unit.

16. The memory control circuit unit according to claim 10, wherein: The memory management circuit is further configured to determine whether the first super entity unit is a first-type entity unit or a second-type entity unit. The memory management circuit is further configured to read the first data and copy the first data to the second super physical unit in response to the first super physical unit being the first type physical unit, and The memory management circuit is further configured to not copy the data stored in the first super physical unit in response to the first super physical unit being the second type physical unit.

17. The memory control circuit unit according to claim 16, wherein: A first total number of physical programming units in the first type of physical units in an erased state is different from a second total number of physical programming units in the second type of physical units in the erased state.

18. The memory control circuit unit according to claim 17, wherein: The first total is non-zero, and the second total is zero.

19. A memory storage device, characterized in that: include: A connection interface unit for coupling to a host system; A rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of super physical units, wherein the super physical unit comprises at least two physical erase units, the at least two physical erase units belong to different operation units, and each of the physical erase units comprises a plurality of physical programming units; and A memory control circuit unit is coupled to the connection interface unit and the rewritable non-volatile memory module. wherein the memory control circuit unit is configured to read data stored in the first super-physical unit that does not have a corresponding array error correction code to obtain the first data when the memory storage device is powered on again and detects an abnormal power failure; The first super entity unit is the last super entity unit to be written with data before the abnormal power failure occurs, and The memory control circuit unit is further configured to copy the first data to the second super physical unit. Before reading data stored in the first super physical unit that does not have a corresponding array error correction code to obtain the first data, the memory control circuit unit is further configured to: When the memory storage device is powered on again and detects an abnormal power outage, scanning the first super physical unit to obtain the amount of written data in the first super physical unit; Determining whether the amount of written data is greater than a first threshold; as well as In response to the amount of written data being no greater than the first threshold, all data stored in the first super physical unit is read to obtain second data, and the second data is copied to the second super physical unit.

20. The memory storage device according to claim 19, wherein Before reading data stored in the first super physical unit that does not have a corresponding array error correction code to obtain the first data, the memory control circuit unit is further configured to: In response to the amount of written data being greater than the first threshold, the first data is obtained and copied to the second super physical unit.

21. The memory storage device according to claim 20, wherein: The first threshold value is determined according to the capacity of the first super entity unit.

22. The memory storage device according to claim 20, wherein: The first threshold value is 1 / 3 of the capacity of the first super-entity unit.

23. The memory storage device according to claim 19, wherein After copying the first data to the second super physical unit, the memory control circuit unit is further configured to receive a write instruction from the host system, and write the data indicated by the write instruction into the second super physical unit following the first data.

24. The memory storage device according to claim 19, wherein After the operation of copying the first data to the second super physical unit, the memory control circuit unit is further used to determine whether the idle time from the last writing to the present in the plurality of super physical units is greater than a preset time, and The memory control circuit unit is further configured to read data other than the first data in the first super physical unit to obtain third data in response to the idle time being greater than the preset time, and copy the third data to a third super physical unit.

25. The memory storage device according to claim 19, wherein The memory control circuit unit is further configured to determine whether the first super entity unit is a first-type entity unit or a second-type entity unit. The memory control circuit unit is further configured to read the first data and copy the first data to the second super physical unit in response to the first super physical unit being the first type physical unit, and The memory control circuit unit is further configured to not copy the data stored in the first super physical unit in response to the first super physical unit being the second type physical unit.

26. The memory storage device according to claim 25, wherein: A first total number of physical programming units in the first type of physical units in an erased state is different from a second total number of physical programming units in the second type of physical units in the erased state.

27. The memory storage device according to claim 26, wherein: The first total is non-zero, and the second total is zero.

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