A method and device for simulating a printed circuit board

Abstract

The present disclosure relates to the technical field of electronic products, and provides a simulation method and device for a printed circuit board. The method comprises: obtaining a design drawing file of a printed circuit board to be inspected, the design drawing file comprising a stacking file and a drilling file; performing area division on the printed circuit board to be inspected according to the stacking file to obtain a first area division result, performing area division on the printed circuit board to be inspected according to the drilling file to obtain a second area division result; determining the first, second and third structural areas of the printed circuit board to be inspected according to the first and second area division results; respectively determining the first, second and third estimated values ​​corresponding to the first, second and third structural areas; performing simulation operations on the first, second and third estimated values ​​to obtain the final simulation result of the printed circuit board to be inspected. The present disclosure not only improves the efficiency of PCB simulation detection, but also improves the effect of PCB simulation detection, and can realize large-scale detection.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic products, and particularly to a simulation method and device for a printed circuit board. Background Art

[0002] A PCB (Printed Circuit Board) is an important electronic component, a support for electronic components, and a carrier for electrical connection of electronic components. In PCB design, PCB layout and wiring are usually involved, and the quality of PCB layout and wiring directly affects the circuit performance of electronic products.

[0003] In order to detect the circuit performance of the entire PCB after layout and wiring, it is usually necessary to perform simulation detection on the entire PCB. However, in the existing PCB simulation detection methods, when performing simulation, complex parameter settings (such as thickness, dielectric constant, port impedance, etc.) still need to be manually set, which is not only cumbersome and time-consuming, but also very likely to have situations such as missing or incorrect parameter settings due to human errors, resulting in low efficiency of simulation detection, poor detection effect, and difficulty in achieving large-scale detection. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a simulation method and device for a printed circuit board to solve the problems of low efficiency, poor effect, and difficulty in achieving large-scale detection in the existing PCB simulation detection.

[0005] In a first aspect of embodiments of the present disclosure, a simulation method for a printed circuit board is provided, including:

[0006] Obtain a design drawing file of the printed circuit board to be inspected, where the design drawing file includes a stack-up file and a drill file;

[0007] Divide the printed circuit board to be inspected according to the stack-up file to obtain a first area division result, and divide the printed circuit board to be inspected according to the drill file to obtain a second area division result;

[0008] Determine a first structural area, a second structural area, and a third structural area of the printed circuit board to be inspected according to the first area division result and the second area division result;

[0009] Input the first structural area, the second structural area, and the third structural area into a preset prediction model for parameter prediction calculation to obtain a first predicted value corresponding to the first structural area, a second predicted value corresponding to the second structural area, and a third predicted value corresponding to the third structural area;

[0010] Perform cascade simulation on the first predicted value, the second predicted value, and the third predicted value to obtain a final simulation result of the printed circuit board to be inspected.

[0011] In a second aspect of the embodiments of the present disclosure, a simulation test device for a printed circuit board is provided, including:

[0012] A file acquisition module, configured to acquire a design drawing file of a printed circuit board to be inspected, where the design drawing file includes a stack-up file and a drilling file;

[0013] A region division module, configured to divide the printed circuit board to be inspected according to the stack-up file to obtain a first region division result, and divide the printed circuit board to be inspected according to the drilling file to obtain a second region division result;

[0014] A region determination module, configured to determine a first structural region, a second structural region, and a third structural region of the printed circuit board to be inspected according to the first region division result and the second region division result;

[0015] A parameter estimation module, configured to input the first structural region, the second structural region, and the third structural region into a preset estimation model for parameter estimation operations, to obtain a first estimated value corresponding to the first structural region, a second estimated value corresponding to the second structural region, and a third estimated value corresponding to the third structural region;

[0016] A simulation operation module, configured to perform cascade simulation on the first estimated value, the second estimated value, and the third estimated value to obtain a final simulation result of the printed circuit board to be inspected.

[0017] In a third aspect of the embodiments of the present disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the above method when executing the computer program.

[0018] In a fourth aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, where the computer-readable storage medium stores a computer program, and the computer program implements the steps of the above method when executed by a processor.

[0019] Compared with the prior art, the beneficial effects of the embodiments of the present disclosure at least include: By obtaining the design drawing file of the printed circuit board to be inspected, the design drawing file includes a stack-up file and a drilling file; dividing the printed circuit board to be inspected according to the stack-up file to obtain a first area division result, and dividing the printed circuit board to be inspected according to the drilling file to obtain a second area division result; determining the first structural area, the second structural area and the third structural area of the printed circuit board to be inspected according to the first area division result and the second area division result; inputting the first structural area, the second structural area and the third structural area into a preset prediction model for parameter prediction calculation to obtain a first predicted value corresponding to the first structural area, a second predicted value corresponding to the second structural area, and a third predicted value corresponding to the third structural area; performing cascade simulation on the first predicted value, the second predicted value and the third predicted value to obtain the final simulation result of the printed circuit board to be inspected. The entire detection process does not require manual setting of a large number of simulation parameters, greatly improving the efficiency of PCB simulation detection; at the same time, it can also effectively reduce the missed detection rate and false detection rate that may occur during the simulation detection process, improving the effect of PCB simulation detection; and large-scale detection can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings in the following descriptions are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 is a schematic flowchart of a method for simulating a printed circuit board provided by an embodiment of the present disclosure;

[0022] Figure 2 is a schematic structural diagram of a device for simulating a printed circuit board provided by an embodiment of the present disclosure;

[0023] Figure 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present disclosure. However, those skilled in the art should clearly understand that the present disclosure can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present disclosure.

[0025] The following will describe in detail a simulation method and apparatus for a printed circuit board according to an embodiment of the present disclosure with reference to the accompanying drawings.

[0026] Figure 1 It is a schematic flowchart of a simulation method for a printed circuit board provided by an embodiment of the present disclosure. As Figure 1 shown, the simulation method for the printed circuit board includes:

[0027] Step S101, obtain the design drawing file of the printed circuit board to be inspected, where the design drawing file includes a stack-up file and a drill file.

[0028] Among them, the design drawing file of the printed circuit board to be inspected is the design drawing file of the entire board PCB that has completed layout and routing, that is, the PCB LAYOUT (printed circuit board layout and routing) design drawing.

[0029] In one embodiment, the relevant design drawing file can be obtained by exporting a picture of the printed circuit board after layout and routing.

[0030] The printed circuit board to be printed can be a single-layer board, a double-layer board, or a multi-layer board. The stack-up file includes the surface information of each layer of the printed circuit board to be printed. For example, if the printed circuit board to be printed is an 8-layer board, then its stack-up file includes the surface information of the 8-layer board. The surface information includes, but is not limited to, the material type of each layer, copper foil distribution, cut-out area, green oil coverage rate, trace line width, line spacing, and stack-up information above and below the trace (whether there is a cut-out area between adjacent layers), etc.

[0031] In one embodiment, some of the above surface information (such as copper foil distribution, cut-out area, green oil coverage rate, trace line width, line spacing) can be obtained by scanning and measuring the surface of each layer of the PCB. And some other surface information can be obtained by reading the relevant design data of the printed circuit board to be inspected stored in advance. In practical applications, during the process of designing the PCB, some surface information of the PCB (such as material type, stack-up information above and below the trace, etc.) can be bound and stored with the printed circuit board to be inspected for subsequent retrieval and use.

[0032] The drill file mainly includes the relevant data of the drills on each layer marked on the PCB. The relevant data includes the aperture of the drill, the shape of the hole, the hole processing process (for example, the process of plugging the via hole, etc.).

[0033] Step S102, divide the printed circuit board to be inspected according to the stack-up file to obtain a first area division result, and divide the printed circuit board to be inspected according to the drill file to obtain a second area division result.

[0034] Generally, various components (such as clock generators, crystal oscillators, microcontrollers, ROM chips, RAM chips, etc.) are layout-designed on the printed circuit board to be inspected, and each component is connected through power lines, data lines, and ground lines according to its functional requirements, etc., to form the entire PCB.

[0035] In practical applications, the entire PCB can be divided into an electrical signal flow-through area and other areas (i.e., areas where electrical signals do not flow through) according to the flow direction of electrical signals. The electrical signal flow-through area usually includes some key components and their connecting lines (such as power lines, data lines, ground lines, etc.). The quality of the layout and wiring design of the electrical signal flow-through area is the key to the overall circuit performance of the PCB. Therefore, the electrical signal flow-through area is the key area of focus for simulation and detection. Dividing the printed circuit board to be inspected according to the stack-up file and drill file mainly involves dividing the electrical signal flow-through area.

[0036] Step S103, determine the first structural area, the second structural area, and the third structural area of the printed circuit board to be inspected according to the first area division result and the second area division result.

[0037] The first structural area, the second structural area, and the third structural area respectively refer to the special structural area, the high-risk structural area, and the general structural area in each layer of the PCB. Among them, the special structural area refers to an area that contains some special structures (such as special holes, that is, holes that exist in one layer but not in other layers, and it can be determined whether there are special holes by judging whether the area contains a hollowed-out area), or is a split ground plane, or an area covered with solder mask on the surface. The high-risk structural area refers to an area that satisfies multiple special factors. For example, if an area contains special holes, is a split ground plane, and is covered with solder mask on the surface at the same time, then this area can be determined as a high-risk area. The general structural area refers to other electrical signal flow-through areas except the above-mentioned special structural areas and high-risk structural areas.

[0038] Step S104, input the first structural area, the second structural area, and the third structural area into a preset estimation model to perform parameter estimation operations, and obtain a first estimated value corresponding to the first structural area, a second estimated value corresponding to the second structural area, and a third estimated value corresponding to the third structural area.

[0039] Among them, the scattering parameters, that is, S parameters, include but are not limited to characteristic impedance, insertion loss, and return loss.

[0040] In an embodiment, an S parameter estimation model (i.e., the preset estimation model) trained by a deep learning neural network (such as a generative adversarial network) can be used to perform parameter estimation operations (i.e., scattering parameter estimation operations) on the first structural area, the second structural area, and the third structural area respectively, to obtain the first estimated value, the second estimated value, and the third estimated value.

[0041] In another embodiment, simulation software (such as finite element analysis software, ANSYS) can also be used to perform parameter prediction operations on the first structural region, the second structural region, and the third structural region respectively, to obtain a first predicted value, a second predicted value, and a third predicted value.

[0042] Step S105: Perform cascade simulation on the first predicted value, the second predicted value, and the third predicted value to obtain the final simulation result of the printed circuit board to be inspected.

[0043] In one embodiment, simulation software (such as finite element analysis software, ANSYS) can be used to perform cascade simulation on the first predicted value, the second predicted value, and the third predicted value to obtain a total parameter prediction operation value, that is, to obtain the final simulation result of the printed circuit board to be inspected. The technical solution provided by the embodiments of the present disclosure does not require manual input of a large number of simulation parameters during the entire detection process of simulating and detecting the printed circuit board to be inspected, and can achieve no need for manual operation of the simulation software, greatly improving the efficiency of PCB simulation detection; at the same time, it can also well solve the simulation errors and omissions caused by reasons such as the negligence or lack of experience of the operator in the traditional simulation method, effectively reducing the missed detection and false detection rates that may occur during the simulation detection process, improving the effect of PCB simulation detection, especially greatly improving the accuracy and efficiency of simulating a PCB with a special structure; and it can achieve large-scale detection and save labor costs.

[0044] In some embodiments, the above step S102 specifically includes:

[0045] Obtain the electrical signal flow direction information of the printed circuit board to be inspected;

[0046] Determine the electrical signal flowing through area of the printed circuit board to be inspected according to the electrical signal flow direction information;

[0047] Classify the electrical signal flowing through area according to the stack-up file to obtain a first area division result;

[0048] Classify the electrical signal flowing through area according to the drill file to obtain a second area division result.

[0049] The electrical signal flow direction information refers to the specific flow direction of the electrical signal of the printed circuit board to be inspected, that is, the entire flow path of the electrical signal starting from which component of the printed circuit board to be inspected, flowing through which lines, and reaching which components. For example, if the electrical signal a on the printed circuit board to be inspected flows through components A→B→C→D→E, then the electrical signal flow direction information is that the flow direction of the electrical signal a is A→B→C→D→E.

[0050] In one embodiment, in combination with the above example, according to the above electrical signal flow information: the flow direction of electrical signal a is A→B→C→D→E, the components and trace areas of A→B→C→D→E through which electrical signal a flows can be determined as the electrical signal flow areas of the printed circuit board to be inspected.

[0051] Next, classify the areas where the electrical signal flows through A→B→C→D→E according to the stack-up file of the printed circuit board to be inspected to obtain the first area division result. Classify the areas where the electrical signal flows through A→B→C→D→E according to the drill file of the printed circuit board to be inspected to obtain the second area division result.

[0052] Among them, the first area division result includes multiple first division factors and the first parameter values corresponding to each first division factor; the second area division result includes multiple second division factors and the second parameter values corresponding to each second division factor. The multiple first division factors can specifically be copper foil distribution (i.e., the copper coating distribution on the PCB), cut-out areas, solder mask coverage rate (liquid photoimageable solder mask (commonly known as solder mask)), trace line width (such as the width of the conductor), and line spacing (such as the spacing between adjacent conductors).

[0053] In this embodiment, according to the first area division result and the second area division result, determining the first structural area, the second structural area, and the third structural area of the printed circuit board to be inspected includes:

[0054] Count the first quantity of the first division factors that meet the first preset condition and the second quantity of the second division factors that meet the second preset condition in each area of the electrical signal flow area;

[0055] Determine the first structural area, the second structural area, and the third structural area of the printed circuit board to be inspected according to the first quantity and the second quantity.

[0056] Before counting the above first quantity and second quantity, it also includes: judging whether each first division factor meets the first preset condition according to the first parameter value of each first division factor and its corresponding first predicted parameter standard;

[0057] Judging whether each second division factor meets the second preset condition according to the second parameter value of each second division factor and its corresponding second predicted parameter standard.

[0058] Among them, the first preset condition can be a judgment condition for determining whether the first parameter value of the first division factor is within a preset standard value range or meets the requirements of a preset technical standard. Meeting the first preset condition means that the first parameter value of the first division factor is within the preset standard value range or meets the requirements of the preset technical standard. For example, the first division factor K is the copper foil distribution, and its first parameter value is 15%. The first preset condition is whether the copper foil distribution rate is within the range of 10% to 20%. Thus, it can be determined that the first division factor K meets the first preset condition. In this example, the copper foil distribution rate within the range of 10% to 20% is the first prediction parameter standard corresponding to the first division factor K.

[0059] The second preset condition can be a judgment condition for determining whether the second parameter value of the second division factor is within a preset standard value range or meets the requirements of a preset technical standard. Meeting the second preset condition means that the second parameter value of the second division factor is within the preset standard value range or meets the requirements of the preset technical standard. For example, the second division factor W is the aperture, and its second parameter value is 0.3 mm. The second preset condition is whether the aperture is within the range of 0.2 mm to 0.5 mm. Thus, it can be determined that the second division factor W meets the second preset condition. In this example, the aperture within the range of 0.2 mm to 0.5 mm is the second prediction parameter standard corresponding to the second division factor W.

[0060] As an example, assume that the printed circuit board to be inspected is a three-layer board, and the three layers can be numbered as board layers 01, 02, and 03 respectively. Then its stack-up file includes the surface information of board layers 01, 02, and 03. Among them, the surface information includes multiple first division factors and multiple second division factors. Among them, the multiple first division factors include copper foil distribution, cut-out area, solder mask coverage, trace line width, and line spacing; the multiple second division factors include the aperture of the drilled hole, the shape of the hole, and the hole processing technology. If the regions through which the electrical signals of the printed circuit board to be inspected flow include a total of five regions A, B, C, D, and E, then the first quantity of the first division factors that meet the first preset condition in each region of the regions through which the electrical signals of the printed circuit board to be inspected flow can be counted. For example, if the region contains one first division factor that meets the first preset condition, its first quantity is 1; if it contains two first division factors that meet the first preset condition, its first quantity is 2. At the same time, the second quantity of the second division factors that meet the second preset condition in each region of the regions through which the electrical signals of the printed circuit board to be inspected flow is counted. For example, if the region contains one second division factor that meets the second preset condition, its second quantity is 1; if it contains two second division factors that meet the second preset condition, its second quantity is 2.

[0061] Exemplarily, assume that after the above steps of statistics, the division factor quantity distribution statistical table shown in Table 1 below is obtained.

[0062] Table 1 Statistical Table of the Number Distribution of Partition Factors

[0063]

[0064] In some embodiments, determining the first structural region, the second structural region, and the third structural region of the printed circuit board to be inspected according to the first quantity and the second quantity includes:

[0065] Determining the region where the first quantity is 1 and the second quantity is 0, or the region where the first quantity is 0 and the second quantity is 1, as the first structural region;

[0066] Determining the region where the first quantity ≥ 3, or the second quantity ≥ 3, or the first quantity ≥ 1 and the second quantity ≥ 1, as the second structural region;

[0067] Determining the third structural region according to the region where the electric signal flows through, the first structural region, and the second structural region.

[0068] Combined with the statistical results of Table 1 in the above example, it can be seen that region B only contains one first partition factor that meets the first preset condition, that is, the first quantity is 1, and it can be determined as the first structural region, that is, the special structural region; region A contains 2 first partition factors that meet the first preset condition and 1 second partition factor that meets the second preset condition, that is, the first quantity ≥ 1 and the second quantity ≥ 1, and it can be determined as the second structural region, that is, the high-risk structural region; region C contains 3 second partition factors that meet the second preset condition, that is, the second quantity ≥ 3, and it can be determined as the second structural region, that is, the high-risk structural region; region D contains 4 first partition factors that meet the first preset condition and 1 second partition factor that meets the second preset condition, that is, the first quantity ≥ 1 and the second quantity ≥ 1, and it can be determined as the second structural region, that is, the high-risk structural region; the first quantity and the second quantity of region E are both 0, and it can be determined as the third structural region.

[0069] In one example, after determining the total number of regions where the electric signal flows through, and the first structural region and the second structural region, determining the region in the regions where the electric signal flows through except for the first structural region and the second structural region as the third structural region.

[0070] In some embodiments, the above step S105 includes:

[0071] Performing a cascaded operation on the first predicted value, the second predicted value, and the third predicted value to obtain a topological circuit structure diagram;

[0072] Analyzing the topological circuit structure diagram to obtain the signal flow information of the topological circuit structure diagram;

[0073] The first estimated value, the second estimated value and the third estimated value are integrated and simulated according to the signal flow information to obtain the final simulation result of the printed circuit board to be tested.

[0074] In this embodiment, the s-parameter cascade algorithm provided by the simulation software ANSYS can be used to perform cascade operations on the first estimated value, the second estimated value, and the third estimated value obtained in the above steps to obtain a topological circuit structure diagram of the printed circuit board to be tested. In this way, the signal flow information of the topological circuit structure diagram, that is, the specific flow direction of the electrical signal, can be obtained. After that, the specific flow direction of the electrical signal in the topological circuit structure diagram is analyzed, and the first estimated value, the second estimated value, and the third estimated value are integrated and simulated to obtain an integrated scattering parameter estimated value, that is, the final simulation result of the printed circuit board to be tested.

[0075] In some embodiments, the final simulation result can be further compared with a preset standard value to obtain a comparison result; and the circuit performance level of the printed circuit board to be tested is determined according to the comparison result.

[0076] Specifically, by comparing the final simulation result with the preset standard value, it is determined whether the final simulation result is within the allowable error range, thereby determining which level the circuit performance of the printed circuit board to be inspected belongs to. Among them, the circuit performance level can be flexibly set according to actual needs, for example, it can be set to include two levels: qualified and unqualified.

[0077] Generally speaking, if the error range between the final simulation result and the preset standard value is within the range of 3% to 5%, it can be determined that the circuit performance of the printed circuit board to be tested is of qualified level.

[0078] All the above optional technical solutions can be combined in any way to form optional embodiments of the present application, and will not be described in detail here.

[0079] The following is an embodiment of the device disclosed herein, which can be used to execute the method embodiment of the present disclosure. For details not disclosed in the device embodiment of the present disclosure, please refer to the method embodiment of the present disclosure.

[0080] Figure 2 is a schematic diagram of a simulation test device for a printed circuit board provided by an embodiment of the present disclosure. Figure 2 As shown, the simulation test device of the printed circuit board includes:

[0081] File acquisition module 201 is configured to acquire the design drawing file of the printed circuit board to be inspected, the design drawing file includes a stacking file and a drilling file;

[0082] ​The region division module 202 is configured to divide the printed circuit board to be inspected according to the stack-up file to obtain a first region division result, and divide the printed circuit board to be inspected according to the drill file to obtain a second region division result;

[0083] The region determination module 203 is configured to determine a first structural region, a second structural region, and a third structural region of the printed circuit board to be inspected according to the first region division result and the second region division result;

[0084] The parameter estimation module 204 is configured to input the first structural region, the second structural region, and the third structural region into a preset estimation model to perform parameter estimation operations, and obtain a first estimated value corresponding to the first structural region, a second estimated value corresponding to the second structural region, and a third estimated value corresponding to the third structural region;

[0085] The simulation operation module 205 is configured to perform cascade simulation on the first estimated value, the second estimated value, and the third estimated value to obtain a final simulation result of the printed circuit board to be inspected.

[0086] The technical solution provided by the embodiments of the present disclosure obtains the design drawing file of the printed circuit board to be inspected through the file acquisition module 201, and the design drawing file includes a stack-up file and a drill file; the region division module 202 divides the printed circuit board to be inspected according to the stack-up file to obtain a first region division result, and divides the printed circuit board to be inspected according to the drill file to obtain a second region division result; the region determination module 203 determines a first structural region, a second structural region, and a third structural region of the printed circuit board to be inspected according to the first region division result and the second region division result; the parameter estimation module 204 inputs the first structural region, the second structural region, and the third structural region into a preset estimation model to perform parameter estimation operations, and obtains a first estimated value corresponding to the first structural region, a second estimated value corresponding to the second structural region, and a third estimated value corresponding to the third structural region; the simulation operation module 205 performs cascade simulation on the first estimated value, the second estimated value, and the third estimated value to obtain a final simulation result of the printed circuit board to be inspected. The entire detection process does not require manual input of a large number of simulation parameters, greatly improving the efficiency of PCB simulation detection; at the same time, it can also effectively reduce the missed detection rate and false detection rate that may occur during the simulation detection process, improving the effect of PCB simulation detection; and it can achieve large-scale detection.

[0087] In some embodiments, the above-mentioned region division module 202 includes:

[0088] The information acquisition unit is configured to acquire the electrical signal flow information of the printed circuit board to be inspected;

[0089] A signal flow region determination unit, configured to determine the signal flow region of the printed circuit board to be inspected according to the electrical signal flow direction information;

[0090] A first classification unit, configured to classify the signal flow region according to the stack-up file to obtain a first region division result;

[0091] A second classification unit, configured to classify the signal flow region according to the drill file to obtain a second region division result.

[0092] In some embodiments, the above first region division result includes a plurality of first division factors and a first parameter value corresponding to each first division factor; the second region division result includes a plurality of second division factors and a second parameter value corresponding to each second division factor.

[0093] In this embodiment, the above region determination module 203 includes:

[0094] A statistics unit, configured to count the first quantity of the first division factors in each region of the signal flow region that meet the first preset condition, and the second quantity of the second division factors that meet the second preset condition;

[0095] A determination unit, configured to determine the first structural region, the second structural region, and the third structural region of the printed circuit board to be inspected according to the first quantity and the second quantity.

[0096] In some embodiments, the above region determination module 203 further includes:

[0097] A first judgment unit, configured to judge whether each first division factor meets the first preset condition according to the first parameter value of each first division factor and its corresponding first predicted parameter standard;

[0098] A second judgment unit, configured to judge whether each second division factor meets the second preset condition according to the second parameter value of each second division factor and its corresponding second predicted parameter standard.

[0099] In some embodiments, the above determination unit can be specifically configured to:

[0100] Determine the region where the first quantity is 1 and the second quantity is 0, or the first quantity is 0 and the second quantity is 1 as the first structural region;

[0101] Determine the region where the first quantity ≥ 3, or the second quantity ≥ 3, or the first quantity ≥ 1 and the second quantity ≥ 1 as the second structural region;

[0102] Determine the third structural region according to the signal flow region, the first structural region, and the second structural region.

[0103] In some embodiments, the above-mentioned simulation operation module 205 includes:

[0104] A cascading unit configured to perform a cascading operation on a first predicted value, a second predicted value, and a third predicted value to obtain a topological circuit structure diagram;

[0105] An analysis unit configured to analyze the topological circuit structure diagram to obtain signal flow information of the topological circuit structure diagram;

[0106] A simulation unit configured to perform an integration and simulation operation on the first predicted value, the second predicted value, and the third predicted value according to the signal flow information to obtain a final simulation result of the printed circuit board to be inspected.

[0107] In some embodiments, the above-mentioned device further includes:

[0108] A comparison module configured to compare the final simulation result with a preset standard value to obtain a comparison result;

[0109] A level determination module configured to determine the circuit performance level of the printed circuit board to be inspected according to the comparison result.

[0110] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not mean the order of execution is prior or posterior. The execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure.

[0111] Figure 3 is a schematic diagram of the electronic device 300 provided by the embodiment of the present disclosure. As Figure 3 shown, the electronic device 300 of this embodiment includes: a processor 301, a memory 302, and a computer program 303 stored in the memory 302 and executable on the processor 301. When the processor 301 executes the computer program 303, the steps in the above-mentioned various method embodiments are implemented. Alternatively, when the processor 301 executes the computer program 303, the functions of each module / unit in the above-mentioned various device embodiments are implemented.

[0112] Exemplarily, the computer program 303 can be divided into one or more modules / units. One or more modules / units are stored in the memory 302 and executed by the processor 301 to complete the present disclosure. One or more modules / units can be a series of computer program instruction segments capable of performing specific functions, and these instruction segments are used to describe the execution process of the computer program 303 in the electronic device 300.

[0113] The electronic device 300 can be a desktop computer, a notebook, a palm computer, a cloud server, and other electronic devices. The electronic device 300 can include, but is not limited to, the processor 301 and the memory 302. Those skilled in the art can understand,Figure 3 This is only an example of the electronic device 300, which does not constitute a limitation on the electronic device 300. It may include more or fewer components than those shown in the figure, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0114] The processor 301 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0115] The memory 302 may be an internal storage unit of the electronic device 300. For example, the hard disk or memory of the electronic device 300. The memory 302 may also be an external storage device of the electronic device 300. For example, the plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc. equipped on the electronic device 300. Further, the memory 302 may also include both the internal storage unit and the external storage device of the electronic device 300. The memory 302 is used to store computer programs and other programs and data required by the electronic device. The memory 302 may also be used to temporarily store the data that has been output or will be output.

[0116] Those skilled in the art can clearly understand that, for the convenience and conciseness of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiments can be integrated into a processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0117] In the above embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0118] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or by a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this disclosure.

[0119] In the embodiments provided in this disclosure, it should be understood that the disclosed device / electronic device and method can be implemented in other ways. For example, the device / electronic device embodiments described above are only illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there can be other division methods. Multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection to each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in electrical, mechanical or other forms.

[0120] The unit described as a separated component may or may not be physically separated, and the component displayed as a unit may or may not be a physical unit, that is, it can be located in one place, or can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0121] In addition, in each of the embodiments of the present disclosure, each functional unit may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0122] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such an understanding, all or part of the processes in the above-mentioned method embodiments of the present disclosure can also be completed by driving related hardware through a computer program. The computer program may be stored in the computer-readable storage medium. When the computer program is executed by a processor, the steps of the above-mentioned method embodiments can be implemented. The computer program may include computer program code, and the computer program code may be in the form of source code, object code, executable file, or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc. It should be noted that the content included in the computer-readable medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0123] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should all be included in the protection scope of the present disclosure.

Claims

1. A method for simulating a printed circuit board, characterized in that: include: Obtaining a design drawing file of a printed circuit board to be inspected, wherein the design drawing file includes a stacking file and a drilling file; Divide the printed circuit board to be inspected into regions according to the stacking file to obtain a first region division result, and divide the printed circuit board to be inspected into regions according to the drilling file to obtain a second region division result; The first area division result includes a plurality of first division factors and a first parameter value corresponding to each of the first division factors; The second area division result includes a plurality of second division factors and a second parameter value corresponding to each of the second division factors; Determine a first structural area, a second structural area, and a third structural area of ​​the printed circuit board to be inspected according to the first area division result and the second area division result; Inputting the first structural region, the second structural region and the third structural region into a preset estimation model to perform a scattering parameter estimation operation to obtain a first estimation value corresponding to the first structural region, a second estimation value corresponding to the second structural region, and a third estimation value corresponding to the third structural region; wherein the scattering parameters include but are not limited to characteristic impedance, insertion loss, and return loss; Performing cascade simulation on the first estimated value, the second estimated value, and the third estimated value to obtain a final simulation result of the printed circuit board to be inspected; Dividing the printed circuit board to be inspected into regions according to the stacking file to obtain a first region division result, and dividing the printed circuit board to be inspected into regions according to the drilling file to obtain a second region division result, including: Acquiring electrical signal flow direction information of the printed circuit board to be inspected; Determining the area where the electrical signal of the printed circuit board to be inspected flows according to the electrical signal flow direction information; Classifying the area through which the electrical signal flows according to the stack file to obtain a first area division result; Classifying the area through which the electrical signal flows according to the drilling file to obtain a second area division result; Determining the first structural area, the second structural area, and the third structural area of ​​the printed circuit board to be inspected according to the first area division result and the second area division result, comprising: Counting a first number of first division factors that meet a first preset condition and a second number of second division factors that meet a second preset condition for each area in which the electrical signal flows; According to the first quantity and the second quantity, a first structural area, a second structural area and a third structural area of ​​the printed circuit board to be inspected are determined.

2. The method according to claim 1, characterized in that Before counting the first number of first division factors that meet the first preset condition and the second number of second division factors that meet the second preset condition in each area where the electrical signal flows through, the method further includes: Determining whether a first preset condition is met according to a first parameter value of each of the first division factors and a first prediction parameter standard corresponding thereto; According to the second parameter value of each of the second division factors and its corresponding second prediction parameter standard, it is determined whether it meets the second preset condition.

3. The method according to claim 2, characterized in that Determining a first structural area, a second structural area, and a third structural area of ​​the printed circuit board to be inspected according to the first quantity and the second quantity includes: Determine a region where the first quantity is 1 and the second quantity is 0, or where the first quantity is 0 and the second quantity is 1, as a first structural region; Determine a region where the first number is ≥3, or the second number is ≥3, or the first number is ≥1 and the second number is ≥1 as a second structural region; A third structural region is determined according to the region through which the electrical signal flows, the first structural region, and the second structural region.

4. The method according to claim 1, characterized in that: Performing cascade simulation on the first estimated value, the second estimated value, and the third estimated value to obtain a final simulation result of the printed circuit board to be inspected, including: Performing cascade simulation on the first estimated value, the second estimated value, and the third estimated value to obtain a topological circuit structure diagram of the printed circuit board to be inspected; Analyzing the topological circuit structure diagram to obtain signal flow information of the topological circuit structure diagram; The first estimated value, the second estimated value and the third estimated value are cascade simulated according to the signal flow direction information to obtain a final simulation result of the printed circuit board to be inspected.

5. The method according to claim 1, characterized in that After performing cascade simulation on the first estimated value, the second estimated value and the third estimated value to obtain a final simulation result of the printed circuit board to be inspected, the method further includes: Comparing the final simulation result with a preset standard value to obtain a comparison result; The circuit performance level of the printed circuit board to be inspected is determined according to the comparison result.

6. A simulation test device for a printed circuit board, characterized in that: include: A file acquisition module is configured to acquire a design drawing file of the printed circuit board to be inspected, wherein the design drawing file includes a stacking file and a drilling file; A region division module is configured to divide the printed circuit board to be inspected into regions according to the stacking file to obtain a first region division result, and divide the printed circuit board to be inspected into regions according to the drilling file to obtain a second region division result; The first area division result includes a plurality of first division factors and a first parameter value corresponding to each of the first division factors; The second area division result includes a plurality of second division factors and a second parameter value corresponding to each of the second division factors; An area determination module is configured to determine a first structural area, a second structural area, and a third structural area of ​​the printed circuit board to be inspected according to the first area division result and the second area division result; A parameter estimation module is configured to input the first structural area, the second structural area and the third structural area into a preset estimation model to perform a scattering parameter estimation operation to obtain a first estimation value corresponding to the first structural area, a second estimation value corresponding to the second structural area, and a third estimation value corresponding to the third structural area; wherein the scattering parameters include but are not limited to characteristic impedance, insertion loss, and return loss; A simulation operation module is configured to perform cascade simulation on the first estimated value, the second estimated value and the third estimated value to obtain a final simulation result of the printed circuit board to be inspected; Dividing the printed circuit board to be inspected into regions according to the stacking file to obtain a first region division result, and dividing the printed circuit board to be inspected into regions according to the drilling file to obtain a second region division result, including: Acquiring electrical signal flow direction information of the printed circuit board to be inspected; Determining the area where the electrical signal of the printed circuit board to be inspected flows according to the electrical signal flow direction information; Classifying the area through which the electrical signal flows according to the stack file to obtain a first area division result; Classifying the area through which the electrical signal flows according to the drilling file to obtain a second area division result; Determining the first structural area, the second structural area, and the third structural area of ​​the printed circuit board to be inspected according to the first area division result and the second area division result, comprising: Counting a first number of first division factors that meet a first preset condition and a second number of second division factors that meet a second preset condition for each area in which the electrical signal flows; According to the first quantity and the second quantity, a first structural area, a second structural area and a third structural area of ​​the printed circuit board to be inspected are determined.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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