Unmapping operation techniques

Abstract

This application relates to unmap operation techniques. A memory system can include volatile memory devices and non-volatile memory devices. The memory system can receive a set of unmap commands, each unmap command including a logical block address associated with unused data. The memory system can determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system can select a first program for executing the set of unmap commands that is different from a second program (e.g., a default program) used to execute the set of unmap commands, and can execute the set of unmap commands using the first program. If the one or more parameters do not satisfy the threshold, the memory system can execute the set of unmap commands using the second program.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 122,174, entitled “Unmap Operation Techniques,” filed December 15, 2020, by Cariello et al., which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves techniques for canceling mapping operations. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to support one of two states, typically corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, either of which can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device to corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0006] Describe an apparatus. The apparatus may include: a memory system comprising volatile memory devices and non-volatile memory devices; and a controller coupled to the memory system and operable to cause the apparatus to: receive a plurality of unmapping commands, each of the plurality of unmapping commands including a logical block address associated with unused data; determine whether one or more parameters associated with the plurality of unmapping commands satisfy a threshold; select a first program for executing the plurality of unmapping commands, the first program being different from a second program for executing the plurality of unmapping commands, based at least in part on the determination that the one or more parameters satisfy the threshold; and execute the plurality of unmapping commands using the first program.

[0007] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive a plurality of unmapping commands, each of the plurality of unmapping commands including a logical block address associated with unused data; determine whether one or more parameters associated with the plurality of unmapping commands satisfy a threshold; select a first program for executing the plurality of unmapping commands, the first program being different from a second program for executing the plurality of unmapping commands, based at least in part on the determination that the one or more parameters satisfy the threshold; and execute the plurality of unmapping commands using the first program.

[0008] A method executed by a memory system is described. The method may include: receiving a plurality of unmapping commands, each of the plurality of unmapping commands including a logical block address associated with unused data; determining whether one or more parameters associated with the plurality of unmapping commands satisfy the threshold; selecting a first program for executing the plurality of unmapping commands, the first program being different from a second program for executing the plurality of unmapping commands, based at least in part on the determination that the one or more parameters satisfy the threshold; and executing the plurality of unmapping commands using the first program. Attached Figure Description

[0009] Figure 1 This document describes examples of systems that support unmapping operations, based on the examples disclosed herein.

[0010] Figure 2 This document describes an example of a process flow that supports unmapping operations, based on the examples disclosed herein.

[0011] Figure 3 This document describes an example of a process flow that supports unmapping operations, based on the examples disclosed herein.

[0012] Figure 4 A block diagram of a memory system supporting unmapping operation techniques based on the examples disclosed herein is shown.

[0013] Figure 5 The flowchart illustrates one or more methods that support unmapping operation techniques based on the examples disclosed herein. Detailed Implementation

[0014] A memory device in a memory system stores data at corresponding physical addresses, where a physical address identifies the physical location of a corresponding memory cell within the memory device. The physical location of data within the memory device may change over time due to factors such as the memory device accommodating additional data writes, maintenance operations performed by the memory device (e.g., waste cell collection), or for any other reason. A host system coupled to the memory system may use logical addresses (e.g., logical block addresses (LBAs), virtual addresses, system addresses, or other logical addresses) to reference data (e.g., if read, write, or other commands associated with the data are issued), and the memory device can generate and maintain a mapping between the logical addresses associated with the data and the physical addresses of the memory cells storing the data, a mapping that allows the memory device to change physical addresses over time.

[0015] A host system can use unmapping commands to release storage space allocated to or used to store unused data in memory devices. For example, the host system can issue (e.g., send) an unmapping command to the memory system, the unmapping command containing an LBA associated with the unused data. In response to receiving the unmapping command, the memory system can update the mapping between the LBA and the physical address of the unused data to indicate that the LBA is unassociated with the physical address. Additionally, the memory system can update a second mapping to indicate that the data stored at the physical address is invalid (e.g., unused). In some cases, the host system may issue a large number of unmapping commands to the memory system within a relatively short period. To execute such a large number of unmapping commands, the memory system may load and unload corresponding mappings of volatile memory devices in the memory system to update the mappings. Due to loading and unloading these mappings, some procedures used to execute the unmapping commands can increase the latency and power consumption of the memory system (e.g., in some cases, the loading and unloading may be unnecessary). Therefore, it may be necessary to improve the technology used to execute the unmapping commands.

[0016] This document describes techniques, systems, and apparatuses for improving the performance of unmapping commands by using a boosting procedure. For example, a host system may issue a set of unmapping commands, each containing LBAs associated with unused data, to a memory system coupled to the host system. The memory system may determine that one or more parameters associated with the set of unmapping commands (e.g., queue depth, data pattern, asymptotic order of LBAs, amount of unmapping commands, or some other parameter) satisfy one or more thresholds. The memory system may select a procedure for executing the set of unmapping commands based on the one or more parameters satisfying the one or more thresholds. For example, if the one or more parameters satisfy the associated thresholds, the memory system may select a boosting procedure for executing the set of unmapping commands, and the boosting procedure may be used to execute the set of unmapping commands. In some cases, the boosting procedure may include a process of grouping changes to some tables (e.g., invalid tables) to increase the number of changes that occur after the tables are loaded from a non-volatile memory device to a volatile memory device. Such techniques can reduce the amount of table transfers between volatile and non-volatile memory devices, thereby reducing the latency of executing the set of unmapping commands. The boosting procedure can be a different program from the default program used to execute the set of unmapping commands, which can reduce latency and power consumption and increase memory system performance associated with executing the unmapping commands, as described herein.

[0017] Firstly, in reference Figure 1 The features of this disclosure are described in the context of the system described. (See references...) Figure 2-3 The features of this disclosure are described within the context of the process flow. These and other features of this disclosure are further illustrated and described with reference to device diagrams and flowcharts, which relate to... Figure 4-5 The described unmapping operation technique.

[0018] Figure 1 This is an example of a system 100 that supports unmapping operations based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form-factor DIMM (SO-DIMM), or a Non-volatile DIMM (NVDIMM), and other possibilities.

[0020] The computing system 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., an airplane, drone, train, car or other means of transportation), device with Internet of Things (IoT) capabilities, embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment or networked commercial device), or any other computing device that includes memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an instance of a control component configured to cause the host system 105 to perform various operations according to the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110 to, for example, write data to and read data from the memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, in the case where the memory system 110 contains more than one memory device 130, the different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. Furthermore, in some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise associated with a command from the host system 105). For example, the memory system controller 115 may translate responses associated with the memory device 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, unused cell collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, a dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include random access memory (RAM) or other memory, such as static random access memory (SRAM), which can be used by the memory system controller 115 for, for example, internal storage or computation related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, if data is read from or written to memory device 130, data may be stored in local memory 120 and may be available in local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0028] although Figure 1 The example of memory system 110 described herein includes memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive RAM (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some instances, memory device 130 may include local controllers 135 (e.g., on the same die or within the same package), which may operate on one or more memory cells of memory device 130. Local controllers 135 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as a multi-level cell (MLC) when configured to store two bits of information, a three-level cell (TLC) when configured to store three bits of information, a four-level cell (TLC) when configured to store four bits of information, or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, may involve narrower read or write tolerances or greater complexity to support the circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, concurrent operations may occur within different planes 165. For example, concurrent operations can be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., regarding command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized in rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but may be erased at a second-level granularity (e.g., at the block level). That is, page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they are rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0036] In some cases, to update some data within block 170 while retaining other data within block 170, memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages 175 of the new block 170. Memory device 130 (e.g., local controller 135) or memory system controller 115 may mark or otherwise represent data held in the old block 170 as invalid or obsolete and update the logical-to-physical (L2P) mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170 rather than the old invalid block 170. In some cases, such copying and remapping may be used instead of erasing and rewriting the entire old block 170, for example, due to latency or attrition considerations. In some cases, one or more copies of the L2P mapping table may be stored within memory cells of memory device 130 (e.g., within one or more blocks 170 or planes 165) for use by local controller 135 or memory system controller 115 (e.g., for reference and updating).

[0037] In some cases, an L2P table can be maintained, and data can be marked as valid or invalid at the page level, and page 175 may contain valid data, invalid data, or no data. Invalid data can be outdated data because the latest version or a newer version of the data is stored in a different page 175 of memory device 130. Invalid data was previously programmed into an invalid page 175 but may no longer be associated with a valid logical address (e.g., a logical address referenced by host system 105). Valid data can be the latest version of such data stored on memory device 130. Page 175 that does not contain data can be a page 175 that has never been written to or has been erased.

[0038] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, waste cell collection, cleanup, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for some or all pages 175 in block 170 to have invalid data for erasure and to reuse block 170, an algorithm called "waste cell collection" may be invoked to allow block 170 to be erased and freed up for subsequent write operations. Waste cell collection may refer to a set of media management operations that include, for example: selecting block 170 containing valid and invalid data; selecting page 175 in block 170 containing valid data; copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected page 175 as invalid; and erasing the selected block 170. Therefore, the number of erased blocks 170 can be increased, allowing more blocks 170 to be used to store subsequent data (e.g., data subsequently received from host system 105).

[0039] Host system 105 may send a set of unmapping commands (e.g., via host system controller 106) to memory system 110 (e.g., to memory system controller 115) to release storage space allocated to or used to store unused data in memory device 130. Memory system 110 (e.g., memory system controller 115) may determine one or more parameters associated with the set of unmapping commands (e.g., queue depth, data mode, progressive order of LBAs, amount of unmapping commands, or some other parameter), and may select a program for executing the set of unmapping commands based on the one or more parameters. For example, if the one or more parameters meet an associated threshold, memory system 110 may select an elevated program for executing the set of unmapping commands, and may use the elevated program to execute the set of unmapping commands. The elevated program may be a program different from the default program for executing the set of unmapping commands, which may reduce latency and power consumption and increase memory system performance associated with executing the unmapping commands, as described herein.

[0040] System 100 may include any number of non-transitory computer-readable media that support unmapping operation techniques. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform the functions attributed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0041] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry combined with a local (e.g., on-die or in-package) controller (e.g., local controller 135). An example of a managed memory system may be an MNAND system.

[0042] Figure 2 This describes an example of a process flow 200 that supports unmapping operations, based on the examples disclosed herein. Process flow 200 may be provided by a memory system (e.g., reference...). Figure 1 The components of the described memory system 110) are executed. For example, process flow 200 may be executed by, for example, reference to... Figure 1 The process flow 200 is executed by a controller or memory device (or both) of a memory system, such as the memory system controller 115. The process flow 200 can depict the selection of a program for executing a demapping command and the execution of the demapping command using the selected program, which can be implemented to reduce latency and power consumption and increase system performance and other benefits. Aspects of the process flow 200 can be implemented by the controller and other components. Alternatively, aspects of the process flow 200 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to the memory system controller 115). For example, instructions executed by the controller (e.g., the memory system controller 115) can cause the controller to perform the operation of the process flow 200.

[0043] In the following description of process flow 200, operations may be performed in different orders or at different times. Some operations may be omitted from process flow 200, or other operations may be added to process flow 200.

[0044] At position 205, a set of unmapping commands can be received. For example, the host system can send a set of unmapping commands to the controller to make the storage space of the memory device available for other purposes. For example, the memory device may not be aware that some data stored in the memory device (e.g., host data) is unused or will no longer be used by the host system. To indicate to the memory device that the data is unused, the host system can send one or more unmapping commands to the controller, each unmapping command containing an LBA associated with the unused data.

[0045] At 210, the one or more parameters associated with the set of unmapping commands can be evaluated to determine whether they satisfy one or more associated thresholds. Examples of the one or more parameters associated with the set of unmapping commands may include the queue depth of the set of unmapping commands, the data pattern associated with the set of unmapping commands, the order of the LBAs included in the set of unmapping commands, the number of unmapping commands, and other parameters, or combinations thereof. The controller can determine whether the one or more parameters satisfy the associated thresholds. For example, the controller can determine whether the queue depth of the set of unmapping commands satisfies a depth threshold (e.g., a queue depth of 4 unmapping commands, or some other queue depth), whether the set of unmapping commands is issued according to a data pattern, whether the set of unmapping commands is issued in a progressive order of LBAs, whether the number of unmapping commands in the set of unmapping commands satisfies a quantity threshold, or combinations thereof. In some instances, a set of unmapping commands issued according to a data pattern may be a set of unmapping commands in which the data associated with the LBA of the unmapping command corresponds to a pattern (e.g., a business pattern, a predefined pattern, or another pattern). In some instances, a set of unmapping commands issued in progressive order of LBAs may be a set of unmapping commands in which the LBA of the unmapping command following the previous unmapping command is greater than the LBA of the previous unmapping command.

[0046] In some cases, one or more parameters satisfying one or more associated thresholds may instruct the controller to use a boosting procedure to execute the set of unmapping commands. For example, in some cases, the host system may issue a large number of unmapping commands to the controller within a finite duration. For example, some host systems (e.g., Android devices) may periodically perform one or more defragmentation operations (e.g., at night, while the battery is charging, or at some other time) to merge unused data pages. To perform defragmentation operations, the host system may issue a large number of unmapping commands to the free pages associated with unused data. However, if some regular or default procedure is used to execute the unmapping commands, executing a large number of unmapping commands (e.g., continuously) may increase latency and power consumption at the memory system containing the controller. Therefore, in some instances, the controller may choose a boosting procedure to execute the unmapping commands to reduce latency and power consumption and increase the memory system performance associated with executing the unmapping commands, as well as other benefits.

[0047] For example, if the controller determines that one or more parameters satisfy one or more associated thresholds, the controller or memory device (or both) may perform steps 215 to 230 as follows. For example, if the controller determines that the queue depth of the set of unmapping commands is greater than (e.g., or equal to) a depth threshold, the set of unmapping commands is issued according to a business model, the set of unmapping commands is issued in progressive order of LBAs, the amount of the unmapping commands in the set of unmapping commands is greater than (e.g., or equal to) an amount threshold, or a combination thereof, the controller or memory device (or both) may perform steps 215 to 230 as follows.

[0048] At 215, an elevation procedure can be selected. For example, the controller can select an elevation procedure to execute the set of unmapping commands based on determining that one or more parameters meet one or more associated thresholds.

[0049] At 220, data stored in a volatile memory device coupled to the controller (e.g., local memory 120, memory device 130 containing volatile memory cells, SRAM device) can be transferred to a non-volatile memory device coupled to the controller (e.g., memory device 130 containing non-volatile memory cells, NAND device). For example, the volatile memory device may be associated with faster operation compared to the non-volatile memory device. In some instances, before executing the set of unmapping commands, the controller may transfer data (e.g., cached data, cached data, or other data stored in the volatile memory device) from the volatile memory device to the non-volatile memory device. In this way, the memory in the volatile memory device can be made available to store information associated with the set of unmapping commands.

[0050] At 225, a buffer for the allocable volatile memory device is provided to store the mappings associated with the set of unmapping commands. For example, to execute an unmapping command, the controller may update at least the entry for a first mapping indicating the relationship between logical addresses and physical addresses, and the entry for a second mapping indicating the validity of data stored at the physical addresses, as well as other operations. The controller may allocate a buffer to store a portion of the first mapping and a portion of the second mapping. In some instances, the portion of the buffer allocated to store the second mapping may be larger than the portion of the buffer allocated to store the first mapping.

[0051] At point 230, an elevation procedure can be used to execute the set of unmapping commands. For example, the controller can use an elevation procedure to execute the set of unmapping commands. See below for reference. Figure 3 Describes aspects of using the elevation procedure to execute the set of unmapping commands.

[0052] If at 210, the controller determines that one or more parameters do not meet the associated threshold, the controller or memory device (or both) may perform steps 235 to 240 as follows. For example, if the controller determines that the queue depth of the set of unmapping commands is less than (e.g., or equal to) a depth threshold, the set of unmapping commands was not issued according to a business mode, the set of unmapping commands was not issued in the progressive order of LBAs, the amount of the unmapping commands in the set of unmapping commands is less than (e.g., or equal to) an amount threshold, or a combination thereof, the controller or memory device (or both) may perform steps 235 to 240 as follows.

[0053] At position 235, a default procedure can be selected. For example, the controller can select a default procedure to execute the set of unmapping commands based on determining that one or more parameters do not meet an associated threshold. In some cases, the default procedure can be any procedure other than the promotion procedure used to execute the set of unmapping commands.

[0054] At point 240, the controller or memory device (or both) may execute the set of unmapping commands using a default procedure. In some instances, executing the unmapping commands using the default procedure may include: transferring a portion of the first mapping and a portion of the second mapping from a non-volatile device to a volatile memory device, updating the entries for the first and second mappings, and subsequently transferring the portion of the first mapping and the portion of the second mapping to the non-volatile memory device. That is, for each unmapping command, the default procedure may include transferring a portion of the first and second mappings to and from the volatile memory device.

[0055] Figure 3This document describes an example of a process flow 300 that supports unmapping operations, based on the examples disclosed herein. Process flow 300 may be provided by a memory system (e.g., reference...). Figure 1 The components of the described memory system 110) are executed. For example, process flow 300 may be executed by, for example, referenced... Figure 1 The memory system controller 115 and other memory system controllers or memory devices (or both) described herein execute this process. Process flow 300 can depict the execution of a demapping command using an elevation procedure, which can be implemented to reduce latency and power consumption and increase system performance, among other benefits. For example, process flow 300 can be referenced... Figure 2 The described 230 instances illustrate the manner in which the set of unmapping commands is executed using an elevation procedure. Aspects of process flow 300 may be implemented by a controller and other components. Alternatively, aspects of process flow 300 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory system controller 115). For example, instructions executed by a controller (e.g., memory system controller 115) may cause the controller to perform operations of process flow 300.

[0056] In some instances, to execute a demapping command, the controller may update at least the entry of a first mapping indicating the relationship between logical addresses and physical addresses, and may update the entry of a second mapping indicating the validity of data stored at the physical address, as well as other operations. In some instances, the first mapping may be an instance of a Physical Pointer Table (PPT) that maps logical addresses (e.g., LBAs) to corresponding physical addresses of non-volatile memory devices coupled to the controller (e.g., memory device 130, a NAND device, or some other non-volatile memory device). In some cases, the PPT table may be referred to as a Logical-to-Physical (L2P) table. In some instances, the second mapping may be an instance of a Page Validity Table (PVT) indicating whether data stored at the physical address is valid. For clarity, process flow 300 uses specific instances of PPT and PVT mappings, but similar procedures apply to other mappings also covered within the scope of this disclosure.

[0057] In the following description of process flow 300, operations may be performed in different orders or at different times. Some operations may be omitted from process flow 300, or other operations may be added to process flow 300.

[0058] At 305, a portion of the PPT map may optionally be loaded into a volatile memory device (e.g., local memory 120, SRAM device) coupled to or included in the controller. For example, to initiate execution of a cancel mapping command in a set of cancel mapping commands, the controller may determine whether a portion of the PPT map containing the LBA of the cancel mapping command is stored in a volatile memory device. If the portion of the PPT map containing the LBA is stored in a volatile memory device, the controller may proceed to 310 without loading any additional portion of the PPT map. If the portion of the PPT map containing the LBA is not stored in a volatile memory device, the controller may transfer at least the portion of the PPT map containing the LBA from a non-volatile memory device to a volatile memory device. In some instances, a single portion of the PPT map may contain multiple LBAs associated with the set of cancel mapping commands if the LBAs associated with the set of cancel mapping commands are incremental, progressive, or both. Therefore, the controller can execute multiple unmapping commands (e.g., update operations) from the set of unmapping commands without loading additional portions of the PPT mapping. Consequently, the controller can reduce the latency and power consumption associated with executing the set of unmapping commands by reducing the number of times portions of the PPT mapping are transferred to the volatile memory device.

[0059] In some cases, volatile memory devices may be associated with faster operation compared to non-volatile memory devices, but non-volatile memory devices may be associated with larger storage capacity compared to volatile memory devices. In some instances, PPT maps and PVT maps may therefore be stored in non-volatile memory devices to save storage space in volatile memory devices or due to storage limitations of volatile memory devices, or both. For example, the volatile memory device may not have the storage capacity to store PPT maps or PVT maps, or both. Therefore, the controller may transfer portions of PPT maps and PVT maps to the volatile memory device to perform operations (e.g., update operations) on the corresponding portions of PPT maps and PVT maps. Thus, at 305, a portion of the PPT map may optionally be loaded into the volatile memory device.

[0060] At 310, the portion of the PPT mapping can be updated. For example, the portion of the PPT mapping may contain entries that each map an LBA to a physical address of a non-volatile memory device. A demapping command may indicate that the data associated with the LBA of the demapping command is unused. Therefore, based on the demapping command, the controller may update the entries in the portion of the PPT mapping corresponding to the LBA of the demapping command to indicate that the LBA is deassociated with the physical address of unused data.

[0061] Additionally, at 310, entries may be stored in a first PVT change log, hereinafter referred to as PVT change log 1. For example, entries in the PVT change log may indicate an update to the corresponding entry of the PVT mapping. PVT mapping entries may indicate whether the data stored at the physical address is valid. Therefore, based on a demapping command, the controller may store entries in PVT change log 1 indicating that the PVT mapping entry corresponding to the LBA of the demapping command will be updated to indicate that the data stored at the physical address is invalid.

[0062] At 315, the controller can determine whether the PVT change log 1 entries are full. If the PVT change log 1 entries are full, the controller can continue to execute 325 to 380 as follows. Executing 315 to 380 reduces the number of times the controller transfers portions of the PVT mapping between the volatile memory device and the non-volatile memory device. For example, executing 315 to 380 can group changes to portions of the PVT mapping to increase the number of changes that occur after a portion of the PVT mapping has been transferred to the volatile memory device. This reduces the number of transfers of portions of the PVT mapping between the volatile memory device and the non-volatile memory device, thereby reducing the latency and power consumption of executing the set of unmapping commands.

[0063] If the PVT change log 1 is not full, at point 320, the controller can determine whether there are any additional unmapping commands to be executed among the set of unmapping commands. If there are additional unmapping commands to be executed, the controller can execute steps 305 to 315 until the PVT change log 1 is full or there are no additional unmapping commands to be executed. If at point 320 there are no additional unmapping commands but there are entries stored in the PVT change log 1, the controller can continue to execute steps 325 to 380 using the PVT change log 1 with the stored entries (e.g., even if the PVT change log 1 is not full).

[0064] At position 325, entries in PVT change log 1 can be retrieved. For example, the controller can retrieve entries stored in PVT change log 1 to update the corresponding entries in the PVT mapping.

[0065] At 330, the controller may determine whether a first portion of the entry corresponding to the retrieved entry in PVT change log 1, contained in the PVT map, is stored in a volatile memory device. For example, the volatile memory device may store one or more portions of the PVT map instead of the entire PVT map (e.g., due to storage capacity limitations of the volatile memory device). Therefore, at 330, the controller may determine whether the volatile memory device stores a first portion of the PVT map.

[0066] If the volatile memory device stores a first portion of the PVT map, then at 335, the first portion of the PVT map can be updated. For example, the controller can update the entry in the PVT map corresponding to the retrieved entry in PVT change log 1 to indicate that the data stored at the physical address is invalid.

[0067] If the volatile memory device does not store the first part of the PVT mapping, then at 340, the controller can determine whether there is available storage space in the volatile memory device to store the first part of the PVT mapping.

[0068] If the volatile memory device has available storage space, then at 345, the first portion of the PVT map can be loaded into the volatile memory device. For example, the controller can transfer the first portion of the PVT map from a non-volatile memory device to the volatile memory device. The controller can then update the entry in the PVT map corresponding to the retrieved entry in PVT change log 1 to indicate that the data stored at the physical address is invalid.

[0069] If the volatile memory device does not have available storage space, at 350, the controller can determine whether the entries in the second PVT change log (hereinafter referred to as PVT change log 2) are full.

[0070] If PVT change log 2 is available to store additional entries (e.g., if the log is not full), retrieved entries from PVT change log 1 can be moved to PVT change log 2. For example, at 355, the controller can move retrieved entries from PVT change log 1 to PVT change log 2.

[0071] After updating the first part of the PVT mapping, or after moving the retrieved entry from PVT change log 1 to PVT change log 2, or if the controller determines that PVT change log 2 is full, at 360, the controller may determine whether the retrieved entry from PVT change log 1 is the last entry stored in PVT change log 1.

[0072] If there are additional entries in PVT change log 1 to be executed (for example, if the retrieved entry in PVT change log 1 is not the last entry in PVT change log 1), the controller may retrieve the next entry in PVT change log 1 and execute 330 to 360, as described above.

[0073] If the retrieved entry in PVT Change Log 1 is the last entry in PVT Change Log 1, then at 365, the controller can determine whether PVT Change Log 2 is full.

[0074] If the controller determines that the entries in PVT change log 2 are full, the controller may execute steps 370 to 375. For example, at step 370, any portion of the PVT mapping stored in the volatile memory device may be cleared. For example, the controller may transfer any portion of the PVT mapping stored in the volatile memory device to the non-volatile memory device.

[0075] At point 375, PVT change log 1 and PVT change log 2 can be merged. For example, the controller can delete any entry in PVT change log 1 whose corresponding entry for PVT mapping has been updated. The controller can store entries from PVT change log 2 in PVT change log 1 and delete those entries. The controller can then retrieve the merged entries from PVT change log 1 and execute steps 330 through 365, as described above.

[0076] If the controller determines that the entries in PVT change log 2 are not full, the controller may determine whether there are any additional unmapping commands to be executed in the set of unmapping commands. If there are additional unmapping commands to be executed, the controller may execute commands 305 to 375 as described above. If there are no additional unmapping commands to be executed but there are entries stored in PVT change log 2, the controller may execute commands 325 to 375 using the entries stored in PVT change log 2 as described above.

[0077] If no entries are stored in PVT Change Log 1 and PVT Change Log 2 and no additional unmapping commands are pending, the controller may terminate the promotion process at 380.

[0078] By using the enhancement procedures described herein, the controller can reduce the number of times it transfers portions of PPT and PVT maps between volatile and non-volatile memory devices. For example, in some cases, if the LBA of a subsequent unmapping command contains a portion of the PPT map currently stored in the volatile memory device, the controller can prevent the transfer of the PPT map portion between the volatile and non-volatile memory devices. Alternatively, the controller can prevent the transfer of the PVT map portion until one or more PVT change log entries are full. Therefore, the controller can update all entries of the PVT map portion indicated by the PVT change log stored in the volatile memory device before transferring the PVT map portion to the non-volatile memory device. This reduces latency and power consumption and increases memory system performance associated with executing unmapping commands compared to using the default procedure.

[0079] Figure 4A block diagram 400 illustrates a memory system 420 supporting unmapping operations, based on an example disclosed herein. The memory system 420 may be a reference... Figures 1 to 3 Examples of various aspects of the described memory system. Memory system 420 or its various components may be examples of constructs for performing various aspects of the unmapping operation techniques described herein. For example, memory system 420 may include communication component 430, parameter component 435, selection component 440, command component 445, mapping manager 450, change log manager 455, update component 460, storage component 465, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0080] Communication component 430 may be configured or otherwise supported for receiving a plurality of unmapping commands, each of the plurality of unmapping commands containing an LBA associated with unused data. Parameter component 435 may be configured or otherwise supported for determining whether one or more parameters associated with the plurality of unmapping commands satisfy a threshold. Selection component 440 may be configured or otherwise supported for selecting, at least in part, a first program for executing the plurality of unmapping commands, different from a second program for executing the plurality of unmapping commands, based on the determination that the one or more parameters satisfy the threshold. Command component 445 may be configured or otherwise supported for executing the plurality of unmapping commands using the first program.

[0081] In some instances, to support determining that one or more parameters meet the threshold, parameter component 435 may be configured or otherwise supported to support components for determining that the queue depth of the plurality of unmapping commands meets a depth threshold. In some instances, to support determining that one or more parameters meet the threshold, parameter component 435 may be configured or otherwise supported to support components for determining that the plurality of unmapping commands were issued according to a certain data pattern.

[0082] In some instances, to support the execution of the plurality of unmapping commands using a first program, the mapping manager 450 may be configured or otherwise support components for transferring a portion of a first mapping indicating the relationship between logical addresses and physical addresses from a non-volatile memory device of the memory system to a volatile memory device of the memory system, the portion of the first mapping including the first LBA of the first unmapping command among the plurality of unmapping commands.

[0083] In some instances, the mapping manager 450 may be configured or otherwise supported to support components for updating a first entry of a first mapping associated with a first LBA to indicate that the first LBA is unassociated from a first physical address. In some instances, the change log manager 455 may be configured or otherwise supported to support components for storing in the change log an entry indicating an update to a first entry of a second mapping, at least in part based on a first unmapping command, the first entry of which indicates whether data stored at a physical address is valid, the first entry of which is associated with the first physical address associated with the first unmapping command.

[0084] In some instances, the change log manager 455 may be configured or otherwise supported to determine whether the change log is full, at least in part, based on storing the entries in the change log.

[0085] In some instances, the mapping manager 450 may be configured or otherwise supported to determine, at least in part, that a first portion of a second mapping containing a first entry of a second mapping is stored in a volatile memory device based on the determination that the change log is full. In some instances, the update component 460 may be configured or otherwise supported to update the first entry of a second mapping, at least in part, based on entries stored in the change log and the determination that a first portion of the second mapping is stored in a volatile memory device, to indicate that invalid data is stored at the first physical address associated with the first unmapping command.

[0086] In some instances, the mapping manager 450 may be configured or otherwise supported to determine, at least in part, that a first portion of a second mapping containing a first entry of a second mapping is not stored in a volatile memory device based on the determination that the change log is full. In some instances, the storage component 465 may be configured or otherwise supported to determine, at least in part, that a volatile memory device has available storage space to store the first portion of the second mapping based on the determination that the first portion of the second mapping is not stored in a volatile memory device. In some instances, the mapping manager 450 may be configured or otherwise supported to transfer the first portion of the second mapping to a volatile memory device, at least in part, based on the determination that the volatile memory device has available storage space to store the first portion of the second mapping. In some instances, the update component 460 may be configured or otherwise supported to update the first entry of the second mapping, at least in part, based on entries stored in the change log and the transfer of the first portion of the second mapping to the volatile memory device, to indicate that invalid data is stored at the first physical address associated with the first unmapping command.

[0087] In some instances, the change log manager 455 may be configured or otherwise supported to determine, at least in part, that a second change log stored in a volatile memory device is available for storing additional entries, based on the determination that the change log is full. In some instances, the change log manager 455 may be configured or otherwise supported to store in the second change log entries indicating updates to the first entry of the second mapping, based at least in part on the determination that the second change log is available for storing additional entries.

[0088] In some instances, the change log manager 455 may be configured or otherwise supported to determine, at least in part, that entries in a second change log stored in a volatile memory device are full based on the determination that entries in the change log are full. In some instances, the mapping manager 450 may be configured or otherwise supported to transfer one or more portions of a second mapping stored in a volatile memory device to a non-volatile memory device, at least in part based on the determination that entries in the second change log are full. In some instances, the change log manager 455 may be configured or otherwise supported to merge the change log and the second change log, at least in part based on the determination that entries in the second change log are full.

[0089] In some instances, the change log manager 455 may be configured or otherwise supported to determine that an entry stored in the change log is the last entry stored in the change log. In some instances, the command component 445 may be configured or otherwise supported to determine, at least in part, that one or more unmapping commands among a plurality of unmapping commands are awaiting execution based on the determination that an entry stored in the change log is the last entry stored in the change log. In some instances, the mapping manager 450 may be configured or otherwise supported to transfer a second portion of a first mapping to a volatile memory device, at least in part based on the determination that one or more unmapping commands among a plurality of unmapping commands have not yet been executed.

[0090] In some instances, the change log manager 455 may be configured or otherwise supported to include components for determining that the change log contains additional entries to be executed. In some instances, the update component 460 may be configured or otherwise supported to include components for retrieving a second entry stored in the change log to update a second mapping, based at least in part on the determination that the change log contains additional entries to be executed.

[0091] In some instances, the mapping manager 450 may be configured or otherwise supported to transfer data stored in a volatile memory device to a non-volatile memory device before executing multiple unmapping commands using a first program, at least in part based on the selection of a first program. In some instances, the mapping manager 450 may be configured or otherwise supported to allocate buffers in a volatile memory device to store a portion of a first mapping indicating the relationship between logical addresses and physical addresses, and one or more portions of a second mapping indicating whether data stored at a physical address is valid.

[0092] In some instances, one or more parameters associated with multiple unmapping commands include the number of unmapping commands, the queue depth, the second LBA of a second unmapping command received after the first unmapping command in the multiple unmapping commands being greater than the first LBA of the first unmapping command, or a combination thereof.

[0093] In some instances, the second program is the default program used to execute the plurality of unmapping commands.

[0094] Figure 5 The flowchart illustrates a method 500 supporting unmapping operations based on the examples disclosed herein. The operation of method 500 can be implemented by the memory system or its components described herein. For example, the operation of method 500 can be implemented by reference to... Figures 1 to 4 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0095] At 505, the method may include receiving a plurality of unmapping commands, each of the plurality of unmapping commands containing an LBA associated with unused data. The operation of 505 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 505 may be referenced. Figure 4 The described communication component 430 is used to perform this.

[0096] At 510, the method may include determining whether one or more parameters associated with the plurality of unmapping commands satisfy a threshold. The operation at 510 can be performed according to the examples disclosed herein. In some instances, aspects of the operation at 510 may be referenced... Figure 4 The described parameter component 435 is executed.

[0097] At 515, the method may include selecting a first procedure for executing the plurality of unmapping commands based at least in part on determining that the one or more parameters satisfy a threshold, the first procedure being different from a second procedure for executing the plurality of unmapping commands. The operation of 515 may be performed according to the examples disclosed herein. In some instances, aspects of the operation of 515 may be referenced... Figure 4 The described selection component 440 is executed.

[0098] At 520, the method may include using a first procedure to execute the plurality of unmapping commands. The operation at 520 may be performed according to the examples disclosed herein. In some instances, aspects of the operation at 520 may be referenced. Figure 4 The described command component 445 is executed.

[0099] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a plurality of unmapping commands, each of the plurality of unmapping commands containing an LBA associated with unused data; determining whether one or more parameters associated with the plurality of unmapping commands satisfy a threshold; selecting a first program for executing the plurality of unmapping commands, the first program being different from a second program for executing the plurality of unmapping commands, based at least in part on the determination that the one or more parameters satisfy the threshold; and executing the plurality of unmapping commands using the first program.

[0100] In some instances of the method 500 and device described herein, determining that the one or more parameters satisfy a threshold may include operations, features, circuit systems, logic, components, or instructions for determining that the queue depth of the plurality of unmapping commands satisfies a depth threshold and that the plurality of unmapping commands can be issued according to a certain data pattern.

[0101] In some instances of the method 500 and apparatus described herein, executing the plurality of unmapping commands using a first program may include operations, features, circuitry, logic, components, or instructions for transferring a portion of a first mapping indicating a relationship between logical addresses and physical addresses from a non-volatile memory device of the memory system to a volatile memory device of the memory system, said portion of the first mapping including a first LBA of the first unmapping command of the plurality of unmapping commands.

[0102] Some examples of the methods 500 and devices described herein may also include operations, features, circuit systems, logic, components, or instructions for: updating a first entry of a first mapping that can be associated with a first LBA to indicate that the first LBA can be deassociated with a first physical address; and storing, at least in part, an entry in a change log indicating an update to a first entry of a second mapping, the first entry of the second mapping indicating whether data stored at a physical address may be valid, the first entry of the second mapping being associated with the first physical address associated with the first demapping command.

[0103] Some examples of the methods 500 and devices described herein may also include operations, features, circuit systems, logic, components, or instructions for determining, at least in part, whether the entries in the change log may be full, based on storing the entries in the change log.

[0104] Some examples of the method 500 and apparatus described herein may also include operations, features, circuit systems, logic, components, or instructions for: determining, at least in part, based on the determination that the change log may be full, that a first portion of a second mapping containing a first entry of the second mapping may be stored in a volatile memory device; and updating the first entry of the second mapping, at least in part based on entries stored in the change log and the determination that the first portion of the second mapping may be stored in a volatile memory device, to indicate that invalid data is stored at the first physical address associated with the first unmapping command.

[0105] Some examples of the method 500 and apparatus described herein may also include operations, features, circuit systems, logic, components, or instructions for: determining, at least in part, based on the determination that the change log may be full, that a first portion of a second mapping containing a first entry of a second mapping may not be stored in a volatile memory device; determining, at least in part, based on the determination that the first portion of the second mapping may not be stored in a volatile memory device, that the volatile memory device may have available storage space to store the first portion of the second mapping; transferring the first portion of the second mapping to a volatile memory device, at least in part, based on the determination that the volatile memory device may have available storage space to store the first portion of the second mapping; and updating the first entry of the second mapping to indicate that invalid data is stored at the first physical address associated with the first unmapping command, based at least in part on the entry stored in the change log and the transfer of the first portion of the second mapping to the volatile memory device.

[0106] Some examples of the methods 500 and devices described herein may also include operations, features, circuit systems, logic, components, or instructions for: determining, at least in part, based on the determination that the entries in the change log may be full, that a second change log stored in a volatile memory device can be used to store additional entries; and storing in the second change log an entry indicating an update to a first entry of a second mapping, at least in part based on the determination that the second change log can be used to store additional entries.

[0107] Some examples of the methods 500 and devices described herein may also include operations, features, circuit systems, logic, components, or instructions for: determining, at least in part, that entries in a second change log stored in a volatile memory device may be full; transferring one or more portions of a second mapping stored in a volatile memory device to a non-volatile memory device, at least in part, based on the determination that entries in the second change log may be full; and merging the change log and the second change log, at least in part, based on the determination that entries in the second change log may be full.

[0108] Some examples of the methods 500 and devices described herein may also include operations, features, circuit systems, logic, components, or instructions for: determining that an entry stored in a change log may be the last entry stored in the change log; determining, at least in part based on the determination that an entry stored in the change log may be the last entry stored in the change log, that one or more of a plurality of unmapping commands may be awaiting execution; and transferring a second portion of the first mapping to a volatile memory device, at least in part based on the determination that one or more of the plurality of unmapping commands may not have been executed.

[0109] Some instances of the method 500 and device described herein may also include operations, features, circuit systems, logic, components, or instructions for: determining that a change log contains additional entries to be executed; and retrieving a second entry stored in the change log to update a second mapping, based at least in part on the determination that the change log contains additional entries to be executed.

[0110] Some examples of the methods 500 and devices described herein may also include operations, features, circuit systems, logic, components, or instructions for: transferring data stored in a volatile memory device to a non-volatile memory device before executing a plurality of unmapping commands using a first program based at least in part on the selection of a first program; and allocating a buffer in the volatile memory device to store a portion of a first mapping indicating a relationship between logical addresses and physical addresses and one or more portions of a second mapping indicating whether data stored at physical addresses may be valid.

[0111] In some instances of the method 500 and device described herein, one or more parameters associated with a plurality of unmapping commands include the amount of unmapping commands, the queue depth, the second LBA of a second unmapping command received after a first unmapping command in the plurality of unmapping commands being greater than the first LBA of the first unmapping command, or a combination thereof.

[0112] In some instances of the method 500 and device described herein, the second program may be the default program for executing multiple unmapping commands.

[0113] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more methods described may be combined.

[0114] Describe an apparatus. The apparatus may include: a memory system comprising volatile memory devices and non-volatile memory devices; and a controller coupled to the memory system and operable to cause the apparatus to: receive a plurality of unmapping commands, each of the plurality of unmapping commands including an LBA associated with unused data; determine whether one or more parameters associated with the plurality of unmapping commands satisfy a threshold; select a first program for executing the plurality of unmapping commands, the first program being different from a second program for executing the plurality of unmapping commands, based at least in part on the determination that the one or more parameters satisfy the threshold; and execute the plurality of unmapping commands using the first program.

[0115] In some instances of the device, to determine that one or more parameters satisfy the threshold, the controller may also be configured to determine that the queue depth of the plurality of unmapping commands satisfies the depth threshold and that the plurality of unmapping commands can be issued according to a certain data pattern.

[0116] In some instances of the device, in order to execute the plurality of unmapping commands using a first program, the controller may also be configured to transfer a portion of a first mapping indicating the relationship between logical addresses and physical addresses from a non-volatile memory device to a volatile memory device, the portion of the first mapping including the first LBA of the first unmapping command among the plurality of unmapping commands.

[0117] In some instances of the device, the controller may also be configured to cause the device to: update a first entry of a first mapping that can be associated with a first LBA to indicate that the first LBA can be unassociated with a first physical address; and store in a change log, at least in part, an entry indicating an update to a first entry of a second mapping, the first entry of which indicates whether data stored at a physical address may be valid, the first entry of which is associated with the first physical address associated with the first unmapping command.

[0118] In some instances of the device, the controller may also be configured to determine, at least in part, whether the entries in the change log are likely to be full based on storing the entries in the change log.

[0119] In some instances of the device, the controller may also be configured to cause the device to: determine, at least in part, that a first portion of a second mapping containing a first entry of a second mapping may be stored in a volatile memory device based on the determination that the change log may be full; and update the first entry of the second mapping, at least in part, based on entries stored in the change log and the determination that the first portion of the second mapping may be stored in a volatile memory device, to indicate that invalid data is stored at the first physical address associated with the first unmapping command.

[0120] In some instances of the device, the controller may also be configured to cause the device to: determine, at least in part, that a first portion of a second mapping containing a first entry of a second mapping may not be stored in a volatile memory device based on the determination that the change log may be full; determine, at least in part, that the volatile memory device may have available storage space to store the first portion of the second mapping based on the determination that the first portion of the second mapping may not be stored in a volatile memory device; transfer the first portion of the second mapping to a volatile memory device based on the determination that the volatile memory device may have available storage space to store the first portion of the second mapping; and update the first entry of the second mapping to indicate that invalid data is stored at the first physical address associated with the first unmapping command, based at least in part on the entry stored in the change log and the transfer of the first portion of the second mapping to the volatile memory device.

[0121] In some instances of the device, the controller may also be configured to cause the device to: determine, at least in part, that a second change log stored in a volatile memory device may be available for storing additional entries based on the determination that the change log may be full; and to store in the second change log an entry indicating an update to the first entry of the second mapping, at least in part based on the determination that the second change log may be available for storing additional entries.

[0122] In some instances of the device, the controller may also be configured to cause the device to: determine, at least in part, that entries in a second change log stored in a volatile memory device may be full; transfer one or more portions of a second mapping stored in a volatile memory device to a non-volatile memory device, at least in part, based on the determination that entries in the second change log may be full; and merge the change log and the second change log, at least in part, based on the determination that entries in the second change log may be full.

[0123] In some instances of the device, the controller may also be configured to cause the device to: determine that an entry stored in the change log may be the last entry stored in the change log; determine, at least in part based on the determination that an entry stored in the change log may be the last entry stored in the change log, that one or more of a plurality of unmapping commands may be awaiting execution; and transfer a second portion of the first mapping to a volatile memory device, at least in part based on the determination that one or more of the plurality of unmapping commands may not have been executed.

[0124] In some instances of the device, the controller may also be configured to cause the device to: determine that the change log contains additional entries to be executed; and retrieve a second entry stored in the change log to update the second mapping, at least in part based on the determination that the change log contains additional entries to be executed.

[0125] In some instances of the device, the controller may also be configured to cause the device to: transfer data stored in a volatile memory device to a non-volatile memory device before executing a plurality of unmapping commands using a first program based at least in part on the selection of a first program; and allocate a buffer in the volatile memory device to store a portion of a first mapping indicating the relationship between logical addresses and physical addresses and one or more portions of a second mapping indicating whether the data stored at the physical address may be valid.

[0126] In some instances of the device, one or more parameters associated with a plurality of unmapping commands include the amount of unmapping commands, the queue depth, the second LBA of a second unmapping command received after the first unmapping command in the plurality of unmapping commands being greater than the first LBA of the first unmapping command, or a combination thereof.

[0127] In some instances of the device, the second program may be the default program for executing the plurality of unmapping commands.

[0128] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0129] The terms "if," "when," "based on," "at least partially based on," and "in response to" are used interchangeably. For example, the terms "if," "when," "based on," "at least partially based on," and "in response to" are used to describe conditional actions or connections between parts of a process.

[0130] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enables the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that enables the flow of signals between them at any given time. At any given time, the conductive path between components that are electronically connected (or electrically contacting, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, may be used to interrupt the signal flow between connected components for a period of time.

[0131] The term "coupling" refers to the condition that moves from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently be transmitted between components via a conductive path, while in a closed-circuit relationship, signals can be transmitted between components via a conductive path. If a component, such as a controller, couples other components together, that component initiates a change to allow signals to flow between the other components via conductive paths that were previously not permitted.

[0132] The term "isolation" refers to a relationship between components in which signals cannot currently flow between them. If an open circuit exists between components, the components are separated from each other. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller implements a change to prevent signals from flowing between the components using previously permitted conductive paths.

[0133] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0134] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, a drain, and a gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0135] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not necessarily "preferred" or "superior to other instances." The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0136] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral for differentiation among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0137] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations.

[0138] For example, the various specification boxes and modules described in connection with the disclosure herein may be implemented or performed by a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0139] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items preceding, for example, "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0140] Computer-readable media includes both non-transitory computer storage media and communication media, wherein the communication media includes any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. For example, and not limitingly, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Additionally, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0141] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: Memory systems, including volatile memory devices and non-volatile memory devices; as well as A controller, coupled to the memory system and operable to cause the memory device to perform the following operations: Receive multiple unmapping commands, each of which includes the logical block address associated with unused data; Determine whether one or more parameters associated with a set of the plurality of unmapping commands meet a threshold, wherein the one or more parameters include a queue depth corresponding to the number of unmapping commands in the set of the plurality of unmapping commands; A first program for executing the plurality of unmapping commands is selected based at least in part on determining that one or more parameters satisfy the threshold, and at least in part on the queue depth satisfying the depth threshold. The first program is different from a second program for executing the plurality of unmapping commands. as well as The first program is used to execute the plurality of unmapping commands.

2. The memory device of claim 1, wherein, in order to determine that the one or more parameters satisfy the threshold, the controller is configured to cause the memory device to perform the following operations: It is determined that the multiple unmapping commands are issued according to a certain data pattern.

3. The memory device of claim 1, wherein the one or more parameters associated with the plurality of unmapping commands include the number of unmapping commands, the queue depth, a second logical block address of a second unmapping command received after a first unmapping command in the plurality of unmapping commands being greater than a first logical block address of the first unmapping command, or a combination thereof.

4. The memory device of claim 1, wherein, in order to execute the plurality of unmapping commands using the first program, the controller is further configured to cause the memory device to perform the following operations: A portion of a first mapping indicating the relationship between logical addresses and physical addresses is transferred from the non-volatile memory device to the volatile memory device, the portion of the first mapping containing the first logical block address of the first unmapping command among the plurality of unmapping commands.

5. The memory device of claim 4, wherein the controller is further configured to cause the memory device to perform the following operations: Update the first entry of the first mapping associated with the first logical block address to indicate that the first logical block address is unassociated with the first physical address; and An entry indicating an update to a first entry of a second mapping is stored in the change log, at least in part based on the first unmapping command. The first entry of the second mapping indicates whether the data stored at the physical address is valid, and the first entry of the second mapping is associated with the first physical address associated with the first unmapping command.

6. The memory device of claim 5, wherein the controller is further configured to cause the memory device to perform the following operations: Whether the change log is full is determined at least in part based on storing the entry in the change log.

7. The memory device of claim 6, wherein the controller is further configured to cause the memory device to perform the following operations: Based at least in part on determining that the change log is full, it is determined that a first portion of the second mapping, including the first entry of the second mapping, is stored in the volatile memory device; and The first entry of the second mapping is updated at least in part based on the entry stored in the change log and determining that the first portion of the second mapping is stored in the volatile memory device, to indicate that invalid data is stored at the first physical address associated with the first unmapping command.

8. The memory device of claim 6, wherein the controller is further configured to cause the memory device to perform the following operations: Based at least in part on the determination that the change log is full, it is determined that a first portion of the second map, including the first entry of the second map, is not stored in the volatile memory device; The volatile memory device is determined to have available storage space to store the first portion of the second mapping, at least in part, based on the determination that the first portion of the second mapping is not stored in the volatile memory device. The first portion of the second mapping is transferred to the volatile memory device at least in part based on the determination that the volatile memory device has the available storage space to store the first portion of the second mapping; as well as The first entry of the second mapping is updated at least in part based on the entry stored in the change log and by transferring the first portion of the second mapping to the volatile memory device to indicate that invalid data is stored at the first physical address associated with the first unmapping command.

9. The memory device of claim 6, wherein the controller is further configured to cause the memory device to perform the following operations: The second change log stored in the volatile memory device is determined to be available for storing additional entries, at least in part based on the fact that the change log is full; and The entry indicating the update of the first entry to the second mapping is stored in the second change log, at least in part, based on the determination that the second change log can be used to store the additional entry.

10. The memory device of claim 6, wherein the controller is further configured to cause the memory device to perform the following operations: The determination that the second change log stored in the volatile memory device is full is based at least in part on the determination that the change log is full. At least in part, based on the determination that the entries in the second change log are full, one or more portions of the second mapping stored in the volatile memory device are transferred to the non-volatile memory device. as well as The change log and the second change log are merged, at least in part, based on the determination that the entries in the second change log are full.

11. The memory device of claim 6, wherein the controller is further configured to cause the memory device to perform the following operations: Determine that the entry stored in the change log is the last entry stored in the change log; The determination that one or more of the plurality of unmapping commands are waiting to be executed is based at least in part on the fact that the entry stored in the change log is the last entry stored in the change log; as well as The second portion of the first mapping is transferred to the volatile memory device, at least in part based on the determination that one or more of the plurality of unmapping commands have not yet been executed.

12. The memory device of claim 6, wherein the controller is further configured to cause the memory device to perform the following operations: Determine that the change log contains additional entries to be executed; and The second entry stored in the change log is retrieved to update the second mapping, at least in part based on the determination that the change log contains the additional entry to be executed.

13. The memory device of claim 1, wherein the controller is further configured to cause the memory device to perform the following operations: Data stored in the volatile memory device is transferred to the non-volatile memory device before the plurality of unmapping commands are executed using the first program, at least in part based on the selection of the first program; and The buffer of the volatile memory device is allocated to store a portion of a first mapping indicating the relationship between logical addresses and physical addresses, and one or more portions of a second mapping indicating whether the data stored at the physical address is valid.

14. The memory device of claim 1, wherein the second program is a default program for executing the plurality of unmapping commands.

15. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: Receive multiple unmapping commands, each of which includes the logical block address associated with unused data; Determine whether one or more parameters associated with a set of the plurality of unmapping commands meet a threshold, wherein the one or more parameters include a queue depth corresponding to the number of unmapping commands in the set of the plurality of unmapping commands; A first program for executing the plurality of unmapping commands is selected based at least in part on determining that one or more parameters satisfy the threshold, and at least in part on the queue depth satisfying the depth threshold. The first program is different from a second program for executing the plurality of unmapping commands. as well as The first program is used to execute the plurality of unmapping commands.

16. The non-transitory computer-readable medium of claim 15, wherein, in order to determine that the one or more parameters satisfy the threshold, the instruction, when executed by the processor of the electronic device, causes the electronic device to: It is determined that the multiple unmapping commands are issued according to a certain data pattern.

17. The non-transitory computer-readable medium of claim 15, wherein, for executing the plurality of unmapping commands using the first program, the instructions, when executed by the processor of the electronic device, further cause the electronic device to transfer a portion of a first mapping indicating a relationship between logical addresses and physical addresses from a non-volatile memory device to a volatile memory device, the portion of the first mapping including the first logical block address of the first unmapping command of the plurality of unmapping commands.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: Update the first entry of the first mapping associated with the first logical block address to indicate that the first logical block address is unassociated with the first physical address; and An entry indicating an update to a first entry of a second mapping is stored in the change log, at least in part based on the first unmapping command. The first entry of the second mapping indicates whether the data stored at the physical address is valid, and the first entry of the second mapping is associated with the first physical address associated with the first unmapping command.

19. The non-transitory computer-readable medium of claim 18, wherein the instructions, when executed by the processor of the electronic device, also cause the electronic device to determine, at least in part, that the change log is full based on storing the entry in the change log.

20. The non-transitory computer-readable medium of claim 15, wherein the one or more parameters associated with the plurality of unmapping commands include the number of unmapping commands, the queue depth, a second logical block address of a second unmapping command received after a first unmapping command of the plurality of unmapping commands being greater than a first logical block address of the first unmapping command, or a combination thereof.

21. A method executed by a memory system, comprising: Receive multiple unmapping commands, each of which includes the logical block address associated with unused data; Determine whether one or more parameters associated with a set of the plurality of unmapping commands meet a threshold, wherein the one or more parameters include a queue depth corresponding to the number of unmapping commands in the set of the plurality of unmapping commands; A first program for executing the plurality of unmapping commands is selected based at least in part on determining that one or more parameters satisfy the threshold, and at least in part on the queue depth satisfying the depth threshold. The first program is different from a second program for executing the plurality of unmapping commands. as well as The first program is used to execute the plurality of unmapping commands.

22. The method of claim 21, wherein determining that the one or more parameters satisfy the threshold comprises: It is determined that the multiple unmapping commands are issued according to a certain data pattern.

23. The method of claim 21, wherein executing the plurality of unmapping commands using the first program comprises: A portion of a first mapping indicating the relationship between logical addresses and physical addresses is transferred from a non-volatile memory device of the memory system to a volatile memory device of the memory system, the portion of the first mapping including the first logical block address of the first unmapping command among the plurality of unmapping commands.

24. The method of claim 23, further comprising: Update the first entry of the first mapping associated with the first logical block address to indicate that the first logical block address is unassociated with the first physical address; as well as An entry indicating an update to a first entry of a second mapping is stored in the change log, at least in part based on the first unmapping command. The first entry of the second mapping indicates whether the data stored at the physical address is valid, and the first entry of the second mapping is associated with the first physical address associated with the first unmapping command.

25. The method of claim 21, wherein the one or more parameters associated with the plurality of unmapping commands include the number of unmapping commands, the queue depth, a second logical block address of a second unmapping command received after a first unmapping command in the plurality of unmapping commands being greater than a first logical block address of the first unmapping command, or a combination thereof.

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