Memory device and method of operating the same

Abstract

The present disclosure relates to a memory device and a method of operating the memory device. The present technology relates to an electronic device. The memory device controls voltages applied to each line during a sensing operation to prevent or mitigate a channel negative boost phenomenon. The memory device includes: a memory block connected to a plurality of lines; a peripheral circuit configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines; and control logic configured to control voltages applied to a drain select line, a source select line, and a word line between the drain select line and the source select line among the plurality of lines during the sensing operation and during an equalization operation performed after the sensing operation. During the sensing operation, the control logic controls the voltage applied to an unselected drain select line based on whether a cell string is shared with a selected drain select line among the drain select lines.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0176723, filed with the Korean Intellectual Property Office on December 16, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer, a smart phone, or a smart tablet computer. The storage device includes: a device that stores data in a magnetic disk, such as a hard disk drive (HDD); a device that stores data in a semiconductor memory, such as a solid state drive (SSD); or a memory card, particularly a non-volatile memory.

[0005] The storage device may include a memory device in which data is stored and a memory controller that stores data in the memory device. The memory device may be classified into a volatile memory and a non-volatile memory. Here, the non-volatile memory includes a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM)), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. Summary of the Invention

[0006] According to an embodiment of the present disclosure, a memory device may include: a memory block connected to a plurality of lines; a peripheral circuit configured to perform a sensing operation on a selected memory cell connected to a selected word line among the plurality of lines; and a control logic configured to control voltages applied to a drain select line, a source select line, and a word line between the drain select line and the source select line among the plurality of lines during a sensing operation and during an equalization operation performed after the sensing operation. During the sensing operation, the control logic may control the voltage applied to an unselected drain select line according to whether a cell string is shared with a selected drain select line among the drain select lines.

[0007] According to one embodiment of the present disclosure, a memory device may include: a memory block connected to a plurality of lines; a peripheral circuit configured to perform a sensing operation on a selected memory cell connected to a selected word line among the plurality of lines; a drain select line controller configured to control a voltage applied to a drain select line among the plurality of lines during a sensing operation and during an equalization operation performed after the sensing operation; a source select line controller configured to control a voltage applied to a source select line among the plurality of lines; a word line controller configured to control a voltage applied to a word line between the drain select line and the source select line among the plurality of lines; and a dummy line controller configured to control a voltage applied to a center dummy line located in the middle of the word lines when the memory block has a plurality of stacked structures. During the sensing operation, the drain select line controller may control the voltage applied to an unselected drain select line based on whether it shares a cell string with the selected drain select line among the drain select lines.

[0008] According to one embodiment of the present disclosure, a method of operating a memory device including a memory block connected to a plurality of lines may include: applying a sensing voltage to a selected word line among the plurality of lines and applying a pass voltage to an unselected word line among the plurality of lines to perform a sensing operation for sensing a selected memory cell connected to the selected word line among the plurality of lines; and applying a voltage to a drain select line among the plurality of lines when the sensing voltage and the pass voltage are applied. The voltage applied to an unselected drain select line may be set differently based on whether it shares a cell string with the selected drain select line among the drain select lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating a storage device.

[0010] Figure 2 is a diagram illustrating Figure 1 the structure of a memory device.

[0011] Figure 3 is a diagram illustrating Figure 2 an embodiment of a memory cell array.

[0012] Figure 4 is a diagram illustrating Figure 3 the circuit diagram of any one memory block BLKa among memory blocks BLK1 to BLKz.

[0013] Figure 5 is a diagram illustrating Figure 3 another embodiment of the circuit diagram of any one memory block BLKb among memory blocks BLK1 to BLKz.

[0014] Figure 6 It is a diagram showing the negative boost of the channel.

[0015] Figure 7 It is a diagram showing the channel potential and the voltage applied to the word line during the sensing operation.

[0016] Figure 8 It is a diagram showing the shift and perturbation of the threshold voltage distribution according to the negative boost of the channel.

[0017] Figure 9 It is a diagram showing the voltage applied to each line during the sensing operation according to the present disclosure.

[0018] Figure 10 It is a diagram showing the structure of a memory block having two cell strings.

[0019] Figure 11 It is a diagram showing the structure of a memory block having four cell strings.

[0020] Figure 12 It is a diagram showing the structure of a memory block having eight cell strings.

[0021] Figure 13 It is a diagram showing during Figure 9 the voltage additionally applied to the dummy line during the sensing operation.

[0022] Figure 14 It is a diagram showing the operation of a memory device according to an embodiment of the present disclosure.

[0023] Figure 15 It is a diagram showing the operation of a memory device according to an embodiment of the present disclosure.

[0024] Figure 16 It is a diagram showing Figure 1 another embodiment of the memory controller.

[0025] Figure 17 It is a block diagram showing a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0026] Figure 18 It is a block diagram showing, for example, a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0027] Figure 19 It is a block diagram showing a user system to which a storage device according to an embodiment of the present disclosure is applied. Detailed Description

[0028] Illustrates a specific structural or functional description of an embodiment according to the concepts disclosed in this specification or application, and is only used to describe embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure can be implemented in various forms, and the description is not limited to the embodiments described in this specification or application.

[0029] Embodiments of the present disclosure provide a memory device that controls the voltage applied to each line during a sensing operation to prevent or mitigate the channel negative boost phenomenon, and a method of operating the memory device.

[0030] According to the present technology, by determining a method of reducing the potential during a sensing operation and before an equalization operation based on whether the drain select lines share a cell string, and by determining a method of setting the potential of the word lines during the equalization operation, the channel negative perturbation phenomenon can be prevented or, in some embodiments, mitigated.

[0031] Figure 1 Is a block diagram illustrating a storage device.

[0032] Reference Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200.

[0033] The storage device 50 may be a device that stores data under the control of a host 300, such as a cellular phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0034] According to the host interface as a communication method with the host 300, the storage device 50 may be manufactured as one type of various types of storage devices. For example, the storage device 50 may be configured as any one type of various types of storage devices, such as an SSD, a multimedia card (in the form of MMC, eMMC, RS-MMC, and micro MMC), a secure digital card (in the form of SD, mini SD, and micro SD), a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0035] The storage device 50 can be fabricated in any one of various types of packages. For example, the storage device 50 can be fabricated in any one of various types of package types, such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level packaged (WFP), and wafer-level stacked package (WSP).

[0036] The memory device 100 can store data. The memory device 100 operates in response to the control of a memory controller 200. The memory device 100 can include a memory cell array that includes a plurality of memory cells for storing data. The memory cell array can include a plurality of memory blocks. Each of the memory blocks can include a plurality of memory cells, and the plurality of memory cells can configure a plurality of pages. In one embodiment, a page can be a unit for storing data in or reading data stored in the memory device 100. A memory block can be a unit for erasing data.

[0037] In one embodiment, the memory device 100 can be a double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc. In this specification, for convenience of description, it is assumed that the memory device 100 is a NAND flash memory.

[0038] The memory device 100 can be implemented in a two-dimensional array structure or a three-dimensional array structure. Hereinafter, a three-dimensional array structure is described as an example, but the present disclosure is not limited to the three-dimensional array structure. The present disclosure can be applied not only to a flash memory device in which a charge storage layer is configured by a conductive floating gate (FG), but also to a charge trapping flash (CTF) in which a charge storage layer is configured by an insulating film.

[0039] In one embodiment, the memory device 100 may operate in a single-level cell (SLC) method, in which one data bit is stored in one memory cell. Alternatively, the memory device 100 may operate in a method of storing at least two data bits in one memory cell. For example, the memory device 100 may operate in the following methods: a multi-level cell (MLC) method of storing two data bits in one memory cell, a triple-level cell (TLC) method of storing three data bits in one memory cell, or a quad-level cell (QLC) method of storing four data bits in one memory cell.

[0040] The memory device 100 is configured to receive commands and addresses from the memory controller 200 and access a region selected by the address in the memory cell array. That is, the memory device 100 may perform an operation corresponding to the command on the region selected by the address. For example, the memory device 100 may perform a write operation (programming operation), a read operation, or an erase operation according to the received command. For example, when a program command is received, the memory device 100 may program data into the region selected by the address. When a read command is received, the memory device 100 may read data from the region selected by the address. When an erase command is received, the memory device 100 may erase the data stored in the region selected by the address.

[0041] In one embodiment, the memory device 100 may include a word line controller 150. When the memory device 100 performs a sensing operation, the word line controller 150 may control the voltages applied to the selected word line and the unselected word lines. Here, the sensing operation may be a read operation or a verify operation among the operations included in a programming cycle.

[0042] For example, during the sensing operation, a sensing voltage may be applied to the selected word line, and a pass voltage may be applied to the unselected word lines. Thereafter, when the sensing is completed, an equalization operation may be performed. The equalization operation may be an operation of setting the potentials of the selected word line and the unselected word lines to be the same. That is, after applying the sensing voltage to the selected word line and the pass voltage to the unselected word lines, the selected word line and the unselected word lines may be simultaneously discharged in a state where the potentials of the selected word line and the unselected word lines are set to be the same. As used herein, the words "simultaneously" and "at the same time" with respect to events mean that the events occur in overlapping time intervals. For example, if a first event occurs within a first time interval and a second event occurs at the same time within a second time interval, then the first interval and the second interval at least partially overlap each other such that there is a time when both the first event and the second event occur.

[0043] Since the selected word lines and the unselected word lines are discharged simultaneously, the potentials of the selected word lines and the unselected word lines can be simultaneously changed to the ground voltage level. Therefore, due to the discharge of the selected word lines and the unselected word lines, the change in the potentials of the selected word lines and the unselected word lines can be prevented or, in some embodiments, mitigated.

[0044] In one embodiment, during the equalization operation, the word line controller 150 may control the potentials of the selected word lines and the unselected word lines to be the same by increasing the voltage of the selected word lines and decreasing the voltage of the unselected word lines.

[0045] In one embodiment, the memory device 100 may include a drain select line controller 160 and a source select line controller 170. During the sensing operation, the drain select line controller 160 may control the voltage applied to the drain select lines among the lines connected to the memory block, and the source select line controller 170 may control the voltage applied to the source select lines among the lines connected to the memory block.

[0046] For example, the drain select line controller 160 may control the application of the voltage to be applied to the drain select lines by dividing the drain select lines into two different groups. For example, the two groups may be the selected drain select lines and the unselected drain select lines. Then, based on which group the drain select line is in, the drain select line controller 160 may apply the voltage assigned to that group. In one embodiment, the drain select lines may be divided into more than two different groups.

[0047] For example, the drain select line controller 160 may apply, during the sensing operation, a voltage for turning on the transistors connected to the selected drain select lines to the selected drain select lines. The drain select line controller 160 may control the voltage applied to the selected drain select lines to be maintained until a preset time after the equalization operation.

[0048] In addition, the drain select line controller 160 may control the voltage applied to the unselected drain select lines according to whether the unselected drain select lines share a cell string with the selected drain select lines. At this time, the selected drain select lines and the unselected drain select lines sharing a cell string may be lines connected to the cell string through one source select line, and the selected drain select lines and the unselected drain select lines not sharing a cell string may be lines not connected to the cell string through one source select line.

[0049] For example, during a sensing operation, when a non-selected drain select line shares a cell string with a selected drain select line, the drain select line controller 160 may sequentially lower the voltage of the non-selected drain select line. However, when a non-selected drain select line does not share a cell string with a selected drain select line, the drain select line controller 160 may apply a voltage to the non-selected drain select line only while a sensing voltage is applied to the selected word line.

[0050] In one embodiment, during a sensing operation, the source select line controller 170 may apply a voltage for turning on a transistor connected to the selected source select line to the selected source select line. The source select line controller 170 may control the voltage applied to the selected source select line to be maintained until a preset time after an equalization operation.

[0051] In one embodiment, the memory device 100 may include a dummy line controller 180. When the drain select line controller 160 applies a voltage to a non-selected drain select line that does not share a cell string with the selected drain select line, the dummy line controller 180 may apply a voltage for turning off a dummy memory cell connected to a dummy line.

[0052] The memory controller 200 may control the overall operation of the storage device 50.

[0053] When a power voltage is applied to the storage device 50, the memory controller 200 may execute firmware. When the memory device 100 is a flash memory device 100, the memory controller 200 may operate firmware such as a flash translation layer (FTL) to control communication between the host 300 and the memory device 100.

[0054] In one embodiment, the memory controller 200 may include firmware (not shown) that may receive data and a logical block address (LBA) from the host 300 and convert the LBA into a physical block address (PBA), where the PBA indicates an address of a memory cell in which data included in the memory device 100 is to be stored. In addition, the memory controller 200 may store a logical-physical address mapping table that configures a mapping relationship between the LBA and the PBA in a buffer memory.

[0055] The memory controller 200 may control the memory device 100 to perform programming operations, read operations, erase operations, etc. according to requests from the host 300. For example, when a programming request is received from the host 300, the memory controller 200 may transform the programming request into a programming command and may provide the programming command, PBA, and data to the memory device 100. When a read request together with an LBA is received from the host 300, the memory controller 200 may change the read request into a read command, select a PBA corresponding to the LBA, and then provide the read command and the PBA to the memory device 100. When an erase request together with an LBA is received from the host 300, the memory controller 200 may change the erase request into an erase command, select a PBA corresponding to the LBA, and then provide the erase command and the PBA to the memory device 100.

[0056] In one embodiment, the memory controller 200 may generate a programming command, an address, and data without a request from the host 300 and may transmit the programming command, the address, and the data to the memory device 100. For example, the memory controller 200 may provide a command, an address, and data to the memory device 100 to perform background operations such as programming operations for wear leveling and programming operations for garbage collection.

[0057] In one embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control the data exchange between the host 300 and the buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store the data input from the host 300 in the buffer memory and then transmit the data temporarily stored in the buffer memory to the memory device 100.

[0058] In various embodiments, the buffer memory may serve as an operating memory and a cache memory of the memory controller 200. The buffer memory may store codes or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

[0059] In one embodiment, the buffer memory may be implemented as a dynamic random access memory (DRAM) or a static random access memory (SRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), DDR4 SDRAM, low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR), or Rambus dynamic random access memory (DRAM).

[0060] In various embodiments, the buffer memory may be connected from outside the storage device 50. In this case, a volatile memory device connected to the outside of the storage device 50 may be used as the buffer memory.

[0061] In one embodiment, the memory controller 200 may control at least two or more memory devices. In this case, the memory controller 200 may control the memory devices according to an interleaving method to improve the operation performance.

[0062] The host 300 may communicate with the storage device 50 using at least one of various communication methods, such as Universal Serial Bus (USB), Serial ATA (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM).

[0063] Figure 2 is a diagram Figure 1 of the structure of the memory device.

[0064] Refer to Figure 2 , the memory device 100 may include a memory cell array 110, a peripheral circuit 120, and a control logic 130. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit operating according to an algorithm and / or a processor executing control logic code.

[0065] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the row decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to the page buffer group 123 through bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line may be defined as a page. Thus, one memory block may include a plurality of pages.

[0066] The row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line.

[0067] Each of the memory cells included in the memory cell array 110 may be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that stores four data bits.

[0068] The peripheral circuit 120 may be configured to perform a programming operation, a read operation, or an erase operation on a selected area of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operation voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0069] The peripheral circuit 120 may include a row decoder 121, a voltage generator 122, a page buffer group 123, a column decoder 124, an input / output circuit 125, and a sense circuit 126.

[0070] The row decoder 121 is connected to the memory cell array 110 through the row line RL. The row line RL may include at least one source selection line, a plurality of word lines, and at least one drain selection line. In one embodiment, the word lines may include normal word lines and dummy word lines. In one embodiment, the row line RL may further include a pipe selection line.

[0071] The row decoder 121 is configured to decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to at least one word line WL.

[0072] For example, during a programming operation, the row decoder 121 may apply a programming voltage to the selected word line and apply a programming pass voltage having a level lower than the programming voltage to the unselected word lines. During a programming verification operation, the row decoder 121 may apply a verification voltage to the selected word line and apply a verification pass voltage higher than the verification voltage to the unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to the selected word line and apply a read pass voltage higher than the read voltage to the unselected word lines.

[0073] In one embodiment, the erase operation of the memory device 100 is performed in units of memory blocks. During the erase operation, the row decoder 121 may select a memory block according to the decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to the word lines connected to the selected memory block.

[0074] The voltage generator 122 operates in response to the control of the control logic 130. The voltage generator 122 is configured to generate a plurality of voltages using an external power voltage supplied to the memory device 100. For example, in response to the operation signal OPSIG, the voltage generator 122 may generate various operation voltages Vop for programming, reading, and erasing operations. For example, in response to the control of the control logic 130, the voltage generator 122 may generate a programming voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc.

[0075] As one embodiment, the voltage generator 122 may generate an internal power voltage by regulating the external power voltage. The internal power voltage generated by the voltage generator 122 is used as the operation voltage of the memory device 100.

[0076] As one embodiment, the voltage generator 122 may generate a plurality of voltages using the external power voltage or the internal power voltage.

[0077] For example, the voltage generator 122 may include a plurality of pumping capacitors that receive the internal power voltage, and may selectively activate the plurality of pumping capacitors in response to the control of the control logic 130 to generate a plurality of voltages.

[0078] The generated plurality of voltages may be supplied to the memory cell array 110 through the row decoder 121.

[0079] The page buffer group 123 includes a first page buffer PB1 to an nth page buffer PBn. The first page buffer PB1 to the nth page buffer PBn are respectively connected to the memory cell array 110 through a first bit line BL1 to an nth bit line BLn. The first page buffer PB1 to the nth page buffer PBn operate in response to the control of the control logic 130. For example, the first page buffer PB1 to the nth page buffer PBn may operate in response to a page buffer control signal PBSIGNALS. For example, the first page buffer PB1 to the nth page buffer PBn may temporarily store the data received through the first bit line BL1 to the nth bit line BLn, or may sense the voltage or current of the bit lines BL1 to BLn during a read or verify operation.

[0080] For example, during a programming operation, when a programming voltage is applied to the selected word line, the first page buffer PB1 to the nth page buffer PBn may transmit the data DATA received through the input / output circuit 125 to the selected memory cells through the first bit line BL1 to the nth bit line BLn. The memory cells of the selected page are programmed according to the transmitted data DATA. During a programming verification operation, the first page buffer PB1 to the nth page buffer PBn may read the page data by sensing the voltage or current received from the selected memory cells through the first bit line BL1 to the nth bit line BLn.

[0081] During a read operation, the first page buffer PB1 to the nth page buffer PBn read the data DATA from the memory cells of the selected page through the first bit line BL1 to the nth bit line BLn, and under the control of the column decoder 124, output the read data DATA to the input / output circuit 125.

[0082] During an erase operation, the first page buffer PB1 to the nth page buffer PBn may float the first bit line BL1 to the nth bit line BLn, or apply an erase voltage.

[0083] The column decoder 124 may transmit data between the input / output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 may exchange data with the first page buffer PB1 to the nth page buffer PBn through a data line DL, or may exchange data with the input / output circuit 125 through a column line CL.

[0084] The input / output circuit 125 may transmit a command CMD and an address ADDR received from the memory controller 200 described in the reference Figure 1 described Figure 1 to the control logic 130, or may exchange data DATA with the column decoder 124.

[0085] The sensing circuit 126 may generate a reference current in response to an enable bit signal VRYBIT during a read operation or a verify operation, and compare a sensed voltage VPB received from the page buffer bank 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0086] The control logic 130 may output an operation signal OPSIG, a row address RADD, page buffer control signals PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR to control the peripheral circuit 120. For example, the control logic 130 may control a read operation of a selected memory block in response to a sub-block read command and an address. In addition, the control logic 130 may control an erase operation of a selected sub-block included in the selected memory block in response to a sub-block erase command and an address. In addition, the control logic 130 may determine whether a verify operation passes or fails in response to a pass signal PASS or a fail signal FAIL.

[0087] In one embodiment, the control logic 130 may include a word line controller 150, a drain select line controller 160, a source select line controller 170, and a dummy line controller 180. In another embodiment, the word line controller 150, the drain select line controller 160, the source select line controller 170, and the dummy line controller 180 may be located outside the control logic 130. Each of the word line controller 150, the drain select line controller 160, the source select line controller 170, and the dummy line controller 180 may output an operation signal OPSIG for controlling a voltage applied to a line, and the voltage generator 122 may generate various operation voltages Vop for a sensing operation based on the operation signal OPSIG.

[0088] In one embodiment, when the memory device 100 performs a sensing operation, the word line controller 150 may control voltages applied to a selected word line and unselected word lines. For example, the word line controller 150 may control voltages applied to a selected word line and unselected word lines during an equalization operation. Here, the equalization operation may be an operation of setting the potentials of a selected word line and unselected word lines to be the same.

[0089] In one embodiment, when the memory device 100 performs a sensing operation, the drain select line controller 160 and the source select line controller 170 may control the voltages applied to the drain select line and the source select line. For example, during the sensing operation, the drain select line controller 160 and the source select line controller 170 may control to maintain the voltages applied to each of the selected drain select line and the selected source select line for a preset time after the equalization operation. As used herein, the term "preset" with respect to a parameter such as a preset time means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0090] In addition, the drain select line controller 160 may control the voltage applied to an unselected drain select line according to whether the unselected drain select line shares a cell string with the selected drain select line. At this time, the selected drain select line and the unselected drain select line sharing the cell string may be lines connected to the cell string through a source select line, and the selected drain select line and the unselected drain select line not sharing the cell string may be lines not connected to the cell string through a source select line.

[0091] For example, during the sensing operation, the drain select line controller 160 may sequentially decrease the voltage applied to the unselected drain select line sharing the cell string with the selected drain select line.

[0092] However, in a case where the unselected drain select line does not share a cell string with the selected drain select line, the drain select line controller 160 may control the unselected drain select line such that a voltage is applied to the unselected drain select line only while a read voltage is applied to the selected word line.

[0093] In addition, during the equalization operation, the drain select line controller 160 may control the unselected drain select line such that a voltage is applied to the unselected drain select line for a preset time after the equalization operation.

[0094] In one embodiment, the dummy line controller 180 may control the dummy line such that a voltage for turning off a dummy cell connected to the dummy line is applied to the dummy line only when a voltage is applied to an unselected drain select line not sharing a cell string with the selected drain select line.

[0095] By the above operations, channel negative boost can be prevented or in some embodiments alleviated.

[0096] Figure 3 Is illustrated Figure 2Diagram of an embodiment of a memory cell array.

[0097] Reference Figure 3 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged along the +X direction, +Y direction, and +Z direction. Reference Figure 4 and Figure 5 Describe the structure of each memory block in more detail.

[0098] Figure 4 is a diagram Figure 3 of any one memory block BLKa among the memory blocks BLK1 to BLKz.

[0099] Reference Figure 4 , the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each cell string among the plurality of cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). In Figure 4 , two cell strings are arranged in the column direction (i.e., the +Y direction). However, this is for convenience of description, and it can be understood that three or more cell strings may be arranged in the column direction.

[0100] Each cell string among the plurality of cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, a pass transistor PT, and at least one drain selection transistor DST.

[0101] The source selection transistor SST of each cell string is connected between a common source line CSL and the memory cells MCl to MCp.

[0102] As an embodiment, the source selection transistors of the cell strings arranged in the same row are connected to a source selection line extending in the row direction, and the source selection transistors of the cell strings arranged in different rows are connected to different source selection lines. In Figure 4 , the source selection transistors of the cell strings CS11 to CS1m in the first row are connected to the first source selection line SSL1. The source selection transistors of the cell strings CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0103] As another embodiment, the source selection transistors of the cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0104] The first memory cell MC1 to the n-th memory cell MCn of each cell string are connected between a source selection transistor SST and a drain selection transistor DST.

[0105] The first memory cell MC1 to the n-th memory cell MCn can be divided into the first memory cell MC1 to the p-th memory cell MCp, and the (p + 1)-th memory cell MCp+1 to the n-th memory cell MCn. The first memory cell MC1 to the p-th memory cell MCp are arranged in sequence in a direction opposite to the +Z direction and are connected in series between the source selection transistor SST and a pipeline transistor PT. The (p + 1)-th memory cell MCp+1 to the n-th memory cell MCn are arranged in sequence in the +Z direction and are connected in series between the pipeline transistor PT and the drain selection transistor DST. The first memory cell MC1 to the p-th memory cell MCp and the (p + 1)-th memory cell MCp+1 to the n-th memory cell MCn are connected to each other through the pipeline transistor PT. The gates of the first memory cell MC1 to the n-th memory cell MCn of each cell string are respectively connected to the first word line WL1 to the n-th word line WLn.

[0106] The gate of the pipeline transistor PT of each cell string is connected to a pipeline line PL.

[0107] The drain selection transistor DST of each cell string is connected between a corresponding bit line and the memory cells MCp+1 to MCn. The cell strings arranged in the row direction are connected to a drain selection line extending in the row direction. The drain selection transistors of the cell strings CS11 to CS1m in the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m in the second row are connected to the second drain selection line DSL2.

[0108] The cell strings arranged in the column direction are connected to a bit line extending in the column direction. In Figure 4 the first column, the cell strings CS11 and CS21 are connected to the first bit line BL1. The cell strings CS1m and CS2m in the m-th column are connected to the m-th bit line BLm.

[0109] The memory cells connected to the same word line in the cell strings arranged in the row direction configure a page. For example, the memory cells among the cell strings CS11 to CS1m in the first row that are connected to the first word line WL1 configure a page. The memory cells among the cell strings CS21 to CS2m in the second row that are connected to the first word line WL1 configure another page. Any one of the drain selection lines DSL1 and DSL2 can be selected to select the cell strings arranged in one row direction. Any one of the word lines WL1 to WLn can be selected to select a page of the selected cell strings.

[0110] As another embodiment, even bit lines and odd bit lines may be provided to replace the first bit line BL1 to the m-th bit line BLm. In addition, the even-numbered cell strings among the cell strings CS11 to CS1m or CS21 to SC2m arranged in the row direction may be respectively connected to the even bit lines, and the odd-numbered cell strings among the cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be respectively connected to the odd bit lines.

[0111] As an embodiment, at least one memory cell among the first memory cell MC1 to the n-th memory cell MCn may be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell is provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the reliability of the operation for the memory block BLKa is improved. However, the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa may be reduced. However, the reliability of the operation for the memory block BLKa may be reduced.

[0112] To efficiently control at least one dummy memory cell, each of the dummy memory cells in the dummy memory cell may have a desired threshold voltage. Before or after the erase operation for the memory block BLKa, a program operation may be performed for all or part of the dummy memory cells. When the erase operation is performed after the program operation, the dummy memory cell may have a desired threshold voltage by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell.

[0113] Figure 5 is a diagram Figure 3 of another embodiment of any one of the memory blocks BLK1 to BLKz, the memory block BLKb.

[0114] Reference Figure 5 , the memory block BLKb includes a plurality of cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, the first memory cell MC1 to the n-th memory cell MCn, and at least one drain select transistor DST, which are stacked on a substrate (not shown) under the memory block BLK1'.

[0115] The source select transistors SST of each cell string are connected between the common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. As another embodiment, the source select transistors of the cell strings CS11' to CS1m' and CS21' to CS2m' can be commonly connected to one source select line.

[0116] The first memory cell MC1 to the nth memory cell MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell MC1 to the nth memory cell MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0117] The drain select transistor DST of each cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to the drain select lines extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0118] As a result, Figure 5 the memory block BLKb has an equivalent circuit similar to that of Figure 4 the memory block BLKa, except that the pipeline transistors PT are excluded from each cell string.

[0119] As another embodiment, even bit lines and odd bit lines can be provided in place of the first bit line BL1 to the mth bit line BLm. Further, the even-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be respectively connected to the even bit lines, and the odd-numbered cell strings among the cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction can be respectively connected to the odd bit lines.

[0120] In addition, in order to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCn, at least one of the first memory cell MC1 to the nth memory cell MCn can be used as a dummy memory cell.

[0121] Figure 6 is a diagram illustrating channel negative boosting.

[0122] Reference Figure 4 and Figure 6 , Figure 6 shows Figure 4 the first drain select line DSL1, the first source select line SSL1, and the first word lines WL1 to WLn between the first drain select line DSL1 and the first source select line SSL1. The content described in Reference Figure 6 can be applied to Figure 5 the memory block structure of Figure 4 and the memory block structure of

[0123] In one embodiment, for reasons such as Figure 2 the end of the sensing operation of the memory device 100, a turn-off voltage can be applied to the first drain select line DSL1 and the first source select line SSL1. That is, the voltage for turning off the transistors connected to the first drain select line DSL1 and the first source select line SSL1 can be applied to the first drain select line DSL1 and the first source select line SSL1.

[0124] In one embodiment, when a turn-off voltage is applied to the first drain select line DSL1 and the first source select line SSL1, the channels of the first word lines WL1 to WLn can be floated. That is, since the turn-off voltage is applied to the first drain select line DSL1 and the first source select line SSL1, the memory cells connected to the first word lines WL1 to WLn and the transistors connected to the first drain select line DSL1 and the first source select line SSL1 can be separated.

[0125] When the channels of the first word lines WL1 to WLn are floated, the charges in the channels of the first word lines WL1 to WLn can be isolated, and the channel potential can become negative. That is, a channel negative boost phenomenon may occur. This is because the gate electrodes of the memory cells are formed of polysilicon in the three-dimensional memory block structure.

[0126] In the present disclosure, in order to prevent or in some embodiments mitigate such a channel negative boost phenomenon, a method of controlling the voltages applied to the word lines, drain select lines, and source select lines is proposed.

[0127] Figure 7 is a diagram showing the channel potential and the voltage applied to the word line during the sensing operation.

[0128] Reference Figure 7 , Figure 7Shows the changes in the voltage applied to the selected word line SELECTED_WL, the voltage applied to the unselected word lines UNSELECTED_WLS, and the channel CHANNEL potential during a sensing operation on the selected word line SELECTED_WL among multiple word lines connected to a memory block.

[0129] In Figure 7 it is assumed that the sensing operation starts at t1. The sensing operation can be an operation to sense the selected word line SELECTED_WL among multiple word lines connected to a memory block. The sensing operation can be a read operation or a verify operation.

[0130] In one embodiment, Figure 2 the control logic 130 of Figure 2 can control the peripheral circuit 120 of

[0131] to perform a sensing operation by applying a sensing voltage to the selected word line SELECTED_WL and a pass voltage VPASS to the unselected word lines UNSELECTED_WLS.

[0132] In another embodiment, the voltage applied to the selected word line SELECTED_WL can be a first verify voltage. The first verify voltage can be a voltage for determining whether the selected memory cell connected to the selected word line SELECTED_WL is programmed to a target programming state. The first read voltage VREAD1 and the first verify voltage can be sensing voltages.

[0133] At t1, the voltage applied to the unselected word lines UNSELECTED_WLS can be the pass voltage VPASS. The pass voltage VPASS can be a voltage for turning on the memory cells connected to the word lines other than the selected word line SELECTED_WL. The voltage applied to the unselected word lines UNSELECTED_WLS can be maintained as the pass voltage VPASS until the sensing is completed.

[0134] At t1, after the sensing operation starts, the data programmed into the memory cells connected to the selected word line SELECTED_WL can be sensed respectively through the bit lines connected to the memory cells.

[0135] From t1 to t2, data sensed through bit lines may be stored in Figure 2 the page buffer group 123. The sensed data may be read data or verify data. The read data may be data read through bit lines to read data programmed into memory cells. The verify data may be data read through bit lines to verify whether programming for the memory cells is completed. The programming state of the memory cells may be determined based on the sensed data.

[0136] After t2, the sensing operation may end and an equalization operation may be performed. The equalization operation may be an operation of setting the potential of the selected word line SELECTED_WL and the potential of the unselected word lines UNSELECTED_WLS to be the same to discharge the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS.

[0137] In one embodiment, when discharging multiple word lines, the voltages applied to the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS are different during the sensing operation, and thus the timings when the discharging operation is completed may be different. Therefore, after the sensing operation, a voltage VPASS may be applied to the selected word line SELECTED_WL, and thus the potential of the selected word line SELECTED_WL and the potential of the unselected word lines UNSELECTED_WLS may be set to be the same.

[0138] In one embodiment, after a voltage VPASS is applied to the selected word line SELECTED_WL, from t2 to t3, the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS may be discharged simultaneously. That is, after the potential of the selected word line SELECTED_WL and the potential of the unselected word lines UNSELECTED_WLS are set to be the same to the voltage VPASS level, the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS may be discharged simultaneously.

[0139] In one embodiment, the channel CHANNEL potential may be the channel potential of multiple memory cells connected to any one of multiple cell strings, and the multiple cell strings are connected to bit lines. Before performing the sensing operation, the channel CHANNEL potential may be 0V.

[0140] At t1, the potential of the channel CHANNEL can increase briefly and then can become 0V again. For example, when a sense voltage and a pass voltage VPASS are applied to a selected word line SELECTED_WL and unselected word lines UNSELECTED_WLS respectively, channel coupling between word lines may occur. When channel coupling between word lines occurs, the potential of the channel CHANNEL can increase. After a predetermined time has passed, the increased potential of the channel CHANNEL can become 0V again.

[0141] The channel CHANNEL potential that becomes 0V again can have various potentials according to the programming state of the memory cells. That is, since multiple memory cells connected to a cell string can have various programming states, the current flowing through the multiple memory cells can be various according to the voltage applied to the word lines. As a result, the channel CHANNEL potential can have various values according to the programming states of the multiple memory cells connected to the cell string.

[0142] After the sensing operation ends (after t2), since the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS are discharged simultaneously from t2 to t3, the potential of the channel CHANNEL can be negative. At this time, the phenomenon in which the potential of the channel CHANNEL becomes negative is called channel negative boosting.

[0143] In one embodiment, since channel negative boosting occurs, a recovery operation for channel negative boosting can be performed.

[0144] That is, from t3 to t4, the potential of the channel CHANNEL can be increased by applying a recovery voltage VREC to the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS.

[0145] After the channel potential increases, the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS can be discharged, and thus the selected word line SELECTED_WL, the unselected word lines UNSELECTED_WLS, and the channel CHANNEL potential can become 0V.

[0146] During the sensing operation, due to the occurrence of channel negative boost, a recovery operation is performed, and thus the time consumed by the sensing operation can be extended. Additionally, during the recovery operation for channel negative boost, a read disturbance phenomenon may occur. That is, since the recovery voltage VREC is applied to the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS, and then the selected word line SELECTED_WL and the unselected word lines UNSELECTED_WLS are discharged, the threshold voltage distribution of the memory cells in the erased state can increase.

[0147] Therefore, in the present disclosure, a method for preventing or in some embodiments alleviating channel negative boost is proposed.

[0148] Figure 8 It is a diagram illustrating the movement and disturbance of the threshold voltage distribution according to channel negative boost.

[0149] Reference Figure 7 and Figure 8 , Figure 8 shows the influence of the channel negative boost described in reference Figure 7 .

[0150] In Figure 8 , it is assumed that the memory cells have any one of the erased state E or the first to seventh programmed states P1 to P7. That is, Figure 8 shows the change in the threshold voltage distribution when the memory cells are programmed by the triple-level cell (TLC) method.

[0151] Figure 8 It can also be applied to the case where the memory cells are programmed by the single-level cell (SLC) method, the multi-level cell (MLC) method, or the quadruple-level cell (TLC) method.

[0152] In one embodiment, hot carrier injection (HCI) can occur due to channel negative boost. Due to the occurrence of HCI, a shift PV SHIFTING and a disturbance DISTURB phenomenon of the threshold voltage distribution may occur.

[0153] Reference Figure 4 and Figure 5 , since Figure 4 and Figure 5 's drain select transistor and source select transistor are turned off, the charge in the channel is isolated, and the isolated charge is moved to the memory cells. Therefore, the threshold voltage of the memory cells in the low programmed state can increase. For example, the threshold voltage of the memory cells in the first to third programmed states P1 to P3 can increase (PV SHIFTING).

[0154] In addition, since the charge in the channel is isolated, the charge trapped in the memory cell is moved to the channel, and thus the threshold voltage of the memory cell in the high programming state can be reduced. For example, the threshold voltages of the memory cells in the fourth programming state P4 to the seventh programming state P7 can be reduced (PV SHIFTING).

[0155] Furthermore, due to the negative channel boost, coupling between the word line and the channel may occur. Therefore, when a recovery voltage is applied to the word line during a recovery operation performed after the negative channel boost, a disturbance DISTURB may occur. Due to the occurrence of the disturbance DISTURB, the threshold voltage of the memory cell in the erase state E can increase.

[0156] As a result, due to the negative channel boost and its recovery operation, the threshold voltage distribution of the memory cells is changed, and since the threshold voltage distribution is changed, the reliability of the data programmed into the memory cells may be reduced.

[0157] Figure 9 is a diagram illustrating the voltages applied to each line during a sensing operation according to the present disclosure.

[0158] Reference Figure 9 , Figure 9 shows the voltages applied to each line before and after an equalization operation to prevent or, in some embodiments, mitigate negative channel boost during a sensing operation. The equalization operation can be an operation performed when Figure 2 the memory device 100 performs a sensing operation, and can be an operation of setting the potential of the selected word line SELECTED_WL and the potential of the unselected word lines UNSELECTED_WLS to be the same after sensing. Here, the sensing operation can be a read operation or a verify operation.

[0159] In Figure 9 , it is assumed that the sensing operation is a read operation.

[0160] In one embodiment, at t11, a read operation can be started. Therefore, at t11, Figure 2 the word line controller 150 of Figure 2 the memory device 100 can be controlled such that a first read voltage VREAD1 is applied to the selected word line SELECTED_WL, and voltages VPASS are respectively applied to the unselected word lines UNSELECTED_WLS.

[0161] Here, the first read voltage VREAD1 may be a voltage for distinguishing between the erased state and the programmed state of the selected memory cells connected to the selected word line SELECTED_WL. The read operation performed using the first read voltage VREAD1 may be the first read operation. In addition, the pass voltage VPASS may be a voltage for turning on the memory cells connected to word lines other than the selected word line SELECTED_WL.

[0162] In one embodiment, at t11 to t12, a read operation may be performed by applying the first read voltage VREAD1 to the selected word line SELECTED_WL. At this time, Figure 2 the word line controller 150 may control Figure 2 the memory device 100 such that the voltage applied to the unselected word lines UNSELECTED_WLS remains at the pass voltage VPASS until sensing is completed.

[0163] In one embodiment, at t11, Figure 2 the drain select line controller 160 may control Figure 2 the memory device 100 to apply a voltage to the drain select lines by dividing the drain select lines into a selected drain select line SELECTED_DSL and an unselected drain select line UNSELECTED_DSL.

[0164] The unselected drain select line UNSELECTED_DSL may be divided according to whether the unselected drain select line UNSELECTED_DSL shares a cell string with the selected drain select line SELECTED_DSL. When the unselected drain select line UNSELECTED_DSL shares a cell string (shared string) with the selected drain select line SELECTED_DSL, channel negative boosting may occur together in the cell string due to the on or off of the transistors connected to the selected drain select line SELECTED_DSL, and thus division is required.

[0165] In addition, different levels of voltage may be applied to the unselected drain select line UNSELECTED_DSL (shared string) that shares a cell string with the selected drain select line SELECTED_DSL, and the unselected drain select line UNSELECTED_DSL (non-shared string) that does not share a cell string with the selected drain select line SELECTED_DSL.

[0166] The selected drain select line SELECTED_DSL and the unselected drain select line UNSELECTED_DSL that share a cell string will be described below by Figures 10 to 12A description will be given.

[0167] In one embodiment, Figure 2 the drain selection line controller 160 of Figure 2 the memory device 100 can control Figure 2 the source selection line controller 170 of Figure 2 the memory device 100 to apply a first turn-on voltage VON1 for turning on the drain selection transistor to the selected drain selection line SELECTED_DSL. Additionally,

[0168] In one embodiment, when the unselected drain selection line UNSELECTED_DSL shares a cell string with the selected drain selection line SELECTED_DSL, the first turn-on voltage VONl can be applied to the unselected drain selection line UNSELECTED_DSL from t11 to t13, and a second turn-on voltage VON2 can be applied to the unselected drain selection line UNSELECTED_DSL from t13 to t14. The second turn-on voltage VON2 can be a voltage lower than the first turn-on voltage VON1 and can be a voltage similar to the first turn-on voltage VON1 for turning on the drain selection transistor.

[0169] That is, the voltage applied to the unselected drain selection line UNSELECTED_DSL sharing a cell string with the selected drain selection line SELECTED_DSL can be sequentially decreased from t11 to t14. By sequentially decreasing the voltage applied to the unselected drain selection line UNSELECTED_DSL, excessive charges in the channel can be moved to the unselected drain selection line UNSELECTED_DSL.

[0170] However, when the unselected drain selection line UNSELECTED_DSL does not share a cell string (non-shared string) with the selected drain selection line SELECTED_DSL, since there is no need to move channel charges, the first turn-on voltage VON1 can be applied only from t11 to t12.

[0171] In one embodiment, after the sensing operation is performed from t11 to t15, the equalization operation can start at t15.

[0172] During the equalization operation, Figure 2The word line controller 150 can increase the potential of the selected word line SELECTED_WL from 0V to the equalization voltage VEQ, and can decrease the potential of the unselected word lines UNSELECTED_WLS from the pass voltage VPASS to the equalization voltage VEQ.

[0173] That is, different from the conventional equalization operation in which only the potential of the selected word line SELECTED_WL is increased from 0V to the pass voltage VPASS, in the present disclosure, while increasing the potential of the selected word line SELECTED_WL, the potential of the unselected word lines UNSELECTED_WLS can be decreased.

[0174] In one embodiment, Figure 2 each of the drain select line controller 160 of Figure 2 and the source select line controller 170 of

[0175] can control the memory device 100 to apply the ground voltage 0V to the selected drain select line SELECTED_DSL and the selected source select line SELECTED_SSL at t16.

[0176] That is, during the sensing operation, after the first conduction voltage VONl applied to the selected drain select line SELECTED_DSL and the selected source select line SELECTED_SSL is maintained for only a preset time t15 to t16 after the start of the equalization operation, the ground voltage 0V can be applied to the selected drain select line SELECTED_DSL and the selected source select line SELECTED_SSL.

[0177] Therefore, during the sensing operation, the charge in the floating channel can be discharged by maintaining the first conduction voltage VONl applied to the selected drain select line SELECTED_DSL and the selected source select line SELECTED_SSL for a predetermined time after the start of the equalization operation. Figure 2 In addition, in order to discharge the charge in the floating channel at t15 to t16,

[0178] the drain select line controller 160 of

[0178] At this time, when the unselected drain select line UNSELECTED_DSL does not share a cell string (non-shared string) with the selected drain select line SELECTED_DSL, the unselected drain select line UNSELECTED_DSL that does not share a cell string with the selected drain select line SELECTED_DSL is not connected to the bit line, and a sensing operation is performed on this bit line. However, according to the programming states of the memory cells in the same memory block or the memory cells of adjacent cell strings, the unselected drain select line UNSELECTED_DSL that does not share a cell string with the selected drain select line SELECTED_DSL may be affected by the channel negative boost, and the second turn-on voltage VON2 can be applied to the unselected drain select line UNSELECTED_DSL. That is, due to the possible occurrence of the downward coupling phenomenon (DCP), at t15 to t16, the second turn-on voltage VON2 can be applied to the unselected drain select line UNSELECTED_DSL, and thus, the channel charge can be moved to the unselected drain select line UNSELECTED_DSL.

[0179] In one embodiment, at t17, the word line can be discharged. By controlling the voltages applied to the drain select line and the source select line at t15 to t16, when the word line is discharged at t17, the channel negative boost can be prevented or, in some embodiments, mitigated.

[0180] Figure 10 FIG. is a diagram showing the structure of a memory block having two cell strings.

[0181] Reference Figure 2 and Figure 10 , Figure 10 shows the lines connected to one of the multiple memory blocks BLK1 to BLKz of Figure 2 .

[0182] In Figure 10 , the memory block may have a structure in which two cell strings are connected.

[0183] For example, among these two cell strings, the first cell string may be a cell string connecting the x1-th drain select line DSLx1 and the x-th source select line SSLx, and the second cell string may be a cell string connecting the x2-th drain select line DSLx2 and the x-th source select line SSLx. The x1-th drain select line DSLx1 and the x2-th drain select line DSLx2 may be connected to the x-th bit line BLx.

[0184] The first cell string and the second cell string may be connected to the word lines included in two stacks.

[0185] For example, the first unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the x-th source select line SSLx and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd STACK includes word lines connected between the x1-th drain select line DSLx1 and the center dummy line CENTER DUMMY LINE.

[0186] In addition, for example, the second unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the x-th source select line SSLx and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd STACK includes word lines connected between the x2-th drain select line DSLx2 and the center dummy line CENTER DUMMY LINE.

[0187] In one embodiment, when the x1-th drain select line DSLx1 is the selected drain select line, since the x1-th drain select line DSLx1 and the x2-th drain select line DSLx2 are connected to each string through the x-th source select line SSLx which serves as a source select line, the x2-th drain select line DSLx2 can be an unselected drain select line and can be a line sharing the unit string with the x1-th drain select line DSLx1.

[0188] Therefore, in the case of a memory block having two or more stack structures, the channel length can be increased. However, due to the increase in the channel length, even if the voltage of each line is controlled as described in the reference Figure 9 to reduce the channel negative boost, the width of the increase in the channel potential can be small.

[0189] In one embodiment, in order to increase the width of the increase in the channel potential, it is necessary to prevent or, in some embodiments, mitigate the sudden increase or decrease in the potential of the center dummy line CENTER DUMMY LINE. That is, when the dummy cells connected to the center dummy line CENTER DUMMY LINE are programmed, since the threshold voltages of adjacent memory cells may be affected, it is necessary to control the voltage applied to the center dummy line CENTER DUMMY LINE.

[0190] Figure 11 is a diagram illustrating the structure of a memory block having four unit strings.

[0191] Reference Figure 2 and Figure 11 , Figure 11 shows a line connected to one of the multiple memory blocks BLK1 to BLKz of Figure 2 .

[0192] Reference Figure 10 and Figure 11 is different from Figure 10 , Figure 11 The memory blocks of may have a structure in which four cell strings are connected.

[0193] For example, among these four cell strings, the first cell string may be a cell string connecting the y1 drain select line DSLy1 and the y source select line SSLy, the second cell string may be a cell string connecting the y2 drain select line DSLy2 and the y source select line SSLy, the third cell string may be a cell string connecting the y3 drain select line DSLy3 and the y source select line SSLy, and the fourth cell string may be a cell string connecting the y4 drain select line DSLy4 and the y source select line SSLy.

[0194] The y1 drain select line DSLy1 and the y2 drain select line DSLy2 may be connected to the y1 bit line BLy1, and the y3 drain select line DSLy3 and the y4 drain select line DSLy4 may be connected to the y2 bit line BLy2.

[0195] Similar to that described in reference Figure 10 , each of the first to fourth cell strings may be connected to word lines included in two stacks.

[0196] For example, the first cell string may be connected to the first stack 1 st STACK and the second stack 2 nd STACK. The first stack 1 st STACK includes word lines connected between the y source select line SSLy and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd STACK includes word lines connected between the y1 drain select line DSLy1 and the center dummy line CENTER DUMMY LINE.

[0197] The second cell string may be connected to the first stack 1 st STACK and the second stack 2 nd STACK. The first stack 1 st STACK includes word lines connected between the y source select line SSLy and the center dummy line CENTER DUMMY LINE, and the second stack 2nd The STACK includes word lines connected between the y2-th drain select line DSLy2 and the center dummy line CENTER DUMMY LINE.

[0198] The third unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the y-th source select line SSLy and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd The STACK includes word lines connected between the y3-th drain select line DSLy3 and the center dummy line CENTER DUMMY LINE.

[0199] The fourth unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the y-th source select line SSLy and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd The STACK includes word lines connected between the y4-th drain select line DSLy4 and the center dummy line CENTER DUMMY LINE.

[0200] In one embodiment, when the y1-th drain select line DSLy1 is the selected drain select line, since the y1-th drain select line DSLy1 to the y4-th drain select line DSLy4 are connected to each string through the y-th source select line SSLy which serves as a source select line, each of the y2-th drain select line DSLy2 to the y4-th drain select line DSLy4 can be an unselected drain select line and can be a line sharing a unit string with the y1-th drain select line DSLy1.

[0201] In addition, as referred to Figure 10 described, in the case of a memory block having two or more stack structures, due to the increase in channel length, in order to increase the increase width of the channel potential, it is necessary to mitigate or in some embodiments prevent a sudden increase or decrease in the potential of the center dummy line CENTER DUMMY LINE. Therefore, it is necessary to control the voltage applied to the center dummy line CENTER DUMMY LINE.

[0202] Figure 12 is a diagram illustrating the structure of a memory block having eight unit strings.

[0203] Refer to Figure 2 andFigure 12 , Figure 12 shows a line connected to one of the multiple memory blocks BLK1 to BLKz of Figure 2 .

[0204] Referring to Figure 10 and Figure 12 , different from Figure 10 , Figure 12 the memory block may have a structure in which eight cell strings are connected therein.

[0205] For example, the first cell string among the eight cell strings may be a cell string connecting the z1-th drain select line DSLzl and the z1-th source select line SSLzl, the second cell string may be a cell string connecting the z2-th drain select line DSLz2 and the z1-th source select line SSLz1, the third cell string may be a cell string connecting the z3-th drain select line DSLz3 and the z1-th source select line SSLz1, and the fourth cell string may be a cell string connecting the z4-th drain select line DSLz4 and the z1-th source select line SSLz1.

[0206] In addition, the fifth cell string may be a cell string connecting the z5-th drain select line DSLz5 and the z2-th source select line SSLz2, the sixth cell string may be a cell string connecting the z6-th drain select line DSLz6 and the z2-th source select line SSLz2, the seventh cell string may be a cell string connecting the z7-th drain select line DSLz7 and the z2-th source select line SSLz2, and the eighth cell string may be a cell string connecting the z8-th drain select line DSLz8 and the z2-th source select line SSLz2.

[0207] The z1-th drain select line DSLz1 to the z4-th drain select line DSLz4 may be connected to the z1-th bit line BLz1, and the z5-th drain select line DSLz5 to the z8-th drain select line DSLz8 may be connected to the z2-th bit line BLz2.

[0208] Similar to that described in reference Figure 10 , each of the first cell string to the eighth cell string may be connected to word lines included in two stacks.

[0209] For example, the first cell string may be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the z1-th source select line SSLzl and the center dummy line CENTER DUMMY LINE, and the second stack 2 ndThe STACK includes word lines connected between the z1-th drain select line DSLz1 and the center dummy line CENTER DUMMY LINE.

[0210] The second unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st The STACK includes word lines connected between the z1-th source select line SSLz1 and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd The STACK includes word lines connected between the z2-th drain select line DSLz2 and the center dummy line CENTER DUMMY LINE.

[0211] The third unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st The STACK includes word lines connected between the z1-th source select line SSLz1 and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd The STACK includes word lines connected between the z3-th drain select line DSLz3 and the center dummy line CENTER DUMMY LINE.

[0212] The fourth unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st The STACK includes word lines connected between the z1-th source select line SSLz1 and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd The STACK includes word lines connected between the z4-th drain select line DSLz4 and the center dummy line CENTER DUMMY LINE.

[0213] For example, the fifth unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st The STACK includes word lines connected between the z2-th source select line SSLz2 and the center dummy line CENTER DUMMY LINE, and the second stack 2 nd The STACK includes word lines connected between the z5-th drain select line DSLz5 and the center dummy line CENTER DUMMY LINE.

[0214] The sixth unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the z2 source selection line SSLz2 and the center dummy line CENTER DUMMY LINE, the second stack 2 nd STACK includes word lines connected between the z6 drain selection line DSLz6 and the center dummy line CENTER DUMMY LINE.

[0215] The seventh unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the z2 source selection line SSLz2 and the center dummy line CENTER DUMMY LINE, the second stack 2 nd STACK includes word lines connected between the z7 drain selection line DSLz7 and the center dummy line CENTER DUMMY LINE.

[0216] The eighth unit string can be connected to the first stack 1 st STACK and the second stack 2 nd STACK, the first stack 1 st STACK includes word lines connected between the z2 source selection line SSLz2 and the center dummy line CENTER DUMMY LINE, the second stack 2 nd STACK includes word lines connected between the z8 drain selection line DSLz8 and the center dummy line CENTER DUMMY LINE.

[0217] In one embodiment, when the z1 drain selection line DSLz1 is the selected drain selection line, since the z1 drain selection line DSLz1 to the z4 drain selection line DSLz4 are connected to each string through the z1 source selection line SSLz1 which serves as a source selection line, each of the z2 drain selection line DSLz2 to the z4 drain selection line DSLz4 can be an unselected drain selection line and can be a line sharing a unit string with the z1 drain selection line DSLz1.

[0218] However, since the z5th to z8th drain select lines DSLz5 to DSLz8 are connected to each string through the z2nd source select line SSLz2 different from the z1st source select line SSLzl, each of the z5th to z8th drain select lines DSLz5 to DSLz8 can be an unselected drain select line and can be a line that does not share a cell string with the z1st drain select line DSLz1.

[0219] In addition, as described in Figure 10 , in the case of a memory block having two or more stacked structures, due to the increase in channel length, in order to increase the increase width of the channel potential, it is necessary to prevent or in some embodiments mitigate the sudden increase or decrease in the potential of the center dummy line CENTER DUMMY LINE. Therefore, it is necessary to control the voltage applied to the center dummy line CENTER DUMMY LINE.

[0220] Figure 13 is a diagram showing the voltage additionally applied to the dummy line during the sensing operation in Figure 9 .

[0221] Referring to Figure 9 and Figure 13 , Figure 13 shows a method of additionally controlling the center dummy line CENTER DUMMY LINE, and Figure 9 the voltage control thereof, in order to prevent or in some embodiments mitigate the channel negative boost during the sensing operation.

[0222] In Figure 13 , the description that duplicates the description in Figure 9 is omitted.

[0223] Referring to Figure 10 and Figure 11 , the center dummy line CENTER DUMMY LINE can be a line located between the word lines of the first stack 1 st STACK and the word lines of the second stack 2 nd STACK, and can be a line for distinguishing the word lines of the first stack 1 st STACK and the word lines of the second stack 2 nd STACK. The number of center dummy lines CENTER DUMMY LINE can be multiple. In addition, a dummy programming operation can be performed on the dummy memory cells connected to the center dummy line CENTER DUMMY LINE.

[0224] In one embodiment, Figure 2 the dummy line controller 180 in Figure 2Memory device 100 such that when a voltage is applied to an unselected drain select line UNSELECTED_DSL (non-shared string) that does not share a cell string with the selected drain select line SELECTED_DSL, the potential of the center dummy line CENTER DUMMY LINE decreases.

[0225] That is, Figure 2 The dummy line controller 180 of can control Figure 2 Memory device 100 such that the voltage applied to the center dummy line CENTER DUMMY LINE and the voltage applied to the unselected drain select line UNSELECTED_DSL (non-shared string) that does not share a cell string with the selected drain select line SELECTED_DSL are interconnected. This is to suppress hot carrier injection (HCI) because when the memory block has a stacked structure, due to the gap between the stacks, the channel potential is changed, and due to the changed channel potential, HCI into the dummy cells connected to the stack connection (i.e., the center dummy line CENTER DUMMY LINE) may occur. In addition, this is to suppress the reduction in the discharge efficiency of the drain select line due to the increase in the channel length.

[0226] In one embodiment, before t11, a third turn-on voltage VON3 can be applied to the center dummy line CENTER DUMMY LINE. The third turn-on voltage VON3 can be a voltage for turning on the center dummy cell connected to the center dummy line CENTER DUMMY LINE.

[0227] Thereafter, the voltage applied to the center dummy line CENTER DUMMY LINE and the voltage applied to the unselected drain select line UNSELECTED_DSL (non-shared string) that does not share a cell string with the selected drain select line SELECTED_DSL are interconnected, and thus at t11 to t12, a fourth turn-on voltage VON4 can be applied to the center dummy line CENTER DUMMY LINE. The fourth turn-on voltage VON4 (e.g., a negative voltage) can be a voltage lower than the third turn-on voltage VON3 (e.g., ground voltage), and can be a voltage for turning on the center dummy cell connected to the center dummy line CENTER DUMMY LINE. In addition, the fourth turn-on voltage VON4 can be a voltage that is not affected when programming the word line adjacent to the center dummy line CENTER DUMMY LINE.

[0228] In one embodiment, during the equalization operation, the fourth turn-on voltage VON4 may be applied to the center dummy line CENTER DUMMY LINE from t15 to t16. That is, also during the equalization operation, the voltage applied to the center dummy line CENTER DUMMY LINE may be interconnected with the voltage applied to the unselected drain select line UNSELECTED_DSL (non-shared string) that does not share a cell string with the selected drain select line SELECTED_DSL.

[0229] Figure 14 FIG. is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0230] Reference Figure 14 , in step S1401, during the sensing operation, the memory device may apply a sensing voltage to the selected word line and a pass voltage to the unselected word lines. When the sensing operation is a read operation, the sensing voltage may be a read voltage, and when the sensing operation is a verify operation, the sensing voltage may be a verify voltage.

[0231] In one embodiment, when applying the sensing voltage and the pass voltage, a turn-on voltage may be applied to the selected drain select line and the selected source select line. The turn-on voltage may be a voltage that can turn on the drain select transistor connected to the selected drain select line and the source select transistor connected to the selected source select line. That is, by turning on the transistors connected to the selected drain select line and the selected source select line, the data programmed into the memory cell can be sensed through the bit line.

[0232] In step S1403, the memory device may discharge the selected word line. That is, when the data programmed into the selected memory cell is sensed by applying a sensing voltage to the selected word line, the selected word line may be discharged.

[0233] In step S1405, the memory device may delay the discharge of the selected drain select line and the selected source select line while increasing the potential of the selected word line and decreasing the potential of the unselected word lines.

[0234] For example, after the memory device senses the memory cell, an equalization operation may be performed. During the equalization operation, the potential of the selected word line and the potential of the unselected word lines may be set to be the same. Thereafter, when the potential of the selected word line and the potential of the unselected word lines are set to be the same, the selected word line and the unselected word lines may be discharged simultaneously.

[0235] In the present disclosure, during an equalization operation, a memory device may change the potential of both selected word lines and unselected word lines simultaneously, rather than changing only the potential of the selected word lines. That is, the memory device may set the potential of the selected word lines and the unselected word lines to be the same by increasing the potential of the selected word lines from the ground voltage (0V) and decreasing the potential of the unselected word lines from the pass voltage.

[0236] In addition, during the equalization operation, discharging may be delayed without discharging the selected drain select line and the selected source select line. That is, when the memory device performs a sensing operation, the memory device may maintain the conduction voltage applied to the selected drain select line and the selected source select line until a specific time after the start of the equalization operation.

[0237] By delaying the discharging of the selected drain select line and the selected source select line, the charge in the floating gate may be discharged, and the channel negative boost phenomenon may be prevented or mitigated in some embodiments.

[0238] Figure 15 is a diagram illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0239] Refer to Figure 15 , in step S1501, when the memory device applies a sensing voltage to the selected word lines and a pass voltage to the unselected word lines during a sensing operation, the memory device may determine whether the unselected drain select line shares a cell string with the selected drain select line. Here, the selected drain select line and the unselected drain select line sharing a cell string may be lines connected to the cell string through a single source select line, and the selected drain select line and the unselected drain select line not sharing a cell string may be lines not connected to the cell string through a single source select line.

[0240] When the unselected drain select line does not share a cell string with the selected drain select line (No), the operation may proceed to step S1503, and when the unselected drain select line shares a cell string with the selected drain select line (Yes), the operation may proceed to step S1505. When the unselected drain select line shares a cell string with the selected drain select line (shared string), due to the conduction or cutoff of the transistors connected to the selected drain select line, channel negative boost may occur together in the shared cell string, and thus differentiation is required.

[0241] In one embodiment, when the unselected drain select line does not share a cell string with the selected drain select line (No), in step S1503, the memory device may apply a conduction voltage to the unselected drain select line and then may lower the potential of the unselected drain select line. At this time, the voltage applied to the unselected drain select line may be applied only while the sense voltage is applied to the selected word line.

[0242] In one embodiment, when the unselected drain select line shares a cell string with the selected drain select line (Yes), in step S1505, the memory device may apply a conduction voltage to the unselected drain select line and then may sequentially lower the potential of the unselected drain select line. That is, when the unselected drain select line shares a cell string with the selected drain select line, since channel negative boosting may occur together, by sequentially lowering the potential of the unselected drain select line, the charge in the channel can be moved to the unselected drain select line side.

[0243] In one embodiment, after applying a voltage to the unselected drain select line according to whether the unselected drain select line shares a cell string with the selected drain select line, the voltage applied to the unselected drain select line may be controlled during an equalization operation.

[0244] In step S1507, after the start of the equalization operation, the memory device may apply a conduction voltage to the unselected drain select line for a preset time. At this time, regardless of whether the unselected drain select line shares a cell string with the selected drain select line, the memory device may turn on the drain select transistor connected to the unselected drain select line only for a preset time.

[0245] In one embodiment, even after the start of the equalization operation, a conduction voltage may be applied to the selected and unselected drain select lines, and thus the charge in the channel can be moved to the drain select line side. Therefore, channel negative boosting can be prevented or, in some embodiments, alleviated.

[0246] Figure 16 is a diagram Figure 1 of another embodiment of the memory controller shown.

[0247] The memory controller 1000 is connected to a host and a memory device. The memory controller 1000 is configured to access the memory device in response to a request from the host. For example, the memory controller 1000 is configured to control writes, reads, erasures, and background operations to the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive firmware for controlling the memory device.

[0248] Reference Figure 16 Figure 16 , the memory controller 1000 may include a processor 1010, a memory buffer 1020, an error correction circuit (ECC) 1030, a host interface 1040, a buffer controller (or buffer control circuit) 1050, a memory interface 1060, and a bus 1070.

[0249] The bus 1070 may be configured to provide a channel between components of the memory controller 1000.

[0250] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logical operations. The processor 1010 may communicate with an external host through the host interface 1040 and with a memory device through the memory interface 1060. In addition, the processor 1010 may communicate with the memory buffer 1020 through the buffer controller 1050. The processor 1010 may use the memory buffer 1020 as an operating memory, a cache memory, or a buffer memory to control the operation of a storage device.

[0251] The processor 1010 may perform the functions of the FTL. The processor 1010 may convert the LBA provided by the host into a PBA through the FTL. The FTL may receive the LBA and convert the LBA into a PBA by using a mapping table. The address mapping method of the flash translation layer includes various mapping methods according to mapping units. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0252] The processor 1010 is configured to randomize the data received from the host. For example, the processor 1010 may randomize the data received from the host by using a randomization seed. The randomized data is provided as data to be stored to the memory device and is programmed into the memory cell array.

[0253] The processor 1010 may perform randomization and derandomization by driving software or firmware.

[0254] The memory buffer 1020 may be used as an operating memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store the code and commands executed by the processor 1010. The memory buffer 1020 may store the data processed by the processor 1010. The memory buffer 1020 may include static RAM (SRAM) or dynamic RAM (DRAM).

[0255] The error correction circuit 1030 can perform error correction. The error correction circuit 1030 can perform error correction coding (ECC coding) based on the data to be written to the memory device through the memory interface 1060. The data subjected to error correction coding can be transmitted to the memory device through the memory interface 1060. The error correction circuit 1030 can perform error correction decoding (ECC decoding) on the data received from the memory device through the memory interface 1060. For example, the error correction circuit 1030 can be included in the memory interface 1060 as a component of the memory interface 1060.

[0256] The host interface 1040 is configured to communicate with an external host under the control of the processor 1010. The host interface 1040 can be configured to perform communication using at least one of various communication methods such as Universal Serial Bus (USB), Serial ATA (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM).

[0257] The buffer controller 1050 is configured to control the memory buffer 1020 under the control of the processor 1010.

[0258] The memory interface 1060 is configured to communicate with the memory device under the control of the processor 1010. The memory interface 1060 can convey commands, addresses, and data to the memory device through a channel.

[0259] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer controller 1050.

[0260] For example, the processor 1010 can use code to control the operation of the memory controller 1000. The processor 1010 can load the code from a non-volatile memory device (e.g., read-only memory) provided inside the memory controller 1000. As another example, the processor 1010 can load the code from the memory device through the memory interface 1060.

[0261] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transfer data within the memory controller 1000, and the control bus can be configured to transfer control information such as commands and addresses within the memory controller 1000. The data bus and the control bus can be separated from each other and can not interfere with or affect each other. The data bus can be connected to the host interface 1040, the buffer controller 1050, the error correction circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer controller 1050, the memory buffer 1020, and the memory interface 1060.

[0262] Figure 17 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0263] Refer to Figure 17 , the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0264] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 is configured to control read, write, erase, and background operations on the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory device 2200 can be implemented in the same manner as the memory device 100 described with reference to Figure 1 described Figure 1 .

[0265] As an example, the memory controller 2100 can include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error correction circuit.

[0266] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) according to a specific communication standard. As an example, the memory controller 2100 is configured to communicate with an external device through at least one of various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. As an example, the connector 2300 may be defined by at least one of the above various communication standards.

[0267] As an example, the memory device 2200 may be implemented as various non-volatile memory elements such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0268] The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), CompactFlash card (CF), SmartMedia card (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, micro MMC, or eMMC), SD card (SD, mini SD, micro SD, or SDHC), and Universal Flash Storage (UFS).

[0269] In one embodiment, the memory device 2200 may perform a sensing operation. The sensing operation may be a read operation or a verify operation. When the memory device 2200 performs the sensing operation, the memory device 2200 may control the voltage applied to a plurality of lines connected to a memory block.

[0270] For example, when the sensing operation starts, the memory device 2200 may apply a sensing voltage to a selected word line among a plurality of lines connected to the memory block and apply a pass voltage to unselected word lines. At this time, the memory device 2200 may control the voltage applied to the drain select line and the source select line among the plurality of lines connected to the memory block together.

[0271] For example, when the memory device 2200 applies a sense voltage to the selected word line, the memory device 2200 may apply a conduction voltage to the selected drain select line and the selected source select line. After the sensing operation ends and the equalization operation starts, the conduction voltage applied to the selected drain select line and the selected source select line may also be maintained for a preset time.

[0272] In addition, when the memory device 2200 applies a sense voltage to the selected word line, the memory device 2200 may control the voltage applied to the unselected drain select line based on whether the unselected drain select line shares a cell string with the selected drain select line.

[0273] For example, in the case where the unselected drain select line shares a cell string with the selected drain select line, the memory device 2200 may sequentially reduce the conduction voltage applied to the unselected drain select line. By sequentially reducing the conduction voltage applied to the unselected drain select line, the charge in the channel can be moved to the unselected drain select line side, and thus channel negative boost can be prevented or mitigated in some embodiments.

[0274] In the case where the unselected drain select line does not share a cell string with the selected drain select line, the memory device 2200 may apply the conduction voltage applied to the unselected drain select line only while the sense voltage is applied to the selected word line.

[0275] In one embodiment, when the memory device 2200 performs an equalization operation after a sensing operation, the memory device 2200 may control the voltages applied to the multiple lines connected to the memory block.

[0276] For example, when the equalization operation starts, the memory device 2200 may control the potential of the selected word line and the potential of the unselected word line to be the same by increasing the potential of the selected word line among the multiple lines connected to the memory block from 0V to the equalization voltage level and decreasing the potential of the unselected word line from the pass voltage level to the equalization voltage level. At this time, the memory device 2200 may control the voltage applied to the unselected drain select line among the multiple lines connected to the memory block together.

[0277] For example, when the memory device 2200 sets the potential of the selected word line and the potential of the unselected word line to be the same, the memory device 2200 may apply a conduction voltage to the unselected drain select line for a preset time. That is, in the case where the potential of the word line increases or decreases during the equalization operation, by turning on the drain select transistor connected to the unselected drain select line, the charge in the channel can be moved to the unselected drain select line side.

[0278] In one embodiment, the memory device 2200 may control the voltage applied to the center dummy line. The center dummy line may be a line connecting to a cell string between stacks in two or more stack structures.

[0279] The memory device 2200 may control the voltage applied to the center dummy line to be interconnected with the voltage applied to an unselected drain select line that does not share a cell string with the selected drain select line. For example, when a turn-on voltage is applied to an unselected drain select line that does not share a cell string with the selected drain select line, the voltage applied to the center dummy line may be reduced.

[0280] Figure 18 is a block diagram illustrating, for example, a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0281] Reference Figure 18 , the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power device 3230, and a buffer memory 3240.

[0282] In one embodiment, the SSD controller 3210 may perform the functions of the memory controller 200 described with reference to Figure 1 described Figure 1 .

[0283] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to the signal SIG received from the host 3100. As an example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0284] The auxiliary power device 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power device 3230 can receive power PWR from the host 3100 and can be charged with this power. When the power supply from the host 3100 is not smooth, the auxiliary power device 3230 can supply power to the SSD 3200. As an example, the auxiliary power device 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power device 3230 can be located on the main board and can supply auxiliary power to the SSD 3200.

[0285] The buffer memory 3240 serves as the buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0286] In one embodiment, the SSD 3200 can perform a sensing operation on the plurality of flash memories 3221 to 322n. The sensing operation can be a read operation or a verify operation. When the SSD 3200 performs the sensing operation, the SSD 3200 can control the voltage applied to the plurality of lines connected to the memory blocks included in the plurality of flash memories 3221 to 322n.

[0287] For example, when the sensing operation starts, the SSD 3200 can apply a sensing voltage to the selected word line among the plurality of lines connected to the memory block, and apply a pass voltage to the unselected word lines. At this time, the SSD 3200 can control the voltage applied to the drain select line and the source select line among the plurality of lines connected to the memory block together.

[0288] For example, when the SSD 3200 applies a sensing voltage to the selected word line, the SSD 3200 can apply a conduction voltage to the selected drain select line and the selected source select line. After the sensing operation ends and the equalization operation starts, the conduction voltage applied to the selected drain select line and the selected source select line can also be maintained for a preset time.

[0289] In addition, when the SSD 3200 applies a sensing voltage to the selected word line, the SSD 3200 can control the voltage applied to the unselected drain select line based on whether the unselected drain select line shares a cell string with the selected drain select line.

[0290] For example, in a case where an unselected drain selection line shares a cell string with a selected drain selection line, the SSD3200 may sequentially lower the conduction voltage applied to the unselected drain selection line. By sequentially lowering the conduction voltage applied to the unselected drain selection line, charges in the channel may be moved to the unselected drain selection line side, and thus channel negative boost may be prevented or alleviated in some embodiments.

[0291] In a case where an unselected drain selection line does not share a cell string with a selected drain selection line, the SSD3200 may apply a conduction voltage to the unselected drain selection line only while a sense voltage is applied to the selected word line.

[0292] In one embodiment, when the SSD 3200 performs an equalization operation after a sensing operation, the SSD 3200 may control the voltages applied to a plurality of lines connected to a memory block.

[0293] For example, when the equalization operation starts, the SSD 3200 may control the potential of a selected word line among a plurality of lines connected to the memory block to be the same as the potential of an unselected word line by increasing the potential of the selected word line from 0V to an equalization voltage level and decreasing the potential of the unselected word line from a pass voltage level to the equalization voltage level. At this time, the SSD 3200 may control the voltage applied to an unselected drain selection line among a plurality of lines connected to the memory block together.

[0294] For example, when the SSD 3200 sets the potential of a selected word line and the potential of an unselected word line to be the same, the SSD 3200 may apply a conduction voltage to the unselected drain selection line for a preset time. That is, in a case where the potential of the word line increases or decreases during the equalization operation, charges in the channel may be moved to the unselected drain selection line side by turning on a drain selection transistor connected to the unselected drain selection line.

[0295] In one embodiment, the SSD 3200 may control the voltage applied to a center dummy line. The center dummy line may be a line connected to a cell string between stacks in two or more stack structures.

[0296] The SSD 3200 may control the voltage applied to the center dummy line to be interconnected with the voltage applied to an unselected drain selection line that does not share a cell string with a selected drain selection line. For example, when a conduction voltage is applied to an unselected drain selection line that does not share a cell string with a selected drain selection line, the voltage applied to the center dummy line may be lowered.

[0297] Figure 19 is a block diagram of a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0298] Referring Figure 19 , the user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0299] The application processor 4100 may drive components, an operating system (OS), user programs, etc. included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphics engine, etc. that control components included in the user system 4000. The application processor 4100 may be provided as a system on a chip (SoC).

[0300] The memory module 4200 may operate as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on package on package (POP) and provided as a semiconductor package.

[0301] The network module 4300 may communicate with external devices. For example, the network module 4300 may support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, Wimax, WLAN, UWB, Bluetooth, and WI-FI. For example, the network module 4300 may be included in the application processor 4100.

[0302] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transfer the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 can be implemented as a non-volatile semiconductor memory element, such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash memory, NOR flash memory, and 3D NAND flash memory. For example, the storage module 4400 can be provided as a removable storage device (removable drive) of the user system 4000 (such as a memory card) and an external drive.

[0303] For example, the storage module 4400 can include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices can operate in the same manner as the memory devices described with reference to Figures 2 to 5 The storage module 4400 can operate in the same manner as the storage device 50 described with reference to Figure 1 described.

[0304] The user interface 4500 can include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 can include a user input interface, such as a keyboard, keypad, button, touch panel, touch screen, touch pad, trackball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric element. The user interface 4500 can include a user output interface, such as a liquid crystal display (LCD), organic light emitting diode (OLED) display device, active matrix OLED (AMOLED) display device, LED, speaker, and monitor.

[0305] In one embodiment, the storage module 4400 can perform a sensing operation. The sensing operation can be a read operation or a verify operation. When the storage module 4400 performs the sensing operation, the storage module 4400 can control the voltage applied to a plurality of lines connected to the memory blocks included in the storage module 4400.

[0306] For example, when the sensing operation starts, the storage module 4400 can apply a sensing voltage to a selected word line among the plurality of lines connected to the memory block, and apply a pass voltage to the unselected word lines. At this time, the storage module 4400 can control the voltage applied to the drain select line and the source select line among the plurality of lines connected to the memory block together.

[0307] For example, when the storage module 4400 applies a sense voltage to the selected word line, the storage module 4400 may apply a conduction voltage to the selected drain select line and the selected source select line. After the sensing operation ends and the equalization operation starts, the conduction voltage applied to the selected drain select line and the selected source select line may also be maintained for a preset time.

[0308] In addition, when the storage module 4400 applies a sense voltage to the selected word line, the storage module 4400 may control the voltage applied to the unselected drain select line based on whether the unselected drain select line shares a cell string with the selected drain select line.

[0309] For example, in the case where the unselected drain select line shares a cell string with the selected drain select line, the storage module 4400 may sequentially reduce the conduction voltage applied to the unselected drain select line. By sequentially reducing the conduction voltage applied to the unselected drain select line, the charge in the channel can be moved to the unselected drain select line side, and thus channel negative boost can be prevented or alleviated in some embodiments.

[0310] In the case where the unselected drain select line does not share a cell string with the selected drain select line, the storage module 4400 may apply the conduction voltage applied to the unselected drain select line only while the sense voltage is applied to the selected word line.

[0311] In one embodiment, when the storage module 4400 performs an equalization operation after a sensing operation, the storage module 4400 may control the voltage applied to a plurality of lines connected to the memory block.

[0312] For example, when the equalization operation starts, the storage module 4400 may control the potential of the selected word line and the unselected word line to be the same by increasing the potential of the selected word line among the plurality of lines connected to the memory block from 0V to the equalization voltage level and decreasing the potential of the unselected word line from the pass voltage level to the equalization voltage level. At this time, the storage module 4400 may jointly control the voltage applied to the unselected drain select line among the plurality of lines connected to the memory block.

[0313] For example, when the storage module 4400 sets the potential of the selected word line and the unselected word line to be the same, the storage module 4400 may apply a conduction voltage to the unselected drain select line for a preset time. That is, in a case where the potential of the word line increases or decreases during the equalization operation, by turning on the drain select transistor connected to the unselected drain select line, the charge in the channel can be moved to the unselected drain select line side.

[0314] In one embodiment, the storage module 4400 may control the voltage applied to the center dummy line. The center dummy line may be a line connected to a cell string between stacks in two or more stacked structures.

[0315] The storage module 4400 may control the voltage applied to the center dummy line to be interconnected with the voltage applied to an unselected drain select line that does not share a cell string with the selected drain select line. For example, when a turn-on voltage is applied to an unselected drain select line that does not share a cell string with the selected drain select line, the voltage applied to the center dummy line may be reduced.

Claims

1. A memory device, comprising: A memory block connected to a plurality of lines; Peripheral circuitry configured to perform a sensing operation on selected memory cells connected to a selected word line among the plurality of lines; And Control logic configured to control voltages applied to a drain select line, a source select line, and a word line between the drain select line and the source select line among the plurality of lines during the sensing operation and during an equalization operation performed after the sensing operation, wherein the equalization operation is an operation of setting the potentials of the selected word line and unselected word lines among the word lines identically, Wherein during the sensing operation, the control logic controls the voltage applied to an unselected drain select line based on whether the unselected drain select line shares a cell string with a selected drain select line among the drain select lines, and wherein the selected drain select line and the unselected drain select line sharing the cell string are lines connected to the cell string through a source select line.

2. The memory device according to claim 1, wherein the sensing operation is a read operation or a verify operation.

3. The memory device according to claim 1, wherein the unselected drain select line sharing the cell string with the selected drain select line shares the cell string with the selected drain select line through the same source select line.

4. The memory device according to claim 1, wherein when the unselected drain select line is a line other than the line sharing the cell string with the selected drain select line, the control logic controls to apply a conduction voltage for turning on a transistor connected to the unselected drain select line only when a sensing voltage is applied to the selected word line.

5. The memory device according to claim 1, wherein when the unselected drain select line is a line sharing the cell string with the selected drain select line, the control logic sequentially reduces the conduction voltage for turning on transistors respectively connected to the unselected drain select line from when the sensing voltage is applied to the selected word line.

6. The memory device according to claim 1, wherein from when the sensing voltage is applied to the selected word line until a preset first time after the start of the equalization operation, the control logic controls to apply a conduction voltage for turning on transistors respectively connected to the selected drain select line among the drain select lines and the selected source select line among the source select lines.

7. The memory device according to claim 1, wherein during the equalization operation, the control logic increases the voltage of the selected word line from the ground voltage to a first voltage, and decreases the voltage of the unselected word lines among the word lines other than the selected word line from a pass voltage to the first voltage, the pass voltage being applied during the sensing operation.

8. The memory device according to claim 1, wherein during the equalization operation, the control logic controls to apply a conduction voltage to the drain select line for a preset second time, the conduction voltage being for turning on the drain select transistors respectively connected to the drain select line.

9. The memory device according to claim 1, wherein when the memory block has a plurality of stacked structures, the line in the middle of the word line is a center dummy line, and during the sensing operation and the equalization operation, the control logic controls the voltage applied to the center dummy line according to the voltage applied to the unselected drain select lines among the drain select lines other than the line sharing the cell string with the selected drain select line among the drain select lines.

10. The memory device according to claim 9, wherein when a conduction voltage is applied to the unselected drain select lines other than the line sharing the cell string with the selected drain select line, the control logic decreases the voltage applied to the center dummy line.

11. A memory device, comprising: a memory block connected to a plurality of lines; a peripheral circuit configured to perform a sensing operation on selected memory cells, the selected memory cells being connected to a selected word line among the plurality of lines; a drain select line controller configured to control the voltage applied to a drain select line among the plurality of lines during the sensing operation and during an equalization operation performed after the sensing operation, wherein the equalization operation is an operation of setting the potentials of the selected word line and the unselected word lines among the plurality of lines to be the same; a source select line controller configured to control the voltage applied to a source select line among the plurality of lines; a word line controller configured to control the voltage applied to a word line among the plurality of lines between the drain select line and the source select line; and a dummy line controller configured to control the voltage applied to a center dummy line when the memory block has a plurality of stacked structures, the center dummy line being located in the middle of the word line, wherein during the sensing operation, the drain select line controller controls the voltage applied to the unselected drain select line according to whether the unselected drain select line shares a cell string with the selected drain select line among the drain select lines, wherein the selected drain select line and the unselected drain select line sharing the cell string are lines connected to the cell string through a source select line.

12. The memory device according to claim 11, wherein when the unselected drain selection line is a line other than the line sharing the cell string with the selected drain selection line, the drain selection line controller controls to apply a conduction voltage for turning on the transistor connected to the unselected drain selection line only when a sense voltage is applied to the selected word line.

13. The memory device according to claim 11, wherein when the unselected drain selection line is a line sharing the cell string with the selected drain selection line, the drain selection line controller sequentially reduces the conduction voltage for turning on the transistors respectively connected to the unselected drain selection lines from when the sense voltage is applied to the selected word line.

14. The memory device according to claim 11, wherein from when the sense voltage is applied to the selected word line until a preset third time after the start of the equalization operation, the drain selection line controller controls to apply a conduction voltage for turning on the transistor connected to the selected drain selection line among the drain selection lines to the selected drain selection line, and the source selection line controller controls to apply a conduction voltage for turning on the transistor connected to the selected source selection line among the source selection lines to the selected source selection line.

15. The memory device according to claim 11, wherein during the equalization operation, the drain selection line controller controls to apply a conduction voltage to the drain selection line for a preset fourth time, the conduction voltage being for turning on the drain selection transistors respectively connected to the drain selection lines.

16. The memory device according to claim 11, wherein during the sense operation and the equalization operation, the dummy line controller controls the voltage applied to the center dummy line according to the voltage applied to the unselected drain selection lines other than the lines sharing the cell string with the selected drain selection line among the drain selection lines.

17. The memory device according to claim 16, wherein when a conduction voltage is applied to the unselected drain selection lines other than the line sharing the cell string with the selected drain selection line, the dummy line controller reduces the voltage applied to the center dummy line.

18. A method of operating a memory device, the memory device including memory blocks connected to a plurality of lines, the method comprising: applying a sense voltage to a selected word line among the plurality of lines and applying a pass voltage to unselected word lines among the plurality of lines to perform a sense operation of sensing a selected memory cell connected to the selected word line among the plurality of lines; and applying a voltage to a drain selection line among the plurality of lines when the sense voltage and the pass voltage are applied. Among them, according to whether the unselected drain selection line shares a cell string with the selected drain selection line among the drain selection lines, the voltage applied to the unselected drain selection line is set differently, and the selected drain selection line and the unselected drain selection line that share the cell string are lines connected to the cell string through one source selection line among the multiple lines.

19. The method according to claim 18, wherein in applying the voltage to the drain selection line, when the unselected drain selection line is a line other than the line that shares the cell string with the selected drain selection line, the conduction voltage for turning on the transistor connected to the unselected drain selection line is applied only when a sense voltage is applied to the selected word line, and when the unselected drain selection line is the line that shares the cell string with the selected drain selection line, starting from when the sense voltage is applied to the selected word line, the conduction voltage applied to the unselected drain selection line is sequentially decreased.

20. The method according to claim 18, wherein starting from when the sense voltage is applied to the selected word line, until a preset fifth time after the start of an equalization operation performed after the sensing operation, the conduction voltage for turning on the transistors respectively connected to the selected drain selection line and the selected source selection line is applied to the selected source selection line among the selected drain selection line and the source selection line, and during the equalization operation, during the fifth time, the conduction voltage is applied to the drain selection line.

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