Passivation layer for integrated circuit devices providing a barrier to moisture and protons

Abstract

Embodiments of the present disclosure relate to a passivation layer for an integrated circuit device that provides a moisture and proton barrier. An integrated circuit device includes a metal contact and a passivation layer that extends on the sidewalls of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is composed of a layer stack including: a tetraethyl orthosilicate (TEOS) layer; a phosphorus-doped TEOS (PTEOS) layer on top of the TEOS layer; and a silicon-rich nitride layer located on top of the PTEOS layer. The TEOS and PTEOS layers extend over a first surface portion of a top surface of the metal contact, but do not extend over a second surface portion. The silicon-rich nitride layer extends over the first and second surface portions and is in contact with the second surface portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 126,096, filed on December 16, 2020, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates generally to integrated circuit devices, and in particular to a passivation layer for such integrated circuit devices that provides a barrier to the intrusion of contaminants, such as moisture and protons. Background Art

[0004] refer to Figure 1 , which shows a cross section of a portion of an integrated circuit device 10. The device shown in this embodiment is, for example, a discrete power transistor of the vertical gate n-channel MOSFET type.

[0005] The semiconductor substrate 12 is lightly doped with a first type of dopant (e.g., N-type). The semiconductor substrate 12 includes a top surface 14 and a bottom surface 16. A peripheral edge surface 18 of the semiconductor substrate 12 connects the top surface 14 and the bottom surface 16. The semiconductor substrate 12 forms a drain region of a discrete power transistor. A metal layer 58 at the bottom surface 16 provides a drain (D) electrical contact. The metal layer 58 can be, for example, composed of a layer stack including: a titanium (Ti) layer; a nickel (Ni) or nickel-vanadium alloy (NiV) layer; and a silver (Ag) or gold (Au) layer.

[0006] A plurality of trenches 20 extend from the top surface 14 into the semiconductor substrate 12. The depth of the trenches 20 is less than the thickness of the semiconductor substrate 12. In one embodiment, each trench 20 has a width (extending in the plane of the cross section) and a length (extending perpendicular to the width and in and out of the cross section in the plane). In one embodiment, the length is significantly greater than the width, so each trench 20 is a strip-shaped trench extending in and out of the cross section and having a rectangular shape in a top view. Each trench 20 is lined with an insulating liner 22, and the remainder of each trench is filled with an electrical conductor 24 that forms a gate electrode of a discrete power transistor. In one embodiment, the insulating liner 22 is made of a dielectric material, such as an oxide, and the electrical conductor 24 is made of a conductive material, such as polysilicon (which may be doped with a suitable dopant species / type if desired).

[0007] The semiconductor substrate 12 further includes a first semiconductor well 26 doped with a second type of dopant (eg, P-type). The first semiconductor well 26 has a depth extending from the top surface 14 that is less than the depth of the trench 20. The first semiconductor well 26 forms the body (channel) region of the discrete power transistor.

[0008] The peripheral termination region PR at the periphery of the semiconductor substrate 12 includes a second semiconductor well 27 doped with a second type of dopant (e.g., P-type). The second semiconductor well 27 has a depth extending from the top surface 14 that is greater than the depth of the trench 20. The second semiconductor well 27 forms a ring region of a discrete power transistor.

[0009] The semiconductor substrate 12 also includes a semiconductor region 28 doped with a first type of dopant. The semiconductor region 28 has a depth extending from the top surface 14 that is less than the depth of the semiconductor well 26. The semiconductor region 28 forms a source region of a discrete power transistor. The semiconductor region 28 does not extend across the entire top surface 14 of the semiconductor substrate 12, but exists only in an active region AR that generally corresponds to the region where the trench 20 exists.

[0010] A field oxide region 30 is provided at the top surface 14 of the semiconductor substrate 12, in the peripheral region PR outside the active region AR, and adjacent to the peripheral edge surface 18. The field oxide region 30 may, for example, surround the active region AR.

[0011] A pre-metallization dielectric layer 32 is deposited to cover the top surface 14 of the semiconductor substrate 12 and the oxidized regions 30. The pre-metallization dielectric layer 32 may be made of a dielectric material, such as tetraethyl orthosilicate (tetraethoxysilane-TEOS). In one embodiment, the pre-metallization dielectric layer 32 may include a layer stack including a TEOS layer covering the top surface 14 of the semiconductor substrate 12 and the oxidized regions 30 and a boron and phosphorus doped TEOS (BPTEOS) layer covering the TEOS layer. In another embodiment, the pre-metallization dielectric layer 32 may include a layer stack including a TEOS layer covering the top surface 14 of the semiconductor substrate 12 and the oxidized regions 30 and a phosphorus doped TEOS (PTEOS) layer covering the TEOS layer.

[0012] A plurality of trenches 34 extend through the pre-metallization dielectric layer 32 and into the semiconductor substrate 12. The depth of the trenches 34 is less than the depth of the semiconductor well 26 and greater than the depth of the semiconductor region 28. Therefore, the trenches 34 extend completely through the pre-metallization dielectric layer 32 and the semiconductor region 28, and partially into the semiconductor well 26. In one embodiment, each trench 34 has a width (extending in the plane of the cross section) and a length (extending perpendicular to the width and in and out of the cross section in the plane). In one embodiment, the length is significantly greater than the width, so each trench 34 is a strip-shaped trench extending in and out of the cross section and having a rectangular shape in a top view. Each trench 34 is located between two trenches 20 (and extends parallel to the two trenches). The upper surface of the pre-metallization dielectric layer 32 and the sidewalls and bottom of each trench 34 are lined with a layer stack 36, which includes, for example, a thin metal layer and a thin metal nitride layer. The thin metal layer can be made of titanium, for example, and the thin metal nitride layer can be made of titanium nitride (TiN) material, for example. The remainder of each trench 34 is filled with an electrical conductor 38 forming the source and body contacts of the discrete power transistor. The electrical conductor 38 may be made of a tungsten (W) material, for example.

[0013] A first metal layer 42 is deposited over the thin metal nitride layer 36. The first metal layer 42 may be made of titanium (Ti), for example.

[0014] A second metal layer 44 is deposited over the first metal layer 42. The second metal layer 44 may be made of, for example, aluminum (Al) or an alloy of copper and aluminum (AlCu).

[0015] Second metal layer 44 , first metal layer 42 , and metal / metal nitride layer stack 36 are photolithographically patterned to define a source (S) electrical contact 46 and a gate (G) electrical contact 48 .

[0016] In areas where source (S) electrical contacts 46 and gate (G) electrical contacts 48 are not present, photolithographic patterning exposes the top surface of pre-metallization dielectric layer 32. Passivation layer 50 is deposited on the exposed upper surfaces of source (S) electrical contacts 46, gate (G) electrical contacts 48, and pre-metallization dielectric layer 32. Details of the configuration of passivation layer 50 at source (S) electrical contacts 46 and gate (G) electrical contacts 48 are shown in FIG. Figure 2 In one embodiment, the passivation layer 50 may include a TEOS layer 50a, or a silicon nitride (SiN) layer 50b, or a layer stack including the TEOS layer 50a and the silicon nitride (SiN) layer 50b. The TEOS layer 50a may have, for example, a thickness of about and the SiN layer 50b may have a thickness of, for example, approximately The passivation layer 50 is photolithographically patterned to form openings that expose the upper surfaces of the source (S) electrical contact 46 and the gate (G) electrical contact 48 .

[0017] The passivation layer 50 is provided to inhibit the intrusion of contaminants such as moisture and protons. However, stress may cause cracks to form in the passivation layer 50. Contaminants may enter through the cracks and cause device failures. For example, moisture penetration may cause temperature humidity deviation (THB) reliability failures, and proton intrusion may cause high temperature reverse bias (HTRB) reliability failures.

[0018] There is a need in the art for a passivation layer that can provide an improved barrier to the intrusion of contaminants such as moisture and protons. Summary of the invention

[0019] In one embodiment, an integrated circuit device includes: a metal contact having a top surface and sidewalls, the top surface of the metal contact including a first surface portion, a second surface portion, and a third surface portion; a passivation layer extending on the sidewalls of the metal contact and on the first and second surface portions of the top surface of the metal contact.

[0020] The passivation layer includes a layer stack including: a tetraethyl orthosilicate (TEOS) layer; a phosphorus-doped TEOS (PTEOS) layer on top of the TEOS layer; and a high-density silicon-rich nitride layer on top of the PTEOS layer.

[0021] The TEOS layer and the PTEOS layer extend over a first surface portion of the top surface of the metal contact but do not extend over a second and a third surface portion of the top surface of the metal contact.

[0022] The high-density silicon-rich nitride layer extends over first and second surface portions of the top surface of the metal contact but does not extend over a third surface portion of the top surface of the metal contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0024] Figure 1 shows a cross section of a portion of an integrated circuit device in the prior art;

[0025] Figure 2 Shows Figure 1 details of the configuration of the passivation layer at the source electrical contact and the gate electrical contact of the integrated circuit device;

[0026] Figure 3 Shown based on Figure 1 Details of the passivation layer configuration at the source electrical contact and the gate electrical contact of the integrated circuit device according to the present application;

[0027] Figure 4A scanning electron micrograph showing an example of a passivation layer configuration according to the present application;

[0028] Figures 5A-5E The invention is shown for manufacturing Figure 3 and 4 Steps of a manufacturing process for a passivation layer configuration;

[0029] Figure 6 Shown based on Figure 1 Details of the passivation layer configuration at the source electrical contact and the gate electrical contact of the integrated circuit device according to the present application;

[0030] Figure 7 shows the relationship between the N / Si ratio and the refractive index of Si-rich silicon nitride materials; and

[0031] Figures 8A-8C A cross section of another integrated circuit device utilizing a passivation layer configuration according to the present application is shown. DETAILED DESCRIPTION

[0032] Reference now Figure 3 and Figure 6 , they show Figure 1 Detail of the configuration of the passivation layer 50' at the source electrical contact 46 and the gate electrical contact 48 of the integrated circuit device of FIG. In this embodiment, the passivation layer 50' comprises a layer stack, the layer stack comprising: a TEOS layer 50a', a phosphorus-doped TEOS (PTEOS) layer 50b' covering the TEOS layer 50a', and a silicon nitride (SiN) layer 50c'. The TEOS layer 50a' may have, for example, a thickness of approximately The PTEOS layer 50b' may have a thickness within a range of about The thickness of the SiN layer 50c' may be within a range of about The thickness is within the range. Figure 6 In the illustrated embodiment, the adhesion of the SiN layer 50c' to the metal layer 44 can be enhanced by using a thin silicon flash layer 70 between the PTEOS layer 50b' and the SiN layer 50c'. For example, the silicon flash layer 70 may have a thickness less than The passivation layer 50 is photolithographically patterned to form openings that expose the upper surfaces of the source (S) electrical contact 46 and the gate (G) electrical contact 48 .

[0033] The TEOS layer 50a' provides a layer made of a material softer than silicon nitride to provide a stress relief structure and also exhibits good adhesion characteristics relative to the aluminum material of the second metal layer 44. The TEOS layer 50a' also provides a diffusion barrier that inhibits the diffusion of phosphorus from the PTEOS layer 50b'. The PTEOS layer 50b' serves as a gettering layer that presents proton H+ gettering centers. The SiN layer 50c' is preferably implemented as a high-density silicon-rich nitride (referred to as "yellow nitride" in the art) and serves as a moisture barrier that prevents the penetration of contaminants such as protons H+ and moisture.

[0034] Figure 4 A scanning electron micrograph of an example of a configuration of a passivation layer 50 ′ with respect to a contact (C) made of aluminum is shown.

[0035] In the area where the source (S) electrical contact 46 and the gate (G) electrical contact 48 are not present (see right side), all three layers 50a', 50b' and 50c' of the stack for the passivation layer 50' extend over the exposed upper surface of the pre-metallization dielectric layer 32. All three layers 50a', 50b' and 50c' of the stack for the passivation layer 50' further extend over the sidewalls (S) of the contact C (i.e., over the side edge surfaces of the lithographically patterned layers 42 and 44). The three layers 50a', 50b' and 50c' of the stack for the passivation layer 50' further extend over a first surface portion 52 of the top surface of the contact C (i.e., over the top surface of the lithographically patterned layer 44). However, only the SiN layer 50c' extends over a second surface portion 54 of the top surface of the contact C. The SiN layer 50c' (together with the flash layer 70, when present) extends over the side edge surfaces of the layers 50a', 50b' at the transition from the first surface portion 52 to the second surface portion 54. The third surface portion 56 of the top surface of the contact C is not covered by any passivation layer 50'. Furthermore, the SiN layer 50c' extends over the sidewalls S1 of the layers 50a', 50b'.

[0036] The fabrication of the passivation layer 50' requires the use of two masks to photolithographically pattern the three layers 50a', 50b' and 50c' (plus layer 70, if present) of the stack. The steps of the fabrication process are as follows: Figures 5A-5E As shown. Figure 5A In the embodiment, layers 50a', 50b' are deposited on the metal contact C (44). Layers 50a' and 50b' can be deposited, for example, using plasma enhanced chemical vapor deposition (PECVD). Figure 5B In the embodiment, the first mask 60 is formed of a developed photoresist. The first mask 60 covers the first surface portion 52 of the top surface of the metal contact. Then an etch is performed to remove the portion of the layer 50a', 50b' not covered by the first mask 60. The first mask 60 is then removed. Figure 5CIn the embodiment, layer 50c' (with an intervening silicon flash layer 70, if necessary, see Figure 6 ) is conformally deposited to cover the patterned layers 50a', 50b' and the second and third surface portions 54 and 56 of the top surface of the metal contact. The layer 50c' can be deposited, for example, using SiH4-based plasma enhanced chemical vapor deposition (PECVD). The stoichiometry of the SiN layer 50c' can include, for example, Si x N y , wherein the bond ratio x:y can be determined, for example, by analytical techniques such as R-ray photoelectron spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIS) or Rutherford backscattering (RBS) showing a N / Si ratio of less than about 1.3 (or x:y greater than 3:4) and a refractive index (e.g. measured by optical ellipsometry) greater than 2 (see Figure 7 ).exist Figure 5D In the embodiment, the second mask 62 is formed of a developed photoresist. The second mask 62 covers the first and second surface portions 52 and 54 of the top surface of the metal contact. Then an etch is performed to remove the portion of the layer 50c' not covered by the second mask 62, thereby providing a contact opening 64 above the third surface portion 56 of the top surface of the metal contact. The second mask 62 is then removed. The result is shown in FIG. Figure 5E shown.

[0037] Although Figure 3 and Figure 6 The use of the passivation layer 50' in conjunction with a power MOSFET transistor is shown, but it should be understood that the passivation layer 50' may be used in conjunction with the metal contacts / bonding pads of any suitable integrated circuit device. Examples of such devices include, but are not limited to: shielded gate trench power MOSFET ( Fig. 8A ), wherein passivation is provided at the source and / or gate contacts; Trench gate field stop IGBT ( Figure 8B ), wherein passivation is provided at the emitter and / or gate contact; Superjunction MOSFET ( Figure 8C ), wherein passivation is provided at the source and / or gate contacts; and power diodes, wherein passivation is provided at the anode and / or cathode contacts.

[0038] Although the invention has been described and illustrated in detail in the drawings and the foregoing description, such description and illustration are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments may be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure, and the appended claims.

Claims

1. An integrated circuit device, comprising: a metal contact having a top surface, the top surface of the metal contact comprising a first surface portion, a second surface portion, and a third surface portion; as well as a passivation layer extending over the first surface portion and the second surface portion of the top surface of the metal contact; wherein the passivation layer comprises a layer stack comprising: Tetraethyl orthosilicate TEOS layer; a phosphorus-doped TEOS (PTEOS) layer on top of said TEOS layer; and a high-density silicon-rich nitride layer on top of the PTEOS layer; wherein the TEOS layer and the PTEOS layer extend over the first surface portion of the top surface of the metal contact but do not extend over the second surface portion and the third surface portion of the top surface of the metal contact; and The high-density silicon-rich nitride layer extends over the first and second surface portions of the top surface of the metal contact, but does not extend over the third surface portion of the top surface of the metal contact. 2 . The integrated circuit device of claim 1 , wherein the high-density silicon-rich nitride layer contacts the second surface portion of the top surface of the metal contact. 3 . The integrated circuit device of claim 1 , wherein the high-density silicon-rich nitride layer contacts side edge surfaces of the TEOS layer and the PTEOS layer at a transition from the first surface portion to the second surface portion. 4 . The integrated circuit device of claim 1 , wherein the TEOS layer contacts the first surface portion of the top surface of the metal contact. 5 . The integrated circuit device of claim 1 , further comprising a silicon flash layer in the layer stack for the passivation layer, wherein the silicon flash layer is located between the PTEOS layer and a high-density silicon-rich nitride layer.

6. The integrated circuit device according to claim 5, wherein the silicon flash layer has a thickness less than Thickness. 7 . The integrated circuit device of claim 5 , wherein the silicon flash layer contacts the second surface portion of the top surface of the metal contact.

8. The integrated circuit device of claim 5, wherein the silicon flash layer contacts side edge surfaces of the TEOS layer and the PTEOS layer at a transition from the first surface portion to the second surface portion.

9. The integrated circuit device of claim 5, wherein the high-density silicon-rich nitride layer is in contact with the silicon flash layer.

10. The integrated circuit device of claim 1, wherein the TEOS layer has Thickness within the range.

11. The integrated circuit device of claim 1 , wherein the PTEOS layer has Thickness within the range.

12. The integrated circuit device of claim 1, wherein the high-density silicon-rich nitride layer has Thickness within the range. 13 . The integrated circuit device of claim 1 , wherein the high-density silicon-rich nitride layer has an N / Si ratio less than 1.3, and the high-density silicon-rich nitride layer has a refractive index greater than 2.

14. The integrated circuit device of claim 1, wherein the stoichiometry of the high-density silicon-rich nitride layer comprises Si x N y , wherein x:y is greater than or equal to 3:4, and the high-density silicon-rich nitride layer has a refractive index greater than 2.

15. The integrated circuit device of claim 1, wherein the metal contact extends over a pre-metallization dielectric layer.

16. The integrated circuit device of claim 15, wherein the pre-metallization dielectric layer is formed of TEOS only.

17. The integrated circuit device of claim 1, wherein the metal contact is a gate contact of a discrete transistor.

18. The integrated circuit device of claim 1, wherein the metal contact is a source contact of a discrete transistor.

19. The integrated circuit device of claim 1, wherein the metal contact comprises a sidewall, and wherein the passivation layer also extends over the sidewall of the metal contact.

20. The integrated circuit device of claim 1, wherein the metal contact is a contact for a transistor source terminal or a gate terminal.

21. The integrated circuit device of claim 1, wherein the metal contact is a contact for an emitter terminal or a base terminal of a transistor.

22. The integrated circuit device of claim 1, wherein the metal contact is a contact for an anode terminal or a cathode terminal of a diode.

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