Thin film transistor including dielectric diffusion barrier and method of forming the same

Abstract

The present disclosure relates to thin film transistors including a dielectric diffusion barrier and methods of forming the same. A semiconductor device includes an insulating layer embedding a gate electrode and covering a substrate; a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer covering a top surface of the gate electrode; and a source electrode and a drain electrode contacting respective portions of a top surface of the active layer. The dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a silicon dielectric compound, and inhibits loss of a metal element in a subsequent anneal process.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to thin film transistors including a dielectric diffusion barrier and methods of forming the same. BACKGROUND

[0002] Thin film transistors (TFTs) made from oxide semiconductors are an attractive option for back-end-of-line (BEOL) integration because the TFTs can be processed at low temperatures, thus not damaging previously fabricated devices. For example, the fabrication conditions and techniques can not damage previously fabricated front-end-of-line (FEOL) and middle-end-of-line (MEOL) devices. SUMMARY

[0003] According to embodiments of the present disclosure, a semiconductor device is provided, comprising: an insulating layer embedding a gate electrode and covering a substrate; a stack of: a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material and covering the gate dielectric, and an active layer, covering a top surface of the gate electrode, wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a silicon dielectric compound; and a source electrode and a drain electrode contacting respective portions of a top surface of the active layer.

[0004] According to embodiments of the present disclosure, a semiconductor device is provided, comprising: an insulating layer embedding a bottom gate electrode and covering a substrate; a first stack of: a bottom gate dielectric including a first gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material and covering the bottom gate dielectric, and an active layer, covering a top surface of the bottom gate electrode, wherein the dielectric diffusion barrier material is different from the first gate dielectric material and is selected from a dielectric metal oxide material and a silicon dielectric compound; a second stack of: a top gate dielectric, and a top gate electrode covering the bottom gate electrode and having an area overlap with the bottom gate electrode in a plan view; and a source electrode and a drain electrode contacting respective portions of a top surface of the active layer.

[0005] According to embodiments of the present disclosure, a method of forming a semiconductor device is provided, comprising: forming a gate electrode within an insulating layer covering a substrate; forming a stack of: a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer, over the gate electrode and the insulating layer, wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a silicon dielectric compound; and forming a source electrode and a drain electrode at ends of the active layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion. FIG. 1 is a vertical cross-sectional view of a first exemplary structure according to embodiments of the present disclosure.

[0007] FIG. 1 FIG. 2 is a vertical cross-sectional view of the first exemplary structure of FIG. 1 after formation of a first metal interconnect structure, an insulating spacer layer, and an optional etch stop dielectric layer in an underlying dielectric layer according to embodiments of the present disclosure.

[0008] FIG. 2A FIG. 3 is a top-down view of a portion of the first exemplary structure of FIG. 1 after formation of an insulating layer according to a first embodiment of the present disclosure.

[0009] FIG. 2B FIG. 4 is a vertical cross-sectional view of the first exemplary structure of FIG. 3 along a vertical plane B-B’ of FIG. 3. FIG. 2A

[0010] FIG. 2C FIG. 5 is a vertical cross-sectional view of the first exemplary structure of FIG. 3 along a vertical plane C-C’ of FIG. 3. FIG. 2A

[0011] FIG. 3A FIG. 6 is a top-down view of a portion of the first exemplary structure of FIG. 3 after formation of a recessed region in the insulating layer according to the first embodiment of the present disclosure.

[0012] FIG. 3B FIG. 7 is a vertical cross-sectional view of the first exemplary structure of FIG. 6 along the vertical plane B-B’ of FIG. 6. FIG. 3A

[0013] FIG. 3C FIG. 8 is a vertical cross-sectional view of the first exemplary structure of FIG. 6 along the vertical plane C-C’ of FIG. 6. FIG. 3A

[0014] FIG. 4A FIG. 9 is a top-down view of a portion of the first exemplary structure of FIG. 6 after formation of a bottom gate electrode according to the first embodiment of the present disclosure.

[0015] FIG. 4B FIG. 10 is a vertical cross-sectional view of the first exemplary structure of FIG. 9 along the vertical plane B-B’ of FIG. 9. FIG. 4A

[0016] FIG. 4C FIG. 11 is a vertical cross-sectional view of the first exemplary structure of FIG. 9 along the vertical plane C-C’ of FIG. 9. FIG. 4A

[0017] FIG. 5A ​​​​​​is a plan view of a region of the first exemplary structure after formation of a continuous bottom gate dielectric layer, a continuous dielectric diffusion barrier liner, and a continuous active layer according to the first embodiment of the present disclosure.

[0018] FIG. 5B is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B' of FIG. 5A

[0019] FIG. 5C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C' of FIG. 5A

[0020] FIG. 6A is a plan view of a region of the first exemplary structure after formation of a bottom gate dielectric, a dielectric diffusion barrier liner, and an active layer according to the first embodiment of the present disclosure.

[0021] FIG. 6B is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B' of FIG. 6A

[0022] FIG. 6C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C' of FIG. 6A

[0023] FIG. 7A is a plan view of a region of the first exemplary structure after formation of a cap dielectric diffusion barrier liner and a top gate dielectric according to the first embodiment of the present disclosure.

[0024] FIG. 7B is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B' of FIG. 7A

[0025] FIG. 7C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C' of FIG. 7A

[0026] FIG. 8A is a plan view of a region of the first exemplary structure after formation of a top gate electrode according to the first embodiment of the present disclosure.

[0027] FIG. 8B is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B' of FIG. 8A

[0028] FIG. 8C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C' of FIG. 8A

[0029] FIG. 9A ​​​​​​​​is a top-down view of a region of the first exemplary structure after formation of a dielectric layer according to the first embodiment of the present disclosure.

[0030] FIG. 9B is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B’ of FIG. 9A

[0031] FIG. 9C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C’ of FIG. 9A

[0032] FIG. 10A is a top-down view of a region of the first exemplary structure after formation of source cavities, drain cavities, and bottom gate contact via cavities according to the first embodiment of the present disclosure.

[0033] FIG. 10B is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B’ of FIG. 10A

[0034] FIG. 10C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C’ of FIG. 10A

[0035] is a top-down view of a region of the first exemplary structure after formation of source electrodes, drain electrodes, and backside electrode contact via structures according to the first embodiment of the present disclosure. FIG. 11A

[0036] is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B’ of FIG. 11B FIG. 11A

[0037] FIG. 11C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C’ of FIG. 11A

[0038] is a top-down view of a region of a first alternative configuration of the first exemplary structure after formation of source electrodes, drain electrodes, and backside electrode contact via structures according to the first embodiment of the present disclosure. FIG. 12A

[0039] is a vertical cross-sectional view of the first exemplary structure along a vertical plane B-B’ of FIG. 12B FIG. 12A

[0040] FIG. 12C is a vertical cross-sectional view of the first exemplary structure along a vertical plane C-C’ of FIG. 12A

[0041] FIG. 13A ​​​​​​​​This is a top view of a region of a second alternative configuration of a first exemplary structure after the formation of a source electrode, drain electrode, and back-side electrode contact via structure according to a first embodiment of the present disclosure.

[0042] FIG. 13B It is along FIG. 13A A vertical cross-sectional view of the first exemplary structure in the vertical plane B-B'.

[0043] FIG. 13C It is along FIG. 13A A vertical cross-sectional view of the first exemplary structure in the vertical plane C-C'.

[0044] FIG. 14A This is a top view of a region of a second exemplary structure after the formation of the top gate dielectric, according to a second embodiment of the present disclosure.

[0045] FIG. 14B It is along FIG. 14A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0046] FIG. 14C It is along FIG. 14A A vertical cross-sectional view of a second exemplary structure in the vertical plane C-C'.

[0047] FIG. 15A This is a top view of a region of a second exemplary structure after the formation of the top gate electrode, according to a second embodiment of the present disclosure.

[0048] FIG. 15B It is along FIG. 15A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0049] FIG. 15C It is along FIG. 15A A vertical cross-sectional view of a second exemplary structure in the vertical plane C-C'.

[0050] FIG. 16A This is a top view of a region of a second exemplary structure after the formation of a dielectric layer, according to a second embodiment of the present disclosure.

[0051] FIG. 16B It is along FIG. 16A A vertical cross-sectional view of the second exemplary structure in the vertical plane B-B'.

[0052] FIG. 16C It is along FIG. 16A A vertical cross-sectional view of a second exemplary structure in the vertical plane C-C'.

[0053] FIG. 17Ais a top-down view of a region of a second exemplary structure after formation of source cavities, drain cavities, gate cavities, and bottom gate contact via cavities according to the second embodiment of the present disclosure.

[0054] FIG. 17B is a vertical cross-sectional view of the second exemplary structure along a vertical plane B-B’ of FIG. 17A

[0055] FIG. 17C is a vertical cross-sectional view of the second exemplary structure along a vertical plane C-C’ of FIG. 17A

[0056] FIG. 18A is a top-down view of a region of a second exemplary structure after formation of source electrodes, drain electrodes, and backside electrode contact via structures according to the second embodiment of the present disclosure.

[0057] FIG. 18B is a vertical cross-sectional view of the second exemplary structure along a vertical plane B-B’ of FIG. 18A

[0058] is a vertical cross-sectional view of the second exemplary structure along a vertical plane C-C’ of FIG. 18C FIG. 18A is a top-down view of a region of a first alternative configuration of a second exemplary structure after formation of source electrodes, drain electrodes, and backside electrode contact via structures according to the second embodiment of the present disclosure.

[0059] FIG. 19A is a vertical cross-sectional view of the second exemplary structure along a vertical plane B-B’ of

[0060] FIG. 19B is a vertical cross-sectional view of the second exemplary structure along a vertical plane C-C’ of FIG. 19A

[0061] FIG. 19C is a vertical cross-sectional view of the third exemplary structure along a vertical plane B-B’ of FIG. 19A

[0062] FIG. 20A is a top-down view of a region of a third exemplary structure after formation of a capping dielectric diffusion barrier lining according to the third embodiment of the present disclosure.

[0063] FIG. 20B is a vertical cross-sectional view of the third exemplary structure along a vertical plane B-B’ of FIG. 20A

[0064] is a vertical cross-sectional view of the third exemplary structure along a vertical plane C-C’ of FIG. 20C FIG. 20A

[0065] FIG. 21A ​​​​​​​is a top-down view of a region of a third exemplary structure after forming dielectric layers and source cavities, drain cavities, gate cavities, and bottom gate contact via cavities according to the third embodiment of the present disclosure.

[0066] FIG. 21B is a vertical cross-sectional view of the third exemplary structure along a vertical plane B-B’ of FIG. 21A

[0067] FIG. 21C is a vertical cross-sectional view of the third exemplary structure along a vertical plane C-C’ of FIG. 21A

[0068] FIG. 22A is a top-down view of a region of a third exemplary structure after forming source electrodes, drain electrodes, and backside electrode contact via structures according to the third embodiment of the present disclosure.

[0069] FIG. 22B is a vertical cross-sectional view of the third exemplary structure along a vertical plane B-B’ of FIG. 22A

[0070] FIG. 22C is a vertical cross-sectional view of the third exemplary structure along a vertical plane C-C’ of FIG. 22A

[0071] FIG. 23A is a top-down view of a region of a fourth exemplary structure after forming dielectric layers according to the fourth embodiment of the present disclosure.

[0072] FIG. 23B is a vertical cross-sectional view of the fourth exemplary structure along a vertical plane B-B’ of FIG. 23A

[0073] FIG. 23C is a vertical cross-sectional view of the fourth exemplary structure along a vertical plane C-C’ of FIG. 23A

[0074] FIG. 24A is a top-down view of a region of a fourth exemplary structure after forming source cavities, drain cavities, gate cavities, and bottom gate contact via cavities according to the fourth embodiment of the present disclosure.

[0075] FIG. 24B is a vertical cross-sectional view of the fourth exemplary structure along a vertical plane B-B’ of FIG. 24A

[0076] FIG. 24C is a vertical cross-sectional view of the fourth exemplary structure along a vertical plane C-C’ of FIG. 24A

[0077] FIG. 25A ​​​​​​​​This is a top view of the region of a fourth exemplary structure after the formation of the source electrode, drain electrode, and back-side electrode contact via structure according to a fourth embodiment of the present disclosure.

[0078] FIG. 25B It is along FIG. 25A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane B-B'.

[0079] FIG. 25C It is along FIG. 25A A vertical cross-sectional view of the fourth exemplary structure in the vertical plane C-C'.

[0080] FIG. 26 This is a vertical cross-sectional view of an exemplary structure after the formation of a memory cell, according to an embodiment of the present disclosure.

[0081] FIG. 27 This is a flowchart illustrating the general process steps for manufacturing the semiconductor devices disclosed herein. Detailed Implementation

[0082] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0083] In addition, for ease of description, spatially related terms (e.g., "below," "below," "lower than," "above," "upper," etc.) may be used herein to describe the relationship of one element or feature shown in the figures relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly. Elements with the same reference numerals refer to the same element and are assumed to have the same material composition and the same thickness range, unless otherwise expressly stated.

[0084] Generally, the structures and methods disclosed herein can be used to form semiconductor structures including at least one thin-film transistor (e.g., multiple thin-film transistors). The thin-film transistor can be formed over any substrate, which can be an insulating substrate, a conductive substrate, or a semiconductor substrate. In embodiments utilizing a conductive or semiconductor substrate, at least one insulating layer can be used to provide electrical isolation between the thin-film transistor and the underlying substrate. In embodiments using a semiconductor substrate such as a single-crystal silicon substrate, a field-effect transistor using portions of the semiconductor substrate as semiconductor channels can be formed on the semiconductor substrate, and a metal interconnect structure embedded in an interconnect-level dielectric layer can be formed on the field-effect transistor. The thin-film transistor can be formed over the field-effect transistor including the single-crystal semiconductor channel and over the metal interconnect structure, referred to herein as a lower-level metal interconnect structure.

[0085] According to one aspect of this disclosure, a dielectric diffusion barrier liner can be formed on the bottom side of each active layer, each active layer including a polycrystalline semiconductor channel of a corresponding thin-film transistor. Specifically, a dielectric diffusion barrier liner can be formed between the bottom gate dielectric and the active layer of each thin-film transistor. Optionally, a capped dielectric diffusion barrier liner can be formed over the active layer. The dielectric diffusion barrier liner and the optional capped dielectric diffusion barrier liner prevent metal elements from diffusing out of the active layer during a subsequent annealing process, thereby preventing changes in the material composition within the active layer and detrimental performance to the transistor characteristics of the thin-film transistor. Various aspects of embodiments of this disclosure will now be described in detail.

[0086] refer to FIG. 1 This illustration shows a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a substrate 8, which may be a semiconductor substrate such as a commercially available silicon substrate. The substrate 8 may include at least a semiconductor material layer 9 on its upper portion. The semiconductor material layer 9 may be a surface portion of a bulk semiconductor substrate, or it may be a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 includes a single-crystal semiconductor material, such as single-crystal silicon. In one embodiment, the substrate 8 may include a single-crystal silicon substrate comprising a single-crystal silicon material.

[0087] A shallow trench isolation structure 720 comprising a dielectric material (e.g., silicon oxide) can be formed in the upper portion of the semiconductor material layer 9. Suitable doped semiconductor wells, such as p-type and n-type wells, can be formed in each region laterally surrounded by a portion of the shallow trench isolation structure 720. Field-effect transistors 701 can be formed above the top surface of the semiconductor material layer 9. For example, each field-effect transistor 701 may include a source electrode 732, a drain electrode 738, a semiconductor channel 735, and a gate structure 750, wherein the semiconductor channel 735 includes a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738. The semiconductor channel 735 may comprise a single-crystal semiconductor material. Each gate structure 750 may include a gate dielectric layer 752, a gate electrode 754, a gate cap dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 can be formed on each source electrode 732, and a drain-side metal-semiconductor alloy region 748 can be formed on each drain electrode 738.

[0088] In embodiments where a memory cell array can be formed at the dielectric layer, the field-effect transistor 701 may include circuitry providing functionality to operate the memory cell array. Specifically, devices in the peripheral region may be configured to control programming, erasing, and sensing (reading) operations of the memory cell array. For example, devices in the peripheral region may include sensing circuitry and / or programming circuitry. Devices formed on the top surface of the semiconductor material layer 9 may include complementary metal-oxide-semiconductor (CMOS) transistors and optional additional semiconductor devices (e.g., resistors, diodes, capacitors, etc.), collectively referred to as CMOS circuitry 700.

[0089] One or more field-effect transistors 701 in the CMOS circuit 700 may include a semiconductor channel 735 that includes a portion of a semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 comprises a single-crystal semiconductor material (e.g., single-crystal silicon), the semiconductor channel 735 of each field-effect transistor 701 in the CMOS circuit 700 may include a single-crystal semiconductor channel, such as a single-crystal silicon channel. In one embodiment, the plurality of field-effect transistors 701 in the CMOS circuit 700 may include corresponding nodes that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently. For example, the plurality of field-effect transistors 701 in the CMOS circuit 700 may include corresponding source electrodes 732 or corresponding drain electrodes 738 that are subsequently electrically connected to the nodes of corresponding ferroelectric memory cells to be formed subsequently.

[0090] In one embodiment, the CMOS circuit 700 may include a programming control circuit configured to control the gate voltage of a set of field-effect transistors 701 for programming corresponding ferroelectric memory cells and controlling the gate voltage of thin-film transistors to be subsequently formed. In this embodiment, the programming control circuit may be configured to provide a first programming pulse that programs a corresponding ferroelectric dielectric layer in a selected ferroelectric memory cell to a first polarization state in which the polarization in the ferroelectric dielectric layer points to a first electrode of the selected ferroelectric memory cell, and the programming control circuit may be configured to provide a second programming pulse that programs the ferroelectric dielectric layer in the selected ferroelectric memory cell to a second polarization state in which the polarization in the ferroelectric dielectric layer points to a second electrode of the selected ferroelectric memory cell.

[0091] In one embodiment, substrate 8 may comprise a monocrystalline silicon substrate, and field-effect transistor 701 may comprise a corresponding portion of the monocrystalline silicon substrate as a semiconductor channel. As used herein, a "semiconductor" element refers to an element having a 1.0 x 10⁻⁶ Ω·cm² content. -6 S / cm up to 1.0x10 5 Components with conductivity in the range of S / cm. As used herein, "semiconductor material" refers to a component having conductivity in the range of 1.0 x 10⁻⁶ S / cm. -6 S / cm up to 1.0x10 5 Materials with conductivity in the range of S / cm (in the absence of electrical dopants) can be produced, and materials with conductivity from 1.0 S / cm to 1.0 x 10⁻⁶ can be generated. 5 Doped materials with conductivity in the range of S / cm (after appropriate doping with an electrical dopant).

[0092] According to one aspect of this disclosure, field-effect transistor 701 may subsequently be electrically connected to the drain and gate electrodes of an access transistor, the access transistor including an active layer to be formed over field-effect transistor 701. In one embodiment, a subset of field-effect transistor 701 may subsequently be electrically connected to at least one of the drain and gate electrodes. For example, field-effect transistor 701 may include a first word line driver and a second word line driver, wherein the first word line driver is configured to apply a first gate voltage to a first word line through a first subset of a subsequent lower-level metal interconnect structure, and the second word line driver is configured to apply a second gate voltage to a second word line through a second subset of the lower-level metal interconnect structure. Furthermore, field-effect transistor 701 may include a bit line driver configured to apply a bit line bias voltage to a subsequently formed bit line, and a sense amplifier configured to detect current flowing through the bit line during a read operation.

[0093] Various metal interconnect structures formed within the dielectric layer can subsequently be formed over the substrate 8 and semiconductor devices (e.g., field-effect transistor 701) thereon. In an illustrative example, the dielectric layer may include, for example, a first dielectric layer 601, a first interconnect level dielectric layer 610, and a second interconnect level dielectric layer 620, wherein the first dielectric layer 601 may be a layer surrounding contact structures connected to the source and drain (sometimes referred to as contact level dielectric layer 601). The metal interconnect structures may include device contact via structures 612 formed in the first dielectric layer 601 and contacting corresponding components of the CMOS circuit 700, a first metal line structure 618 formed in the first interconnect level dielectric layer 610, a first metal via structure 622 formed in the lower portion of the second interconnect level dielectric layer 620, and a second metal line structure 628 formed in the upper portion of the second interconnect level dielectric layer 620.

[0094] Each of the dielectric layers (601, 610, 620) may include a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, amorphous fluorinated carbon, porous variants thereof, or combinations thereof. Each of the metal interconnect structures (612, 618, 622, 628) may include at least one conductive material, which may be a combination of a metal liner (e.g., a metal nitride or a metal carbide) and a metal filler material. Each metal liner may include TiN, TaN, WN, TiC, TaC, and WC, and each metal filler portion may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metal liners and metal fillers within the disclosed scope may also be used. In one embodiment, the first metal via structure 622 and the second metal wire structure 628 may be formed as an integrated wire and via structure by a dual damascene process. The dielectric layers (601, 610, 620) are referred to herein as lower-level dielectric layers. The metal interconnect structures (612, 618, 622, 628) formed within the lower dielectric layer are referred to herein as lower metal interconnect structures.

[0095] While this disclosure is described using embodiments in which thin-film transistors can be formed above the second interconnect level dielectric layer 620, other embodiments are clearly contemplated herein, in which memory cell arrays can be formed at different metal interconnect levels. Furthermore, while this disclosure is described using embodiments in which a semiconductor substrate is used as substrate 8, embodiments in which an insulating or conductive substrate is used as substrate 8 are clearly contemplated herein.

[0096] The collection of all dielectric layers formed prior to the formation of the thin-film transistor array or ferroelectric memory cell array is collectively referred to as the lower dielectric layer (601, 610, 620). The collection of all metal interconnect structures formed within the lower dielectric layers (601, 610, 620) is referred to herein as the first metal interconnect structure (612, 618, 622, 628). Typically, the first metal interconnect structure (612, 618, 622, 628) formed within at least one lower dielectric layer (601, 610, 620) can be formed above the semiconductor material layer 9 located in the substrate 8.

[0097] According to one aspect of this disclosure, thin-film transistors (TFTs) can subsequently be formed in a metal interconnect stage that covers a metal interconnect stage comprising a lower dielectric layer (601, 610, 620) and a first metal interconnect structure (612, 618, 622, 628). In one embodiment, a planar dielectric layer of uniform thickness can be formed over the lower dielectric layer (601, 610, 620). The planar dielectric layer is referred to herein as an insulating spacer layer 635. The insulating spacer layer 635 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a porous dielectric material, and can be deposited by chemical vapor deposition. The thickness of the insulating spacer layer 635 can range from 20 nm to 300 nm, but smaller and larger thicknesses can also be used.

[0098] Typically, an interconnect-level dielectric layer (e.g., a lower-level dielectric layer (601, 610, 620)) containing a metal interconnect structure (e.g., a first metal interconnect structure (612, 618, 622, 628)) can be formed above the semiconductor device. An insulating spacer layer 635 can be formed above the interconnect-level dielectric layer.

[0099] In one embodiment, substrate 8 may include a monocrystalline silicon substrate, and a lower-level dielectric layer (601, 610, 620) with embedded lower-level metal interconnect structures (612, 618, 622, 628) may be located above the monocrystalline silicon substrate. A field-effect transistor 701, comprising a corresponding portion of the channel on the monocrystalline silicon substrate, may be embedded within the lower-level dielectric layer (601, 610, 620). The field-effect transistor may then be electrically connected to one or more of a subsequently formed thin-film transistor, or at least one of the gate, source, and drain electrodes of each thin-film transistor.

[0100] An etch-stop dielectric layer 636 may optionally be formed over the insulating spacer layer 635. The etch-stop dielectric layer 636 includes an etch-stop dielectric material that provides enhanced resistance to etching chemicals during a subsequent anisotropic etching process that etches the dielectric material subsequently deposited over the etch-stop dielectric layer 636. For example, the etch-stop dielectric layer 636 may include silicon carbonitride, silicon nitride, silicon oxynitride, or a dielectric metal oxide such as aluminum oxide. The thickness of the etch-stop dielectric layer 636 may range from 2 nm to 40 nm, for example, from 4 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0101] refer to FIGS. 2A-2C The diagram illustrates a region of a first exemplary structure, corresponding to a region where a thin-film transistor will subsequently be formed. Although this disclosure has been described using a single instance of a thin-film transistor, it should be understood that multiple instances of thin-film transistors may be formed simultaneously in any of the exemplary structures of this disclosure.

[0102] An insulating layer 42 may be formed over the insulating spacer layer 635 and an optional etch-stop dielectric layer 636. The insulating layer 42 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a porous dielectric material, and may be deposited by chemical vapor deposition. The thickness of the insulating layer 42 may range from 20 nm to 300 nm, but smaller and larger thicknesses are also possible. Multiple thin-film transistors may subsequently be formed over the insulating layer 42. In one embodiment, the multiple thin-film transistors may be arranged along a first horizontal direction hd1 and a second horizontal direction hd2, the second horizontal direction hd2 being perpendicular to the first horizontal direction hd1.

[0103] refer to FIGS. 3A-3C A photoresist layer (not shown) may be applied above the top surface of the insulating layer 42 and may be photolithographically patterned to form an opening in the illustrated region. In one embodiment, the opening may be a rectangular opening having a pair of lateral sidewalls along a first horizontal direction and a pair of longitudinal sidewalls along a second horizontal direction (hd2). An anisotropic etching process may be performed to transfer the pattern of the opening in the photoresist layer into the upper portion of the insulating layer 42. A recessed region 11 may be formed in the upper portion of the insulating layer 42. The recessed region 11 is also referred to as a bottom gate trench.

[0104] In one embodiment, the width of the recessed region 11 along the first horizontal direction hd1 can be in the range of 20 nm to 300 nm, but smaller and larger widths are also possible. In one embodiment, the length of the recessed region 11 along the second horizontal direction hd2 can be in the range of 30 nm to 3000 nm, but smaller and larger lengths are also possible. The depth of the recessed region 11 can be the same as the thickness of the insulating layer 42. Therefore, the top surface of the optional etch stop dielectric layer 636 or the top surface of the insulating spacer layer 635 (in embodiments where the etch stop dielectric layer 636 is not used) can be physically exposed at the bottom of the recessed region 11. The photoresist layer can then be removed, for example, by ashing.

[0105] refer to FIGS. 4A-4C At least one conductive material may be deposited in the recessed region 11. The at least one conductive material may include, for example, a metal barrier liner material (e.g., TiN, TaN, and / or WN) and a metal filler material (e.g., Cu, W, Mo, Co, Ru, etc.). Other suitable metal liners and metal fillers within the disclosed intended scope may also be used. Excess portions of the at least one conductive material may be removed from above the horizontal plane including the top surface of the insulating layer 42 by a planarization process, which may include a chemical mechanical polishing (CMP) process and / or a recess etching process. The planarization process may use a chemical mechanical polishing process or a recess etching process. A bottom gate electrode 15 may be formed in the recessed region 11. The bottom gate electrode 15 may be the only electrode of the thin-film transistor to be subsequently formed, or, in embodiments where a top gate electrode is subsequently formed, may be one of the two gate electrodes of the thin-film transistor. The top surface of the bottom gate electrode 15 may lie in the same horizontal plane as the top surface of the insulating layer 42.

[0106] refer to FIGS. 5A-5CA continuous bottom gate dielectric layer 10C, a continuous dielectric diffusion barrier liner 12C, and a continuous active layer 20C can be sequentially deposited over the insulating layer 42 and the bottom gate electrode 15 as a continuous material layer. The continuous bottom gate dielectric layer 10C can be formed by depositing at least one gate dielectric material. The gate dielectric material can include, but is not limited to, silicon oxide, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.) or stacks thereof. Other suitable dielectric materials are also within the scope of the disclosure. The gate dielectric material can be deposited by atomic layer deposition or chemical vapor deposition. The thickness of the continuous bottom gate dielectric layer 10C can be in the range of 1 nm to 12 nm, for example, in the range of 2 nm to 6 nm, but smaller and larger thicknesses can also be used. The continuous bottom gate dielectric layer 10C can be annealed at elevated temperatures to enhance electrical properties, such as reducing surface states. The elevated temperature can range from 300°C to 700°C, for example, from 350°C to 600°C, and / or from 400°C to 500°C. In one embodiment, the elevated temperature can be higher than 400°C. The duration of the annealing process can range from 10 minutes to 240 minutes, for example, from 20 minutes to 120 minutes, but shorter and longer durations are also possible. Annealing at 400°C or higher can provide enhanced crystallinity of the material in the continuous bottom gate dielectric layer 10C compared to annealing below 400°C.

[0107] The continuous dielectric diffusion barrier liner 12C includes a dielectric material capable of preventing the outward diffusion of metal elements within the continuous active layer 20C. For example, the continuous active layer 20C may include a semiconductor metal oxide material comprising at least two metal elements, such as indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. In this embodiment, at least one metal element (e.g., indium) within the semiconductor metal oxide material of the continuous active layer 20C may have a high bulk diffusion rate and may diffuse outward at a faster rate than other metal elements within the continuous active layer 20C during an annealing process, wherein the annealing process may be performed after the formation of the continuous active layer 20C. The dielectric material of the continuous dielectric diffusion barrier liner 12C can suppress the outward diffusion of at least one metal element with a high bulk diffusion rate and maintain the stoichiometry of the semiconductor metal oxide material within the continuous active layer 20C throughout the annealing process. In one embodiment, the continuous dielectric diffusion barrier liner 12C may be formed as a compositionally graded material layer with a vertical composition gradient, and / or may be formed as a multilayer stack comprising at least two dielectric layers with different material compositions.

[0108] A continuous active layer 20C can be deposited over a continuous dielectric diffusion barrier liner 12C. In one embodiment, the semiconductor material comprises materials that, after being appropriately doped with an electrical dopant (which may be a p-type or n-type dopant), exhibit a conductivity from 1.0 S / m to 1.0 × 10⁻⁶. 5 Materials within the S / m range. Exemplary semiconductor materials that can be used for continuous active layers include, but are not limited to, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Other suitable semiconductor materials are within the scope of the disclosure. In one embodiment, the semiconductor material of the continuous active layer 20C may include indium gallium zinc oxide.

[0109] The continuous active layer 20C may comprise a polycrystalline semiconductor material or an amorphous semiconductor material, the amorphous semiconductor material of which may subsequently be annealed to a polycrystalline semiconductor material having a larger average grain size. The continuous active layer 20C may be deposited by physical vapor deposition, although other suitable deposition processes may be used. The thickness of the continuous active layer 20C may range from 1 nm to 100 nm, for example, from 2 nm to 50 nm and / or from 4 nm to 15 nm, but smaller and larger thicknesses are also possible. The continuous active layer 20C may be annealed at elevated temperatures to enhance electrical performance, for example, by reducing surface states and increasing the average grain size. The elevated temperatures may range from 250°C to 400°C, for example, from 300°C to 375°C. In one embodiment, the elevated temperature may be below 350°C. The duration of the annealing process may range from 10 minutes to 240 minutes, for example, from 20 minutes to 120 minutes, but shorter and longer durations are also possible. Typically, performing two separate annealing processes on the material of the continuous bottom gate dielectric layer 10C and the material of the continuous active layer 20C allows for enhanced electrical properties of the bottom gate dielectric layer 10C material before deposition of the continuous active layer 20C (therefore, there is no temperature limitation imposed by material diffusion of the continuous active layer 20C). For example, the annealing process on the material of the continuous bottom gate dielectric layer 10C can be performed at a temperature above 400 degrees Celsius, while the annealing temperature of the material of the continuous active layer 20C is limited to a temperature that does not cause significant indium outward diffusion (e.g., an annealing temperature below 350 degrees Celsius). In one embodiment, a first annealing process for annealing the continuous bottom gate dielectric layer 10C before deposition of the continuous active layer 20C can be performed at a first temperature above 400 degrees Celsius, and a second annealing process for annealing the continuous active layer 20C can be performed at a second annealing temperature below 350 degrees Celsius.

[0110] According to one aspect of this disclosure, the material of the continuous dielectric diffusion barrier liner 12C can be selected to provide effective diffusion barrier for metal elements within the continuous active layer 20C. In one embodiment, the continuous active layer 20C comprises a compound semiconductor material, and / or is substantially composed of a compound semiconductor material comprising at least two metal elements and oxygen. In one embodiment, the continuous dielectric diffusion barrier liner 12C can be formed by depositing an oxide material comprising at least one metal element selected from the at least two metal elements described above.

[0111] In one embodiment, the continuous active layer 20C comprises an indium-containing semiconductor metal oxide material, and the continuous dielectric diffusion barrier liner 12C comprises an indium-free dielectric material (i.e., comprising indium with an atomic concentration of less than 10 parts per million (e.g., less than 1 part per million),) and / or is substantially composed of an indium-free dielectric material.

[0112] In one embodiment, the continuous active layer 20C comprises an indium-containing semiconductor metal oxide material, and the continuous dielectric diffusion barrier liner 12C comprises a material selected from metal oxide materials, and / or is substantially composed of a material selected from metal oxide materials, wherein the metal oxide material does not include indium and comprises at least one metal different from indium and present within the indium-containing semiconductor metal oxide material of the continuous active layer 20C. In one embodiment, the continuous dielectric diffusion barrier liner 12C comprises a material selected from gallium oxide, zinc oxide, and gallium zinc oxide, and / or is substantially composed of a material selected from gallium oxide, zinc oxide, and gallium zinc oxide.

[0113] In one embodiment, the continuous active layer 20C comprises an indium-containing semiconductor metal oxide material, and the continuous dielectric diffusion barrier liner 12C comprises an alkaline earth metal oxide, and / or is substantially composed of an alkaline earth metal oxide. For example, the continuous dielectric diffusion barrier liner 12C comprises CaO or SrO, and / or is substantially composed of CaO or SrO.

[0114] In one embodiment, the continuous active layer 20C comprises an indium-containing semiconductor metal oxide material, and the continuous dielectric diffusion barrier liner 12C comprises a dielectric oxide of a transition metal or aluminum oxide, and / or is substantially composed of a dielectric oxide of a transition metal or aluminum oxide. For example, the continuous dielectric diffusion barrier liner 12C comprises and / or is substantially composed of: aluminum oxide, chromium oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, compounds thereof, homogeneous mixtures thereof, and their layer stacks.

[0115] In one embodiment, the continuous active layer 20C comprises an indium-containing semiconductor metal oxide material, and the continuous dielectric diffusion barrier liner 12C comprises a material selected from silicon nitride and silicon oxide, and / or is substantially composed of a material selected from silicon nitride and silicon oxide.

[0116] Typically, the material for the continuous dielectric diffusion barrier liner 12C can be deposited using atomic layer deposition, physical vapor deposition, chemical vapor deposition, or a combination thereof. In one embodiment, the continuous diffusion barrier liner 12C may comprise a stack of layers of any two or more of the materials listed above for the continuous diffusion barrier liner 12C. The thickness of the continuous dielectric diffusion barrier liner 12C can range from 0.5 nm to 30 nm, for example, from 3 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0117] refer to FIGS. 6A-6C A photoresist layer (not shown) may be applied over a continuous active layer 20C and may be photolithographically patterned to form discrete patterned portions of photoresist material spanning a corresponding bottom gate electrode 15 along a first horizontal direction hd1. In one embodiment, each patterned portion of the photoresist layer may have a rectangular or rounded rectangular horizontal cross-sectional shape. By performing an anisotropic etching process, the pattern in the photoresist layer can be transferred through the continuous active layer 20C, the continuous dielectric diffusion barrier liner 12C, and the continuous bottom gate dielectric layer 10C. Each patterned portion of the continuous active layer 20C includes an active layer 20. Each patterned portion of the continuous dielectric diffusion barrier liner 12C includes a dielectric diffusion barrier liner 12. Each patterned portion of the continuous bottom gate dielectric layer 10C includes a bottom gate dielectric 10.

[0118] In one embodiment, each active layer 20 may have a rectangular or rounded rectangular horizontal cross-sectional shape. In one embodiment, each active layer 20 may have a lateral dimension along a first horizontal direction hd1 in the range of 60 nm to 1000 nm (e.g., in the range of 100 nm to 300 nm), but smaller and larger lateral dimensions may also be used. In one embodiment, each active layer 20 may have a lateral dimension along a second horizontal direction hd2 in the range of 20 nm to 500 nm (e.g., in the range of 40 nm to 250 nm), but smaller and larger lateral dimensions may also be used. The ratio of the lateral dimension along the first horizontal direction hd1 to the lateral dimension along the second horizontal direction hd2 in each active layer 20 may be in the range of 0.5 to 4, for example, in the range of 1 to 2, but smaller and larger ratios may also be used. Typically, a vertical stack of the bottom gate electrode 15, bottom gate dielectric 10, dielectric diffusion barrier liner 12, and active layer 20 can be formed above the lower dielectric layers (601, 610, 620) covering the substrate 8. The sidewalls of the bottom gate dielectric 10, dielectric diffusion barrier liner 12, and active layer 20 can overlap in the vertical direction, i.e., they can be located in the same vertical plane. The photoresist layer can then be removed, for example, by ashing.

[0119] refer to FIGS. 7A-7CAn optional cap dielectric diffusion barrier liner 22 and a top gate dielectric 30 may be formed over each of the stacked layers of the bottom gate dielectric 10, the dielectric diffusion barrier liner 12 and the active layer 20.

[0120] Optional cap dielectric diffusion barrier liner 22 (if present) includes any material that can be used in cap dielectric diffusion barrier liner 22, and / or is substantially composed of any material that can be used in cap dielectric diffusion barrier liner 22. The material of cap dielectric diffusion barrier liner 22 may be the same as or different from the material of dielectric diffusion barrier liner 12. The dielectric material of cap dielectric diffusion barrier liner 22 is referred to herein as cap dielectric metal oxide material.

[0121] According to one aspect of this disclosure, the material of the capped dielectric diffusion barrier liner 22 can be selected to provide effective diffusion barrier for metal elements within the active layer 20. In one embodiment, the active layer 20 comprises a compound semiconductor material, and / or is substantially composed of a compound semiconductor material comprising at least two metal elements and oxygen. In one embodiment, the capped dielectric diffusion barrier liner 22 can be formed by depositing an oxide material comprising at least one metal element selected from the at least two metal elements mentioned above. The capped dielectric diffusion barrier liner 22 comprises a capped dielectric metal oxide material, and / or is substantially composed of a capped dielectric metal oxide material that contacts a portion of the top surface of the active layer 20 covering the bottom gate electrode 15. Each surface of the active layer 20 may contact a corresponding surface selected from the surfaces of the dielectric diffusion barrier liner 12 and the surface of the capped dielectric diffusion barrier liner 22.

[0122] In one embodiment, the active layer 20 comprises an indium-containing semiconductor metal oxide material, and the capping dielectric diffusion barrier liner 22 comprises an indium-free dielectric material (i.e., comprising indium with an atomic concentration of less than 10 parts per million (e.g., less than 1 part per million),) and / or is substantially composed of an indium-free dielectric material.

[0123] In one embodiment, the active layer 20 comprises an indium-containing semiconductor metal oxide material, and the capping dielectric diffusion barrier liner 22 comprises a material selected from metal oxide materials, and / or is substantially composed of a material selected from metal oxide materials, wherein the metal oxide material does not include indium and comprises at least one metal different from indium and present within the indium-containing semiconductor metal oxide material of the active layer 20. In one embodiment, the capping dielectric diffusion barrier liner 22 comprises a material selected from gallium oxide, zinc oxide, and gallium zinc oxide, and / or is substantially composed of a material selected from gallium oxide, zinc oxide, and gallium zinc oxide.

[0124] In one embodiment, the active layer 20 comprises an indium-containing semiconductor metal oxide material, and the capping dielectric diffusion barrier liner 22 comprises an alkaline earth metal oxide, and / or is substantially composed of an alkaline earth metal oxide. For example, the capping dielectric diffusion barrier liner 22 comprises CaO or SrO, and / or is substantially composed of CaO or SrO.

[0125] In one embodiment, the active layer 20 comprises an indium-containing semiconductor metal oxide material, and the capped dielectric diffusion barrier liner 22 comprises a dielectric oxide of a transition metal or aluminum oxide, and / or is substantially composed of a dielectric oxide of a transition metal or aluminum oxide. For example, the capped dielectric diffusion barrier liner 22 comprises and / or is substantially composed of: aluminum oxide, chromium oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, tantalum oxide, compounds thereof, homogeneous mixtures thereof, and their layer stacks.

[0126] In one embodiment, the active layer 20 comprises an indium-containing semiconductor metal oxide material, and the cap dielectric diffusion barrier liner 22 comprises a material selected from silicon nitride and silicon oxide, and / or is substantially composed of a material selected from silicon nitride and silicon oxide.

[0127] Typically, the material of the cap dielectric diffusion barrier liner 22 can be deposited by atomic layer deposition, physical vapor deposition, chemical vapor deposition, or a combination thereof. The thickness of the cap dielectric diffusion barrier liner 22 can range from 0.5 nm to 30 nm, for example, from 3 nm to 10 nm, but smaller and larger thicknesses can also be used.

[0128] The top gate dielectric 30 can be formed by depositing at least one top gate dielectric material. The at least one top gate dielectric material can be, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.), or stacks thereof. Other suitable dielectric materials are within the disclosed scope. The at least one top gate dielectric material can be deposited by atomic layer deposition or chemical vapor deposition. The thickness of the top gate dielectric 30 can be in the range of 1 nm to 12 nm, for example, in the range of 2 nm to 6 nm, but smaller and larger thicknesses can also be used. When performing an annealing process to anneal the material of the top gate dielectric 30, the annealing process rise temperature can be below 350 degrees Celsius to limit the diffusion of indium from the active layer 20.

[0129] refer to FIGS. 8A-8CAt least one conductive material layer may be deposited over the top gate dielectric 30. The at least one conductive material layer may comprise at least one metallic material and / or at least one heavily doped semiconductor material (e.g., heavily doped polysilicon). A photoresist layer (not shown) may be applied over the at least one conductive material layer and may be photolithographically patterned to form discrete photoresist material portions. The pattern in the photoresist material portions can be transferred through the at least one conductive material layer by performing an anisotropic etching process. In one embodiment, the anisotropic etching process may be selective for the material of the top gate dielectric 30. Each patterned portion of the at least one conductive material layer constitutes the top gate electrode 35. The photoresist layer may subsequently be removed, for example, by ashing. The top gate electrode 35 spans the active layer 20 along a second horizontal direction hd2. The height of the top gate electrode 35, measured in the region covering the active layer 20 between the bottom and top surfaces of the top gate electrode 35, may range from 50 nm to 300 nm, for example, from 100 nm to 200 nm, but smaller and larger heights may also be used.

[0130] refer to FIGS. 9A-9C A dielectric layer 48 may be deposited over the top gate electrode 35 and the top gate dielectric 30. This dielectric layer is also referred to as an electrode-level dielectric layer. The dielectric layer 48 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, or a stack thereof. Optionally, the dielectric layer 48 may be planarized to provide a flat top surface. The dielectric material of the dielectric layer 48 may be planarized such that the planarized horizontal top surface of the dielectric layer 48 is formed within a horizontal plane including the top surface of the top gate electrode 35. The assembly of the insulating layer 42 and the dielectric layer 48 is referred to herein as a thin-film transistor-level (TFT-level) dielectric layer 40, i.e., a dielectric layer located at the thin-film transistor level.

[0131] refer to FIGS. 10A-10CA photoresist layer (not shown) may be applied over the TFT-level dielectric layer 40 and may be photolithographically patterned to form discrete openings therein. The pattern of the discrete openings in the photoresist layer may be transferred through the dielectric layer 48, the top gate dielectric layer 30, and the cap dielectric diffusion barrier liner 22 by at least one etching process to form the source cavity 51, the drain cavity 59, and the bottom gate contact via cavity 19. At least one etching process may include a first anisotropic etching process, an isotropic etching process, or a second anisotropic etching process, as well as an isotropic etching process or a third anisotropic etching process, wherein the first anisotropic etching process etches the material of the dielectric layer 48 (selectively for the material of the top gate dielectric 30), the isotropic etching process or the second anisotropic etching process etches the material of the top gate dielectric 30 (selectively for the material of the cap dielectric diffusion barrier liner 22), and the isotropic etching process or the third anisotropic etching process etches the material of the cap dielectric diffusion barrier liner 22 (selectively for the material of the active layer 20).

[0132] Source cavity 51 and drain cavity 59 may be formed at opposite ends of active layer 20 and may be laterally spaced from each other along a first horizontal direction hd1. In one embodiment, the end sidewalls of active layer 20 extending laterally along a second horizontal direction hd2 and a pair of sidewall segments of active layer 20 extending laterally along the first horizontal direction hd1 may be physically exposed at the bottom of each of source cavity 51 and drain cavity 59. A rectangular portion of the top surface of active layer 20 may be physically exposed at the bottom of each of source cavity 51 and drain cavity 59. The top surface of bottom gate electrode 15 may be physically exposed at the bottom of back electrode contact via cavity 19. The photoresist layer may then be removed, for example, by ashing.

[0133] refer to FIGS. 11A-11C At least one conductive material may be deposited in the cavities (51, 19, 59) and above the TFT-level dielectric layer 40. The at least one conductive material may include a metal liner material and a metal filler material. The metal liner material may include conductive metal nitrides or conductive metal carbides, such as TiN, TaN, WN, TiC, TaC, and / or WC. The metal filler material may include W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable materials within the disclosed scope may also be used.

[0134] Excess portions of at least one conductive material can be removed from a horizontal plane above the top surface of the TFT-level dielectric layer 40 using a planarization process, which may employ CMP and / or trench etching processes. Other suitable planarization processes may also be used. Each remaining portion of the at least one conductive material filling the source cavity 51 constitutes a source electrode 52. Each remaining portion of the at least one conductive material filling the drain cavity 59 constitutes a drain electrode 56. Each remaining portion of the at least one conductive material filling the back-side electrode contact via cavity 19 constitutes a back-side electrode contact via structure 18, which contacts the top surface of the bottom gate electrode 15.

[0135] In one embodiment, each source electrode 52 may include a source metal liner 53 as the remainder of the metal liner material and a source metal filler portion 54 as the remainder of the metal filler material. Each drain electrode 56 may include a drain metal liner 57 as the remainder of the metal liner material and a drain metal filler portion 58 as the remainder of the metal filler material. Each back-side electrode contact via structure 18 may include a bottom gate contact metal liner 16 as the remainder of the metal liner material and a bottom gate contact metal filler portion 17 as the remainder of the metal filler material.

[0136] The active layer 20 and a set of electrode structures (52, 15, 35, 56) can be formed within the TFT-level dielectric layer 40. The top surfaces of the source electrode 52, drain electrode 56, top gate electrode 35, and bottom gate electrode contact structure 18 can be located within a horizontal plane including the top surface of the TFT-level dielectric layer 40 (i.e., can be coplanar with this horizontal plane).

[0137] Typically, the source electrode 52 and the drain electrode 56 can be formed directly on the ends of the active layer 20 through the cap dielectric diffusion barrier liner 22. The cap dielectric diffusion barrier liner 22 can contact the sidewalls of the bottom gate dielectric 10, the sidewalls of the dielectric diffusion barrier liner 12, and the top surface of the dielectric diffusion barrier liner 12.

[0138] refer to FIGS. 12A-12C By patterning the top gate electrode 35 (in FIGS. 8A-8C After the process steps (at which point), the unmasked portion of the top gate dielectric 30 is removed, and it can be obtained from... FIGS. 11A-11C The first exemplary structure shown is obtained by a first alternative configuration of the first exemplary structure. Removal of the unmasked portion of the top gate dielectric 30 can be performed selectively on the material of the cap dielectric diffusion barrier liner 22. The photoresist layer can then be removed, and subsequently... FIGS. 9A-11C The process steps to provide FIGS. 12A-12C The first alternative configuration of the first exemplary structure shown.

[0139] refer to FIGS. 13A-13C By patterning the top gate electrode 35 (in FIGS. 8A-8C After the process steps (at which point), the unmasked portion of the top gate dielectric 30 and the unmasked portion of the cap dielectric diffusion barrier liner 22 are removed, allowing it to be removed from the process steps. FIGS. 11A-11C The first exemplary structure shown is obtained with a second alternative configuration of the first exemplary structure. Removal of the unmasked portion of the top gate dielectric 30 can be performed selectively on the material of the cap dielectric diffusion barrier liner 22. Removal of the unmasked portion of the cap dielectric diffusion barrier liner 22 can be performed selectively on the material of the active layer 20. The photoresist layer can then be removed, and subsequently... FIGS. 9A-11C The process steps to provide FIGS. 13A-13C A second alternative configuration of the first exemplary structure shown.

[0140] refer to FIGS. 14A-14C Through execution FIGS. 7A-7C The process steps form the top gate dielectric 30 without forming an optional cap dielectric diffusion barrier liner 22, which can be obtained from... FIGS. 6A-6C The first exemplary structure yields the second exemplary structure according to the second embodiment of this disclosure. Thus, the top gate dielectric 30 can be directly formed on the physically exposed surface of the active layer 20, the sidewalls of the dielectric diffusion barrier liner 12, the sidewalls of the bottom gate dielectric 10, and the top surface of the bottom gate electrode 15 and the insulating layer 42.

[0141] refer to FIGS. 15A-15C It can be executed FIGS. 8A-8C The process steps are to form a top gate electrode 35 on the top surface of the top gate dielectric 30 above each active layer 20.

[0142] refer to FIGS. 16A-16C It can be executed FIGS. 9A-9C The process steps are used to form a dielectric layer 48, which has a top surface located within a horizontal plane including the top surface of the top gate electrode 35. The assembly of the insulating layer 42 and the dielectric layer 48 is referred to herein as a thin-film transistor-level (TFT-level) dielectric layer 40, i.e., a dielectric layer located at the thin-film transistor level.

[0143] refer to FIGS. 17A-17C It can be executed FIGS. 10A-10C The process steps are used to form a source cavity 51, a drain cavity 59, and a back electrode contact via cavity 19 that pass through the dielectric layer 48 and the top gate dielectric 30.

[0144] refer to FIGS. 18A-18C It can be executed FIGS. 11A-11CThe process steps are used to form the source electrode 52, the drain electrode 56, and the back electrode contact via structure 18.

[0145] refer to FIGS. 19A-19C By patterning the top gate electrode 35 (in FIGS. 15A-15C After the process steps (at which point), the unmasked portion of the top gate dielectric 30 is removed, and it can be obtained from... FIGS. 18A-18C The second exemplary structure shown is an alternative configuration of the second exemplary structure. Removal of the unmasked portion of the top gate dielectric 30 can be performed selectively on the material of the active layer 20. The photoresist layer can then be removed, and subsequently... FIGS. 16A-18C The process steps to provide FIGS. 19A-19C An alternative configuration of the second exemplary structure shown.

[0146] refer to FIGS. 20A-20C This illustrates a third exemplary structure according to a third embodiment of the present disclosure. By using... FIGS. 7A-7C The process steps involve depositing a cap dielectric diffusion barrier liner 22, and using... FIGS. 9A-9C The process steps form the dielectric layer 48, which can be obtained from FIGS. 6A-6C The first exemplary structure shown yields a third exemplary structure. The formation of the top gate dielectric or top gate electrode is omitted.

[0147] refer to FIGS. 21A-21C It can be executed FIGS. 10A-10C The process steps are to form the source cavity 51, drain cavity 59 and back electrode contact via cavity 19 through the dielectric layer 48 and the cap dielectric diffusion barrier liner 22.

[0148] refer to FIGS. 22A-22C It can be executed FIGS. 11A-11C The process steps are used to form the source electrode 52, the drain electrode 56, and the back electrode contact via structure 18.

[0149] refer to FIGS. 23A-23C This illustrates a fourth exemplary structure according to a fourth embodiment of the present disclosure. By using... FIGS. 9A-9C The process steps form the dielectric layer 48, which can be obtained from FIGS. 6A-6C The first exemplary structure shown yields the fourth exemplary structure. (The remaining text is omitted.) FIGS. 7A-7C and FIGS. 8A-8C The process steps. In other words, no cap dielectric diffusion barrier liner or top gate dielectric is formed.

[0150] refer to FIGS. 24A-24C It can be executed FIGS. 10A-10C The process steps are used to form the source cavity 51, drain cavity 59 and back electrode contact via cavity 19 through the dielectric layer 48.

[0151] refer to FIGS. 25A-25C It can be executed FIGS. 11A-11C The process steps are used to form the source electrode 52, the drain electrode 56, and the back electrode contact via structure 18.

[0152] refer to FIG. 26 This illustrates an exemplary structure after the formation of a thin-film transistor. It can be seen from... FIGS. 11A-13C The first exemplary structure shown FIGS. 18A-19C The second exemplary structure shown FIGS. 22A-22C The third exemplary structure shown, or FIGS. 25A-25C The fourth exemplary structure shown provides this exemplary structure. For example, a second metal via structure 632 may be formed simultaneously with, before or after the formation of the source electrode 52, drain electrode 56, optional top gate electrode 35 and back electrode contact via structure 18. This second metal via structure 632 passes through the TFT-level dielectric layer 40 and insulating spacer layer 635 on a corresponding one of the second metal line structures 628.

[0153] A dielectric layer, referred to herein as a third-line dielectric layer 637, may be deposited above the TFT-level dielectric layer 40. A third metal line structure 638 may be formed in the third-line dielectric layer 637 on a corresponding metal structure within the metal structures (52, 56, 35, 18) embedded in the TFT-level dielectric layer 40.

[0154] Additional metal interconnect structures embedded in the additional dielectric layer may subsequently be formed over the thin-film transistor and the third-level dielectric layer 637. In an illustrative example, the dielectric layer may include, for example, a fourth interconnect-level dielectric layer 640, a fifth interconnect-level dielectric layer 650, etc. The additional metal interconnect structures may include a third metal via structure (not shown) and a fourth metal line 648 embedded in the fourth interconnect-level dielectric layer 640, a fourth metal via structure 652 and a fifth metal line structure 658 embedded in the fifth interconnect-level dielectric layer 650, etc.

[0155] Optionally, the memory cells 150 can be formed below, above, or on the same horizontal plane as the thin-film transistor. In embodiments where the thin-film transistor is formed as a two-dimensional periodic array, the memory cells 150 can be formed as a two-dimensional periodic array of memory cells 150. Each memory cell 150 may include a magnetic tunnel junction, a ferroelectric tunnel junction, a phase-change memory material, or a vacancy-modulated conductive oxide material portion. Furthermore, each memory cell 150 may include a first electrode 126 and a second electrode 158, the first electrode 126 comprising a metallic material and the second electrode 158 comprising a metallic material and protecting the lower data storage portion of the memory cell 150. The memory element is disposed between the first electrode 126 (i.e., the bottom electrode) and the second electrode 158 (i.e., the top electrode).

[0156] In an illustrative example, in an embodiment where memory cell 150 includes a magnetic tunnel junction, memory cell 150 may include a layer stack comprising, from bottom to top, a first electrode 126, a metal seed layer 128 for promoting crystal growth of a cover material layer, a synthetic antiferromagnetic (SAF) structure 140, a tunnel blocking layer 146, a free magnetization layer 148, and a second electrode 158. While this disclosure is described using embodiments in which thin-film transistors are used as access transistors for memory cell 150, it is expressly contemplated herein that thin-film transistors are used as logic devices, as components of peripheral circuitry for a memory array, or for any other semiconductor circuitry.

[0157] In one embodiment, substrate 8 comprises a monocrystalline silicon substrate. Lower-level dielectric layers (601, 610, 620) with embedded lower-level metal interconnect structures (612, 618, 622, 628) may be located between the monocrystalline silicon substrate and insulating layer 42. Field-effect transistors 701, comprising a corresponding portion of the channel on the monocrystalline silicon substrate, may be embedded in the lower-level dielectric layers (601, 610, 620) and may be electrically connected to at least one of the gate electrode (15, 35), source electrode 52, and drain electrode 56.

[0158] FIG. 27 This is a flowchart illustrating the general process steps for manufacturing the semiconductor device of this disclosure. Refer to step 2710 and... FIGS. 1-4C , FIGS. 12A-13C , FIGS. 14A-14C , FIGS. 19A-19C , FIGS. 20A-20C and FIGS. 23A-23C The gate electrode (e.g., bottom gate electrode 15) may be formed within the insulating layer 42 covering the substrate 8. Refer to steps 2720 and... FIGS. 5A-6C , FIGS. 12A-13C , Figures 14A-14C , Figures 19A-19C , Figures 20A-20C and Figures 23A-23CA stack of a gate dielectric material (e.g., bottom gate dielectric 10), a dielectric diffusion barrier liner 12, and an active layer 20 may be formed over a gate electrode (e.g., bottom gate electrode 15) and an insulating layer 42. The dielectric diffusion barrier material differs from the gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds. Refer to step 2730 and... Figures 7A-11C , Figures 12A-13C , Figures 15A-18C , Figures 19A-19C , Figures 20A-22C and Figures 23A-25C The source electrode 52 and the drain electrode 56 can be formed on the end of the active layer 20.

[0159] Referring to all the accompanying drawings and various embodiments of the present disclosure, a semiconductor device including a thin-film transistor is provided. The thin-film transistor includes: an insulating layer 42 embedded with a gate electrode (e.g., a bottom gate electrode 15) and covering a substrate 8; a stack of the following items covering the top surface of the gate electrode (e.g., the bottom gate electrode 15): a gate dielectric (e.g., a bottom gate dielectric 10) including a gate dielectric material, a dielectric diffusion barrier liner 12 including a dielectric diffusion barrier material and covering the gate dielectric, and an active layer 20 wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; and a source electrode 52 and a drain electrode 56 contacting corresponding portions of the top surface of the active layer 20.

[0160] In one embodiment, the sidewalls of the gate dielectric (e.g., the bottom gate dielectric 10), the sidewalls of the dielectric diffusion barrier liner 12, and the sidewalls of the active layer 20 overlap each other in the vertical direction, i.e., they are located in a common vertical plane.

[0161] In one embodiment, the active layer 20 comprises a compound semiconductor material comprising at least two metal elements and oxygen; and the dielectric diffusion barrier liner 12 comprises an oxide material comprising at least one metal element selected from the aforementioned at least two metal elements.

[0162] In one embodiment, the active layer 20 comprises an indium-containing semiconductor metal oxide material; and the dielectric diffusion barrier liner 12 comprises an indium-free dielectric material, i.e., comprising indium with an atomic concentration of less than 10 parts per million (e.g., less than 1 part per million).

[0163] In one embodiment, the active layer 20 comprises indium gallium zinc oxide; and the dielectric diffusion barrier liner 12 comprises a material selected from gallium oxide, zinc oxide, and gallium zinc oxide.

[0164] In one embodiment, the dielectric diffusion barrier liner 12 comprises a metal oxide of an alkaline earth metal. In one embodiment, the dielectric diffusion barrier liner 12 comprises a dielectric oxide of a transition metal or aluminum oxide. In one embodiment, the dielectric diffusion barrier liner 12 comprises a material selected from silicon nitride and silicon oxide.

[0165] In one embodiment, the semiconductor device includes a capped dielectric diffusion barrier liner 22, which includes a portion of a capped dielectric metal oxide material and contacts a portion of the top surface of the active layer 20 that covers a gate electrode (e.g., a bottom gate electrode 15). In one embodiment, each surface of the active layer 20 may contact a corresponding surface selected from: the top surface of the dielectric diffusion barrier liner 12, the surface of the source electrode 52, the surface of the drain electrode 56, and the surface of the capped dielectric diffusion barrier liner 22.

[0166] In one embodiment, the source electrode 52 contacts the first sidewall of the gate dielectric (e.g., the bottom gate dielectric 10) and the first sidewall of the dielectric diffusion barrier liner 12; and the drain electrode 56 contacts the second sidewall of the gate dielectric and the second sidewall of the dielectric diffusion barrier liner 12.

[0167] In one embodiment, substrate 8 comprises a monocrystalline silicon substrate; and a lower-level dielectric layer (601, 610, 620) with embedded lower-level metal interconnect structures (612, 618, 622, 628) is located between the monocrystalline silicon substrate and the insulating layer 42. A field-effect transistor 701, comprising a corresponding portion of the channel on the monocrystalline silicon substrate, may be embedded within the lower-level dielectric layer (601, 610, 620). Field-effect transistor 701 may be electrically connected to at least one of a gate electrode (e.g., bottom gate electrode 15 or top gate electrode 35), a source electrode 52, and a drain electrode 56.

[0168] According to one aspect of this disclosure, the semiconductor device may include: an insulating layer 42, in which a bottom gate electrode 15 is embedded and covers a substrate 8; a first stack of the following items covering the top surface of the bottom gate electrode 15: a bottom gate dielectric 10 including a first gate dielectric material, a dielectric diffusion barrier liner 12 including a dielectric diffusion barrier material and covering the bottom gate dielectric, and an active layer 20, wherein the dielectric diffusion barrier material is different from the first gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; a second stack of the following items: a top gate dielectric 30 and a top gate electrode 35, wherein the top gate electrode 35 covers the bottom gate electrode 15 and overlaps with the bottom gate electrode in a plan view (i.e., a perspective view along a vertical direction perpendicular to the top surface of the substrate 8); and a source electrode 52 and a drain electrode 56, contacting corresponding portions of the top surface of the active layer 20.

[0169] In one embodiment, the semiconductor device includes a capped dielectric diffusion barrier liner 22 comprising a capped dielectric metal oxide material and contacting the top surface of the active layer 20 located between the source electrode 52 and the drain electrode 56, wherein each surface of the active layer 20 is in contact with a corresponding surface selected from: the top surface of the dielectric diffusion barrier liner 12, the surface of the source electrode 52, the surface of the drain electrode 56, and the surface of the capped dielectric diffusion barrier liner 22.

[0170] In one embodiment, the semiconductor device includes: a dielectric layer (e.g., dielectric layer 48) laterally surrounding a stack of a bottom gate dielectric 10 and an active layer 20; and a back-side electrode contact via structure 18 contacting the top surface of the bottom gate electrode 15, wherein the source electrode 52, the drain electrode 56, the top gate electrode 35, and the top surface of the back-side electrode contact via structure 18 are located in a horizontal plane including the top surface of the dielectric layer.

[0171] According to one aspect of this disclosure, a method for forming a semiconductor device is provided. The method may include: forming a gate electrode within an insulating layer covering a substrate; forming a stack of the following over the gate electrode and the insulating layer: a gate dielectric comprising a gate dielectric material, a dielectric diffusion barrier liner comprising a dielectric diffusion barrier material, and an active layer, wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; and forming a source electrode and a drain electrode at the ends of the active layer.

[0172] In one embodiment, the method may further include annealing the dielectric diffusion barrier liner at a first annealing temperature above 400 degrees Celsius; and annealing the active layer at a second annealing temperature below 350 degrees Celsius.

[0173] In one embodiment, an active layer can be formed by depositing and patterning a compound semiconductor material comprising at least two metal elements and oxygen; and a dielectric diffusion barrier liner can be formed by depositing and patterning an oxide material comprising at least one metal element selected from the aforementioned at least two metal elements.

[0174] In one embodiment, the active layer may include an indium-containing semiconductor metal oxide material; and the dielectric diffusion barrier liner may include an indium-free dielectric material.

[0175] In one embodiment, the method may further include forming a capped dielectric diffusion barrier liner, which may include a capped dielectric metal oxide material, on the top surface of the active layer, wherein the source electrode and the drain electrode are formed directly on the active layer through the capped dielectric diffusion barrier liner.

[0176] Various embodiments of this disclosure can be used to reduce the outward diffusion of metal elements such as indium from the active layer 20 by providing a metal diffusion-resistant barrier structure or by providing at least one metal source structure (e.g., an indium source). The metal diffusion-resistant barrier structure or at least one metal source structure may include a dielectric diffusion barrier liner 12, an optional cap dielectric diffusion barrier liner 22, a source electrode 52, a drain electrode 56, and an optional top gate electrode 35. Preventing the outward diffusion of metal from the active layer 20 prevents compositional changes within the active layer 20, thus helping to maintain constant device characteristics of the thin-film transistor throughout its operational lifetime.

[0177] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0178] Example 1 is a semiconductor device comprising: an insulating layer having a gate electrode embedded therein and covering a substrate; a stack of the following covering a top surface of the gate electrode: a gate dielectric comprising a gate dielectric material, a dielectric diffusion barrier liner comprising a dielectric diffusion barrier material and covering the gate dielectric, and an active layer wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; and source electrodes and drain electrodes contacting corresponding portions of the top surface of the active layer.

[0179] Example 2 is the semiconductor device described in Example 1, wherein the sidewalls of the gate dielectric, the sidewalls of the dielectric diffusion barrier liner, and the sidewalls of the active layer coincide with each other in the vertical direction.

[0180] Example 3 is the semiconductor device described in Example 1, wherein: the active layer comprises a compound semiconductor material, the compound semiconductor material comprising at least two metal elements and oxygen; and the dielectric diffusion barrier liner comprises an oxide material, the oxide material comprising at least one metal element selected from the at least two metal elements.

[0181] Example 4 is the semiconductor device described in Example 3, wherein: the active layer comprises an indium-containing semiconductor metal oxide material; and the dielectric diffusion barrier liner comprises an indium-free dielectric material.

[0182] Example 5 is the semiconductor device described in Example 3, wherein: the active layer comprises indium gallium zinc oxide; and the dielectric diffusion barrier liner comprises a material selected from gallium oxide, zinc oxide, and gallium zinc oxide.

[0183] Example 6 is the semiconductor device described in Example 1, wherein the dielectric diffusion barrier liner comprises an alkaline earth metal oxide.

[0184] Example 7 is the semiconductor device described in Example 1, wherein the dielectric diffusion barrier liner comprises a dielectric oxide of a transition metal or aluminum oxide.

[0185] Example 8 is the semiconductor device described in Example 1, wherein the dielectric diffusion barrier liner comprises a material selected from silicon nitride and silicon oxide.

[0186] Example 9 is the semiconductor device described in Example 1, further comprising a capped dielectric diffusion barrier liner, the capped dielectric diffusion barrier liner comprising a capped dielectric metal oxide material and contacting a portion of the top surface of the active layer covering the gate electrode.

[0187] Example 10 is the semiconductor device described in Example 9, wherein each surface of the active layer is in contact with a corresponding surface selected from the following: the top surface of the dielectric diffusion barrier liner, the surface of the source electrode, the surface of the drain electrode, and the surface of the cap dielectric diffusion barrier liner.

[0188] Example 11 is the semiconductor device described in Example 1, wherein the cap dielectric diffusion barrier liner contacts the sidewall of the gate dielectric, the sidewall of the dielectric diffusion barrier liner, and the top surface of the active layer.

[0189] Example 12 is the semiconductor device described in Example 1, wherein: the substrate comprises a monocrystalline silicon substrate; a lower-level dielectric layer with a lower-level metal interconnect structure is located between the monocrystalline silicon substrate and the insulating layer; and a field-effect transistor is embedded in the lower-level dielectric layer and electrically connected to at least one of a gate electrode, a source electrode, and a drain electrode, wherein the field-effect transistor includes a corresponding portion of the monocrystalline silicon substrate as a channel.

[0190] Example 13 is a semiconductor device comprising: an insulating layer having a bottom gate electrode embedded therein and covering a substrate; a first stack covering a top surface of the bottom gate electrode of the following: a bottom gate dielectric comprising a first gate dielectric material, a dielectric diffusion barrier liner comprising a dielectric diffusion barrier material and covering the bottom gate dielectric, and an active layer, wherein the dielectric diffusion barrier material is different from the first gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; a second stack of the following: a top gate dielectric and a top gate electrode, the top gate electrode covering the bottom gate electrode and having a regional overlap with the bottom gate electrode in a plan view; and source electrodes and drain electrodes contacting corresponding portions of the top surface of the active layer.

[0191] Example 14 is a semiconductor device of Example 13, further comprising a capped dielectric diffusion barrier liner comprising a capped dielectric metal oxide material and contacting a top surface of the active layer located between the source electrode and the drain electrode, wherein each surface of the active layer is in contact with a corresponding surface selected from: the top surface of the dielectric diffusion barrier liner, the surface of the source electrode, the surface of the drain electrode, and the surface of the capped dielectric diffusion barrier liner.

[0192] Example 15 is the semiconductor device described in Example 14, further comprising: a dielectric layer laterally surrounding the stack of the bottom gate dielectric and the active layer; and a back-side electrode contact via structure contacting the top surface of the bottom gate electrode, wherein the source electrode, the drain electrode, the top gate electrode, and the top surface of the back-side electrode contact via structure are located in a horizontal plane including the top surface of the dielectric layer.

[0193] Example 16 is a method of forming a semiconductor device, comprising: forming a gate electrode within an insulating layer covering a substrate; forming a stack of the following over the gate electrode and the insulating layer: a gate dielectric comprising a gate dielectric material, a dielectric diffusion barrier liner comprising a dielectric diffusion barrier material, and an active layer, wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; and forming a source electrode and a drain electrode at an end of the active layer.

[0194] Example 17 is the method of Example 16, further comprising: annealing the dielectric diffusion barrier liner at a first annealing temperature above 400 degrees Celsius; and annealing the active layer at a second annealing temperature below 350 degrees Celsius.

[0195] Example 18 is the method of Example 16, wherein: the active layer is formed by deposition and patterning of a compound semiconductor material comprising at least two metal elements and oxygen; and the dielectric diffusion barrier liner is formed by deposition and patterning of an oxide material comprising at least one metal element selected from the at least two metal elements.

[0196] Example 19 is the method of Example 18, wherein: the active layer comprises an indium-containing semiconductor metal oxide material; and the dielectric diffusion barrier liner comprises an indium-free dielectric material.

[0197] Example 20 is the method of Example 16, further comprising forming a capped dielectric diffusion barrier liner comprising a capped dielectric metal oxide material on the top surface of the active layer, wherein the source electrode and the drain electrode are formed directly on the active layer through the capped dielectric diffusion barrier liner.

Claims

1. A semiconductor device, comprising: An insulating layer, with embedded gate electrodes and covering the substrate; A stack of the following items covering the top surface of the gate electrode: a gate dielectric comprising a gate dielectric material, a dielectric diffusion barrier liner comprising a dielectric diffusion barrier material and covering the gate dielectric, and an active layer, wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; The source electrode and drain electrode contact the corresponding portions of the top surface of the active layer; as well as A capped dielectric diffusion barrier liner includes a capped dielectric metal oxide material and a portion covering the gate electrode that contacts the top surface of the active layer, wherein the capped dielectric diffusion barrier liner contacts the sidewalls of the gate dielectric, the sidewalls of the dielectric diffusion barrier liner, and the top surface of the active layer. The active layer comprises an indium-containing semiconductor metal oxide material, and the dielectric diffusion barrier liner comprises an indium-free dielectric material.

2. The semiconductor device as claimed in claim 1, wherein, The sidewalls of the gate dielectric, the sidewalls of the dielectric diffusion barrier liner, and the sidewalls of the active layer overlap each other in the vertical direction.

3. The semiconductor device as claimed in claim 1, wherein: The active layer comprises a compound semiconductor material, wherein the compound semiconductor material comprises at least two metal elements and oxygen; and The dielectric diffusion barrier liner comprises an oxide material, wherein the oxide material comprises at least one metal element selected from the at least two metal elements.

4. The semiconductor device of claim 3, wherein: The active layer comprises indium gallium zinc oxide; and The dielectric diffusion barrier liner comprises a material selected from gallium oxide, zinc oxide, and zinc gallium oxide.

5. The semiconductor device as claimed in claim 1, wherein, The dielectric diffusion barrier liner comprises an alkaline earth metal oxide.

6. The semiconductor device of claim 1, wherein, The dielectric diffusion barrier liner comprises a dielectric oxide of a transition metal or aluminum oxide.

7. The semiconductor device of claim 1, wherein the dielectric diffusion barrier liner comprises a material selected from silicon nitride and silicon oxide.

8. The semiconductor device of claim 1, wherein, Each surface of the active layer is in contact with a corresponding surface selected from the following: the top surface of the dielectric diffusion barrier liner, the surface of the source electrode, the surface of the drain electrode, and the surface of the cap dielectric diffusion barrier liner.

9. The semiconductor device of claim 1, wherein: The substrate includes a monocrystalline silicon substrate; A lower-level dielectric layer with embedded lower-level metal interconnect structures is located between the single-crystal silicon substrate and the insulating layer; and A field-effect transistor is embedded within the lower dielectric layer and electrically connected to at least one of a gate electrode, a source electrode, and a drain electrode, wherein the field-effect transistor includes a corresponding portion of the monocrystalline silicon substrate as a channel.

10. A semiconductor device, comprising: An insulating layer, with an embedded bottom gate electrode and covering the substrate; A first stack covering the top surface of the bottom gate electrode includes the following: a bottom gate dielectric comprising a first gate dielectric material, a dielectric diffusion barrier liner comprising a dielectric diffusion barrier material and covering the bottom gate dielectric, and an active layer, wherein the dielectric diffusion barrier material is different from the first gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds. The second stack of the following items: top gate dielectric and top gate electrode, the top gate electrode covering the bottom gate electrode and having a region of overlap with the bottom gate electrode in a plan view; The source electrode and drain electrode contact corresponding portions of the top surface of the active layer; and A capped dielectric diffusion barrier liner, comprising a capped dielectric metal oxide material, and contacting the top surface and sidewalls of the active layer and the horizontal bottom surface of the portion of the top gate dielectric located below the top gate electrode. The active layer comprises an indium-containing semiconductor metal oxide material, and the dielectric diffusion barrier liner comprises an indium-free dielectric material.

11. The semiconductor device of claim 10, wherein each surface of the active layer is in contact with a corresponding surface selected from: the top surface of the dielectric diffusion barrier liner, the surface of the source electrode, the surface of the drain electrode, and the surface of the cap dielectric diffusion barrier liner.

12. The semiconductor device of claim 11, further comprising: A dielectric layer, laterally surrounding the stack of the bottom gate dielectric and the active layer; as well as The back-side electrode contact via structure contacts the top surface of the bottom gate electrode. The top surfaces of the source electrode, the drain electrode, the top gate electrode, and the back electrode contact via structure are located within a horizontal plane including the top surface of the dielectric layer.

13. A method of forming a semiconductor device, comprising: A gate electrode is formed within an insulating layer covering the substrate; A stack of the following is formed over the gate electrode and the insulating layer: a gate dielectric comprising a gate dielectric material, a dielectric diffusion barrier liner comprising a dielectric diffusion barrier material, and an active layer, wherein the dielectric diffusion barrier material is different from the gate dielectric material and is selected from dielectric metal oxide materials and silicon dielectric compounds; A capped dielectric diffusion barrier liner comprising a capped dielectric metal oxide material is formed on the top surface of the active layer; as well as A source electrode and a drain electrode are formed at the ends of the active layer, wherein the source electrode and the drain electrode are formed directly on the active layer through the cap dielectric diffusion barrier liner. The active layer comprises an indium-containing semiconductor metal oxide material, and the dielectric diffusion barrier liner comprises an indium-free dielectric material.

14. The method of claim 13, further comprising: The dielectric diffusion barrier liner is annealed at a first annealing temperature above 400 degrees Celsius; as well as The active layer is annealed at a second annealing temperature below 350 degrees Celsius.

15. The method of claim 13, wherein: The active layer is formed by depositing and patterning a compound semiconductor material comprising at least two metal elements and oxygen; and The dielectric diffusion barrier liner is formed by depositing and patterning an oxide material, the oxide material comprising at least one metal element selected from the at least two metal elements.

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