Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method for fabricating the same are disclosed. The method for fabricating the semiconductor device includes forming a gate structure on a substrate, forming a first spacer next to the gate structure, forming a second spacer next to the first spacer, forming an epitaxial layer next to the second spacer, forming a second cap layer on the epitaxial layer, and forming a first cap layer on the second cap layer, wherein a top surface of the first cap layer includes a V-shape, and the first cap layer and the second cap layer include different materials.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a device with a V-shaped cap layer. BACKGROUND

[0002] To increase the carrier mobility of a semiconductor structure, a compressive or tensile stress can be applied to the gate channel. For example, if a compressive stress is desired, a selective epitaxial growth (SEG) technique is often used to form an epitaxial structure, such as a silicon germanium (SiGe) epitaxial structure, in a silicon substrate. The lattice constant of the silicon germanium epitaxial structure is larger than that of the silicon substrate, which results in a stress on the channel region of a P-type metal-oxide-semiconductor transistor, increases the carrier mobility of the channel region, and increases the speed of the metal-oxide-semiconductor transistor. Conversely, if an N-type semiconductor transistor is desired, a silicon carbide (SiC) epitaxial structure can be formed in the silicon substrate to apply a tensile stress to the gate channel region.

[0003] In a conventional transistor process, a recess is formed on both sides of a gate structure before an epitaxial layer is formed by an epitaxial growth process. However, the epitaxial layer formed by the epitaxial growth process often has an uneven surface profile, which affects the operation of the device. Therefore, how to improve the conventional fabrication process to solve the bottleneck is an important issue. SUMMARY

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. A gate structure is formed on a substrate, a first spacer is formed beside the gate structure, a second spacer is formed beside the first spacer, an epitaxial layer is formed beside the second spacer, a second cap layer is formed on the epitaxial layer, and a first cap layer is formed on the second cap layer, wherein the top surface of the first cap layer comprises a V-shape, and the first cap layer and the second cap layer comprise different materials.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly comprises a gate structure formed on a substrate,

[0006] an epitaxial layer formed beside the gate structure, and a first cap layer formed on the epitaxial layer, wherein the top surface of the first cap layer comprises a V-shape. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1 to 5This is a schematic diagram of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0008] Figure 6 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0009] Figure 7 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0010] Figure 8 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention.

[0011] Explanation of main component symbols

[0012] 12: Base

[0013] 14: Gate Structure

[0014] 16: Gate Structure

[0015] 18: Gate dielectric layer

[0016] 20: Gate material layer

[0017] 22: Hard Mask

[0018] 24: Spacer wall

[0019] 26: Lightly doped drain

[0020] 28: Groove

[0021] 30: Epitaxial layer

[0022] 32: Buffer layer

[0023] 34: First Linear Main Layer

[0024] 36: Second Linear Main Layer

[0025] 38: Main body layer

[0026] 40: Covering layer

[0027] 42: Source / Drain Region

[0028] 44: Contact hole etching stop layer

[0029] 46: Interlayer dielectric layer

[0030] 48: Dielectric layer

[0031] 50: High dielectric constant dielectric layer

[0032] 52: Work function metal layer

[0033] 54: Low-resistivity metal layer

[0034] 56: Hard Mask

[0035] 58: Contact plug

[0036] 60 layers of shielding

[0037] 62: V-shape

[0038] 64: Flat surface

[0039] 66: Curved Surface Detailed Implementation

[0040] Please refer to Figures 1 to 5 , Figures 1 to 5 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, and then at least one gate structure 14, 16 is formed on the substrate 12. In this embodiment, the gate structures 14, 16 are preferably formed by sequentially forming a gate dielectric layer, a gate material layer, and a hard mask on the substrate 12, and using a patterned photoresist (not shown) as a mask to perform a pattern transfer fabrication process, removing part of the hard mask, part of the gate material layer, and part of the gate dielectric layer in a single etch or successive etch step, and then stripping the patterned photoresist to form at least one gate structure 14, 16 on the substrate 12, which is composed of a patterned gate dielectric layer 18, a patterned gate material layer 20, and a patterned hard mask 22. In this embodiment, the number of gate structures 14 and 16 is two, but it is not limited to this. In order to highlight the buffer layer and epitaxial layer formed between the two gate structures 14 and 16, this embodiment only shows part of the gate structures 14 and 16, for example, only the right half of the gate structure 14 and the left half of the gate structure 16.

[0041] In this embodiment, the substrate 12 is, for example, a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The gate dielectric layer 18 may comprise silicon dioxide (SiO2), silicon nitride (SiN), or a high dielectric constant (high-k) material; the gate material layer 20 may comprise conductive materials such as metal, polysilicon, or metal silicide; the hard mask 22 may be selected from the group consisting of silicon oxide, silicon nitride, silicon carbide (SiC), and silicon oxynitride (SiON), but is not limited thereto.

[0042] In one embodiment, a plurality of doped wells (not shown) or a plurality of shallow trench isolation (STI) for electrical isolation can also be formed in the substrate 12 in advance. In addition, although the present embodiment is described with respect to planar transistors, the semiconductor fabrication process of the present application can also be applied to non-planar transistors, such as fin transistors (Fin-FET), in which case, Figure 1 The substrate 12 is shown as a fin structure formed on a substrate 12.

[0043] At least one spacer 24 is then formed on the sidewalls of the gate structures 14, 16, and a selective light doped ion implantation is performed, followed by a rapid thermal anneal process at a temperature of about 930 °C to activate the implanted dopants in the substrate 12 to form a light doped drain 26 in the substrate 12 on both sides of the spacer 24. In the present embodiment, the spacer 24 can be a single spacer or a composite spacer, such as a combination of a bias spacer (not shown) and a main spacer (not shown), in which the bias spacer and the main spacer are preferably made of different materials, and can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbon nitride, but not limited thereto.

[0044] A dry etching and / or wet etching process is then performed to etch the substrate 12 along the spacer 24 to form a recess 28 in the substrate 12 on both sides of the gate structures 14, 16 using the gate structures 14, 16 and the spacer 24 as etching masks. For example, the etching process can include a dry etching step to form an initial trench (not shown) in the substrate 12 on both sides of the gate structures 14, 16, followed by a wet etching process to isotropically enlarge the initial trench to form the recess 28. In one embodiment of the present application, the wet etching process can use an etching liquid such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH). It is noted that the recess 28 can be formed by a single or multiple dry etching and / or wet etching process, and is not limited to the dry etching and wet etching process described above. For example, in one embodiment, the recess 28 can have different cross-sectional shapes, such as a circular arc, a hexagon (also known as sigma Σ), or an octagon, and the present embodiment is described with respect to a circular arc cross-sectional shape, but is not limited thereto.

[0045] Subsequently, as shown in FIG. 2B, a first epitaxial layer 30 is formed on the substrate 12 on both sides of the gate structures 14, 16 and the spacer 24. In the present embodiment, the first epitaxial layer 30 is formed by a selective epitaxial growth (SEG) process, and can be made of a material such as polysilicon, but is not limited thereto. Figure 2As shown, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer 30 in each recess 28 using a gas such as dichlorosilane (DCS), wherein the epitaxial layer 30 includes a buffer layer 32 disposed on the surface of the recess 28, a first linear bulk layer 34 disposed on the buffer layer 32, a second linear bulk layer 36 disposed on the first linear bulk layer 34, a bulk layer 38 disposed on the second linear bulk layer 36, and a cap layer 40 disposed on the bulk layer 38.

[0046] In the present embodiment, the top surface of the epitaxial layer 30 is preferably flush with the top surface of the substrate 12, and preferably has the same cross-sectional shape as the recess 28, such as a circular, hexagonal (also known as sigma) or octagonal cross-sectional shape, but other cross-sectional shapes are also possible. In the preferred embodiment of the present application, the epitaxial layer 30 can have different materials depending on the type of metal-oxide-semiconductor (MOS) transistor, for example, if the metal-oxide-semiconductor transistor is a P-type transistor (PMOS), the epitaxial layer 30 can be selected to include silicon-germanium (SiGe), silicon-germanium-boron (SiGeB) or silicon-germanium-tin (SiGeSn). In another embodiment of the present application, if the metal-oxide-semiconductor transistor is an N-type transistor (NMOS), the epitaxial layer 30 can be selected to include silicon-carbon (SiC), silicon-carbon-phosphorus (SiCP) or silicon-phosphorus (SiP). In addition, the selective epitaxial growth process can be performed in a single layer or multiple layers, and the hetero-atoms (such as germanium atoms or carbon atoms) can be gradually changed in layers, but preferably the surface of the epitaxial layer 30 is relatively free of germanium atoms or free of germanium atoms to facilitate the formation of a subsequent metal silicide layer. On the other hand, although the present embodiment is described with the epitaxial layer 30 having a top surface flush with the top surface of the substrate 12, in other embodiments of the present application, the epitaxial layer 30 can be selected to extend further upward above the top surface of the substrate 12.

[0047] A subsequent ion implantation fabrication process is performed to form a source / drain region 42 in a portion or all of the epitaxial layer 30. In another embodiment, the source / drain region 42 can also be formed in-situ with the selective epitaxial growth fabrication process. For example, when the metal oxide semiconductor is a PMOS, a germanium silicide epitaxial layer, a germanium silicide boron epitaxial layer or a germanium silicide tin epitaxial layer can be formed, which can be accompanied by implantation of P-type dopants; or when the metal oxide semiconductor is an NMOS, a carbon silicide epitaxial layer, a carbon silicide phosphorus epitaxial layer or a phosphorus silicide epitaxial layer can be formed, which can be accompanied by implantation of N-type dopants. Thus, the subsequent ion implantation step to form the source / drain region of the P-type / N-type transistor can be omitted. In addition, in another embodiment, the dopants of the source / drain region 42 can also be formed in a graded manner.

[0048] It is noted that the epitaxial layer 30 disclosed in the present embodiment preferably comprises a germanium silicide (SiGe), and the buffer layer 32, the first linear body layer 34, the second linear body layer 36, the body layer 38 and the cap layer 40 in the epitaxial layer 30 have different concentration distributions and distribution curves, respectively. For example, in the present embodiment, the germanium concentration of the buffer layer 32 is preferably less than the germanium concentration of the first linear body layer 34, the germanium concentration of the first linear body layer 34 is less than the germanium concentration of the second linear body layer 36, the germanium concentration of the second linear body layer 36 is less than the germanium concentration of the body layer 38, and the germanium concentration of the cap layer 40 is less than the germanium concentration of the body layer 38, wherein the slope of the germanium concentration of the first linear body layer 34 is preferably less than the slope of the germanium concentration of the second linear body layer 36, and the thickness of the second linear body layer 36 is also less than the thickness of the first linear body layer 34.

[0049] According to the preferred embodiment of the present application, the germanium concentration of the buffer layer 32 is preferably between 30% and 33%, the germanium concentration of the first linear body layer 34 is preferably less than 39%, the germanium concentration of the second linear body layer 36 is preferably between 39% and 47%, the germanium concentration of the body layer 38 is preferably between 47% and 60%, and the germanium concentration of the cap layer 40 is preferably between 28% and 30%. In addition, in terms of thickness, the thickness of the buffer layer 32 is preferably about 100 angstroms, the thickness of the first linear body layer 34 is preferably about 100 angstroms, the thickness of the second linear body layer 36 is preferably between 30-50 angstroms, and the thickness of the body layer 38 is preferably between 200-300 angstroms.

[0050] Next, as shown in FIG. 3, a selective epitaxial growth process is performed to form a first linear body layer 34 and a second linear body layer 36 on the buffer layer 32. The first linear body layer 34 and the second linear body layer 36 are formed by a selective epitaxial growth process, and the first linear body layer 34 and the second linear body layer 36 have different thicknesses and different germanium concentrations, respectively. For example, the thickness of the first linear body layer 34 is preferably greater than the thickness of the second linear body layer 36, and the germanium concentration of the first linear body layer 34 is preferably less than the germanium concentration of the second linear body layer 36. Figure 3As shown, a silicon-based masking layer 60 is formed on the surface of the masking layer 40 using silane (SiH4) and dichlorosilane (DCS) as precursors, along with other gases. It is noteworthy that the step of forming the masking layer 60 is preferably performed by introducing the aforementioned precursors and other reactive gases, such as hydrogen chloride (HCl) and / or diborane (B2H2), without introducing a germanium-containing gas, such as germanane (GeH4). The flow rate of silane is preferably between 180 and 300 standard cubic centimeters per minute (sccm), the flow rate of dichlorosilane is between 60 and 100 sccm, the flow rate of hydrogen chloride is between 40 and 100 sccm, and the flow rate of diborane is between 200 and 300 sccm. In addition, the deposition time of the cover layer is preferably between 120 and 170 seconds, the manufacturing temperature is preferably between 740 and 770 degrees Celsius, and the pressure is preferably between 5 and 20 Torr.

[0051] According to a preferred embodiment of the present invention, a roughly bowl-shaped cover layer 60 can be formed on the surface of the cover layer 40 of the epitaxial layer 30 by means of the above-described formulation. The top surface of the cover layer 60 preferably includes a V-shaped profile 62 and two flat surfaces 64 respectively connecting the two sides of the V-shaped profile 62. This specially profiled cover layer 60 can be used to protect the spacer walls, especially the offset spacer walls, from being eroded by the etching process in subsequent series of fabrication processes and thus not be worn away to form voids, thereby reducing the probability of defects in semiconductor devices.

[0052] like Figure 4 As shown, a contact etch stop layer (CESL) 44 made of silicon nitride is selectively formed on the substrate 12, covering the gate structures 14 and 16 and the masking layer 60. Then, an interlayer dielectric layer 46 is formed on the contact etch stop layer 44. Next, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 46 and part of the contact etch stop layer 36 so that the upper surface of the hard mask 22 is flush with the upper surface of the interlayer dielectric layer 46.

[0053] A metal gate replacement process is then performed to convert the gate structures 14, 16 into metal gates. For example, a selective dry etching or wet etching process can be performed first to remove the hard mask 22, the gate material layer 20, and even the gate dielectric layer 18 in the gate structures 14, 16 to form recesses (not shown) in the ILD layer 46. Subsequently, a dielectric layer 48, a high-k dielectric layer 50, and a conductive layer including at least a work function metal layer 52 and a low impedance metal layer 54 are formed in the recesses, and a planarization process is performed to make the surfaces of the U-shaped high-k dielectric layer 50, the U-shaped work function metal layer 52, and the low impedance metal layer 54 flush with the surface of the ILD layer 46.

[0054] In this embodiment, the high-k dielectric layer 50 includes a dielectric material having a dielectric constant greater than 4, such as selected from the group consisting of hafnium oxide (Hf02), hafnium silicon oxide (HfSi04), hafnium silicon oxynitride (HfSiON), aluminum oxide (AI2O3), lanthanum oxide (La203), tantalum oxide (Ta205), yttrium oxide (Y203), zirconium oxide (Zr02), strontium titanate oxide (SrTi03), zirconium silicon oxide (ZrSi04), hafnium zirconium oxide (HfZr04), strontium bismuth tantalate (SrBi2Ta20g, SBT), lead zirconate titanate (PbZrTi03, PZT), barium strontium titanate (BaSrTi03, BST), or a combination thereof. x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0055] The work function metal layer 52 is preferably used to adjust the work function of the metal gate to make it suitable for N-type transistors (NMOS) or P-type transistors (PMOS). If the transistor is an N-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto; if the transistor is a P-type transistor, the work function metal layer 52 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) may be included between the work function metal layer 52 and the low impedance metal layer 54. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low impedance metal layer 54 may be selected from low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), or combinations thereof. Since the conversion of a dummy gate into a metal gate according to the metal gate replacement fabrication process is a well-known technique in this field, it will not be described in detail here. Next, a portion of the high dielectric constant dielectric layer 50, a portion of the work function metal layer 52, and a portion of the low impedance metal layer 54 may be removed to form a groove (not shown). Then, a hard mask 56 is filled into the groove and made flush with the surface of the interlayer dielectric layer 46. The hard mask 56 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide.

[0056] like Figure 5 As shown, a pattern transfer fabrication process can then be performed. For example, a patterned mask can be used to remove a portion of the interlayer dielectric layer 46 and a portion of the contact hole etching stop layer 44 adjacent to the gate structures 14 and 16 to form multiple contact holes (not shown) and expose the underlying cover layer 60. Then, the desired metal material is filled into each contact hole, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. A planarization fabrication process is then performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs 58 in each contact hole to electrically connect the source / drain regions 42. This completes the fabrication of the semiconductor device according to the preferred embodiment of the present invention.

[0057] Please refer to this again. Figure 5 , Figure 5A semiconductor device structure is disclosed in one embodiment of the present application. As shown in Figure 5 The semiconductor device includes at least one gate structure 14 disposed on a substrate 12, a spacer 24 disposed on sidewalls of the gate structure 14, an epitaxial layer 30 disposed in the substrate 12 on both sides of the spacer 24, and a cap layer 60 disposed on the epitaxial layer 30, wherein the epitaxial layer 30 includes a buffer layer 32, a first linear body layer 34, a second linear body layer 36, a body layer 38, and a cap layer 40.

[0058] In this embodiment, the top surface of the cap layer 40 is higher than the top surface of the substrate 12, the bottom surface of the cap layer 40 is flush with the top surface of the substrate 12, the buffer layer 32, the first linear body layer 34, the second linear body layer 36, the body layer 38, and the cap layer 40 in the epitaxial layer 30 preferably include the same material, for example, are all composed of silicon germanium (SiGe), but as mentioned above can include different concentration profiles, the cap layer 40 and the cap layer 60 preferably include different materials, for example, the cap layer 60 is preferably composed of silicon, the bottom surface of the cap layer 60 is higher than the top surface of the substrate 12, and the top surface of the cap layer 60 can be selected to be slightly lower than half the height of the gate structure 14 or slightly higher than half the height of the gate structure 14.

[0059] The cap layer 60 as a whole preferably has a shape of a bowl in terms of shape, wherein the top surface of the cap layer 60 can include a V-shaped portion 62 and two flat surfaces 64 parallel to the surface of the substrate 12 connected to both sides of the V-shaped portion 62. However, it is not limited thereto, as shown in Figure 6 Another embodiment of the present application Figure 5 is shown in The V-shaped portion 62 can be replaced by a concave curved surface 66 connected to the two flat surfaces 64 in addition to the V-shaped bottom of the cap layer 60 as a whole having a V-shaped top surface, and this change is also within the scope of the present application.

[0060] Figures 7 to 8 Please refer to Figures 7 to 8 for the structure of a semiconductor device in different embodiments of the present application. As shown in Figure 7 Compared with Figure 5 the contact plug 58 in only has a V-shaped profile at the bottom or only contacts the V-shaped top profile of the cap layer 60, the present application can also adjust the width of the contact plug 58 so that the bottom of the contact plug 58 simultaneously straddles the V-shaped 62 profile and the flat surface 64 of the cap layer 60 or the bottom of the contact plug 58 itself has a V-shaped 62 profile and the flat surface 64 is located on both sides of the V-shaped 62 profile, and this change is also within the scope of the present application.

[0061] Figure 8 In addition, as shown in Figure 7In another variation, the width of the contact plug 58 is again enlarged and the ILD 46 is omitted such that the bottom of the contact plug 58 has a V-shaped profile 62 and flat surfaces 64 on both sides of the V-shaped profile 62. The sidewalls of the contact plug 58 on both sides of the V-shaped profile 62 directly contact the contact hole etch stop layer 44 instead of the ILD 46. This variation is also within the scope of the present application.

[0062] In summary, the present application is directed to forming a bowl-shaped cap layer 60 having a V-shaped top profile and two flat surfaces on a silicon-containing epitaxial layer after forming the epitaxial layer including a buffer layer, a body layer and a cap layer made of silicon-germanium. According to the preferred embodiment of the present application, the bowl-shaped cap layer 60 formed by a specific recipe of fabrication process can be used to protect the spacer sidewall, especially the offset spacer sidewall, from being eroded by subsequent fabrication processes and from forming voids, thereby reducing the probability of defects in semiconductor devices.

[0063] The above description is only the preferred embodiment of the present application. Any equivalent variation and modification made according to the claims of the present application should be within the scope of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, Comprising: forming a gate structure on a substrate; forming a spacer next to the gate structure; forming an epitaxial layer next to the spacer, wherein an upper surface of the epitaxial layer is level with or higher than an upper surface of the substrate; and forming a first cap layer on the epitaxial layer, wherein the first cap layer comprises a V-shaped upper surface with a bottom higher than the upper surface of the substrate, wherein the first cap layer directly contacts the spacer.

2. The method of claim 1, wherein the epitaxial layer comprises a second cap layer, and the first cap layer is disposed on the second cap layer.

3. The method of claim 2, wherein an upper surface of the second cap layer is higher than the upper surface of the substrate.

4. The method of claim 2, wherein a lower surface of the second cap layer is level with the upper surface of the substrate.

5. The method of claim 2, wherein the first cap layer and the second cap layer comprise different materials.

6. The method of claim 1, wherein the epitaxial layer and the first cap layer comprise different materials.

7. The method of claim 1, wherein a lower surface of the first cap layer is higher than the upper surface of the substrate.

8. The method of claim 1, wherein an upper surface of the first cap layer is higher than half a height of the gate structure.

9. A semiconductor element characterized by comprising: Comprising: a gate structure disposed on a substrate; an epitaxial layer disposed next to the gate structure, wherein an upper surface of the epitaxial layer is level with or higher than an upper surface of the substrate; a first cap layer disposed on the epitaxial layer, wherein the first cap layer comprises a V-shaped upper surface with a bottom higher than the upper surface of the substrate; a spacer disposed next to the gate structure; and the epitaxial layer disposed next to the spacer, wherein the first cap layer directly contacts the spacer.

10. The semiconductor element of claim 9, wherein the epitaxial layer comprises a second cap layer, and the first cap layer is disposed on the second cap layer.

11. The semiconductor element of claim 10, wherein an upper surface of the second cap layer is higher than the upper surface of the substrate.

12. The semiconductor element of claim 10, wherein a lower surface of the second cap layer is level with the upper surface of the substrate.

13. The semiconductor element of claim 10, wherein the first cap layer and the second cap layer comprise different materials.

14. The semiconductor element of claim 9, wherein the epitaxial layer and the first cap layer comprise different materials.

15. The semiconductor element of claim 9, wherein a lower surface of the first cap layer is higher than the upper surface of the substrate.

16. The semiconductor element of claim 9, wherein an upper surface of the first cap layer is higher than half a height of the gate structure.

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