AlGaInP-based red light emitting diode chip and preparation method thereof

Abstract

The present disclosure provides an AlGaInP-based red light emitting diode chip and a preparation method thereof, belonging to the field of optoelectronic manufacturing technology. The AlGaInP-based red light emitting diode chip includes: a substrate, a light emitting structure, a distributed Bragg reflector layer, a passivation layer, a first solder block and a second solder block; the light emitting structure, the distributed Bragg reflector layer and the passivation layer are sequentially stacked on the substrate, the passivation layer has a first through hole and a second through hole exposing the distributed Bragg reflector layer, the hole wall of the first through hole and the hole wall of the second through hole have a concave-convex structure; the first solder block is located in the first through hole and is in contact with the hole wall of the first through hole, and the second solder block is located in the second through hole and is in contact with the hole wall of the second through hole. The embodiment of the present disclosure can improve the problem of relative looseness between the solder block and the via hole, so that the light emitting structure is well fixed in the chip, and the reliability of the chip is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technology, and in particular to an AlGaInP-based red light emitting diode chip and a preparation method thereof. Background Art

[0002] Micro LEDs (Micro Light Emitting Diodes) refer to ultra-small light-emitting diodes with side lengths ranging from 10μm to 100μm. Due to their small size, micro LEDs can be arranged more densely, significantly improving resolution. They also have self-luminous properties, and have the characteristics of high brightness, high contrast, high responsiveness, and energy saving.

[0003] In related technologies, a red light-emitting diode chip generally includes a substrate, a light-emitting structure, a distributed Bragg reflector layer, a passivation layer, and two solder joint blocks. The light-emitting structure, the distributed Bragg reflector layer, and the passivation layer are sequentially stacked on the surface of the substrate. The passivation layer has two vias exposing the distributed Bragg reflector layer. The two solder joint blocks are respectively located in the two vias and are electrically connected to the two electrodes in the light-emitting structure through the through holes on the distributed Bragg reflector layer.

[0004] However, during the use of the chip, the two solder blocks will be subjected to greater pressure. If the connection between the solder block and the via hole is poor, the solder block will become loose in the via hole, making it difficult to properly fix the light-emitting structure, affecting the reliability of the chip. Summary of the Invention

[0005] The disclosed embodiments provide an AlGaInP-based red light-emitting diode chip and its manufacturing method, which can improve the relative looseness between the solder joint block and the via hole, allowing the light-emitting structure to be well fixed within the chip and improving the chip's reliability. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides an AlGaInP-based light-emitting diode chip, wherein the AlGaInP-based red light-emitting diode chip includes: a substrate, a light-emitting structure, a distributed Bragg reflector layer, a passivation layer, a first solder block and a second solder block; the light-emitting structure, the distributed Bragg reflector layer and the passivation layer are sequentially stacked on the substrate, the passivation layer has a first through hole and a second through hole exposing the distributed Bragg reflector layer, and the hole wall of the first through hole and the hole wall of the second through hole have a concave-convex structure; the first solder block is located in the first through hole and is in contact with the hole wall of the first through hole, and the second solder block is located in the second through hole and is in contact with the hole wall of the second through hole.

[0007] Optionally, the concave-convex structure includes at least one of a sawtooth protrusion, a strip-shaped ridge and a strip-shaped groove.

[0008] Optionally, the first solder block and the second solder block both include a Ti layer, a first Ni layer, a composite layer, a second Ni layer and a Sn alloy layer stacked in sequence, the composite layer includes a first alloy layer, a W layer and a second alloy layer stacked in sequence, and the first alloy layer and the second alloy layer both include W and Ni.

[0009] Optionally, in the first alloy layer, the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%; in the second alloy layer, the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%.

[0010] Optionally, the thickness of the Ti layer is 800 angstroms to 1200 angstroms, the thickness of the first Ni layer is 800 angstroms to 1200 angstroms, the thickness of the composite layer is 4000 angstroms to 6000 angstroms, the thickness of the second Ni layer is 2500 angstroms to 3500 angstroms, and the thickness of the Sn alloy layer is 80,000 angstroms to 100,000 angstroms; in the composite layer, the thickness of the first alloy layer is 800 angstroms to 1200 angstroms, the thickness of the W layer is 2500 angstroms to 3500 angstroms, and the thickness of the second alloy layer is 800 angstroms to 1200 angstroms.

[0011] Optionally, the thickness of the passivation layer is not less than the sum of the thicknesses of the Ti layer, the first Ni layer and the composite layer.

[0012] Optionally, the light-emitting structure includes: a first semiconductor layer, a multi-quantum well layer, a second semiconductor layer, a first electrode and a second electrode, the first semiconductor layer, the multi-quantum well layer and the second semiconductor layer are stacked in sequence on a substrate, the second electrode is located on the surface of the second semiconductor layer, the surface of the second semiconductor layer has a connecting groove exposing the first semiconductor layer, the first electrode is located on the surface of the first semiconductor layer and on the bottom of the connecting groove, and the distributed Bragg reflector layer at least covers the surfaces of the first semiconductor layer, the first electrode, the connecting groove, the second semiconductor layer and the second electrode.

[0013] On the other hand, the present disclosure also provides a method for preparing an AlGaInP-based red light emitting diode chip, the method comprising:

[0014] providing a substrate;

[0015] forming a light-emitting structure, a distributed Bragg reflector layer, and a passivation layer on the substrate in sequence, wherein the passivation layer has a first through hole and a second through hole exposing the distributed Bragg reflector layer, and the hole walls of the first through hole and the hole walls of the second through hole have a concave-convex structure;

[0016] A first soldering point block is made in the first through hole, and a second soldering point block is made in the second through hole. The first soldering point block is attached to the hole wall of the first through hole, and the second soldering point block is attached to the hole wall of the second through hole.

[0017] Optionally, forming a passivation layer on the distributed Bragg reflector layer includes: depositing the passivation layer on the surface of the distributed Bragg reflector layer, and during the deposition process, controlling the deposition temperature to alternate between a first temperature and a second temperature, the first temperature being greater than the second temperature, and the alternation between the first temperature and the second temperature is completed once each time the passivation layer of a set thickness is deposited.

[0018] Optionally, the first temperature is 280° C. to 320° C., the second temperature is 180° C. to 220° C., and the set thickness is 500 angstroms to 1500 angstroms.

[0019] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0020] The AlGaInP-based red light-emitting diode chip provided in the embodiments of the present disclosure includes a substrate, a light-emitting structure, a distributed Bragg reflector layer, and a passivation layer stacked in sequence. The passivation layer has a first through-hole and a second through-hole exposing the distributed Bragg reflector layer, and the walls of the first through-hole and the second through-hole are both provided with a concave-convex structure. The first solder block is arranged in the first through hole, and the side wall of the first solder block matches the concave-convex structure on the hole wall of the first through hole, so that when the first solder block is in the first through hole, the side wall of the first solder block can be well combined with the hole wall of the first through hole, thereby improving the connection stability between the first solder block and the first through hole, and avoiding relative looseness between the first solder block and the first through hole; the second solder block is arranged in the second through hole, and similarly, the side wall of the second solder block can be well combined with the hole wall of the second through hole, so as to improve the connection stability between the second solder block and the second through hole, and avoid relative looseness between the first solder block and the first through hole; this can also allow the light-emitting structure located under the two solder blocks to be better fixed in the chip, thereby improving the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 This is a schematic structural diagram of an AlGaInP-based red light-emitting diode chip provided by an embodiment of the present disclosure;

[0023] Figure 2 is a schematic structural diagram of a first through hole in a passivation layer provided by an embodiment of the present disclosure;

[0024] Figure 3 1 is a top view of an AlGaInP-based red light-emitting diode chip provided by an embodiment of the present disclosure;

[0025] Figure 4 is a structural schematic diagram of a solder joint block provided by an embodiment of the present disclosure;

[0026] Figure 5 This is a flow chart of a method for preparing an AlGaInP-based red light emitting diode chip provided by an embodiment of the present disclosure;

[0027] Figure 6 This is a schematic diagram of a preparation process of an AlGaInP-based red light emitting diode chip provided by an embodiment of the present disclosure;

[0028] Figure 7 This is a schematic diagram of the preparation process of an AlGaInP-based red light emitting diode chip provided in an embodiment of the present disclosure.

[0029] The descriptions of the marks in the figure are as follows:

[0030] 10. Substrate; 11. GaAs substrate;

[0031] 20. Light-emitting structure; 21. First semiconductor layer; 22. Multi-quantum well layer; 23. Second semiconductor layer; 24. First electrode; 25. Second electrode; 26. First via hole; 27. Second via hole; 28. Connecting groove;

[0032] 30. Distributed Bragg reflector layer;

[0033] 40. passivation layer; 41. first through hole; 42. second through hole; 43. concave-convex structure;

[0034] 51. First solder joint block; 52. Second solder joint block; 510. Ti layer; 520. First Ni layer; 530. Composite layer; 531. First alloy layer; 532. W layer; 533. Second alloy layer; 540. Second Ni layer; 550. Sn alloy layer. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0036] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by a person of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," "third," and similar words used in the patent specification and claims of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish between different components. Similarly, terms such as "a" or "an" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprise" mean that the elements or objects preceding "include" or "comprises" encompass the elements or objects listed after "include" or "comprises," and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," "right," "top," and "bottom" are used only to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0037] Figure 1 This is a schematic structural diagram of an AlGaInP-based red light emitting diode chip provided by an embodiment of the present disclosure. Figure 1 As shown, the AlGaInP-based red light emitting diode chip includes: a substrate 10 , a light emitting structure 20 , a distributed Bragg reflector layer 30 , a passivation layer 40 , a first soldering point block 51 and a second soldering point block 52 .

[0038] like Figure 1 As shown, the light emitting structure 20, the distributed Bragg reflector layer 30 and the passivation layer 40 are sequentially stacked on the substrate 10, and the passivation layer 40 has a first through hole 41 and a second through hole 42 exposing the distributed Bragg reflector layer 30, and the hole wall of the first through hole 41 and the hole wall of the second through hole 42 have a concave-convex structure 43.

[0039] like Figure 1 As shown, the first soldering point block 51 is located in the first through hole 41 and is in contact with the hole wall of the first through hole 41 , and the second soldering point block 52 is located in the second through hole 42 and is in contact with the hole wall of the second through hole 42 .

[0040] The AlGaInP-based red light-emitting diode chip provided in the embodiment of the present disclosure includes a substrate 10, a light-emitting structure 20, a distributed Bragg reflector layer 30, and a passivation layer 40, which are stacked in sequence. The passivation layer 40 has a first through-hole 41 and a second through-hole 42 that expose the distributed Bragg reflector layer 30. The walls of the first through-hole 41 and the second through-hole 42 are both provided with a concave-convex structure 43. The first solder block 51 is arranged in the first through hole 41, and the side wall of the first solder block 51 also matches the concave-convex structure 43 on the hole wall of the first through hole 41, so that when the first solder block 51 is in the first through hole 41, the side wall of the first solder block 51 can be well combined with the hole wall of the first through hole 41, thereby improving the connection stability between the first solder block 51 and the first through hole 41, and avoiding relative looseness between the first solder block 51 and the first through hole 41; the second solder block 52 is arranged in the second through hole 42, and similarly, the side wall of the second solder block 52 can be well combined with the hole wall of the second through hole 42, so as to improve the connection stability between the second solder block 52 and the second through hole 42, and avoid relative looseness between the first solder block 51 and the first through hole 41; this can also allow the light-emitting structure 20 located below the two solder blocks to be better fixed in the chip, thereby improving the reliability of the chip.

[0041] Alternatively, as Figure 1 As shown, the light emitting structure 20 includes: a first semiconductor layer 21 , a multi-quantum well layer 22 , a second semiconductor layer 23 , a passivation layer 40 , a first electrode 24 and a second electrode 25 .

[0042] like Figure 1 As shown, the first semiconductor layer 21, the multi-quantum well layer 22 and the second semiconductor layer 23 are stacked in sequence on the substrate 10, the second electrode 25 is located on the surface of the second semiconductor layer 23, the surface of the second semiconductor layer 23 has a connection groove 28 exposing the first semiconductor layer 21, the first electrode 24 is located on the surface of the first semiconductor layer 21, and is located on the bottom of the connection groove 28, and the distributed Bragg reflector layer 30 covers at least the surfaces of the first semiconductor layer 21, the first electrode 24, the connection groove 28, the second semiconductor layer 23 and the second electrode 25.

[0043] A first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23 are stacked in sequence on a substrate 10, wherein a second electrode 25 is arranged on the surface of the second semiconductor layer 23, and the surface of the second semiconductor layer 23 has a connecting groove 28 exposing the first semiconductor layer 21, that is, part of the second semiconductor layer 23 and the multi-quantum well layer 22 are removed through the connecting groove 28, so that the first electrode 24 is directly arranged on the surface of the first semiconductor layer 21 through the connecting groove 28, so that the overall thickness of the epitaxial structure is thinned.

[0044] Optionally, the concave-convex structure 43 includes at least one of a sawtooth-shaped protrusion, a strip-shaped ridge, and a strip-shaped groove.

[0045] For example, Figure 2 Schematic diagram of the structure of the first through hole of the passivation layer provided by the embodiment of the present disclosure. Figure 2 As shown, the concavo-convex structure 43 includes a serrated protrusion, and the sidewall of the first solder block 51 located in the first through-hole 41 is also serrated, so that the sidewall of the first solder block 51 located in the first through-hole 41 can be closely connected to the hole wall of the first through-hole 41. The sidewall of the second solder block 52 located in the second through-hole 42 is also serrated, so that the sidewall of the second solder block 52 located in the second through-hole 42 can be closely connected to the hole wall of the second through-hole 42.

[0046] By forming a sawtooth-like concave-convex structure 43 on the walls of the first through-hole 41 and the second through-hole 42, the walls of the two through-holes have a sawtooth-like feature. The solder blocks disposed within the two through-holes are also configured with a sawtooth structure that matches the concave-convex structure 43, so that the solder blocks and the through-holes form a nearly integrated structure. This allows the side walls of the solder blocks to be well integrated with the walls of the through-holes, thereby improving the stability of the connection between the solder blocks and the through-holes, preventing relative looseness, and enhancing chip reliability.

[0047] For example, Figure 2 As shown, the concave-convex structure 43 may include strip-shaped ridges. The sidewall of the first soldering point block 51 located in the first through hole 41 has a strip-shaped groove so that the sidewall of the first soldering point block 51 located in the first through hole 41 can be attached to the hole wall of the first through hole 41.

[0048] For example, the concave-convex structure 43 may include a strip-shaped groove. The sidewall of the first soldering point block 51 located in the first through hole 41 has a strip-shaped ridge, so that the sidewall of the first soldering point block 51 located in the first through hole 41 can be attached to the hole wall of the first through hole 41.

[0049] Figure 3 FIG. 1 is a top view of an AlGaInP-based red light emitting diode chip provided by an embodiment of the present disclosure. Figure 3 As shown, the first soldering point block 51 and the second soldering point block 52 are both rectangular blocks, which increase the area and facilitate electrical conduction. In addition, the first soldering point block 51 and the second soldering point block 52 are spaced apart on the surface of the passivation layer 40.

[0050] Figure 4 Schematic diagram of a solder joint block provided by an embodiment of the present disclosure. Figure 4 As shown, the first solder block 51 and the second solder block 52 each include a Ti layer 510 , a first Ni layer 520 , a composite layer 530 , a second Ni layer 540 and a Sn alloy layer 550 stacked in sequence.

[0051] like Figure 4 As shown, the composite layer 530 includes a first alloy layer 531 , a W layer 532 , and a second alloy layer 533 stacked in sequence, and both the first alloy layer 531 and the second alloy layer 533 include W and Ni.

[0052] By providing a first Ni layer 520 and a second Ni layer 540 of a certain thickness in the metal layer of the solder block, the toughness of the two solder blocks can be enhanced, and the deformation resistance of the two solder blocks can be improved. By providing a Ti layer 510 of a certain thickness in the metal layer of the solder block, the strength of the two solder blocks can be enhanced, and the reliability of the two solder blocks can be improved.

[0053] At the same time, a composite layer 530 containing tungsten metal is disposed between the two Ni layers. The tungsten metal effectively increases the hardness of the solder block, enhancing its ability to withstand stress and preventing deformation, allowing the solder block to be well-matched and integrated with the concave-convex structure 43 on the sidewall of the through-hole. Furthermore, alloy layers comprising tungsten and Ni are disposed on both sides of the W layer 532 in the composite layer 530. This ensures the strength of the composite layer 530 while also improving the adhesion between the tungsten metal in the composite layer 530 and the first and second Ni layers 520 and 540, thereby enhancing the overall stability of the solder block.

[0054] Illustratively, in the first alloy layer 531 , the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%; in the second alloy layer 533 , the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%.

[0055] As an example, in the embodiment of the present disclosure, in the first alloy layer 531 , the mass percentage of W is 20%, and the mass percentage of Ni is 80%; in the second alloy layer 533 , the mass percentage of W is 20%, and the mass percentage of Ni is 80%.

[0056] By setting the W metal and Ni metal in the alloy layer to this ratio, the strength of the alloy layer can be ensured while improving the adhesion between the W metal and the Ni layer in the alloy layer to enhance the overall stability of the solder joint block.

[0057] Illustratively, the thickness of the Ti layer 510 is 800 angstroms to 1200 angstroms, the thickness of the first Ni layer 520 is 800 angstroms to 1200 angstroms, the thickness of the composite layer 530 is 4000 angstroms to 6000 angstroms, the thickness of the second Ni layer 540 is 2500 angstroms to 3500 angstroms, and the thickness of the Sn alloy layer 550 is 80,000 angstroms to 100,000 angstroms.

[0058] In the composite layer 530 , the thickness of the first alloy layer 531 is 800 angstroms to 1200 angstroms, the thickness of the W layer 532 is 2500 angstroms to 3500 angstroms, and the thickness of the second alloy layer 533 is 800 angstroms to 1200 angstroms.

[0059] As an example, the thickness of the Ti layer 510 is 1000 angstroms, the thickness of the first Ni layer 520 is 1000 angstroms, the thickness of the composite layer 530 is 5000 angstroms, the thickness of the second Ni layer 540 is 3000 angstroms, and the thickness of the Sn alloy layer 550 is 90,000 angstroms.

[0060] In the composite layer 530 , the thickness of the first alloy layer 531 is 1000 angstroms, the thickness of the W layer 532 is 3000 angstroms, and the thickness of the second alloy layer 533 is 1000 angstroms.

[0061] Optionally, the thickness of the passivation layer 40 is not less than the sum of the thicknesses of the Ti layer 510, the first Ni layer 520, and the composite layer 530. This ensures that the composite layer 530 is located within the first through-hole 41 and the second through-hole 42, allowing the W metal with high hardness in the solder joint block to be located at the sidewalls of the through-holes and to be bonded to the concave-convex structure 43 on the sidewalls, allowing the sidewalls of the solder joint block to be well combined with the sidewalls of the through-holes to achieve an optimal bonding effect.

[0062] For example, the thickness of the passivation layer 40 may be 8000 angstroms to 12000 angstroms. For example, the thickness of the passivation layer 40 may be 10000 angstroms.

[0063] In the embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer.

[0064] As an example, the first semiconductor layer 21 is an n-type layer, the first electrode 24 is an n-type electrode, the second semiconductor layer 23 is a p-type layer, and the second electrode 25 is a p-type electrode.

[0065] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light emitting diode has good luminous effect and stability.

[0066] Optionally, the first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0067] Optionally, the multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0068] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0069] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0070] Optionally, the second semiconductor layer 23 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0071] Optionally, the distributed Bragg reflector (DBR) layer includes a plurality of periodically alternately stacked SiO2 layers and TiO2 layers, and the number of periods of the DBR layer may be between 20 and 50. For example, the number of periods of the DBR layer is 32.

[0072] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0073] In addition to the passivation function, the DBR layer is also used to reflect the light emitted from the multi-quantum well layer 22 to the passivation layer 40 to the substrate 10, thereby improving the light extraction effect.

[0074] Figure 5 This is a flow chart of a method for preparing an AlGaInP-based red light emitting diode chip provided by an embodiment of the present disclosure. Figure 1 The AlGaInP-based red light emitting diode chip shown. Figure 5 As shown, the preparation method comprises:

[0075] S11: providing a substrate 10.

[0076] S12 : forming a light emitting structure 20 , a distributed Bragg reflector layer 30 and a passivation layer 40 in sequence on the substrate 10 .

[0077] The passivation layer 40 has a first through hole 41 and a second through hole 42 exposing the distributed Bragg reflector layer 30 .

[0078] S13 : manufacturing a first soldering point block 51 in the first through hole 41 , and manufacturing a second soldering point block 52 in the second through hole 42 .

[0079] Among them, the first solder point block 51 is located on the surface of the distributed Bragg reflector layer 30, the second solder point block 52 is located on the surface of the distributed Bragg reflector layer 30, and the side walls of the first through hole 41 and the second through hole 42 are both provided with a concave-convex structure 43. The side wall of the first solder point block 51 located in the first through hole 41 extends to the groove of the concave-convex structure 43 of the first through hole 41, and the side wall of the second solder point block 52 located in the second through hole 42 extends to the groove of the concave-convex structure 43 of the second through hole 42.

[0080] The AlGaInP-based red light-emitting diode chip prepared by this method includes a substrate 10, a light-emitting structure 20, a distributed Bragg reflector layer 30, and a passivation layer 40, which are stacked in sequence. The passivation layer 40 has a first through-hole 41 and a second through-hole 42 that expose the distributed Bragg reflector layer 30. The sidewalls of the first through-hole 41 and the second through-hole 42 are both provided with a concave-convex structure 43. The first solder block 51 is arranged in the first through hole 41, and the side wall of the first solder block 51 also matches the concave-convex structure 43 on the side wall of the first through hole 41, so that when the first solder block 51 is in the first through hole 41, the side wall of the first solder block 51 can be well combined with the concave-convex structure 43 on the side wall of the first through hole 41, thereby improving the connection stability between the first solder block 51 and the first through hole 41 and avoiding relative looseness between the first solder block 51 and the first through hole 41; the second solder block 52 is arranged in the second through hole 42, and similarly, the side wall of the second solder block 52 can be well combined with the concave-convex structure 43 on the side wall of the second through hole 42 to improve the connection stability between the second solder block 52 and the second through hole 42 and avoid relative looseness between the first solder block 51 and the first through hole 41; this can also allow the light-emitting structure 20 located below the two solder blocks to be better fixed in the chip, thereby improving the reliability of the chip.

[0081] Optionally, the substrate 10 is a sapphire substrate 10. The sapphire substrate 10 has a relatively high light transmittance, that is, the substrate 10 is a transparent substrate 10. In addition, the sapphire material is relatively hard and has relatively stable chemical properties, so that the red light emitting diode has good luminous effect and stability.

[0082] In step S11, the sapphire substrate 10 may be pre-treated by placing the sapphire substrate 10 in a MOCVD (Metal-organic Chemical Vapor Deposition) reaction chamber and baking the sapphire substrate 10 for 12 to 18 minutes. For example, in the embodiment of the present disclosure, the sapphire substrate 10 is baked for 15 minutes.

[0083] Specifically, the baking temperature may be 1000° C. to 1200° C., and the pressure in the MOCVD reaction chamber during baking may be 100 mbar to 200 mbar.

[0084] The light emitting structure 20 grown in step S12 includes a first semiconductor layer 21 , a multi-quantum well layer 22 , and a second semiconductor layer 23 sequentially stacked on the substrate 10 .

[0085] That is, in step S13 , only the epitaxial layer including the first semiconductor layer 21 , the multi-quantum well layer 22 and the second semiconductor layer 23 in the light emitting structure 20 is grown.

[0086] like Figure 6 As shown, the process of growing the epitaxial layer may include: first, growing the second semiconductor layer 23 on the GaAs substrate 11 .

[0087] For example, the second semiconductor layer 23 is an indium-doped p-type AlInP layer, and the thickness of the p-type AlInP layer may be 0.5 μm to 3 μm.

[0088] like Figure 6 As shown, after the second semiconductor layer 23 is grown, the multi-quantum well layer 22 is grown on the second semiconductor layer 23 .

[0089] The multi-quantum well layer 22 includes alternately grown AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and the AlGaInP quantum barrier layers is different. The multi-quantum well layer 22 may include 3 to 8 periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0090] As an example, in the embodiment of the present disclosure, the multi-quantum well layer 22 includes five periods of alternately stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0091] Optionally, the thickness of the multi-quantum well layer 22 may be 150 nm to 200 nm.

[0092] like Figure 6 As shown, after the multi-quantum well layer 22 is grown, the first semiconductor layer 21 is grown on the multi-quantum well layer 22 .

[0093] The first semiconductor layer 21 is an n-type AlGaInP layer, and the thickness of the n-type AlGaInP layer may be 0.5 μm to 3 μm.

[0094] In step S12 , a GaAs layer and an etching stop layer may be grown before growing the second semiconductor layer 23 , and an AlInP carrier confinement layer may be grown before growing the multi-quantum well layer 22 .

[0095] After growing the first semiconductor layer 21 , a GaP window layer may be further grown, wherein the thickness of the GaP window layer is 2 μm to 5 μm.

[0096] Exemplarily, the thickness of the GaP window layer is 3 μm.

[0097] After step S12, the process further includes bonding the substrate 10 and the light-emitting structure 20. Specifically, this process may include coating the surface of the first semiconductor layer 21 of the light-emitting structure 20 with liquid silicon oxide; and curing the liquid silicon oxide at a curing temperature of 250°C to 350°C to form a bonding layer. After bonding the light-emitting structure 20 to the substrate 10, the GaAs substrate 11 is removed.

[0098] Illustratively, the bonding temperature may be 300°C.

[0099] In the embodiment of the present disclosure, the substrate 10 and the light emitting structure 20 are bonded to form a complete light emitting structure 20 .

[0100] First, the connection groove 28 of the first semiconductor layer 21 is exposed by etching the surface of the second semiconductor layer 23 .

[0101] like Figure 7 As shown, the method may specifically include: removing a portion of the second semiconductor layer by dry etching until the first semiconductor layer 21 is exposed. The etching depth is 1 μm to 2 μm, for example, 1.5 μm.

[0102] After etching the connection groove 28 , a first electrode 24 may be formed on the first semiconductor layer 21 , and a second electrode 25 may be formed on the second semiconductor layer 23 .

[0103] The forming of the first electrode 24 and the second electrode 25 may include: processing the first electrode 24 and the second electrode 25 separately by using a negative resist stripping method.

[0104] like Figure 7 As shown, the second electrode 25 is located on the surface of the second semiconductor layer 23 , and the first electrode 24 is located on the bottom surface of the connection groove 28 .

[0105] The first electrode 24 is mainly composed of gold-beryllium, and the second electrode 25 is evaporated with gold-germanium as the base material. When evaporating the gold-germanium alloy, the evaporation power must be guaranteed and the evaporation time must not exceed 5 seconds to prevent the deviation of the alloy composition, and annealing is performed.

[0106] Then, a distributed Bragg reflector layer 30 is fabricated. The distributed Bragg reflector layer 30 may be a DBR layer, which includes a plurality of periodically alternating SiO2 layers and TiO2 layers. The number of periods in the DBR layer may be between 20 and 50. For example, the number of periods in the DBR layer is 32.

[0107] The thickness of the SiO2 layer in the DBR layer may be 800 angstroms to 1200 angstroms, and the thickness of the TiO2 layer may be 500 angstroms to 900 angstroms.

[0108] After forming the distributed Bragg reflector layer 30, as shown in FIG. Figure 7 As shown, the preparation method may further include: forming a first via hole 26 and a second via hole 27 on the surface of the distributed Bragg reflector layer 30 away from the substrate 10 , wherein the first via hole 26 extends to the surface of the first semiconductor layer 21 , and the second via hole 27 extends to the surface of the second semiconductor layer 23 .

[0109] Then, a passivation layer 40 is formed on the surface of the distributed Bragg reflector layer 30. The passivation layer 40 has a first through hole 41 and a second through hole 42 exposing the distributed Bragg reflector layer 30. The first through hole 41 is connected to the first via hole 26, and the second through hole 42 is connected to the second via hole 27.

[0110] Exemplarily, forming the passivation layer 40 on the distributed Bragg reflector layer 30 includes:

[0111] A passivation layer 40 is deposited on the surface of the distributed Bragg reflector layer 30. During the deposition process, the deposition temperature is controlled to alternate between a first temperature and a second temperature, where the first temperature is greater than the second temperature. The alternation between the first temperature and the second temperature is completed once each time the passivation layer 40 of a set thickness is deposited.

[0112] The first temperature is 280° C. to 320° C., the second temperature is 180° C. to 220° C., and the thickness is set to 500 angstroms to 1500 angstroms.

[0113] As an example, the first temperature is 300° C., the second temperature is 200° C., and the set thickness is 1000 angstroms.

[0114] By controlling the deposition temperature in such a high-low temperature alternating manner, the passivation layer 40 can be formed more stably and reliably.

[0115] Then, a first through hole 41 and a second through hole 42 are formed on the passivation layer 40 by mainly chemical etching. Figure 1 As shown, the sidewall of the first through hole 41 is serrated, and the sidewall of the second through hole 42 is serrated.

[0116] In step S13, a first solder block 51 is formed on the surface of the distributed Bragg reflector layer 30 by photolithography, so that the first solder block 51 is located in the first through hole 41 and is connected to the first electrode 24 through the first via 26; then, a second solder block 52 is formed on the surface of the distributed Bragg reflector layer 30 by photolithography, so that the second solder block 52 is located in the second through hole 42 and is connected to the second electrode 25 through the second via 27.

[0117] The first solder block 51 and the second solder block 52 each include a Ti layer 510, a first Ni layer 520, a composite layer 530, a second Ni layer 540, and a Sn alloy layer 550 stacked in sequence. The composite layer 530 includes a first alloy layer 531, a W layer 532, and a second alloy layer 533 stacked in sequence. The first alloy layer 531 and the second alloy layer 533 both include W and Ni.

[0118] Illustratively, in the first alloy layer 531 , the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%; in the second alloy layer 533 , the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%.

[0119] As an example, in the embodiment of the present disclosure, in the first alloy layer 531 , the mass percentage of W is 20%, and the mass percentage of Ni is 80%; in the second alloy layer 533 , the mass percentage of W is 20%, and the mass percentage of Ni is 80%.

[0120] Illustratively, the thickness of the Ti layer 510 is 800 angstroms to 1200 angstroms, the thickness of the first Ni layer 520 is 800 angstroms to 1200 angstroms, the thickness of the composite layer 530 is 4000 angstroms to 6000 angstroms, the thickness of the second Ni layer 540 is 2500 angstroms to 3500 angstroms, and the thickness of the Sn alloy layer 550 is 80,000 angstroms to 100,000 angstroms.

[0121] In the composite layer 530 , the thickness of the first alloy layer 531 is 800 angstroms to 1200 angstroms, the thickness of the W layer 532 is 2500 angstroms to 3500 angstroms, and the thickness of the second alloy layer 533 is 800 angstroms to 1200 angstroms.

[0122] As an example, the thickness of the Ti layer 510 is 1000 angstroms, the thickness of the first Ni layer 520 is 1000 angstroms, the thickness of the composite layer 530 is 5000 angstroms, the thickness of the second Ni layer 540 is 3000 angstroms, and the thickness of the Sn alloy layer 550 is 90,000 angstroms.

[0123] In the composite layer 530 , the thickness of the first alloy layer 531 is 1000 angstroms, the thickness of the W layer 532 is 3000 angstroms, and the thickness of the second alloy layer 533 is 1000 angstroms.

[0124] When forming the solder joint block, a large-angle plating pot is used for processing, which is conducive to better entry of the metal material into the jagged side wall of the through hole.

[0125] For example, in the embodiment of the present disclosure, the passivation layer 40 may be a silicon oxide layer, and the thickness of the silicon oxide layer is 2000 angstroms.

[0126] After forming the passivation layer 40 , the sapphire substrate 10 is thinned to a final thickness of 80 μm.

[0127] Finally, the sapphire can be cut and scratched invisible, which can effectively reduce the loss of brightness. Then, the AlGaInP-based red light emitting diode chip is obtained through testing.

[0128] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. An AlGaInP-based red light emitting diode chip, characterized in that: The AlGaInP-based red light emitting diode chip comprises: a substrate (10), a light emitting structure (20), a distributed Bragg reflector layer (30), a passivation layer (40), a first soldering point block (51) and a second soldering point block (52); The light-emitting structure (20), the distributed Bragg reflector layer (30) and the passivation layer (40) are sequentially stacked on the substrate (10); the passivation layer (40) has a first through hole (41) and a second through hole (42) for exposing the distributed Bragg reflector layer (30); the hole wall of the first through hole (41) and the hole wall of the second through hole (42) have a concave-convex structure (43); and in the same through hole, the concave-convex structures (43) on two adjacent hole walls are disconnected; The first soldering point block (51) is located in the first through hole (41) and is in contact with the hole wall of the first through hole (41); the second soldering point block (52) is located in the second through hole (42) and is in contact with the hole wall of the second through hole (42); The first solder block (51) and the second solder block (52) both comprise a Ti layer (510), a first Ni layer (520), a composite layer (530), a second Ni layer (540), and a Sn alloy layer (550) stacked in sequence; the composite layer (530) comprises a first alloy layer (531), a W layer (532), and a second alloy layer (533) stacked in sequence; the first alloy layer (531) and the second alloy layer (533) both comprise W and Ni; the thickness of the passivation layer (40) is not less than the sum of the thicknesses of the Ti layer (510), the first Ni layer (520), and the composite layer (530); and the thickness of the passivation layer (40) is 8,000 angstroms to 12,000 angstroms; In the first alloy layer (531), the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%; in the second alloy layer (533), the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%; The thickness of the Ti layer (510) is 800 angstroms to 1200 angstroms, the thickness of the first Ni layer (520) is 800 angstroms to 1200 angstroms, the thickness of the composite layer (530) is 4000 angstroms to 6000 angstroms, the thickness of the second Ni layer (540) is 2500 angstroms to 3500 angstroms, and the thickness of the Sn alloy layer (550) is 80,000 angstroms to 100,000 angstroms; in the composite layer (530), the thickness of the first alloy layer (531) is 800 angstroms to 1200 angstroms, the thickness of the W layer (532) is 2500 angstroms to 3500 angstroms, and the thickness of the second alloy layer (533) is 800 angstroms to 1200 angstroms.

2. The AlGaInP-based red light emitting diode chip according to claim 1, characterized in that: The concave-convex structure (43) includes at least one of a sawtooth-shaped protrusion, a strip-shaped ridge, and a strip-shaped groove.

3. The AlGaInP-based red light emitting diode chip according to claim 1 or 2, characterized in that: The light emitting structure (20) comprises: a first semiconductor layer (21), a multi-quantum well layer (22), a second semiconductor layer (23), a first electrode (24) and a second electrode (25). The first semiconductor layer (21), the multi-quantum well layer (22) and the second semiconductor layer (23) are sequentially stacked on a substrate (10); the second electrode (25) is located on the surface of the second semiconductor layer (23); the surface of the second semiconductor layer (23) has a connection groove (28) exposing the first semiconductor layer (21); the first electrode (24) is located on the surface of the first semiconductor layer (21) and on the bottom surface of the connection groove (28); and the distributed Bragg reflector layer (30) at least covers the surfaces of the first semiconductor layer (21), the first electrode (24), the connection groove (28), the second semiconductor layer (23) and the second electrode (25).

4. A method for preparing an AlGaInP-based red light emitting diode chip, characterized in that: The preparation method comprises: providing a substrate; A light-emitting structure, a distributed Bragg reflector layer, and a passivation layer are sequentially formed on the substrate, wherein the passivation layer has a first through hole and a second through hole exposing the distributed Bragg reflector layer, the hole walls of the first through hole and the hole walls of the second through hole have a concave-convex structure, and the concave-convex structures on two adjacent hole walls in the same through hole are disconnected; A first solder block is made in the first through hole, and a second solder block is made in the second through hole, the first solder block is bonded to the hole wall of the first through hole, and the second solder block is bonded to the hole wall of the second through hole; the first solder block and the second solder block each include a Ti layer, a first Ni layer, a composite layer, a second Ni layer and a Sn alloy layer stacked in sequence, the composite layer includes a first alloy layer, a W layer and a second alloy layer stacked in sequence, the first alloy layer and the second alloy layer each include W and Ni, the thickness of the passivation layer is not less than the sum of the thicknesses of the Ti layer, the first Ni layer and the composite layer, the thickness of the passivation layer is 8000 angstroms to 12000 angstroms, and the mass percentage of W in the first alloy layer is 10 % to 30%, and the mass percentage of Ni is 70% to 90%; in the second alloy layer, the mass percentage of W is 10% to 30%, and the mass percentage of Ni is 70% to 90%; the thickness of the Ti layer is 800 angstroms to 1200 angstroms, the thickness of the first Ni layer is 800 angstroms to 1200 angstroms, the thickness of the composite layer is 4000 angstroms to 6000 angstroms, the thickness of the second Ni layer is 2500 angstroms to 3500 angstroms, and the thickness of the Sn alloy layer is 80000 angstroms to 100000 angstroms; in the composite layer, the thickness of the first alloy layer is 800 angstroms to 1200 angstroms, the thickness of the W layer is 2500 angstroms to 3500 angstroms, and the thickness of the second alloy layer is 800 angstroms to 1200 angstroms.

5. The preparation method according to claim 4, characterized in that Forming a passivation layer on the distributed Bragg reflector layer comprises: The passivation layer is deposited on the surface of the distributed Bragg reflector layer. During the deposition process, the deposition temperature is controlled to alternate between a first temperature and a second temperature, the first temperature is greater than the second temperature, and the alternation between the first temperature and the second temperature is completed once each time the passivation layer of a set thickness is deposited.

6. The preparation method according to claim 5, characterized in that The first temperature is 280° C. to 320° C., the second temperature is 180° C. to 220° C., and the set thickness is 500 angstroms to 1500 angstroms.

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