Semiconductor device driving circuit

Abstract

The object of the present application is to provide a semiconductor device driving circuit which stably prevents malfunction accompanying dV / dt application. The semiconductor device driving circuit (HVIC1) has a pulse transfer circuit (7a, 7b) which outputs an on pulse transfer signal (HON), an off pulse transfer signal (HOFF) based on a level shift on pulse signal (HONm), a level shift off pulse signal (HOFFm); a dV / dt detection circuit (9) which detects a dV / dt period based on the signals (HONm, HOFFm); a logic filter circuit (4) which does not change the output (S_H, R_H) when the signals (HON, HOFF) are simultaneously input; and a latch circuit (5) which outputs a signal (Q_H) synchronized with the output of the logic filter circuit (4). The pulse transfer circuit (7a) has an impedance adjustment section (8a, 8b) which lowers the signal level of the signals (HON, HOFF) during the dV / dt period.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device driving circuit. BACKGROUND

[0002] In a semiconductor device driving circuit in which level shifting from a primary side circuit to a secondary side circuit is accompanied, a false signal is sometimes generated due to variation of a secondary side reference potential VS. Hereinafter, the variation of the secondary side reference potential VS is also referred to as dV / dt. In Patent Literature 1, a method of adjusting the impedance of a level shifting circuit at the time of dV / dt in order to suppress generation of a false signal is disclosed.

[0003] Patent Literature 1: International Publication No. 2017 / 159058

[0004] According to the method disclosed in Patent Literature 1, the impedance of the level shifting circuit itself is adjusted at the time of dV / dt. A dV / dt detection circuit receives an output signal of the level shifting circuit, detects the dV / dt period, and outputs it to an impedance adjustment section. Since the dV / dt detection circuit receives feedback resulting from driving by the impedance adjustment section, the dV / dt detection circuit cannot stably detect the dV / dt period, and there is a problem in that the output of the level shifting circuit becomes unstable. SUMMARY

[0005] The present application has been made in order to solve the above problem, and has an object to provide a semiconductor device driving circuit in which false operation at the time of dV / dt is stably prevented.

[0006] The semiconductor device driving circuit of the present application has a pulse generating circuit which outputs an on-pulse signal in synchronization with a rising edge of an input signal and an off-pulse signal in synchronization with a falling edge; an on-side level shift circuit which outputs a level-shifted on-pulse signal in which a reference potential of the on-pulse signal is level-shifted from a primary-side reference potential to a secondary-side reference potential; an off-side level shift circuit which outputs a level-shifted off-pulse signal in which a reference potential of the off-pulse signal is level-shifted from the primary-side reference potential to the secondary-side reference potential; an on-side pulse transfer circuit which outputs an on-pulse transfer signal based on the level-shifted on-pulse signal; an off-side pulse transfer circuit which outputs an off-pulse transfer signal based on the level-shifted off-pulse signal; a dV / dt detection circuit which detects a dV / dt period in which the secondary-side reference potential is varied, based on the level-shifted on-pulse signal and the level-shifted off-pulse signal; a logic filter circuit which is provided at a stage subsequent to the on-side pulse transfer circuit and the off-side pulse transfer circuit and does not cause an output to change when the on-pulse transfer signal and the off-pulse transfer signal are simultaneously input; and a latch circuit which outputs a signal in synchronization with an output of the logic filter circuit. The on-side pulse transfer circuit has an on-side impedance adjustment section which lowers a signal level of the on-pulse transfer signal during the dV / dt period. The off-side pulse transfer circuit has an off-side impedance adjustment section which lowers a signal level of the off-pulse transfer signal during the dV / dt period.

[0007] Effects of the Invention

[0008] The semiconductor device driving circuit of the present application prevents the semiconductor device from being erroneously driven by lowering the signal levels of the on-pulse transfer signal and the off-pulse transfer signal during the dV / dt period. In addition, since the on-pulse transfer signal and the off-pulse transfer signal are not input to the dV / dt detection circuit, the dV / dt period can be stably detected. Therefore, the erroneous operation during the dV / dt period can be stably prevented. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a circuit block diagram showing the structure of a half-bridge circuit of a comparative example.

[0010] Figure 2 is a circuit diagram of a level shift circuit.

[0011] Figure 3 is a circuit block diagram showing the structure of a half-bridge circuit using the semiconductor device driving circuit of Embodiment 1.

[0012] Figure 4 is a circuit diagram of the semiconductor device driving circuit of Embodiment 1.

[0013] Figure 5 FIG. 2 is a diagram showing each signal waveform at the time of dV / dt in the semiconductor device driving circuit of Embodiment 1.

[0014] Figure 6 FIG. 4 is a circuit block diagram showing the structure of a half-bridge circuit using the semiconductor device driving circuit of Embodiment 2.

[0015] Figure 7 FIG. 5 is a circuit diagram of the semiconductor device driving circuit of Embodiment 2.

[0016] Figure 8 FIG. 6 is a diagram showing each signal waveform at the time of dV / dt in the semiconductor device driving circuit of Embodiment 2. DETAILED DESCRIPTION

[0017] [A. Comparative Example]

[0018] Figure 1 FIG. 1 is a circuit block diagram showing the structure of a half-bridge circuit 100 of the comparative example. The half-bridge circuit 100 has a P-side switching element, i.e., an IGBT (Insulated Gate Bipolar Transistor) 18p, an N-side switching element, i.e., an IGBT 18n, and semiconductor device driving circuits HVIC0, LVIC0.

[0019] 18p, an N-side switching element, i.e., an IGBT 18n, and semiconductor device driving circuits HVIC0, LVIC0.

[0020] The semiconductor device driving circuit HVIC0 has a primary-side circuit 11 that operates with reference to a primary-side reference potential GND and a secondary-side circuit 12 that operates with reference to a secondary-side reference potential VS. The semiconductor device driving circuit HVIC0 receives an input signal HIN with reference to the primary-side reference potential GND, outputs a high-potential-side drive signal HO with reference to the secondary-side reference potential VS, and drives the IGBT 18p that operates with reference to the secondary-side reference potential VS. The semiconductor device driving circuit LVIC0 receives an input signal LIN with reference to the primary-side reference potential GND, outputs a low-potential-side drive signal LO that is synchronized with the input signal LIN, and drives the IGBT 18n.

[0021] A power supply 17a is connected between the primary side circuit 11 of the semiconductor device driving circuit HVIC0 and a primary side reference potential GND. That is, the primary side circuit 11 of the semiconductor device driving circuit HVIC0 and the semiconductor device driving circuit LVIC0 are driven by a power supply potential VCC generated by the power supply 17a. A power supply 17b is connected between the secondary side circuit 12 of the semiconductor device driving circuit HVIC0 and a secondary side reference potential VS. That is, the secondary side circuit 12 of the semiconductor device driving circuit HVIC0 is driven by a power supply potential VB generated by the power supply 17b. A power supply 17c is connected between the collector of the IGBT 18p and GND. That is, the collector of the IGBT 18p is applied with a power supply potential VE generated by the power supply 17c.

[0022] The semiconductor device driving circuit HVIC0 is configured to have a pulse generating circuit 1, a level shift circuit 2, inverters 3a, 3b, a logic filter circuit 4, a latch circuit 5, and a driving circuit 6. The primary side of the pulse generating circuit 1 and the level shift circuit 2 constitute the primary side circuit 11, and the secondary side of the level shift circuit 2, the inverters 3a, 3b, the logic filter circuit 4, the latch circuit 5, and the driving circuit 6 constitute the secondary side circuit 12.

[0023] The pulse generating circuit 1 receives an input signal HIN, and outputs an on-pulse signal LON in synchronization with the rising edge of the input signal HIN, and an off-pulse signal LOFF in synchronization with the falling edge.

[0024] The level shift circuit 2 has an on-side level shift circuit, i.e., a level shift circuit 2a, and an off-side level shift circuit, i.e., a level shift circuit 2b.

[0025] The level shift circuit 2a outputs a level-shifted on-pulse signal HONm by inverting the on-pulse signal LON and performing level shifting of the reference potential from the primary side reference potential GND to the secondary side reference potential VS.

[0026] The level shift circuit 2b outputs a level-shifted off-pulse signal HOFFm by inverting the off-pulse signal LOFF and performing level shifting of the reference potential from the primary side reference potential GND to the secondary side reference potential VS.

[0027] The inverter 3a outputs an on-pulse transfer signal HON by inverting the level-shifted on-pulse signal HONm by receiving the level-shifted on-pulse signal HONm.

[0028] The inverter 3b outputs an off-pulse transfer signal HOFF by inverting the level-shifted off-pulse signal HOFFm by receiving the level-shifted off-pulse signal HOFFm.

[0029] The logic filter circuit 4 is a circuit that does not receive any input and does not change the output when the on-pulse transmission signal HON and the off-pulse transmission signal HOFF are simultaneously input, that is, when the signal levels of the on-pulse transmission signal HON and the off-pulse transmission signal HOFF are HIGH. The logic filter circuit 4 outputs S_H when only the on-pulse transmission signal HON is input, and outputs R_H when only the off-pulse transmission signal HOFF is input. That is, one output S_H of the logic filter circuit 4 becomes HIGH when the on-pulse transmission signal HON is HIGH and the off-pulse transmission signal HOFF is LOW, and the other output R_H becomes HIGH when the on-pulse transmission signal HON is LOW and the off-pulse transmission signal HOFF is HIGH.

[0030] The latch circuit 5 receives S_H and R_H and outputs a signal Q_H that rises in synchronization with the rising edge of S_H and falls in synchronization with the rising edge of R_H.

[0031] The drive circuit 6 outputs a high-potential side drive signal HO that rises in synchronization with the rising edge of Q_H and falls in synchronization with the falling edge of Q_H.

[0032] Next, a false operation caused by a change (dV / dt) in VS will be described.

[0033] Figure 2 is a circuit diagram of the level shift circuit 2. As shown in Figure 2 The level shift circuit 2 is configured to have high-voltage NMOSs 21a, 21b, resistors 22a, 22b, and diodes 23a, 23b.

[0034] The sources of the high-voltage NMOSs 21a, 21b are connected to the primary-side reference potential GND. The resistor 22a is connected between the drain of the high-voltage NMOS 21a and the power supply potential VB, and the diode 23a is connected between the drain of the high-voltage NMOS 21a and the secondary-side reference potential VS in such a manner that the cathode faces the drain. The resistor 22b is connected between the drain of the high-voltage NMOS 21b and the power supply potential VB, and the diode 23b is connected between the drain of the high-voltage NMOS 21b and the secondary-side reference potential VS in such a manner that the cathode faces the drain. The drain voltage of the high-voltage NMOS 21a is a level-shift on-pulse signal HONm, and the drain voltage of the high-voltage NMOS 21b is a level-shift off-pulse signal HOFFm. The on-pulse signal LON is input to the gate of the high-voltage NMOS 21a, and the off-pulse signal LOFF is input to the gate of the high-voltage NMOS 21b.

[0035] The diode 23a functions to prevent the potential of the level-shifted-on pulse signal HONm from becoming less than or equal to the secondary-side reference potential VS, and the diode 23b functions to prevent the potential of the level-shifted-off pulse signal HOFFm from becoming less than or equal to the secondary-side reference potential VS.

[0036] When the signal levels of the on pulse signal LON and the off pulse signal LOFF are high, both the high-voltage NMOS 21a and the high-voltage NMOS 21b are turned on, and the signal levels of the level-shifted-on pulse signal HONm and the level-shifted-off pulse signal HOFFm are changed from high to low.

[0037] When the secondary-side reference potential VS generates a variation of dV / dt, the power source potential VB, which is higher than the secondary-side reference potential VS by the amount of the power source voltage of the power source 17b, also generates a variation following VS. Also, since each of the high-voltage NMOS 21a and the high-voltage NMOS 21b has a parasitic capacitance 24a and a parasitic capacitance 24b, respectively, a displacement current caused by the parasitic capacitances 24a and 24b flows through the resistors 22a and 22b. Therefore, during the dV / dt period, when the on pulse signal LON and the off pulse signal LOFF are not input, that is, when the signal levels of the on pulse signal LON and the off pulse signal LOFF are low, the signal levels of the level-shifted-on pulse signal HONm and the level-shifted-off pulse signal HOFFm also become low.

[0038] According to manufacturing fluctuations or charged states of the parasitic capacitances 24a, 24b, the signal levels of the level-shifted turn-on pulse signal HONm and the level-shifted turn-off pulse signal HOFFm differ slightly in the time from low to high caused by dV / dt. Therefore, sometimes the low caused by dV / dt of the level-shifted turn-on pulse signal HONm or the level-shifted turn-off pulse signal HOFFm cannot be removed by the logic filter circuit 4 of the subsequent stage. For example, when dV / dt occurs while the high-potential-side drive signal HO is low, in a case where the signal level of the level-shifted turn-on pulse signal HONm recovers from low to high later than the signal level of the level-shifted turn-off pulse signal HOFFm after the signal levels of the level-shifted turn-on pulse signal HONm and the level-shifted turn-off pulse signal HOFFm become low, the logic filter circuit 4 cannot remove the high turn-on pulse transfer signal HON caused by the low level-shifted turn-on pulse signal HONm, and outputs S_H at a high level. As a result, the high-potential-side drive signal HO becomes high, and the IGBT 18p can be erroneously turned on. Similarly, when dV / dt occurs while the high-potential-side drive signal HO is high, in a case where the signal level of the level-shifted turn-off pulse signal HOFFm recovers from low to high later than the signal level of the level-shifted turn-on pulse signal HONm after the signal levels of the level-shifted turn-on pulse signal HONm and the level-shifted turn-off pulse signal HOFFm become low, the logic filter circuit 4 cannot remove the high turn-on pulse transfer signal HOFF caused by the low level-shifted turn-off pulse signal HOFFm, and outputs R_H at a high level. As a result, the high-potential-side drive signal HO becomes low, and the IGBT 18p can be erroneously turned off.

[0039] For the purpose of suppressing such erroneous operation, for example, in International Publication No. 2012 / 043750 or International Publication No. 2017 / 159058, a method of changing the impedance of a level shift circuit at dV / dt is disclosed. For example, the semiconductor device driving circuit disclosed in International Publication No. 2012 / 043750 detects a dV / dt period by a dV / dt detection circuit, and reduces the signal level of the output of the level shift circuit by reducing the impedance of the level shift circuit on the turn-on side and the turn-off side during the dV / dt period.

[0040] However, in the semiconductor device driving circuit disclosed in International Publication No. 2012 / 043750, since the output of the level shift circuit is received by the dV / dt detection circuit, the dV / dt detection circuit does not output the dV / dt detection signal after the signal level of the level shift circuit is lowered. Then, the impedance of the level shift circuit returns to the original state, and thus the level shift circuit outputs the signal again, and the dV / dt detection circuit outputs the dV / dt detection signal again. Thus, there is a problem that the dV / dt detection circuit cannot stably detect the dV / dt period, and the output of the level shift circuit becomes unstable. An object of the present application is to prevent the oscillation operation of the level shift circuit.

[0041] <B. Embodiment 1>

[0042] <B-1. Configuration>

[0043] Figure 3 is a circuit block diagram showing the configuration of the half-bridge circuit 101 using the semiconductor device driving circuit HVIC1 of Embodiment 1. The half-bridge circuit 101 is a configuration in which the semiconductor device driving circuit HVIC0 of the comparative example is replaced with the semiconductor device driving circuit HVIC1. The semiconductor device driving circuit HVIC1 is different from the semiconductor device driving circuit HVIC0 of the comparative example in that the semiconductor device driving circuit HVIC1 has the pulse transmission circuits 7a, 7b and the dV / dt detection circuit 9 instead of the inverters 3a, 3b.

[0044] The pulse transmission circuit 7a is provided on the turn-on side, and receives the output signal of the level shift circuit 2a, that is, the level shift turn-on pulse signal HONm. Further, the pulse transmission circuit 7a outputs, as the turn-on pulse transmission signal HON, a signal in which the level shift turn-on pulse signal HONm is inverted, in a case where the secondary-side reference potential Vs does not change. The pulse transmission circuit 7a has the impedance adjustment section 8a. The pulse transmission circuit 7a is also referred to as a turn-on side pulse transmission circuit, and the impedance adjustment section 8a is also referred to as a turn-on side impedance adjustment section.

[0045] The pulse transmission circuit 7b is provided on the turn-off side, and receives the output signal of the level shift circuit 2a, that is, the level shift turn-off pulse signal HOFFm. Further, the pulse transmission circuit 7b outputs, as the turn-off pulse transmission signal HOFF, a signal in which the level shift turn-off pulse signal HOFFm is inverted, in a case where the secondary-side reference potential Vs does not change. The pulse transmission circuit 7b has the impedance adjustment section 8b. The pulse transmission circuit 7b is also referred to as a turn-off side pulse transmission circuit, and the impedance adjustment section 8b is also referred to as a turn-off side impedance adjustment section.

[0046] The dV / dt detection circuit 9 receives the level-shifted turn-on pulse signal HONm and the level-shifted turn-off pulse signal HOFFm. The dV / dt detection circuit 9 detects a dV / dt period in which the masking signal MASK is output to the impedance adjustment sections 8a, 8b, based on the level-shifted turn-on pulse signal HONm and the level-shifted turn-off pulse signal HOFFm. That is, the signal level of the masking signal MASK becomes high in the dV / dt period and becomes low in a period other than this. If the masking signal MASK of high level is received, the impedance adjustment sections 8a, 8b lower the impedance of the pulse transmission circuit 7a, 7b, and suppress the output of the pulse transmission circuit 7a, 7b, that is, the turn-on pulse transmission signal HON and the turn-off pulse transmission signal HOFF, that is, set the signal levels thereof to low.

[0047] Thus, the semiconductor device driving circuit HVIC 1 does not change the impedance of the pulse transmission circuit 7a, 7b but changes the impedance of the pulse transmission circuit 7a, 7b during dV / dt, thereby suppressing the false output of the IGBT 18p caused by dV / dt. Since the output signal of the pulse transmission circuit 7a, 7b, that is, the turn-on pulse transmission signal HON and the turn-off pulse transmission signal HOFF is not input to the dV / dt detection circuit 9, the dV / dt detection circuit 9 stably outputs even if the impedance of the pulse transmission circuit 7a, 7b is changed. Therefore, the generation of the false signal caused by dV / dt is stably suppressed.

[0048] <B-2. Detailed structure>

[0049] Figure 4 is a circuit diagram of the semiconductor device driving circuit HVIC 1. Figure 5 shows the waveforms of each signal during dV / dt in the semiconductor device driving circuit HVIC 1.

[0050] The pulse transmission circuit 7a is configured to have a PMOS 71a, a resistor 72a, an NMOS 81a, and a buffer 74a. Among these, the NMOS 81a corresponds to the impedance adjustment section 8a. The level-shifted turn-on pulse signal HONm is input to the gate of the PMOS 71a. The source of the PMOS 71a is connected to the power supply potential VB, and the resistor 72a, the NMOS 81a, and the buffer 74a are connected to the drain. One end of the resistor 72a is connected to the drain of the PMOS 71a, and the other end is connected to the secondary-side reference potential VS. The drain of the NMOS 81a is connected to the drain of the PMOS 71a, and the source of the NMOS 81a is connected to the secondary-side reference potential VS. One end of the buffer 74a is connected to the drain of the PMOS 71a, and the other end is connected to the input of the logic filter circuit 4.

[0051] The pulse transmission circuit 7b is configured with a PMOS 71b, a resistor 72b, an NMOS 81b, and a buffer 74b. Among them, the NMOS 81b corresponds to the impedance adjustment section 8b. The level shift-off pulse signal HOFFm is input to the gate of the PMOS 71b. The source of the PMOS 71b is connected to the power supply potential VB, and the resistor 72b, the NMOS 81b, and the buffer 74b are connected to the drain. One end of the resistor 72b is connected to the drain of the PMOS 71b, and the other end is connected to the secondary-side reference potential VS. The drain of the NMOS 81b is connected to the drain of the PMOS 71b, and the source of the NMOS 81b is connected to the secondary-side reference potential VS. One end of the buffer 74b is connected to the drain of the PMOS 71b, and the other end is connected to the input of the logic filter circuit 4.

[0052] The dV / dt detection circuit 9 is configured with PMOSs 91, 92, resistors 93, 94, buffers 95, 96, and an AND gate 97.

[0053] The source of the PMOS 91 is connected to the power supply potential VB, and the gate is input with the level shift-on pulse signal HONm. The resistor 93 and the buffer 95 are connected to the drain of the PMOS 91. One end of the resistor 93 is connected to the drain of the PMOS 91, and the other end is connected to the secondary-side reference potential VS. One end of the buffer 95 is connected to the drain of the PMOS 91, and the other end is connected to one input of the AND gate 97.

[0054] The source of the PMOS 92 is connected to the power supply potential VB, and the gate is input with the level shift-off pulse signal HOFFm. The resistor 94 and the buffer 96 are connected to the drain of the PMOS 92. One end of the resistor 94 is connected to the drain of the PMOS 92, and the other end is connected to the secondary-side reference potential VS. One end of the buffer 96 is connected to the drain of the PMOS 92, and the other end is connected to the other input of the AND gate 97.

[0055] The output of the AND gate 97 is the MASK signal, which is input to the gate of the NMOS 81a, 81b corresponding to the impedance adjustment sections 8a, 8b.

[0056] First, the operation in the case where the reference potential VS on the secondary side is not changed will be described. Since the outputs LON, LOFF of the pulse generating circuit 1 do not become high at the same time, the signal level of the level shift-on pulse signal HONm of the level shift circuit 2a and the signal level of the level shift-off pulse signal HOFFm of the level shift circuit 2b do not both become low, but either one or both become high. In the case where the signal level of the level shift-on pulse signal HONm of the level shift circuit 2a is low and the signal level of the level shift-off pulse signal HOFFm of the level shift circuit 2b is high, the following operation is performed.

[0057] If the signal level of the level shift-on pulse signal HONm of the level shift circuit 2a becomes low, the PMOS 71a is turned on and a current flows through the resistor 72a. As a result, the signal HONn obtained by inverting the level shift-on pulse signal HONm is input to the buffer 74a. The buffer 74a outputs the on pulse transmission signal HON to the logic filter circuit 4 by shaping the signal HONn.

[0058] The output of the level shift circuit 2a, i.e., the level shift-on pulse signal HONm, is also input to the PMOS 91. If the signal level of the level shift-on pulse signal HONm becomes low, the PMOS 91 is turned on and a current flows through the resistor 93. As a result, an inverted signal of the level shift-on pulse signal HONm is input to the buffer 95. As a result, a high-level signal is input to one input terminal of the AND gate 97 from the buffer 95.

[0059] On the other hand, since the signal level of the level shift-off pulse signal HOFFm is high, the PMOS 92 is not turned on, and a low-level signal is input to the other input terminal of the AND gate 97 from the buffer 96. Therefore, the signal level of the output of the AND gate 97, i.e., the masking signal MASK, becomes low.

[0060] In the case where the signal level of the level shift-on pulse signal HONm of the level shift circuit 2a is high and the signal level of the level shift-off pulse signal HOFFm of the level shift circuit 2b is low, the output level of the buffer 95 is low and the output level of the buffer 96 is high, contrary to the above. In this case, the signal level of the output of the AND gate 97, i.e., the masking signal MASK, also becomes low.

[0061] Next, the operation at dV / dt is described. At dV / dt, the signal levels of the level shift on pulse signal HONm and the level shift off pulse signal HOFFm are simultaneously changed to low. In this case, the pMOS 71a, 71b, 91, 92 are simultaneously turned on, and a current flows through the resistors 72a, 72b, 93, 94. As a result, the output levels of the buffers 74a, 74b, 95, 96 are changed to high. Since the output levels of the buffers 95, 96 are changed to high, the output of the AND gate 97, that is, the signal level of the mask signal MASK is changed to high. Also, the NMOS 81a, 81b are turned on by the mask signal MASK being input to the gates, and the signal levels of HONn, HOFFn are lowered. When the signal levels of HONn, HOFFn are each lower than the threshold values Vtha, Vthb of the buffers 74a, 74b, the output of the buffers 74a, 74b, that is, the signal levels of the on pulse transfer signal HON and the off pulse transfer signal HOFF are changed to low. Here, since the signal level of the mask signal MASK is not affected by the turning on of the NMOS 81a, 81b, it is stably changed to high during dV / dt.

[0062] By the above operation, according to the semiconductor device driving circuit HVIC1, the level shift on pulse signal HONm and the level shift off pulse signal HOFFm can be stably output, and the generation of false signals caused by dV / dt is suppressed.

[0063] <B-3. Modification>

[0064] In addition to the on pulse transfer signal HON and the off pulse transfer signal HOFF, the logic filter circuit 4 can also receive the mask signal MASK. Also, the logic filter circuit 4 can be structured such that, in addition to the case where the signal levels of the on pulse transfer signal HON and the off pulse transfer signal HOFF are simultaneously high, the input of the on pulse transfer signal HON and the off pulse transfer signal HOFF is not received in the case where the signal level of the mask signal MASK is high.

[0065] In Figure 1 and Figure 3 , the driving target switching element of the semiconductor device driving circuit HVIC0 is set to an IGBT, but can also be a SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In the case where the switching element uses a SiC-MOS, since the variation of VS becomes sharp, the VS potential itself oscillates (damped oscillation), and thus the structure of the present application is particularly effective.

[0066] <B-4. Effects>

[0067] The semiconductor device driving circuit HVIC1 of Embodiment 1 has a pulse generating circuit 1 that outputs an ON pulse signal LON in synchronization with a rising edge of an input signal HIN and an OFF pulse signal LOFF in synchronization with a falling edge, a level shift circuit 2a that outputs a level-shifted ON pulse signal HONm in which a reference potential of the ON pulse signal LON is level-shifted from a primary-side reference potential GND to a secondary-side reference potential VS, a level shift circuit 2b that outputs a level-shifted OFF pulse signal HOFFm in which a reference potential of the OFF pulse signal LOFF is level-shifted from the primary-side reference potential GND to the secondary-side reference potential VS, a pulse transfer circuit 7a that outputs an ON pulse transfer signal HON based on the level-shifted ON pulse signal HONm, a pulse transfer circuit 7b that outputs an OFF pulse transfer signal HOFF based on the level-shifted OFF pulse signal HOFFm, a dV / dt detection circuit 9 that detects a dV / dt period in which the secondary-side reference potential VS is varied, based on the level-shifted ON pulse signal HONm and the level-shifted OFF pulse signal HOFFm, a logic filter circuit 4 that is provided at a stage subsequent to the pulse transfer circuit 7a and the pulse transfer circuit 7b and does not cause an output S_H, R_H to change when the ON pulse transfer signal HON and the OFF pulse transfer signal HOFF are simultaneously input, and a latch circuit 5 that outputs a signal Q_H in synchronization with an output of the logic filter circuit. The pulse transfer circuit 7a has an impedance adjustment section 8a that lowers a signal level of the ON pulse transfer signal HON during the dV / dt period, and the pulse transfer circuit 7b has an impedance adjustment section 8b that lowers a signal level of the OFF pulse transfer signal HOFF during the dV / dt period.

[0068] With the above structure, the semiconductor device driving circuit HVIC1 lowers the signal levels of the ON pulse transfer signal HON and the OFF pulse transfer signal HOFF during the dV / dt period, whereby the erroneous output of the switching element can be suppressed. In addition, since the ON pulse transfer signal HON and the OFF pulse transfer signal HOFF are not input to the dV / dt detection circuit 9, the dV / dt period can be stably detected. Therefore, the semiconductor device driving circuit HVIC1 can stably suppress the erroneous output of the switching element.

[0069] <C. Embodiment 2>

[0070] <C-1. Structure>

[0071] Figure 6is a circuit block diagram showing the structure of the half-bridge circuit 102 for which the semiconductor device driving circuit HVIC2 of Embodiment 2 is used. The half-bridge circuit 102 differs from the half-bridge circuit 101 of Embodiment 1 in that the semiconductor device driving circuit HVIC2 is used instead of the semiconductor device driving circuit HVICl.

[0072] The semiconductor device driving circuit HVIC2 has the pulse transfer circuit 7c instead of the pulse transfer circuit 7a and the pulse transfer circuit 7d instead of the pulse transfer circuit 7b, as compared with the semiconductor device driving circuit HVICl of Embodiment 1. The pulse transfer circuit 7c is also called the turn-on side pulse transfer circuit, and the pulse transfer circuit 7d is also called the turn-off side pulse transfer circuit. The pulse transfer circuit 7c has the impedance adjustment section 8c, and the pulse transfer circuit 7d has the impedance adjustment section 8d. The impedance adjustment section 8c receives the output Q_H of the latch circuit 5 via the NOT gate 10. The impedance adjustment section 8d receives the output Q_H of the latch circuit 5. In other respects, the semiconductor device driving circuit HVIC2 is the same as the semiconductor device driving circuit HVICl.

[0073] In the semiconductor device driving circuit HVIC2, the impedance adjustment sections 8a, 8b receive the mask signal MASK and Q_H, and determine the state of Q_H. Further, only the impedance adjustment sections 8a, 8b on the side capable of changing the state of Q_H drive the outputs of the corresponding pulse transfer circuits 7a, 7b.

[0074] Here, regarding the side capable of changing the state of Q_H, the impedance adjustment section 8b on the turn-off pulse transfer side when Q_H is high, and the impedance adjustment section 8a on the turn-on pulse transfer side when Q_H is low.

[0075] Thus, the generation of the false signal originating from dV / dt can be more reliably suppressed.

[0076] <C-2. Detailed structure>

[0077] Figure 7 is a circuit diagram of the semiconductor device driving circuit HVIC2. Figure 8 shows the waveforms of the respective signals at the time of dV / dt in the semiconductor device driving circuit HVIC2.

[0078] The impedance adjustment section 8c is configured to have the NMOS 81a and the AND gate 82a. The output of the AND gate 97, that is, the mask signal MASK is input to one input terminal of the AND gate 82a, and the output Q_H of the latch circuit 5 is input to the other input terminal via the NOT gate 10. The output terminal of the AND gate 82a is connected to the gate of the NMOS 81a.

[0079] The impedance adjustment section 8d is configured to have an NMOS 81b and an AND gate 82b. The output of the AND gate 97, that is, the masking signal MASK is input to one input terminal of the AND gate 82b, and the output Q H of the latch circuit 5 is input to the other input terminal. The output terminal of the AND gate 82b is connected to the gate of the NMOS 81b.

[0080] When the signal level of the masking signal MASK is high, if Q H is high, the NMOS 81b is turned on, whereby the impedance of the pulse transfer circuit 7d is reduced, and if Q H is low, the NMOS 81a is turned on, whereby the impedance of the pulse transfer circuit 7c is reduced.

[0081] <C-3. Effects>

[0082] In the semiconductor device driving circuit HVIC2 of Embodiment 2, the pulse transfer circuit 7a and the pulse transfer circuit 7b receive the output signal Q H of the latch circuit, the impedance adjustment section 8a reduces the signal level of the turn-on pulse transfer signal HON when in the dV / dt period and the output signal Q H of the latch circuit is low, and the impedance adjustment section 8b reduces the signal level of the turn-off pulse transfer signal HON when in the dV / dt period and the output signal Q H of the latch circuit is high. With the above structure, according to the semiconductor device driving circuit HVIC2, it is possible to more reliably suppress the generation of false signals originating from dV / dt.

[0083] Furthermore, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted.

[0084] Explanation of Reference Numerals

[0085] 1 pulse generation circuit, 2, 2a, 2b level shift circuit, 3a, 3b inverter, 4 logic filter circuit, 5 latch circuit, 6 drive circuit, 7a, 7b, 7c, 7d pulse transfer circuit, 8a, 8b, 8c, 8d impedance adjustment section, 9 dV / dt detection circuit, 10 NOT gate, 11 primary side circuit, 24a, 24b parasitic capacitance, 17a, 17b, 17c power supply, 12 secondary side circuit, 21a, 21b high voltage NMOS, 22a, 22b, 72a, 72b, 93, 94 resistor, 23a, 23b diode, 71a, 71b, 91, 92 PMOS, 74a, 74b, 95, 96 buffer, 81a, 81b NMOS, 82a, 82b, 97 AND gate, 100, 101, 102 half bridge circuit.

Claims

1. A semiconductor device driving circuit, comprising: a pulse generating circuit that outputs an on-pulse signal in synchronization with a rising edge of an input signal and an off-pulse signal in synchronization with a falling edge; an on-side level shift circuit that outputs a level-shifted on-pulse signal in which a reference potential of the on-pulse signal is level-shifted from a primary-side reference potential to a secondary-side reference potential; an off-side level shift circuit that outputs a level-shifted off-pulse signal in which a reference potential of the off-pulse signal is level-shifted from the primary-side reference potential to the secondary-side reference potential; an on-side pulse transfer circuit that outputs an on-pulse transfer signal based on the level-shifted on-pulse signal; an off-side pulse transfer circuit that outputs an off-pulse transfer signal based on the level-shifted off-pulse signal; a dV / dt detection circuit that detects a dV / dt period in which the secondary-side reference potential varies, based on the level-shifted on-pulse signal and the level-shifted off-pulse signal; a logic filter circuit that is provided at a stage subsequent to the on-side pulse transfer circuit and the off-side pulse transfer circuit, and does not cause an output to change when the on-pulse transfer signal and the off-pulse transfer signal are simultaneously input; and a latch circuit that outputs a signal in synchronization with an output of the logic filter circuit, the on-side pulse transfer circuit has an on-side impedance adjustment section that lowers a signal level of the on-pulse transfer signal during the dV / dt period, the off-side pulse transfer circuit has an off-side impedance adjustment section that lowers a signal level of the off-pulse transfer signal during the dV / dt period, the on-side pulse transfer circuit and the off-side pulse transfer circuit receive an output signal of the latch circuit, the on-side impedance adjustment section lowers the signal level of the on-pulse transfer signal when the dV / dt period is in progress and the output signal of the latch circuit is low, and the off-side impedance adjustment section lowers the signal level of the off-pulse transfer signal when the dV / dt period is in progress and the output signal of the latch circuit is high. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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