Multi-stage digital precision time delay control method and system for optical fiber time transfer

Abstract

The application discloses a kind of multistage digital precision time delay control method and system for optical fiber time transfer, the method comprises the following steps: step 1, obtains initial time delay control quantity;Step 2, based on initial time delay control quantity obtains the integer multiple clock period of FPGA phase shift, according to the integer multiple clock period of FPGA phase shift compensation;Step 3, whether update time delay control quantity is in the preset threshold range;If not, then jump to execute step 4, if yes, then jump to execute step 5;Step 4, based on update time delay control quantity obtains the integer multiple clock period of FPGA phase shift, according to the integer multiple clock period of FPGA phase shift compensation, and jump to execute step 3;Step 5, according to update time delay control quantity adopts DPLL and carries out phase shift.The application can realize coarse adjustment and fine adjustment of phase delay by the combination of FPGA technology and DPLL phase shift technology, and can realize multistage digital precision time delay control of large range time delay.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of optical fiber time transfer, and particularly relates to a multi-stage digital precise time delay control method and system for optical fiber time transfer. BACKGROUND

[0002] Optical fiber time transfer has gradually become an important way of high-precision time transfer at home and abroad due to its obvious stability and security advantages such as stable transmission medium, low loss, anti-electromagnetic interference, less environmental interference, and single path. In an optical fiber time transfer system, the transmission time delay between two places is usually obtained by estimation or measurement, and then the transmission time delay is compensated to realize time transfer synchronization.

[0003] The current time delay control technology applied to optical fiber time transfer mainly includes: a phase shifter is used to generate a stable phase difference; this technology may have signal discontinuity and has a very narrow control range, generally 10 ns; a programmable delay line has high resolution, but it is also difficult to achieve large-range time delay control, generally only a few tens of ns or less; an FPGA (field programmable gate array) is used to realize phase movement, and since the resolution of the FPGA phase shift depends on the clock frequency of the FPGA, the resolution is greatly limited; two-stage adjustment is a combination of FPGA coarse adjustment and PLL phase shift fine adjustment for large-range precise time delay control, and this method mainly uses analog circuits for implementation, which has high requirements for the selection, processing and debugging of hardware circuits and cannot view the intermediate state of compensation. SUMMARY

[0004] The present application aims to provide a multi-stage digital precise time delay control method and system for optical fiber time transfer to solve one or more of the above technical problems. The multi-stage digital precise time delay control method provided by the present application can realize coarse and fine adjustment of phase delay and large-range multi-stage digital precise time delay control through the combination of FPGA technology and DPLL phase shift technology.

[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0006] The multi-stage digital precise time delay control method for optical fiber time transfer of the present application comprises the following steps:

[0007] Step 1: obtaining the initial time delay control quantity of the local end and the remote end;

[0008] Step 2: obtaining an integer multiple clock period of FPGA phase shift based on the initial time delay control quantity, compensating according to the integer multiple clock period of FPGA phase shift, and obtaining an updated time delay control quantity after compensation;

[0009] Step 3, determine whether the update delay control amount is within a preset threshold range; if not, jump to step 4; if yes, jump to step 5;

[0010] Step 4: Obtain an integer multiple of the FPGA phase shift clock cycle based on the update delay control amount, perform compensation based on the integer multiple of the FPGA phase shift clock cycle, obtain the compensated update delay control amount, and jump to step 3;

[0011] Step 5: Use DPLL to perform phase shifting according to the updated delay control value to complete multi-level digital precision delay control.

[0012] A further improvement of the method of the present invention is that step 1 specifically comprises:

[0013] The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA is measured by the measurement unit. As the initial delay control amount.

[0014] A further improvement of the method of the present invention is that step 2 specifically comprises:

[0015] Determine the FPGA clock period as T, according to After the formula processes the initial delay control amount, the number of cycles N of full-cycle phase shift is set, and the FPGA outputs a 1PPS signal after delaying N cycles.

[0016] A further improvement of the method of the present invention is that step 3 specifically comprises:

[0017] Determine whether the update delay control amount is between plus or minus 150ns; if not, jump to step 4; if yes, jump to step 5.

[0018] A further improvement of the method of the present invention is that step 5 specifically comprises:

[0019] Step 5.1, configure the maximum threshold ξ of the internal phase accumulator of the numerically controlled oscillator max , minimum threshold value of phase accumulator ξ min And the center value of the frequency control word is ξ m ,ξ m =2 n-1 , n is the number of bits of the phase accumulator inside the digital controlled oscillator; the maximum threshold value of the coarse phase accumulator ξ max , minimum threshold value of phase accumulator ξ min And configure the coarse frequency control word value ξ according to the time interval measurement value between the sending and receiving ends, β is the proportional factor between the phase accumulator and the frequency control word; determines whether the coarse frequency control word value ξ is greater than the maximum threshold ξ max or less than the minimum threshold ξ min; If not, configure the coarse frequency control word value ξ according to the initial value, if so, configure the coarse frequency control word value ξ according to the maximum threshold max Or the minimum threshold ξ min Configure the coarse frequency control word value ξ;

[0020] Step 5.2: Determine the time interval measurement value between the sending and receiving ends Is it within plus or minus 300 ps? If not, jump to step 5.1; if yes, jump to step 5.3.

[0021] Step 5.3: Phase detection is performed between the 10 MHz output of the numerically controlled oscillator and the external input 10 MHz. The frequency control word value is configured to change the minimum step value δ according to the phase detection value. The frequency control word value ξ is precisely changed in the positive or negative direction according to the minimum step value δ, where ξ = ξ ± δ.

[0022] Step 5.4: Determine the time interval measurement value between the sending and receiving ends Is it between plus or minus 30ps? If not, jump to step 5.3. If yes, then the multi-level digital precision delay control is completed.

[0023] The present invention provides a multi-stage digital precision delay control system for optical fiber time transfer, comprising:

[0024] A measurement acquisition module is used to obtain the initial delay control value between the local end and the remote end;

[0025] A compensation module, configured to obtain an integer multiple of the FPGA phase shift clock cycle based on the initial delay control amount, perform compensation according to the integer multiple of the FPGA phase shift clock cycle, and obtain a compensated updated delay control amount;

[0026] A judgment module, configured to judge whether the update delay control amount is within a preset threshold range; if not, jump to execute the steps of the iteration module; if yes, jump to execute the steps of the phase shift module;

[0027] An iterative module is used to obtain an integer multiple of the FPGA phase shift clock cycle based on the update delay control amount, perform compensation according to the integer multiple of the FPGA phase shift clock cycle, obtain the compensated update delay control amount, and jump to the steps of the judgment module;

[0028] The phase shift module is used to perform phase shifting using DPLL according to the updated delay control value to complete multi-level digital precision delay control.

[0029] A further improvement of the system of the present invention is that the steps performed by the measurement acquisition module specifically include:

[0030] The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA is measured by the measurement unit. As the initial delay control amount.

[0031] A further improvement of the system of the present invention is that the steps performed by the compensation module specifically include:

[0032] Determine the FPGA clock period as T, according to After the formula processes the initial delay control amount, the number of cycles N of full-cycle phase shift is set, and the FPGA outputs a 1PPS signal after delaying N cycles.

[0033] A further improvement of the system of the present invention is that the steps performed by the judgment module specifically include:

[0034] Determine whether the update delay control amount is between plus or minus 150ns; if not, jump to the steps of the iteration module; if so, jump to the steps of the phase shift module.

[0035] A further improvement of the system of the present invention is that the steps performed by the phase shift module specifically include:

[0036] Step 5.1, configure the maximum threshold ξ of the internal phase accumulator of the numerically controlled oscillator max , minimum threshold value of phase accumulator ξ min And the center value of the frequency control word is ξ m ,ξ m =2 n-1 , n is the number of bits of the phase accumulator inside the digital controlled oscillator; the maximum threshold value of the coarse phase accumulator ξ max , minimum threshold value of phase accumulator ξ min And configure the coarse frequency control word value ξ according to the time interval measurement value between the sending and receiving ends, β is the proportional factor between the phase accumulator and the frequency control word; determines whether the coarse frequency control word value ξ is greater than the maximum threshold ξ max or less than the minimum threshold ξ min ; If not, configure the coarse frequency control word value ξ according to the initial value, if so, configure the coarse frequency control word value ξ according to the maximum threshold max Or the minimum threshold ξ min Configure the coarse frequency control word value ξ;

[0037] Step 5.2: Determine the time interval measurement value between the sending and receiving ends Is it within plus or minus 300 ps? If not, jump to step 5.1; if yes, jump to step 5.3.

[0038] Step 5.3: Phase detection is performed between the 10 MHz output of the numerically controlled oscillator and the external input 10 MHz. The frequency control word value is configured to change the minimum step value δ according to the phase detection value. The frequency control word value ξ is precisely changed in the positive or negative direction according to the minimum step value δ, where ξ = ξ ± δ.

[0039] Step 5.4: Determine the time interval measurement value between the sending and receiving ends Is it between plus or minus 30ps? If not, jump to step 5.3. If yes, then the multi-level digital precision delay control is completed.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The present invention implements a multi-stage digital precision delay control method for optical fiber time transfer through the application of FPGA and DPLL phase-shifting technology. Relying on high-precision optical fiber time transfer, the present invention provides a method for multi-stage digital precision control of a wide range of delays. This invention can retrieve data to view the current work progress status, improve problem location efficiency in the event of equipment failure, and facilitate standardized, integrated production and intelligent promotion. Specifically, the present invention can implement multi-stage digital precision delay control for optical fiber time transfer, with a delay control accuracy better than 30ps. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art; obviously, the drawings described below are some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0043] Figure 1 This is a flow chart of a multi-stage digital precision delay control method for optical fiber time transfer according to an embodiment of the present invention;

[0044] Figure 2 The figure is a schematic diagram of a multi-stage digital precision delay control system for optical fiber time transfer according to an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] The present invention is described in further detail below with reference to the accompanying drawings:

[0048] A multi-stage digital precision delay control method for optical fiber time transfer according to an embodiment of the present invention includes the following steps:

[0049] Step 1: Obtain the initial delay control value between the local end and the remote end;

[0050] Step 2: obtaining an integer multiple of the FPGA phase shift clock cycle based on the initial delay control amount, performing first-level compensation according to the integer multiple of the FPGA phase shift clock cycle, and obtaining an updated delay control amount after the first-level compensation;

[0051] Step 3, determining whether the update delay control amount is within a preset threshold range; if not, jump to step 4; if so, jump to step 5;

[0052] Step 4: Obtain an integer multiple of the FPGA phase shift clock cycle based on the update delay control amount, perform first-level compensation based on the integer multiple of the FPGA phase shift clock cycle, obtain the updated delay control amount after first-level compensation, and jump to step 3;

[0053] Step 5: Use DPLL to perform phase shifting according to the updated delay control value to complete multi-level digital precision delay control.

[0054] The embodiment of the present invention discloses a multi-level digital precision delay control method for optical fiber time transfer based on FPGA and DPLL phase shifting technology. Relying on high-precision optical fiber time transfer, multi-level digital precision control of a wide range of delay quantities can be performed. The current work progress status can be viewed by retrieving data, and the efficiency of problem location can be improved in the event of equipment failure, which is conducive to standardized and integrated production and intelligent promotion.

[0055] See also Figure 1 A multi-stage digital precision delay control method for optical fiber time transfer according to an embodiment of the present invention includes the following steps:

[0056] 1. The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA is measured by the measurement unit. As a delay control quantity.

[0057] 2. The delay control amount described in step 1 The control unit sends the delay control value that is an integer multiple of the clock period to the FPGA, starts the first level of delay compensation, enters state A and locks.

[0058] 3. After the state A is locked in step 2, the clock cycle of FPGA is determined to be T, and the control chip collects the time interval between the sending and receiving ends, according to After the formula processes the measured data, the number of cycles N of the full-cycle phase shift is set. The FPGA outputs a 1PPS signal after a delay of N cycles and enters state B.

[0059] 4. The main control unit in step 2 determines the time interval measurement value between the sending and receiving ends Is it between plus or minus 150ns? If it does not meet the judgment conditions, it returns to state A. If it meets the judgment conditions, state B is locked.

[0060] 5. The main control unit starts to configure the maximum threshold ξ of the internal phase accumulator of the NCO from step 2 max Sum phase accumulator minimum threshold ξ min , the center value of the frequency control word is ξ m (ξ m =2 n-1 , n is the number of bits of the phase accumulator inside the NCO), the maximum threshold value of the coarse phase accumulator ξ max Sum phase accumulator minimum threshold ξ min And configure the coarse frequency control word value according to the time interval measurement value between the sending and receiving ends β is the proportional factor between the phase accumulator and the frequency control word. The main control unit determines whether the coarse frequency control word value ξ is greater than the maximum threshold ξ. max or less than the minimum threshold ξ min If it is between the two, the NCO configures the coarse frequency control word value ξ according to the initial value. If it is not between the two, the NCO configures the coarse frequency control word value ξ according to the maximum threshold value max Or the minimum threshold ξ min Configure the coarse frequency control word value ξ and enter state C.

[0061] 6. The main control unit in step 2 further determines the time interval measurement value between the sending and receiving ends Is it between plus or minus 300ps? If it does not meet the judgment conditions, it returns to state B. If it meets the judgment conditions, state C is locked;

[0062] 7. At this time, the delay has been controlled within 300ps. The 10MHz output by the NCO and the external input 10MHz need to be phase-detected, and the phase-detected value is fed back to the main control unit described in step 2. The frequency control word value is further configured to change the minimum step value δ. The NCO accurately changes the frequency control word value ξ (ξ=ξ±δ) in the forward or reverse direction according to the change in the minimum step value δ, and enters state D.

[0063] 8. The main control unit in step 2 finally determines the time interval measurement value between the sending and receiving ends Is it between plus or minus 30ps? If so, the system enters the final locking state, namely state D lock. If the judgment condition is not met, it jumps to state C to continue adjusting the delay, and finally controls the delay within 30ps and locks in state D.

[0064] Thus, multi-level digital precision delay control applied to optical fiber time transfer has been realized, with a delay control accuracy better than 30ps.

[0065] The following are device embodiments of the present invention, which can be used to perform the method embodiments of the present invention. For details not disclosed in the device embodiments, please refer to the method embodiments of the present invention.

[0066] See also Figure 2 A multi-stage digital precision delay control system for optical fiber time transfer according to an embodiment of the present invention includes a measurement unit, a main control unit, an FPGA, an NCO (numerically controlled oscillator), a DPD (digital phase and frequency detector), and a DLF (digital loop filter). The NCO, DPD, and DLF form a DPLL phase-shift loop. The system uses an external 1PPS signal transmitted from the local end via an optical fiber link, an external 10 MHz signal, and a 1PPS signal output by the FPGA as input signals. The output signal is a delayed time signal.

[0067] In response to the shortcomings of current technologies, the embodiments of the present invention propose a multi-level digital precision delay control method for optical fiber time transfer based on FPGA coarse adjustment and PLL phase shift fine adjustment, thereby realizing multi-level digital precision delay control for a large range of delays. This method can provide a more intuitive digital identification status for the internal delay control state and the locking state. By retrieving data, the current work progress status can be viewed, which is conducive to standardized, integrated production and intelligent promotion; the specific advantages include: 1. The system has a very high delay control resolution and uses DPLL (digital phase-locked loop) phase shift technology to achieve high-resolution delay control. 2. FPGA is used to perform full-cycle phase shifting to enter the first-level state for coarse delay adjustment, which can control a large range of delays within one FPGA clock cycle. 3. Entering the next level state, multi-segment cyclic digital adjustment is used for the delay error within one FPGA clock cycle until the control delay is within the precision range, that is, entering the final locked state.

[0068] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0069] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the steps in the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0070] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0071] These computer program instructions can also be loaded into a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 Figure 1

[0072] Finally, it should be noted that the above examples are merely intended to describe the technical solutions of the present application, rather than limiting the same. Although the present application has been described in detail with reference to the above examples, those skilled in the art should understand that the specific embodiments of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and any modification or equivalent replacement without departing from the spirit and scope of the present application should be covered within the protection scope of the claims of the present application.​​

Claims

1. A multi-stage digital precision delay control method for optical fiber time transfer, characterized in that: The following steps are involved: Step 1: Obtain the initial delay control value between the local end and the remote end; Step 2: obtaining an integer multiple of the FPGA phase shift clock cycle based on the initial delay control amount, performing compensation according to the integer multiple of the FPGA phase shift clock cycle, and obtaining a compensated updated delay control amount; Step 3, determine whether the update delay control amount is within a preset threshold range; if not, jump to step 4; if yes, jump to step 5; Step 4: Obtain an integer multiple of the FPGA phase shift clock cycle based on the update delay control amount, perform compensation based on the integer multiple of the FPGA phase shift clock cycle, obtain the compensated update delay control amount, and jump to step 3; Step 5: Use DPLL to perform phase shifting according to the updated delay control value to complete multi-level digital precision delay control; in, Step 1 specifically includes: The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA is measured by the measurement unit. As the initial delay control amount; Step 2 specifically includes: Determine the FPGA clock period as T, according to After the formula processes the initial delay control amount, the number of cycles N of full-cycle phase shift is set, and the FPGA outputs a 1PPS signal after delaying N cycles; Step 5 specifically includes: Step 5.1, configure the maximum threshold ξ of the internal phase accumulator of the numerically controlled oscillator max , minimum threshold value of phase accumulator ξ min And the center value of the frequency control word is ξ m ,ξ m =2 n-1 , n is the number of bits of the phase accumulator inside the digital controlled oscillator; the maximum threshold value of the coarse phase accumulator ξ max , minimum threshold value of phase accumulator ξ min And configure the coarse frequency control word value ξ according to the time interval measurement value between the sending and receiving ends, β is the proportional factor between the phase accumulator and the frequency control word; determines whether the coarse frequency control word value ξ is greater than the maximum threshold ξ max or less than the minimum threshold ξ min ; If not, configure the coarse frequency control word value ξ according to the initial value, if so, configure the coarse frequency control word value ξ according to the maximum threshold max Or the minimum threshold ξ min Configure the coarse frequency control word value ξ; Step 5.2: Determine the time interval measurement value between the sending and receiving ends Is it within plus or minus 300 ps? If not, jump to step 5.1; if yes, jump to step 5.

3. Step 5.3: Phase detection is performed between the 10 MHz output of the numerically controlled oscillator and the external input 10 MHz. The frequency control word value is configured to change the minimum step value δ according to the phase detection value. The frequency control word value ξ is precisely changed in the positive or negative direction according to the minimum step value δ, where ξ = ξ ± δ. Step 5.4: Determine the time interval measurement value between the sending and receiving ends Is it between plus or minus 30ps? If not, jump to step 5.

3. If yes, then the multi-level digital precision delay control is completed.

2. A multi-stage digital precision delay control method for optical fiber time transfer according to claim 1, characterized in that: Step 3 specifically includes: Determine whether the update delay control amount is between plus or minus 150ns; if not, jump to step 4; if yes, jump to step 5.

3. A multi-stage digital precision delay control system for optical fiber time transfer, characterized in that: include: A measurement acquisition module is used to obtain the initial delay control value between the local end and the remote end; A compensation module, configured to obtain an integer multiple of the FPGA phase shift clock cycle based on the initial delay control amount, perform compensation according to the integer multiple of the FPGA phase shift clock cycle, and obtain a compensated updated delay control amount; A judgment module, used to judge whether the update delay control amount is within a preset threshold range; If not, jump to the steps of the iteration module, if so, jump to the steps of the phase shift module; An iterative module is used to obtain an integer multiple of the FPGA phase shift clock cycle based on the update delay control amount, perform compensation according to the integer multiple of the FPGA phase shift clock cycle, obtain the compensated update delay control amount, and jump to the steps of the judgment module; Phase shift module, used to perform phase shifting using DPLL according to the updated delay control value, completing multi-level digital precision delay control; in, The steps performed by the measurement acquisition module specifically include: The actual delay between the external 1PPS signal transmitted by the optical fiber link and the 1PPS signal generated by the FPGA is measured by the measurement unit. As the initial delay control amount; The steps performed by the compensation module specifically include: Determine the FPGA clock period as T, according to After the formula processes the initial delay control amount, the number of cycles N of full-cycle phase shift is set, and the FPGA outputs a 1PPS signal after delaying N cycles; The steps performed by the phase shift module specifically include: Step 5.1, configure the maximum threshold ξ of the internal phase accumulator of the numerically controlled oscillator max , minimum threshold value of phase accumulator ξ min And the center value of the frequency control word is ξ m ,ξ m =2 n-1 , n is the number of bits of the phase accumulator inside the digital controlled oscillator; the maximum threshold value of the coarse phase accumulator ξ max , minimum threshold value of phase accumulator ξ min And configure the coarse frequency control word value ξ according to the time interval measurement value between the sending and receiving ends, β is the proportional factor between the phase accumulator and the frequency control word; determines whether the coarse frequency control word value ξ is greater than the maximum threshold ξ max or less than the minimum threshold ξ min ; If not, configure the coarse frequency control word value ξ according to the initial value, if so, configure the coarse frequency control word value ξ according to the maximum threshold max Or the minimum threshold ξ min Configure the coarse frequency control word value ξ; Step 5.2: Determine the time interval measurement value between the sending and receiving ends Is it within plus or minus 300 ps? If not, jump to step 5.1; if yes, jump to step 5.

3. Step 5.3: Phase detection is performed between the 10 MHz output of the numerically controlled oscillator and the external input 10 MHz. The frequency control word value is configured to change the minimum step value δ according to the phase detection value. The frequency control word value ξ is precisely changed in the positive or negative direction according to the minimum step value δ, where ξ = ξ ± δ. Step 5.4: Determine the time interval measurement value between the sending and receiving ends Is it between plus or minus 30ps? If not, jump to step 5.

3. If yes, then the multi-level digital precision delay control is completed.

4. A multi-stage digital precision delay control system for optical fiber time transfer according to claim 3, characterized in that: The steps executed by the judgment module specifically include: Determine whether the update delay control amount is between plus or minus 150ns; if not, jump to the steps of the iteration module; if so, jump to the steps of the phase shift module.

Images