A wide voltage domain, low jitter clock distributor circuit

Abstract

The present invention relates to a wide voltage range, low-jitter clock distributor circuit, belonging to the field of clock distributor circuits. The circuit comprises a first signal receiving amplifier unit, a second signal receiving amplifier unit, a first no-input output reset "0" unit, a second no-input output reset "0" unit, a first logic determination unit, a second logic determination unit, a frequency division path selection and voltage domain conversion unit, a first phase-locked loop unit, a second phase-locked loop unit, a power supply voltage conversion circuit, an output logic voltage domain conversion unit, and an LVDS output array. The circuit features automatic input signal detection, a wide bandwidth, a large voltage range, and low noise.

Description

Technical Field

[0001] The present invention belongs to the field of clock distributor circuits, and relates to a wide voltage domain, low-jitter clock distributor circuit, and in particular to the field of large-scale digital clocks. Background Art

[0002] Driven by factors such as cost, integration, and power consumption, CMOS process technology has advanced rapidly. High-speed, high-precision ADCs, clock synchronization networks, and RF transceivers are placing increasingly stringent demands on frequency synthesis. Frequency synthesizers have become a key module in determining electronic system performance, playing an irreplaceable role in fields such as communications and radar.

[0003] Phase-locked loop (PLL) technology is currently the most important tool in frequency synthesis. A typical PLL system includes modules such as a phase frequency detector, charge pump, filter, voltage-controlled oscillator, and programmable frequency divider. The bandwidth of the PLL often results in a design compromise between suppressing low-frequency and high-frequency noise. Single-stage CMOS PLLs struggle to achieve extremely low phase noise over a wide bandwidth. At the same time, designers of large-scale circuit systems hope to reduce the use of voltage domains to avoid multi-voltage domain interference and multi-power domain protection circuits, and to improve product reliability by increasing input signal paths. Therefore, it is necessary to design a chip with a wide voltage domain, broadband, low noise, and automatic input signal monitoring. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a clock distributor circuit suitable for CMOS process, which meets the requirements of 1.8V / 2.5V / 3.3V wide voltage range power supply, automatic input signal detection and extremely low phase noise.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions:

[0006] A wide voltage domain, low jitter clock distributor circuit includes a first signal receiving amplifier unit 100, a second signal receiving amplifier unit 200, a first no-input and output setting "0" unit 300, a second no-input and output setting "0" unit 400, a first logic determination unit 500, a second logic determination unit 600, a frequency division path selection and voltage domain conversion unit 700, a first phase-locked loop unit 800, a second phase-locked loop unit 900, a power supply voltage conversion circuit 1000, an output logic voltage domain conversion unit 1100, and an LVDS output array 1200; the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 are cascaded to the first no-input and output setting "0" unit 300 and the second no-input and output setting "0" unit 400, respectively. The outputs of the logic unit 300 and the second no-input output set to "0" unit 400 are respectively connected to the inputs of the first logic determination unit 500 and the second logic determination unit 600. The outputs of the first logic determination unit 500 and the second logic determination unit 600 are simultaneously connected to the frequency division path selection and voltage domain conversion unit 700. The output of the frequency division path selection and voltage domain conversion unit 700 is connected to the input of the first phase-locked loop unit 800. The output of the first phase-locked loop unit 800 is connected to the input of the second phase-locked loop unit 900. The power supply voltage conversion circuit 1000 supplies power to the first phase-locked loop unit 800 and the second phase-locked loop unit 900. The input of the output logic voltage domain conversion unit 1100 is connected to the output of the second phase-locked loop unit 900. The output of the output logic voltage domain conversion unit 1100 is cascaded to the LVDS output array 1200.

[0007] Furthermore, the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 each include a first resistor 101, a second resistor 102, a first transistor 103, a second transistor 104, and a third transistor 105; one end of the first resistor 101 and the second resistor 102 are both connected to Vdd1, and the other ends are respectively connected to the drain of the first transistor 103 and the second transistor 104; the gates of the first transistor 103 and the second transistor 104 are respectively connected to the positive signal input terminal and the reverse signal input terminal, and the sources are commonly connected to the drain of the third transistor 105; the gate of the third transistor 105 is connected to V BIAS1 , the source is grounded; the drain of the second transistor 104 is connected to the signal output end of this unit.

[0008] Furthermore, the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 are designed with 3.3V withstand voltage transistors and are powered by 3.3V, 2.5V or 8V.

[0009] Furthermore, the input signals of the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 are two sets of differential input signals, namely V1+ and V1- and V2+ and V2-; V1+ and V1- are respectively connected to the positive signal input terminal and the negative signal input terminal of the first signal receiving amplifier unit 100; V2+ and V2- are respectively connected to the positive signal input terminal and the negative signal input terminal of the second signal receiving amplifier unit 200; the signal output terminal V out1 and V out2 The signal output terminals of the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 are connected to each other respectively.

[0010] Furthermore, the first no-input and output-set-to-"0" unit 300 and the second no-input and output-set-to-"0" unit 400 both include a first inverter 301, a fourth transistor 302 and a first AND gate 303; one input end of the first AND gate 303 and the first inverter 301 are commonly connected to the reset signal input end of this unit, the other input end of the first AND gate 303 and the drain of the fourth transistor 302 are respectively connected to the signal output end of the first signal receiving amplifier unit 100, the output end of the first inverter 301 is connected to the gate end of the fourth transistor 302, the source of the fourth transistor 302 is connected to the ground, and the output end of the first AND gate 303 is connected to the signal output end of this unit.

[0011] Furthermore, the signal input terminals of the first no-input-output-set-to-0 unit 300 and the second no-input-output-set-to-0 unit 400 are connected to the signal output terminals V of the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200, respectively. out1 、V out2 , the signal output terminals are respectively connected to the output terminals OUT3 and OUT4; and the fourth transistor 302 is implemented by an NMOS tube, and the reset signal input terminals of the first no-input-output-set-0 unit 300 and the second no-input-output-set-0 unit 400 are commonly connected to the RESET signal terminal; the reset signal adopts a logic signal that jumps from logic "0" to logic "1" and remains.

[0012] Furthermore, the first logic determination unit 500 and the second logic determination unit 600 have the same structure, and both include a second inverter 501, a third inverter 502, a fourth inverter 503, a fifth inverter 504, a fifth transistor 505, a sixth transistor 506, a third resistor 507, a first capacitor 508, and a first comparator 509; the input terminals of the second inverter 501 and the fourth inverter 503 are connected to the logic signal input terminals of the units, and the output terminals are connected to the input terminals of the third inverter 502 and the fifth inverter 504, respectively; the output terminal of the third inverter 502 is connected to the output signal terminal ; The output end of the fifth inverter 504 is connected to the gate of the fifth transistor 505; the gate of the fifth transistor 505 is also connected to the gate of the sixth transistor 506, the source is connected to the power supply voltage Vdd1, and the drain is connected to the drain of the sixth transistor 506; the source of the sixth transistor 506 is grounded, and the drain is connected to one end of the third resistor 507; the other end of the third resistor 507 is simultaneously connected to one end of the first capacitor 508 and the inverting input end of the first comparator 509; the positive input end of the first comparator 509 is connected to the voltage, and the output end is connected to the signal output end of this unit; the other end of the first capacitor 508 is grounded.

[0013] Furthermore, the logic signal input terminals of the first logic determination unit 500 and the second logic determination unit 600 are respectively connected to the signal output terminals OUT3 and OUT4 of the first no-input-output-set-to-"0" unit 300 and the second no-input-output-set-to-"0" unit 400, and the signal output terminals are respectively connected to the output terminals X and Y; the fifth transistor 505 is implemented by a PMOS transistor, and the sixth transistor 506 is implemented by an NMOS transistor.

[0014] Furthermore, the frequency division path selection and voltage domain conversion unit 700 includes a first frequency divider 701, a second frequency divider 702, a sixth inverter 703, a second AND gate 704, a first 2-to-1 output gate 705, a seventh transistor 706, an eighth transistor 707, a ninth transistor 708, and a tenth transistor 709; the signal input terminals of the first frequency divider 701 and the second frequency divider 702 are respectively connected to the output signal terminals of the first logic determination unit 500 and the second logic determination unit 600, and the output terminals are respectively connected to the signal input terminals of the first 2-to-1 output gate 705; the enable signal input terminal of the first frequency divider 701 and the first inverter 703 are simultaneously connected to the first logic determination unit 500. The input terminal of the first AND gate 704 is connected to the output terminal of the first inverter 703 and the output terminal Y of the second logic judgment unit 600 at the same time, and the output terminal is connected to the signal enable signal input terminal of the second frequency divider 702; the signal output terminal of the first 2-to-1 output gate 705 is connected to the gate of the seventh transistor 706 and the eighth transistor 707 at the same time; the source of the seventh transistor 706 is connected to Vdd1, and the drain is connected to the drain of the second transistor 707; the source of the eighth transistor 707 is grounded; the gates of the ninth transistor 708 and the tenth transistor 709 are connected to the drain of the seventh transistor 706 at the same time, the drains are connected to the output signal OUT7 at the same time, and the sources are connected to Vdd2 and ground respectively.

[0015] Furthermore, the power supply Vdd2 is 1.8V; the frequency dividers start to work when the enable signals of the first frequency divider 701 and the second frequency divider 702 are high level.

[0016] Furthermore, the first phase-locked loop unit 800 includes a first phase frequency detector 801, a first charge pump 802, a first filter 803, a first voltage-controlled oscillator 804, and a third frequency divider 805; the second phase-locked loop unit 900 includes a second phase frequency detector 901, a second charge pump 902, a second filter 903, a second voltage-controlled oscillator 904, a fourth frequency divider 905, and a fifth frequency divider 906;

[0017] The signal input terminal of the first phase frequency detector 801 is connected to the output terminal OUT7 signal of the frequency division path selection and voltage domain conversion unit 700 and the output terminal of the third frequency divider 805 at the same time, the signal output terminal is connected to the signal input terminal of the first charge pump 802, the signal output terminal of the first charge pump 802 is connected to the signal input terminal of the first filter 803, the signal output terminal of the first filter 803 is connected to the signal input terminal of the first voltage-controlled oscillator 804, the signal output terminal of the first voltage-controlled oscillator 804 and the signal output terminal of the fourth frequency divider 905 are simultaneously connected to the signal input terminal of the second phase frequency detector 901; The signal output end of the frequency detector and phase detector 901 is connected to the signal input end of the second charge pump 902, the signal output end of the second charge pump 902 is connected to the signal input end of the second filter 903, the signal output end of the second filter 903 is connected to the signal input end of the second voltage-controlled oscillator 904, the output end of the second voltage-controlled oscillator 904 is connected to the signal input end of the fourth frequency divider 905, the signal input end of the fourth frequency divider 905 is connected to the signal input end of the fifth frequency divider 906, and the signal output end of the fifth frequency divider 906 is connected to the input signal end of the third frequency divider 805 and the signal output end OUT8 of this unit.

[0018] Furthermore, all system modules of the first phase-locked loop unit 800 and the second phase-locked loop unit 900 are powered by 1.8V, and the 1.8V voltage is provided by the power supply voltage conversion circuit 1000 .

[0019] Furthermore, the output logic voltage domain conversion unit 1100 includes a seventh inverter 1101, an eighth inverter 1102, a ninth inverter 1103, a tenth inverter 1109, an eleventh inverter 1110, an eleventh transistor 1105, a twelfth transistor 1106, a thirteenth transistor 1107, a fourteenth transistor 1108, a fifteenth transistor 1111, a sixteenth transistor 1112, a seventeenth transistor 1113, an eighteenth transistor 1114 and a third AND gate 1104; the seventh inverter 1101 01 and the inverter input end of the ninth inverter 1103 are connected to the output end OUT8 of the second phase-locked loop unit 900; the output end of the seventh inverter 1101 is connected to the signal input end of the eighth inverter 1102, and the output end of the ninth inverter 1103 is connected to the two input ends of the third AND gate 1104; the output end of the third AND gate 1104 and the output end of the eighth inverter 1102 are connected to the gates of the twelfth transistor 1106 and the fourteenth transistor 1108 respectively; the twelfth transistor 1106 and the fourteenth transistor 1108 are connected to the gates of the twelfth transistor 1106 and the fourteenth transistor 1108 respectively. The sources of the eleventh transistor 1105 and the thirteenth transistor 1107 are grounded at the same time; the gate of the eleventh transistor 1105 is connected to the drains of the thirteenth transistor 1107 and the fourteenth transistor 1108 at the same time; the gate of the thirteenth transistor 1107 is connected to the drains of the eleventh transistor 1105 and the twelfth transistor 1106 at the same time; the drains of the eleventh transistor 1105 and the thirteenth transistor 1107 are connected to the input terminals of the tenth inverter 1109 and the eleventh inverter 1110, respectively; the gate of the tenth transistor 1105 is connected to the drains of the thirteenth transistor 1107 and the fourteenth transistor 1108 at the same time; the gate of the thirteenth transistor 1107 is connected to the drains of the eleventh transistor 1105 and the twelfth transistor 1106 at the same time; the drains of the eleventh transistor 1105 and the thirteenth transistor 1107 are connected to the input terminals of the tenth inverter 1109 and the eleventh inverter 1110, respectively; The gates of the fifth transistor 1111 and the sixteenth transistor 1112 are simultaneously connected to the output end of the tenth inverter 1109, the drains are connected together, and the sources are respectively connected to Vdd3 and the ground; the gates of the seventeenth transistor 1113 and the eighteenth transistor 1114 are simultaneously connected to the output end of the eleventh inverter 1110, the drains are connected together, and the sources are respectively connected to Vdd3 and the ground; the drain of the fifteenth transistor 1111 is connected to the output signal terminal OUT9, and the drain of the seventeenth transistor 1113 is connected to the output signal terminal OUT10.

[0020] Furthermore, the eleventh transistor 1105 and the thirteenth transistor 1107 are PMOS transistors, and the twelfth transistor 1106 and the fourteenth transistor 1108 are NMOS transistors; Vdd2 is powered by 1.8V, and the eleventh transistor 1105, the twelfth transistor 1106, the thirteenth transistor 1107, the fourteenth transistor 1108, the fifteenth transistor 1111, the sixteenth transistor 1112, the seventeenth transistor 1113 and the eighteenth transistor 1114 are designed as 3.3V transistors; the power supply voltage Vdd3 is 1.8V, 2.5V or 3.3V.

[0021] Furthermore, the LVDS output array 1200 is composed of 12 parallel output LVDS channel units; each LVDS channel unit includes nineteenth to twenty-fourth transistors 1201-1206, a first amplifier 1207, a second capacitor 1212, a fourth resistor 1208, a fifth resistor 1209, a sixth resistor 1210, and a seventh resistor 1211; the gates of the nineteenth transistor 1201 and the twentieth transistor 1202 are simultaneously connected to the output terminal OUT9 of the output logic voltage domain conversion unit 1100; the drains of the nineteenth transistor 1201 and the twenty-first transistor 1202 are simultaneously connected to one end of the first resistor 1208 and one end of the sixth resistor 1210; the other ends of the fourth resistor 1208 and the sixth resistor 1210 are respectively connected to one end of the fifth resistor 1209 and the seventh resistor 1211; the other ends of the fifth resistor 1209 and the seventh resistor 1211 are simultaneously connected to the drains of the twenty-first transistor 1203 and the twenty-second transistor 1204; The source of the twenty-third transistor 1205 is simultaneously connected to the drain of the twenty-third transistor 1205, the source of the twenty-third transistor 1205 is connected to Vdd3, and the gate is connected to IBIAS1; the gates of the twenty-first transistor 1203 and the twenty-second transistor 1204 are connected to the output terminal OUT10 of the output logic voltage domain conversion unit 1100, the sources of the twentieth transistor 1202 and the twenty-second transistor 1204 are connected to the drain of the twenty-fourth transistor 1206, and the source of the twenty-fourth transistor 1206 is grounded; the 1.25V voltage is simultaneously connected to the inverting input terminal of the first amplifier 1207 and one end of the second capacitor 1212, and the other end of the second capacitor 1212 is simultaneously connected to the output terminal of the first amplifier 1207 and the gate of the twenty-fourth transistor 1206; the non-inverting input terminal of the first amplifier 1207 is connected to the node where the fourth resistor 1208 and the fifth resistor 1209 are connected; the inverting output signal terminal OUTN is connected to the drain of the nineteenth transistor 1201, and the non-inverting output signal terminal OUTP is connected to the drain of the twenty-first transistor 1203.

[0022] Furthermore, the bias current of the twenty-third transistor 1205 is 7 mA, the resistance values of the fourth resistor 1208, the fifth resistor 1209, the sixth resistor 1210 and the seventh resistor 1211 are all 50 ohms; the power supply voltage Vdd3 is 1.8V, 2.5V or 3.3V; the nineteenth to twenty-second transistors 1201-1204 are 3.3V voltage-resistant transistors.

[0023] Compared with the prior art, the present invention has the following advantages:

[0024] The present invention has the advantages of automatic detection of input signals, wide frequency band, large voltage range, low noise, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1This is a schematic diagram of a cascade circuit of a parallel signal receiving amplifier unit, a no-input and output setting "0" unit, and a logic decision unit proposed by the present invention;

[0026] Figure 2 This is a circuit schematic diagram of the frequency division path selection and voltage domain conversion unit proposed by the present invention;

[0027] Figure 3 This is a schematic diagram of the phase-locked loop unit circuit proposed by the present invention;

[0028] Figure 4 This is a schematic diagram of the output logic voltage domain conversion unit circuit proposed by the present invention;

[0029] Figure 5 This is a schematic diagram of the LVDS output array circuit proposed by the present invention. DETAILED DESCRIPTION

[0030] To further illustrate the technical solutions disclosed in the present invention, the following is a detailed description of the technical solutions disclosed in the present invention in conjunction with the accompanying drawings and specific embodiments. Those skilled in the art should know that any optimized designs and improved methods made without violating the spirit of the invention fall within the scope of protection of the present invention, and conventional techniques in the field will not be described in detail in this specific embodiment.

[0031] Example 1

[0032] In order to achieve the above object, the present invention adopts the following technical solutions:

[0033] like Figure 1As shown, a wide voltage domain, low jitter clock distributor circuit includes a first signal receiving amplifier unit 100, a second signal receiving amplifier unit 200, a first no-input and output setting "0" unit 300, a second no-input and output setting "0" unit 400, a first logic determination unit 500, a second logic determination unit 600, a frequency division path selection and voltage domain conversion unit 700, a first phase-locked loop unit 800, a second phase-locked loop unit 900, a power supply voltage conversion circuit 1000, an output logic voltage domain conversion unit 1100, and an LVDS output array 1200; the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 are cascaded corresponding to the first no-input and output setting "0" unit 300 and the second no-input and output setting "0" unit 400, respectively. The outputs of unit 300 and the second no-input output set to "0" unit 400 are respectively connected to the inputs of the first logic determination unit 500 and the second logic determination unit 600. The outputs of the first logic determination unit 500 and the second logic determination unit 600 are simultaneously connected to the frequency division path selection and voltage domain conversion unit 700. The output of the frequency division path selection and voltage domain conversion unit 700 is connected to the input of the first phase-locked loop unit 800, and the output of the first phase-locked loop unit 800 is connected to the input of the second phase-locked loop unit 900. The power supply voltage conversion circuit 1000 provides power to the first phase-locked loop unit 800 and the second phase-locked loop unit 900. The input of the output logic voltage domain conversion unit 1100 is connected to the output of the second phase-locked loop unit 900, and the output of the output logic voltage domain conversion unit 1100 is cascaded to the LVDS output array 1200.

[0034] In order to receive the differential input signals of the two channels and amplify the input signals of the current channels to an amplitude acceptable to the subsequent circuit, the system front end has two parallel signal receiving amplifier units, namely a first signal receiving amplifier unit 100 and a second signal receiving amplifier unit 200. The first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 both include a first resistor 101, a second resistor 102, a first transistor 103, a second transistor 104 and a third transistor 105; one end of the first resistor 101 and the second resistor 102 are connected to Vdd1, and the other ends are connected to the drains of the first transistor 103 and the second transistor 104 respectively; the gates of the first transistor 103 and the second transistor 104 are connected to the positive signal input terminal and the reverse signal input terminal respectively, and the sources are commonly connected to the drain of the third transistor 105; the gate of the third transistor 105 is connected to V BIAS1 , the source is grounded; the drain of the second transistor 104 is connected to the signal output end of this unit.

[0035] Among them, the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200 of this patent are designed with 3.3V voltage-resistant transistors and can use 3.3V / 2.5V / 1.8V power supply.

[0036] The gain of the amplifier:

[0037] A v =g m1 R (1)

[0038] g m1 represents the transconductance of the first transistor 103, and R represents the resistance of the first resistor 101. In this embodiment, the gain of the amplifier is 10 times.

[0039] Furthermore, the system input signal is two sets of differential input signals, namely V1+, V1- and V2+, V2-. V1+ and V1- are connected to the positive signal input terminal and the negative signal input terminal of the first signal receiving amplifier unit 100 respectively; V2+ and V2- are connected to the positive signal input terminal and the negative signal input terminal of the second signal receiving amplifier unit 200 respectively; V out1 、V out2 The signal output terminals of the first and second signal receiving amplifier units are connected respectively.

[0040] In order to ensure that when there is no input signal in the system, the signal is logically judged to be in a logic "0" state in the channel, the present invention proposes a first no-input-output-set-to-"0" unit 300 and a second no-input-output-set-to-"0" unit 400 with the same architecture. Both units include a first inverter 301, a fourth transistor 302, and a first AND gate 303. One input terminal of the first AND gate 303 and the first inverter 301 are connected to the reset signal input terminal of the unit, the other input terminal of the first AND gate 303 and the drain of the fourth transistor 302 are respectively connected to the signal output terminal of the first signal receiving amplifier unit 100, the output terminal of the first inverter 301 is connected to the gate terminal of the fourth transistor 302, the source of the fourth transistor 302 is connected to ground, and the output terminal of the first AND gate 303 is connected to the signal output terminal of the unit.

[0041] Furthermore, the signal input terminals of the first no-input-output-set-to-0 unit 300 and the second no-input-output-set-to-0 unit 400 are connected to the signal output terminals V of the first signal receiving amplifier unit 100 and the second signal receiving amplifier unit 200, respectively. out1 、V out2, the signal output terminals are respectively connected to the output terminals OUT3 and OUT4; and the fourth transistor 302 is implemented by an NMOS tube, and the reset signal input terminals of the first no-input-output-set-0 unit 300 and the second no-input-output-set-0 unit 400 are commonly connected to the RESET signal terminal; the reset signal adopts a logic signal that jumps from logic "0" to logic "1" and remains.

[0042] When the system is powered on, the RESET signal transitions from logic "0" to logic "1," and the outputs of OUT3 and OUT4 are fixed to logic "0." When an input signal is present, the outputs of OUT3 and OUT4 are the amplified input signal; when no input signal is present, OUT3 and OUT4 are fixed to logic "0." This fixed logic ensures the accuracy of subsequent logic decisions.

[0043] In order to achieve the purpose of automatically detecting the input signal channel and shutting down the other input channel to reduce power consumption; or when both channels of the system input signals, the system only passes the signal of channel 1; or when the system has no input signal, it automatically shuts down the two channels, the present invention proposes a first logic determination unit 500 and a second logic determination unit 600 with the same structure. Both include a second inverter 501, a third inverter 502, a fourth inverter 503, a fifth inverter 504, a fifth transistor 505, a sixth transistor 506, a third resistor 507, a first capacitor 508 and a first comparator 509; the input terminals of the second inverter 501 and the fourth inverter 503 are connected to the logic signal input terminals of the units, and the output terminals are connected to the input terminals of the third inverter 502 and the fifth inverter 504 respectively; the output terminal of the third inverter 502 is connected to the output signal terminal; the output terminal of the fifth inverter 504 is connected to the first comparator 509 ... The gate of the fifth transistor 505; the gate of the fifth transistor 505 is also connected to the gate of the sixth transistor 506, the source is connected to the power supply voltage Vdd1, and the drain is connected to the drain of the sixth transistor 506; the source of the sixth transistor 506 is grounded, and the drain is connected to one end of the third resistor 507; the other end of the third resistor 507 is simultaneously connected to one end of the first capacitor 508 and the inverting input end of the first comparator 509; the positive input end of the first comparator 509 is connected to the voltage, and the output end is connected to the signal output end of this unit; the other end of the first capacitor 508 is grounded.

[0044] Furthermore, OUT3 and OUT4 are connected to the logic signal input terminals of the first and second logic determination units, respectively, and the output signal terminals X and Y are connected to the signal output terminals of the first and second logic determination units, respectively. The fifth transistor is implemented using a PMOS transistor, and the sixth transistor is implemented using an NMOS transistor.

[0045] Furthermore, when the channel input is "0", the inverting input terminal of the first comparator outputs "1", and the comparator outputs logic "0". When there is a signal input to the channel, the inverting input terminal of the first comparator outputs "0", and the comparator outputs logic "1".

[0046] like Figure 2 As shown, the frequency division path selection and voltage domain conversion unit 700 proposed by the present invention includes a first frequency divider 701, a second frequency divider 702, a sixth inverter 703, a second AND gate 704, a first 2-to-1 output gate 705, a seventh transistor 706, an eighth transistor 707, a ninth transistor 708 and a tenth transistor 709; the signal input terminals of the first frequency divider 701 and the second frequency divider 702 are respectively connected to the output signal terminals of the first logic determination unit 500 and the second logic determination unit 600, and the output terminals are respectively connected to the signal input terminal of the first 2-to-1 output gate 705; the enable signal input terminal of the first frequency divider 701 and the first inverter 703 are simultaneously connected to the first logic determination unit 500 and the output signal terminal of the second logic determination unit 600. 00; the input terminal of the first AND gate 704 is simultaneously connected to the output terminal of the first inverter 703 and the output terminal Y of the second logic judgment unit 600, and the output terminal is connected to the signal enable signal input terminal of the second frequency divider 702; the signal output terminal of the first 2-to-1 output gate 705 is simultaneously connected to the gate of the seventh transistor 706 and the eighth transistor 707; the source of the seventh transistor 706 is connected to Vdd1, and the drain is connected to the drain of the second transistor 707; the source of the eighth transistor 707 is grounded; the gates of the ninth transistor 708 and the tenth transistor 709 are simultaneously connected to the drain of the seventh transistor 706, the drains are simultaneously connected to the output signal OUT7, and the sources are respectively connected to Vdd2 and ground.

[0047] The enable signal input terminal of the first frequency divider 701 is logic A, and the enable signal input terminal of the second frequency divider 702 is logic B. According to the above logic requirements, the following truth table can be obtained:

[0048] Table 1 Frequency division module control truth table

[0049]

[0050] According to the truth table, we can get the following logical expression:

[0051]

[0052]

[0053] Furthermore, the power supply Vdd2 is 1.8V; the frequency dividers start to work when the enable signals of the first frequency divider 701 and the second frequency divider 702 are high level.

[0054] like Figure 3As shown, the first phase-locked loop unit 800 includes a first phase frequency detector 801, a first charge pump 802, a first filter 803, a first voltage-controlled oscillator 804, and a third frequency divider 805; the second phase-locked loop unit 900 includes a second phase frequency detector 901, a second charge pump 902, a second filter 903, a second voltage-controlled oscillator 904, a fourth frequency divider 905, and a fifth frequency divider 906;

[0055] The signal input terminal of the first phase frequency detector 801 is connected to the output terminal OUT7 signal of the frequency division path selection and voltage domain conversion unit 700 and the output terminal of the third frequency divider 805 at the same time, the signal output terminal is connected to the signal input terminal of the first charge pump 802, the signal output terminal of the first charge pump 802 is connected to the signal input terminal of the first filter 803, the signal output terminal of the first filter 803 is connected to the signal input terminal of the first voltage-controlled oscillator 804, the signal output terminal of the first voltage-controlled oscillator 804 and the signal output terminal of the fourth frequency divider 905 are simultaneously connected to the signal input terminal of the second phase frequency detector 901; The signal output end of the frequency detector and phase detector 901 is connected to the signal input end of the second charge pump 902, the signal output end of the second charge pump 902 is connected to the signal input end of the second filter 903, the signal output end of the second filter 903 is connected to the signal input end of the second voltage-controlled oscillator 904, the output end of the second voltage-controlled oscillator 904 is connected to the signal input end of the fourth frequency divider 905, the signal input end of the fourth frequency divider 905 is connected to the signal input end of the fifth frequency divider 906, and the signal output end of the fifth frequency divider 906 is connected to the input signal end of the third frequency divider 805 and the signal output end OUT8 of this unit.

[0056] Here we only give the system transfer function of the cascaded phase-locked loop:

[0057]

[0058] N1 represents the frequency division number of the third frequency divider 805, and N2 represents the frequency division number of the fourth frequency divider 905. Z1 represents the first zero point, ω Z2 represents the second zero point, ω PLL1 represents the first phase-locked loop bandwidth, ω PLL2 Indicates the second phase-locked loop bandwidth. In this embodiment, ω PLL1 =90Hz,ω PLL2 =70Khz. ω Z1 =10 Hz, ω Z2 =20khz. N1=4, N2=32.

[0059] Furthermore, to ensure the operating speed of the first and second phase-locked loop units, all system modules in this unit are powered by a 1.8V voltage, generated by power supply voltage conversion circuit 1000. The first-stage phase-locked loop (PLL) uses a bandwidth of less than 90Hz and an off-chip, high-stability voltage-controlled rubidium crystal oscillator. This provides a clean reference signal for the second stage. The second stage uses a 500kHz bandwidth to suppress the phase noise of its own VCO, generating a low-phase noise signal through high- and low-pass filtering.

[0060] like Figure 4 As shown, the output logic voltage domain conversion unit 1100 includes a seventh inverter 1101, an eighth inverter 1102, a ninth inverter 1103, a tenth inverter 1109, an eleventh inverter 1110, an eleventh transistor 1105, a twelfth transistor 1106, a thirteenth transistor 1107, a fourteenth transistor 1108, a fifteenth transistor 1111, a sixteenth transistor 1112, a seventeenth transistor 1113, an eighteenth transistor 1114 and a third AND gate 1104; the seventh inverter 110 1 and the inverter input end of the ninth inverter 1103 are connected to the output end OUT8 of the second phase-locked loop unit 900; the output end of the seventh inverter 1101 is connected to the signal input end of the eighth inverter 1102, and the output end of the ninth inverter 1103 is connected to the two input ends of the third AND gate 1104; the output end of the third AND gate 1104 and the output end of the eighth inverter 1102 are connected to the gates of the twelfth transistor 1106 and the fourteenth transistor 1108 respectively; the twelfth transistor 1106 and the fourteenth transistor 1108 are connected to the gates of the twelfth transistor 1106 and the fourteenth transistor 1108 respectively; 8 are grounded at the same time; the sources of the eleventh transistor 1105 and the thirteenth transistor 1107 are grounded at the same time, the gate of the eleventh transistor 1105 is connected to the drains of the thirteenth transistor 1107 and the fourteenth transistor 1108 at the same time; the gate 1107 of the thirteenth transistor is connected to the drains of the eleventh transistor 1105 and the twelfth transistor 1106 at the same time; the drains of the eleventh transistor 1105 and the thirteenth transistor 1107 are connected to the input terminals of the tenth inverter 1109 and the eleventh inverter 1110, respectively; the gate of the fifteenth transistor is connected to the drains of the eleventh transistor 1105 and the twelfth transistor 1106 at the same time; the drains of the eleventh transistor 1105 and the thirteenth transistor 1107 are connected to the input terminals of the tenth inverter 1109 and the eleventh inverter 1110, respectively; The gates of the transistor 1111 and the sixteenth transistor 1112 are simultaneously connected to the output end of the tenth inverter 1109, the drains are connected together, and the sources are respectively connected to Vdd3 and the ground; the gates of the seventeenth transistor 1113 and the eighteenth transistor 1114 are simultaneously connected to the output end of the eleventh inverter 1110, the drains are connected together, and the sources are respectively connected to Vdd3 and the ground; the drain of the fifteenth transistor 1111 is connected to the output signal terminal OUT9, and the drain of the seventeenth transistor 1113 is connected to the output signal terminal OUT10.

[0061] Furthermore, the eleventh transistor 1105 and the thirteenth transistor 1107 are PMOS transistors, and the twelfth transistor 1106 and the fourteenth transistor 1108 are NMOS transistors; Vdd2 is powered by 1.8V, and the eleventh transistor 1105, the twelfth transistor 1106, the thirteenth transistor 1107, the fourteenth transistor 1108, the fifteenth transistor 1111, the sixteenth transistor 1112, the seventeenth transistor 1113 and the eighteenth transistor 1114 are designed as 3.3V transistors; the power supply voltage Vdd3 is 1.8V, 2.5V or 3.3V.

[0062] like Figure 5 As shown, the LVDS output array 1200 is composed of 12 parallel output LVDS channel units; each LVDS channel unit includes nineteenth to twenty-fourth transistors 1201-1206, a first amplifier 1207, a second capacitor 1212, a fourth resistor 1208, a fifth resistor 1209, a sixth resistor 1210, and a seventh resistor 1211; the gates of the nineteenth transistor 1201 and the twentieth transistor 1202 are simultaneously connected to the output terminal OUT9 of the output logic voltage domain conversion unit 1100, the drains of the nineteenth transistor 1201 and the twenty-first transistor 1202 are simultaneously connected to one end of the first resistor 1208 and the sixth resistor 1210, the other ends of the fourth resistor 1208 and the sixth resistor 1210 are respectively connected to one end of the fifth resistor 1209 and the seventh resistor 1211; the other ends of the fifth resistor 1209 and the seventh resistor 1211 are simultaneously connected to the drains of the twenty-first transistor 1203 and the twenty-second transistor 1204; The source is simultaneously connected to the drain of the twenty-third transistor 1205, the source of the twenty-third transistor 1205 is connected to Vdd3, and the gate is connected to IBIAS1; the gates of the twenty-first transistor 1203 and the twenty-second transistor 1204 are connected to the output terminal OUT10 of the output logic voltage domain conversion unit 1100, the sources of the twentieth transistor 1202 and the twenty-second transistor 1204 are connected to the drain of the twenty-fourth transistor 1206, and the source of the twenty-fourth transistor 1206 is grounded; the 1.25V voltage is simultaneously connected to the inverting input terminal of the first amplifier 1207 and one end of the second capacitor 1212, and the other end of the second capacitor 1212 is simultaneously connected to the output terminal of the first amplifier 1207 and the gate of the twenty-fourth transistor 1206; the non-inverting input terminal of the first amplifier 1207 is connected to the node where the fourth resistor 1208 and the fifth resistor 1209 are connected; the inverting output signal terminal OUTN is connected to the drain of the nineteenth transistor 1201, and the non-inverting output signal terminal OUTP is connected to the drain of the twenty-first transistor 1203.

[0063] Furthermore, the bias current of the twenty-third transistor 1205 is 7 mA, the resistance values of the fourth resistor 1208, the fifth resistor 1209, the sixth resistor 1210 and the seventh resistor 1211 are all 50 ohms; the power supply voltage Vdd3 is 1.8V, 2.5V or 3.3V; the nineteenth to twenty-second transistors 1201-1204 are 3.3V voltage-resistant transistors.

Claims

1. A wide voltage range, low jitter clock distributor circuit, characterized by: The invention comprises a first signal receiving amplifier unit (100), a second signal receiving amplifier unit (200), a first no-input-output setting "0" unit (300), a second no-input-output setting "0" unit (400), a first logic determination unit (500), a second logic determination unit (600), a frequency division path selection and voltage domain conversion unit (700), a first phase-locked loop unit (800), a second phase-locked loop unit (900), a power supply voltage conversion circuit (1000), an output logic voltage domain conversion unit (1100) and an LVDS output array (1200); the first signal receiving amplifier unit (100) and the second signal receiving amplifier unit (200) are cascaded to the first no-input-output setting "0" unit (300) and the second no-input-output setting "0" unit (400), respectively; the first no-input-output setting "0" unit (300) and the second no-input-output setting "0" unit (400) are cascaded to the first no-input-output setting "0" unit (300) and the second no-input-output setting "0" unit (400). The output of the output setting "0" unit (400) is respectively connected to the input of the first logic determination unit (500) and the second logic determination unit (600); the outputs of the first logic determination unit (500) and the second logic determination unit (600) are simultaneously connected to the frequency division path selection and voltage domain conversion unit (700); the output of the frequency division path selection and voltage domain conversion unit (700) is connected to the input of the first phase-locked loop unit (800); the output of the first phase-locked loop unit (800) is connected to the input of the second phase-locked loop unit (900); the power supply voltage conversion circuit (1000) supplies power to the first phase-locked loop unit (800) and the second phase-locked loop unit (900); the input of the output logic voltage domain conversion unit (1100) is connected to the output of the second phase-locked loop unit (900); the output of the output logic voltage domain conversion unit (1100) is cascaded to the LVDS output array (1200).

2. The wide voltage range, low jitter clock distributor circuit according to claim 1, wherein: The first signal receiving amplifier unit (100) and the second signal receiving amplifier unit (200) both comprise a first resistor (101), a second resistor (102), a first transistor (103), a second transistor (104) and a third transistor (105); one end of the first resistor (101) and the second resistor (102) are both connected to Vdd1, and the other ends are respectively connected to the drains of the first transistor (103) and the second transistor (104); the gates of the first transistor (103) and the second transistor (104) are respectively connected to the forward signal input terminal and the reverse signal input terminal, and the sources are commonly connected to the drain of the third transistor (105); the gate of the third transistor (105) is connected to V BIAS1 , the source is grounded; the drain of the second transistor (104) is connected to the signal output end of this unit.

3. The wide voltage range, low jitter clock distributor circuit according to claim 2, wherein: The first signal receiving amplifier unit (100) and the second signal receiving amplifier unit (200) are designed with 3.3V voltage-resistant transistors and are powered by 3.3V, 2.5V or 8V.

4. The wide voltage range, low jitter clock distributor circuit according to claim 2, wherein: The input signals of the first signal receiving amplifier unit (100) and the second signal receiving amplifier unit (200) are two groups of differential input signals, namely V1+ and V1- and V2+ and V2-; V1+ and V1- are respectively connected to the positive signal input terminal and the negative signal input terminal of the first signal receiving amplifier unit (100); V2+ and V2- are respectively connected to the positive signal input terminal and the negative signal input terminal of the second signal receiving amplifier unit (200); the signal output terminal V out1 and V out2 The signal output ends are respectively connected to the first signal receiving amplifier unit (100) and the second signal receiving amplifier unit (200).

5. The wide voltage range, low jitter clock distributor circuit according to claim 1, wherein: The first no-input and output-set-to-0 unit (300) and the second no-input and output-set-to-0 unit (400) both comprise a first inverter (301), a fourth transistor (302) and a first AND gate (303); one input end of the first AND gate (303) and the first inverter (301) are commonly connected to the reset signal input end of the unit, the other input end of the first AND gate (303) and the drain of the fourth transistor (302) are respectively connected to the signal output end of the first signal receiving amplifier unit (100), the output end of the first inverter (301) is connected to the gate end of the fourth transistor (302), the source of the fourth transistor (302) is connected to the ground, and the output end of the first AND gate (303) is connected to the signal output end of the unit.

6. The wide voltage range, low jitter clock distributor circuit according to claim 5, characterized in that: The signal input terminals of the first no-input-output-set-to-0 unit (300) and the second no-input-output-set-to-0 unit (400) are respectively connected to the signal output terminals V of the first signal receiving amplifier unit (100) and the second signal receiving amplifier unit (200). out1 、V out2 , the signal output terminals are respectively connected to the output terminals OUT3 and OUT4; and the fourth transistor (302) is implemented by an NMOS tube, and the reset signal input terminals of the first no-input-output-set-0 unit (300) and the second no-input-output-set-0 unit (400) are commonly connected to the RESET signal terminal; the reset signal is a logic signal that jumps from logic "0" to logic "1" and remains.

7. The wide voltage domain, low jitter clock distributor circuit according to claim 1, wherein: The first logic determination unit (500) and the second logic determination unit (600) have the same structure, and both include a second inverter (501), a third inverter (502), a fourth inverter (503), a fifth inverter (504), a fifth transistor (505), a sixth transistor (506), a third resistor (507), a first capacitor (508) and a first comparator (509); the input ends of the second inverter (501) and the fourth inverter (503) are connected to the logic signal input end of the unit, and the output ends are respectively connected to the input ends of the third inverter (502) and the fifth inverter (504); the output end of the third inverter (502) is connected to the output signal input end. The output terminal of the fifth inverter (504) is connected to the gate of the fifth transistor (505); the gate of the fifth transistor (505) is simultaneously connected to the gate of the sixth transistor (506), the source is connected to the power supply voltage Vdd1, and the drain is connected to the drain of the sixth transistor (506); the source of the sixth transistor (506) is grounded, and the drain is connected to one end of the third resistor (507); the other end of the third resistor (507) is simultaneously connected to one end of the first capacitor (508) and the inverting input terminal of the first comparator (509); the positive input terminal of the first comparator (509) is connected to the voltage, and the output terminal is connected to the signal output terminal of this unit; the other end of the first capacitor (508) is grounded.

8. The wide voltage domain, low jitter clock distributor circuit according to claim 7, characterized in that: The logic signal input terminals of the first logic determination unit (500) and the second logic determination unit (600) are respectively connected to the signal output terminals OUT3 and OUT4 of the first no-input and output-set-to-0 unit (300) and the second no-input and output-set-to-0 unit (400), and the signal output terminals are respectively connected to the output terminals X and Y; the fifth transistor (505) is implemented by a PMOS transistor, and the sixth transistor (506) is implemented by an NMOS transistor.

9. The wide voltage domain, low jitter clock distributor circuit according to claim 1, characterized in that: The frequency division path selection and voltage domain conversion unit (700) comprises a first frequency divider (701), a second frequency divider (702), a sixth inverter (703), a second AND gate (704), a first 2-to-1 output gate (705), a seventh transistor (706), an eighth transistor (707), a ninth transistor (708) and a tenth transistor (709); the signal input ends of the first frequency divider (701) and the second frequency divider (702) are respectively connected to the output signal ends of the first logic determination unit (500) and the second logic determination unit (600), and the output ends are respectively connected to the signal input ends of the first 2-to-1 output gate (705); the enable signal input end of the first frequency divider (701) and the first inverter (703) are simultaneously connected to the first logic determination unit (500). 0); the input end of the first AND gate (704) is simultaneously connected to the output end of the first inverter (703) and the output end Y of the second logic determination unit (600), and the output end is connected to the signal enable signal input end of the second frequency divider (702); the signal output end of the first 2-to-1 output gate (705) is simultaneously connected to the gates of the seventh transistor (706) and the eighth transistor (707); the source of the seventh transistor (706) is connected to Vdd1, and the drain is connected to the drain of the second transistor (707); the source of the eighth transistor (707) is grounded; the gates of the ninth transistor (708) and the tenth transistor (709) are simultaneously connected to the drain of the seventh transistor (706), the drains are simultaneously connected to the output signal OUT7, and the sources are respectively connected to Vdd2 and ground.

10. The wide voltage domain, low jitter clock distributor circuit according to claim 9, characterized in that: The power supply Vdd2 is 1.8V; the frequency dividers start to work when the enable signals of the first frequency divider (701) and the second frequency divider (702) are high level.

11. The wide voltage domain, low jitter clock distributor circuit according to claim 1, characterized in that: The first phase-locked loop unit (800) includes a first phase frequency detector (801), a first charge pump (802), a first filter (803), a first voltage-controlled oscillator (804), and a third frequency divider (805); the second phase-locked loop unit (900) includes a second phase frequency detector (901), a second charge pump (902), a second filter (903), a second voltage-controlled oscillator (904), a fourth frequency divider (905), and a fifth frequency divider (906); The signal input end of the first frequency detector (801) is simultaneously connected to the output end OUT7 signal of the frequency division path selection and voltage domain conversion unit (700) and the output end of the third frequency divider (805), the signal output end is connected to the signal input end of the first charge pump (802), the signal output end of the first charge pump (802) is connected to the signal input end of the first filter (803), the signal output end of the first filter (803) is connected to the signal input end of the first voltage-controlled oscillator (804), the signal output end of the first voltage-controlled oscillator (804) and the signal output end of the fourth frequency divider (905) are simultaneously connected to the signal input end of the second frequency detector (901); The signal output end of the frequency phase detector (901) is connected to the signal input end of the second charge pump (902), the signal output end of the second charge pump (902) is connected to the signal input end of the second filter (903), the signal output end of the second filter (903) is connected to the signal input end of the second voltage-controlled oscillator (904), the output end of the second voltage-controlled oscillator (904) is connected to the signal input end of the fourth frequency divider (905), the signal input end of the fourth frequency divider (905) is connected to the signal input end of the fifth frequency divider (906), and the signal output end of the fifth frequency divider (906) is connected to the input signal end of the third frequency divider (805) and the signal output end OUT8 of this unit.

12. The wide voltage domain, low jitter clock distributor circuit according to claim 11, characterized in that: All system modules of the first phase-locked loop unit (800) and the second phase-locked loop unit (900) are powered by 1.8V, and the 1.8V voltage is provided by the power supply voltage conversion circuit (1000).

13. The wide voltage domain, low jitter clock distributor circuit according to claim 1, characterized in that: The output logic voltage domain conversion unit (1100) includes a seventh inverter (1101), an eighth inverter (1102), a ninth inverter (1103), a tenth inverter (1109), an eleventh inverter (1110), an eleventh transistor (1105), a twelfth transistor (1106), a thirteenth transistor (1107), a fourteenth transistor (1108), a fifteenth transistor (1111), a sixteenth transistor (1112), a seventeenth transistor (1113), an eighteenth transistor (1114) and a third AND gate (1104); the seventh inverter (1101) The inverter inputs of the seventh inverter (1101) and the ninth inverter (1103) are connected to the output OUT8 of the second phase-locked loop unit (900); the output of the seventh inverter (1101) is connected to the signal input of the eighth inverter (1102); the output of the ninth inverter (1103) is connected to the two inputs of the third AND gate (1104); the output of the third AND gate (1104) and the output of the eighth inverter (1102) are connected to the gates of the twelfth transistor (1106) and the fourteenth transistor (1108) respectively; the twelfth transistor (1106) and the fourteenth transistor (1108) are connected to the gates of the twelfth transistor (1106) and the fourteenth transistor (1108). The sources of the eleventh transistor (1105) and the thirteenth transistor (1107) are simultaneously grounded; the sources of the eleventh transistor (1105) and the thirteenth transistor (1107) are simultaneously grounded; the gate of the eleventh transistor (1105) is simultaneously connected to the drains of the thirteenth transistor (1107) and the fourteenth transistor (1108); the gate of the thirteenth transistor (1107) is simultaneously connected to the drains of the eleventh transistor (1105) and the twelfth transistor (1106); the drains of the eleventh transistor (1105) and the thirteenth transistor (1107) are respectively connected to the drains of the tenth inverter (1109) and the eleventh inverter (1110). The gates of the fifteenth transistor (1111) and the sixteenth transistor (1112) are simultaneously connected to the output terminal of the tenth inverter (1109), the drains are connected together, and the sources are respectively connected to Vdd3 and the ground; the gates of the seventeenth transistor (1113) and the eighteenth transistor (1114) are simultaneously connected to the output terminal of the eleventh inverter (1110), the drains are connected together, and the sources are respectively connected to Vdd3 and the ground; the drain of the fifteenth transistor (1111) is connected to the output signal terminal OUT9, and the drain of the seventeenth transistor (1113) is connected to the output signal terminal OUT10.

14. The wide voltage domain, low jitter clock distributor circuit according to claim 13, characterized in that: The eleventh transistor (1105) and the thirteenth transistor (1107) are PMOS transistors, and the twelfth transistor (1106) and the fourteenth transistor (1108) are NMOS transistors; Vdd2 is powered by 1.8V, and the eleventh transistor (1105), the twelfth transistor (1106), the thirteenth transistor (1107), the fourteenth transistor (1108), the fifteenth transistor (1111), the sixteenth transistor (1112), the seventeenth transistor (1113) and the eighteenth transistor (1114) are designed as 3.3V transistors; the power supply voltage Vdd3 is 1.8V, 2.5V or 3.3V.

15. The wide voltage domain, low jitter clock distributor circuit according to claim 1, characterized in that: The LVDS output array (1200) is composed of 12 parallel output LVDS channel units; each LVDS channel unit includes nineteenth to twenty-fourth transistors (1201-1206), a first amplifier (1207), a second capacitor (1212), a fourth resistor (1208), a fifth resistor (1209), a sixth resistor (1210) and a seventh resistor (1211); the gates of the nineteenth transistor (1201) and the twentieth transistor (1202) are simultaneously connected to the output terminal OUT9 of the output logic voltage domain conversion unit (1100). The drains of the nineteenth transistor (1201) and the twentieth transistor (1202) are simultaneously connected to one end of the first resistor (1208) and the sixth resistor (1210), and the other ends of the fourth resistor (1208) and the sixth resistor (1210) are respectively connected to one end of the fifth resistor (1209) and the seventh resistor (1211); the other ends of the fifth resistor (1209) and the seventh resistor (1211) are simultaneously connected to the drains of the twenty-first transistor (1203) and the twenty-second transistor (1204); the nineteenth transistor (1201) and the twenty-first transistor (1202) are simultaneously connected to one end of the first resistor (1208) and the sixth resistor (1210), and the other ends of the fifth resistor (1209) and the seventh resistor (1211) are respectively connected to one end of the fifth resistor (1209) and the seventh resistor (1211). The source of the 20th transistor (1202) and the 22nd transistor (1204) is connected to the drain of the 24th transistor (1206), and the source of the 24th transistor (1206) is connected to the ground; the 1.25V voltage The inverting input terminal of the first amplifier (1207) and one end of the second capacitor (1212) are simultaneously connected, and the other end of the second capacitor (1212) is simultaneously connected to the output terminal of the first amplifier (1207) and the gate of the twenty-fourth transistor (1206); the non-inverting input terminal of the first amplifier (1207) is connected to the node where the fourth resistor (1208) and the fifth resistor (1209) are connected; the inverting output signal terminal OUTN is connected to the drain of the nineteenth transistor (1201), and the non-inverting output signal terminal OUTP is connected to the drain of the twenty-first transistor (1203).

16. The wide voltage domain, low jitter clock distributor circuit according to claim 15, characterized in that: The bias current of the twenty-third transistor (1205) is 7 mA, the resistance values of the fourth resistor (1208), the fifth resistor (1209), the sixth resistor (1210) and the seventh resistor (1211) are all 50 ohms; the power supply voltage Vdd3 is 1.8 V, 2.5 V or 3.3 V; the nineteenth to twenty-second transistors (1201-1204) are 3.3 V withstand voltage transistors.

Images