Decoding circuit, TDC circuit, data processing chip, optical system, decoding method

Abstract

A decoding circuit includes: a code bit generating unit, adapted to generate a set of logic codes based on a set of phase logic values, wherein every two phase logic values ​​correspond to one logic code, and the logic code corresponding to the two phase logic values ​​that meet predetermined requirements is different from other logic codes in the set of logic codes, and is used to mark a phase signal at a sudden edge in the set of phases; the two phase logic values ​​represent the phases of a pair of multi-phase clock signals at a sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals; and a decoding unit, adapted to obtain a first code based on the set of logic codes.

Description

Technical Field

[0001] The present invention relates to the field of electronics, and in particular to a decoding circuit, a TDC circuit, a data processing chip, an optical system, and a decoding method. Background Art

[0002] The time-to-digital converter (TDC), a device dedicated to time interval quantization, is currently the primary method for implementing time interval measurement. Analog TDCs primarily utilize capacitor charging and discharging to amplify time, representing it as a voltage signal; digital TDCs directly quantize the output in the digital domain using delay cells. Compared to analog TDC designs, digital TDCs based on programmable logic circuits and digital signal processing offer unparalleled advantages in design flexibility, stability, high integration, and low cost. With the advancement of integrated circuits, TDCs have increasingly become available on application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs).

[0003] Currently, TDC chips are mostly designed using CMOS technology. Their circuit architecture primarily utilizes internal CMOS gates to form various delay lines for digital TDC quantization, such as tapped delay chains, differential delay chains, multi-phase clock sampling, and pulse pinching. Multi-phase clock sampling transforms the direct counting method of a single reference clock into the equivalent quantization of fixed-interval time intervals using multiple fixed-phase clocks. In TDCs based on multi-phase sampling, a decoder is required to convert the sampled multi-phase information into quantized time information. However, existing TDCs often suffer from inaccurate quantization time. Summary of the Invention

[0004] The present invention solves the problem that multi-phase clock sampling easily leads to inaccurate quantization time.

[0005] To solve the above problems, the present invention provides a decoding circuit, comprising: a code bit generating unit, adapted to generate a set of logic codes based on a set of phase logic values, wherein every two phase logic values ​​correspond to one logic code, and the logic codes corresponding to the two phase logic values ​​that meet predetermined requirements are different from other logic codes in the set of logic codes, and are used to indicate the phase signal at a sudden edge in the set of phases; the two phase logic values ​​represent the phases of a pair of multi-phase clock signals at a sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals; and a decoding unit, adapted to obtain a first code based on the set of logic codes.

[0006] Optionally, the phase logic value is 0 or 1, the phase logic value 0 represents a phase of 0, and the phase logic value 1 represents a phase of π.

[0007] Optionally, when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the previous multi-phase clock signal is 1, and the phase logic value corresponding to the next multi-phase clock signal is 0; when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirement includes: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

[0008] Optionally, when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the previous multi-phase clock signal is 0, and the phase logic value corresponding to the next multi-phase clock signal is 1; when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirement includes: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

[0009] Optionally, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 1, and the other logic codes in the group of logic codes are 0; or, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 0, and the other logic codes in the group of logic codes are 1.

[0010] Optionally, the code bit generating unit includes: multiple groups of sub-generating units, each sub-generating unit includes: an inverter and a NAND gate; one input end of the NAND gate and the input end of the inverter are suitable for respectively inputting two phase logic values ​​corresponding to one bit of logic code, the output end of the inverter is connected to the other input end of the NAND gate, and the output end of the NAND gate is suitable for outputting the logic code.

[0011] Optionally, when the two phase logic values ​​corresponding to a one-bit logic code are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, one input end of the NAND gate is suitable for inputting the phase logic value corresponding to the previous multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the next multi-phase clock signal; when the two phase logic values ​​corresponding to a one-bit logic code are the phase logic values ​​corresponding to the last and first multi-phase clock signals, one input end of the NAND gate is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

[0012] Optionally, when the two phase logic values ​​corresponding to a one-bit logic code are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the previous multi-phase clock signal, and one input end of the NAND gate is suitable for inputting the phase logic value corresponding to the next multi-phase clock signal; when the two phase logic values ​​corresponding to a one-bit logic code are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and one input end of the NAND gate is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

[0013] Optionally, the decoding unit is adapted to arrange the set of logical codes in sequence to obtain a set of one-hot codes, obtain binary codes corresponding to the set of one-hot codes according to the set of one-hot codes, and use the binary codes as the first codes.

[0014] Optionally, the decoding unit includes: a one-hot decoder; an input end of the one-hot decoder is suitable for inputting the set of logical codes, and an output end of the one-hot decoder is suitable for outputting the first code.

[0015] The present invention also provides a TDC circuit, comprising: the above-mentioned decoding circuit, and a phase sampling circuit, suitable for sampling the phase of the multi-phase clock signal at the sampling moment to generate a set of phase logic values; a processing circuit, suitable for obtaining quantized fine time based on at least the first encoding.

[0016] Optionally, the TDC circuit also includes: a clock signal generating unit, suitable for generating the multi-phase clock signal; the clock signal generating unit includes: multiple delay units, the output ends of the multiple delay units are suitable for outputting the multi-phase clock signal; the output end of the previous delay unit is connected to the input end of the next delay unit, and the output end of the last delay unit is connected to the input end of the first delay unit.

[0017] Optionally, the TDC circuit further includes: a counting unit adapted to calculate and output the number of cycles of a multi-phase clock signal cycle before the sampling moment; and the processing circuit further adapted to obtain quantized coarse time based at least on the number of cycles.

[0018] Optionally, the processing circuit is adapted to obtain the quantized coarse time according to the period time of the multi-phase clock signal and the number of periods of the cycle.

[0019] Optionally, the counting unit includes: a first counter, suitable for calculating the number of cycles of a multi-phase clock signal cycle before the sampling moment; a second counter, suitable for calculating the number of cycles of another multi-phase clock signal cycle before the sampling moment; a selection unit, suitable for selecting a counter that is not in a jump state from the first counter and the second counter, and using the number of cycles calculated by the counter as the output of the counting unit.

[0020] Optionally, both the first counter and the second counter are in a jump state when a sudden edge of the multi-phase clock signal occurs; the selection unit includes: a judgment unit, suitable for determining which of the first counter or the second counter is not in a jump state according to the phase logic value.

[0021] Optionally, the judgment unit is further adapted to output a flag bit, wherein the flag bit indicates: which counter among the first counter and the second counter is used to calculate the number of cycles as the output of the counting unit.

[0022] Optionally, the processing circuit is adapted to obtain quantized fine time according to the delay difference between the multi-phase clock signals and the first encoding.

[0023] The present invention further provides a data processing chip, comprising: the above-mentioned TDC circuit, wherein the TDC circuit is suitable for cooperating with one or more photodetectors.

[0024] The present invention also provides an optical system, comprising: the above-mentioned TDC circuit, a front-end circuit and at least one photoelectric conversion unit, wherein the photoelectric conversion unit is suitable for generating a first pulse in response to a laser pulse; the front-end circuit is suitable for generating a trigger signal based on the pulse signal, wherein the trigger signal includes a trigger pulse, and the sudden edge of the trigger pulse corresponds to the sudden edge of the first pulse; the moment when the sudden edge of the trigger signal occurs corresponds to the sampling moment of the multi-phase clock signal.

[0025] The present invention also provides a decoding method, comprising: generating a set of logic codes based on a set of phase logic values, wherein every two phase logic values ​​correspond to one logic code, and the logic code corresponding to the two phase logic values ​​that meet predetermined requirements is different from other logic codes in the set of logic codes, and is used to indicate the phase signal at a sudden edge in the set of phases; the two phase logic values ​​represent the phase of a pair of multi-phase clock signals at a sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals; and obtaining a first code based on the set of logic codes.

[0026] Optionally, the phase logic value is 0 or 1, the phase logic value 0 represents a phase of 0, and the phase logic value 1 represents a phase of π.

[0027] Optionally, when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the previous multi-phase clock signal is 1, and the phase logic value corresponding to the next multi-phase clock signal is 0; when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirement includes: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

[0028] Optionally, when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the previous multi-phase clock signal is 0, and the phase logic value corresponding to the next multi-phase clock signal is 1; when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirement includes: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

[0029] Optionally, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 1, and the other logic codes in the group of logic codes are 0; or, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 0, and the other logic codes in the group of logic codes are 1.

[0030] Optionally, obtaining the first code according to the set of logical codes includes: arranging the set of logical codes in order to obtain a set of one-hot codes, obtaining binary codes corresponding to the set of one-hot codes according to the set of one-hot codes, and using the binary codes as the first code.

[0031] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0032] A decoding circuit generates a set of logic codes based on a set of phase logic values. Two phase logic values ​​that meet predetermined requirements generate a specific logic code different from other logic codes, which can indicate which phase signal is at a rising edge or a falling edge. A first code is generated based on the above logic code, thereby knowing the position of the sampling moment in the delay, and then obtaining a more accurately quantized fine time. The quantized fine time has a quantization result deviation of at most one least significant bit (LSB) and is not affected by the duty cycle, thereby reducing the complexity of the design. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 1 is a schematic diagram of the TDC circuit structure according to an embodiment of the present invention;

[0034] Figure 2 1 is a schematic diagram of waveforms of signals related to a TDC circuit in one embodiment of the present invention;

[0035] Figure 3 1 is a schematic structural diagram of a voltage-controlled oscillator according to an embodiment of the present invention;

[0036] Figure 4 1 is a waveform diagram of a multi-phase clock signal according to an embodiment of the present invention;

[0037] Figure 5 1 is a schematic diagram of the structure of a decoding circuit according to an embodiment of the present invention;

[0038] Figure 6 is a schematic structural diagram of a decoding circuit according to another embodiment of the present invention;

[0039] Figure 7 This is a schematic diagram of the connection between the photoelectric detection unit and the data processing chip of the present invention;

[0040] Figure 8 It is a schematic structural diagram of the optical system of the present invention. DETAILED DESCRIPTION

[0041] To find the cause of the inaccurate quantization time, the inventors conducted further research on digital TDCs based on multi-phase clock sampling:

[0042] Take the example of using a single photon avalanche diode (SPAD) as a detector in a laser ranging system and using a digital TDC based on multi-phase clock sampling for time quantization. In laser ranging applications, the solution of using a single SPAD device as a pixel will bring obvious noise interference, making it difficult to distinguish noise factors such as dark counts and ambient light from effective signals, and the application effect will be relatively poor. Therefore, multiple SPAD devices are usually used as a pixel, that is, multiple SPADs are connected in parallel to a TDC to obtain trigger information. Through certain conditional judgments, noise filtering can be achieved, effective signals can be obtained more accurately, and the dynamic range can be improved. At the same time, multiple pixels are arranged in a certain array to form a planar array SPAD detector, which can increase the detector's photosensitive surface to increase the detectable field of view.

[0043] Combine Figure 1 and Figure 2, taking a macro pixel composed of four SPADs as an example. After the SPAD is triggered to avalanche, a high-level pulse is generated. The front-end circuit (detection front-end) 11 generates a trigger signal TRG based on the high-level pulse generated after the SPAD is triggered to avalanche. Each pulse in the trigger signal TRG has a width of approximately 1nS. It is understandable that if multiple SPADs are triggered within the duration of one pulse of the trigger signal TRG, the trigger signal TRG will only generate one pulse.

[0044] For example, the front-end circuit 11 generates the first pulse of the trigger signal TRG based on the first pulse of the SPAD1 signal generated after the first SPAD avalanche, generates the second pulse of the trigger signal TRG based on the first pulse of the SPAD2 signal generated after the second SPAD avalanche, and generates the third pulse of the trigger signal TRG based on the first pulse of the SPAD3 signal generated after the third SPAD avalanche. Because the rising edge of the first pulse of SPAD4 generated after the fourth SPAD avalanche occurs within the duration of the third pulse of the trigger signal TRG and is very short from the rising edge of the first pulse of SPAD3, no additional pulse is generated.

[0045] The front-end circuit 11 also outputs a photon count signal photon count. The photon count signal photon count indicates how many SPADs are triggered within the duration of one pulse of the trigger signal TRG. Figure 2 In the figure, Cnt=1 indicates that one SPAD is triggered, and Cnt=2 indicates that two SPADs are triggered.

[0046] The rising edge of the trigger signal TRG can trigger the phase sampler 12 to sample the phases of the multi-phase clock signals ph and phb generated by the voltage-controlled oscillator (VCO) 18, and at the same time, trigger the count samplers 13 and the count samplers 14 to sample the outputs of the first counter counter and the second counter counter_b.

[0047] like Figure 3As shown, the voltage-controlled oscillator 18 can be a ring oscillator, providing multiple phases for the TDC. A ring oscillator with an n-level differential structure can output 2n phases. Taking a five-level differential structure as an example, the voltage-controlled oscillator 18 includes five delay units. The first delay unit outputs a first multi-phase clock signal ph0, which is input to the second delay unit. After delaying by the second delay unit, the second multi-phase clock signal ph1 is output to the third delay unit. After delaying by the third delay unit, the third multi-phase clock signal ph2 is output to the fourth delay unit. After delaying by the fourth delay unit, the fourth multi-phase clock signal ph3 is output to the fifth delay unit. After delaying by the fifth delay unit, the fifth multi-phase clock signal ph4 is output to the first delay unit.

[0048] The first delay unit delays the fifth multi-phase clock signal ph4 to output a sixth multi-phase clock signal phb0 to the second delay unit. After being delayed by the second delay unit, the sixth multi-phase clock signal phb1 is output to the third delay unit. After being delayed by the third delay unit, the eighth multi-phase clock signal phb2 is output to the fourth delay unit. After being delayed by the fourth delay unit, the ninth multi-phase clock signal phb3 is output to the fifth delay unit. After being delayed by the fifth delay unit, the tenth multi-phase clock signal phb4 is output to the first delay unit. The first delay unit delays the tenth multi-phase clock signal phb4 to output the first multi-phase clock signal ph0.

[0049] From the above working process, it can be seen that the first multi-phase clock signal ph0 returns to the first delay unit after 10 delays along the oscillator loop, completing a cycle. The number of delays of the multi-phase clock signal in one cycle is related to the number of delay units in the oscillator. By detecting the 10 multi-phase clock signals output by the 5 delay units along the oscillator loop, we can obtain Figure 4 The signal waveform is shown.

[0050] The first counter, counter, receives the first multi-phase clock signal ph0. During each period T, the first multi-phase clock signal ph0 triggers the first counter to jump once. The counter sampler 13 samples the position of the first counter counter on the rising edge of the trigger signal TRG to obtain a first coarse time. For example, if the first multi-phase clock signal ph0 passes through five periods, triggering the first counter counter to jump five times, the first coarse time is 5*T.

[0051] If the sampling moment falls on the transition edge of the first counter, it may be impossible to determine the position of the counter. This situation is called metastable, and sampling errors may occur. To this end, a second counter, counter_b, can be set at a predetermined interval from the first counter. In this embodiment, the sixth multi-phase clock signal phb0 is input into the second counter, counter_b. During each cycle T, the sixth multi-phase clock signal phb0 triggers the second counter to transition once. The counter sampler 14 samples the position of the second counter on the rising edge of the trigger signal TRG to obtain the second rough time. This ensures that the first and second counters, counter_b, will not be in the transition state at the same time.

[0052] The phase sampler 12 samples the phases of the 10 multi-phase clock signals, and the logic circuit 15 outputs a selection signal sel according to the phase sampling results of the 10 multi-phase clock signals. The selection signal sel can indicate which of the first counter counter and the second counter counter_b is not in the jump state.

[0053] Based on the selection signal sel, selector 16 selects one of the first and second coarse times as the final coarse time (i.e., the high bit of the quantized time). Simultaneously, logic circuit 15 outputs a flag bit res, which indicates which of the first counter counter and the second counter counter_b outputs is used as the final coarse time. This prevents errors in the coarse time calculation caused by metastability.

[0054] For the first multi-phase clock signal ph0 through the tenth multi-phase clock signal phb4, there is a delay difference ΔT. This means that the first multi-phase clock signal ph0 is transmitted sequentially at intervals of delay difference ΔT. Based on the position of the waveform at the sampling moment, the time with a resolution of delay difference ΔT can be determined, which is called fine time.

[0055] Figure 4 The two dashed lines in the figure represent the sampling of the multi-phase clock signal phases at time T0 and time T0+ΔT, respectively. After a delay of ΔT from time T0, the second multi-phase clock signal ph1 changes from a phase of 0 to a phase of π (a low level to a high level), and the seventh multi-phase clock signal phb1 changes from a phase of π to a phase of 0 (a high level to a low level).

[0056] Phase sampler 12 samples the phases of ten multi-phase clock signals ten times at intervals of delay ΔT to obtain phase logic values. These values ​​are then fed into decoder 17, resulting in the codes shown in Table 1. The entries ph0-phb4 in the table correspond to phase logic values, each representing the phase of a multi-phase clock signal at the sampling moment. A phase logic value of 0 indicates a phase of 0, while a phase logic value of 1 indicates a phase of π. Based on these phase logic values, the codes and binary codes shown in Table 1 are derived.

[0057] Table 1

[0058] ph0 ph1 ph2 ph3 ph4 phb0 phb1 phb2 phb3 phb4 code binary 1 0 0 0 0 0 1 1 1 1 0 0000 1 1 0 0 0 0 0 1 1 1 1 0001 1 1 1 0 0 0 0 0 1 1 2 0010 1 1 1 1 0 0 0 0 0 1 3 0011 1 1 1 1 1 0 0 0 0 0 4 0100 0 1 1 1 1 1 0 0 0 0 5 0101 0 0 1 1 1 1 1 0 0 0 6 0110 0 0 0 1 1 1 1 1 0 0 7 0111 0 0 0 0 1 1 1 1 1 0 8 1000 0 0 0 0 0 1 1 1 1 1 9 1001

[0059] As shown in Table 1, the phases of the first multi-phase clock signal ph0 through the tenth multi-phase clock signal phb4 determine the sampling instant's position within the 10 delays, representing the fine quantized time (i.e., the least significant bit of the quantized time). This yields a fine time accuracy of ΔT, reducing the coarse quantized time of counter or counter_b to one-tenth of a period. For example, if the decoder output is 0010, this indicates that 2*ΔT has elapsed.

[0060] As an asynchronous sampling TDC, when sampling a multi-phase clock signal, if it is jumping, the sampling time falls on its transition edge ( Figure 4 If the phase sampler 12 outputs a phase signal with a rising edge or a falling edge, metastable sampling may occur, and the phase logic value output by the phase sampler 12 may be inaccurate.

[0061] Depend on Figure 4 It can be seen that each quantization time jump corresponds to a level jump in two phases. For example, at time T0, from the first multi-phase clock signal ph0 to the tenth multi-phase clock signal phb4, the first multi-phase clock signal ph0 is on a rising edge, and the sixth multi-phase clock signal phb0 is on a falling edge. In other words, the first multi-phase clock signal ph0 and the sixth multi-phase clock signal phb0 are both in a jump state. In this case, the first multi-phase clock signal ph0 and the sixth multi-phase clock signal phb0 may both be misidentified, resulting in incorrect phase logic values ​​corresponding to ph0 and phb0.

[0062] When the decoder 17 generates a decoding result based on the 10 phase logic values ​​ph0 to phb4, since there are 2 wrong phase logic values ​​among the 10 phase logic values, a quantization result will have an error of 2 LSBs.

[0063] In order to reduce the quantization error and control the quantization error within 1 LSB, the inventors of this application provide a new decoding circuit. In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0064] It is worth noting that when this embodiment involves the content that has been described in detail above, it will be directly quoted without further details, and the content of the same part belongs to the scope covered by the embodiment of this application.

[0065] The inventors of this application carefully studied the phase logic values ​​and waveforms of multi-phase clock signals and found that, within a refined time (ΔT time), when the phase logic value corresponding to a multi-phase clock signal is 1, and the phase logic value of the subsequent multi-phase clock signal is 0, it can be determined that the multi-phase clock signal has a rising edge flip.

[0066] Please refer to Table 2. When the phase logic value corresponding to a multi-phase clock signal is 1, and the phase logic value of the subsequent multi-phase clock signal is 0, a phase logic value combination of [1 0] will appear in the table. Based on the phase logic value combination of [1 0], it can be determined which multi-phase clock signal has a rising edge flip. In the result of a phase sampling, the phase logic value combination of [1 0] will only appear once, and it will not be affected by the phase logic value combination of [0 1] caused by the falling edge.

[0067] Table 2

[0068]

[0069] Based on the above analysis, the decoding circuit proposed by the inventors of this application includes: a code bit generating unit and a decoding unit.

[0070] The code bit generation unit can generate a set of logic codes based on a set of phase logic values, wherein every two phase logic values ​​correspond to one logic code, and the logic code corresponding to the two phase logic values ​​that meet predetermined requirements is different from other logic codes in the set of logic codes; the two phase logic values ​​represent the phases of a pair of multi-phase clock signals at a sampling time; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals. The decoding unit can obtain a first code based on the set of logic codes.

[0071] The set of phase logic values ​​is obtained by phase sampling a multi-phase clock signal within a cycle. The multi-phase clock signal is a clock signal generated by a ring oscillator composed of multiple delay units. The phase logic value is 0 or 1, where a phase logic value of 0 indicates a phase of 0, and a phase logic value of 1 indicates a phase of π.

[0072] Taking the multi-phase clock signal including the first multi-phase clock signal ph0 to the tenth multi-phase clock signal phb4 as an example, the pair of multi-phase clock signals includes: the first multi-phase clock signal ph0 and the second multi-phase clock signal ph1, the second multi-phase clock signal ph1 and the third multi-phase clock signal ph2, the third multi-phase clock signal ph2 and the fourth multi-phase clock signal ph3, ..., the ninth multi-phase clock signal phb3 and the tenth multi-phase clock signal phb4, and the tenth multi-phase clock signal phb4 (the last multi-phase clock signal) and the first multi-phase clock signal ph0.

[0073] The phases of the first multi-phase clock ph0 to the tenth multi-phase clock signal phb4 are sampled 10 times at intervals of the delay difference ΔT, and the phase logic values ​​corresponding to ph0-phb4 in Table 3 can be obtained.

[0074] Table 3

[0075]

[0076] The code bit generating unit generates a logic code according to the phase logic value corresponding to the one-to-multi-phase clock signal, and a group of phase logic values ​​corresponds to a group of logic codes. The decoding unit generates a first code according to the group of logic codes.

[0077] The first encoding may be a one-hot code, and the decoding unit sequentially arranges the set of logic codes to obtain a set of one-hot codes, which is shown in the one-hot code item in Table 3. The number of multi-phase clock signals is the same as the number of bits of the one-hot code, and the multi-phase clock signals correspond one-to-one to the logic codes in the first encoding, and each multi-phase clock signal corresponds to one bit of the logic code in the one-hot code.

[0078] When the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirements are: the phase logic value corresponding to the previous multi-phase clock signal is 1, and the phase logic value corresponding to the next multi-phase clock signal is 0.

[0079] For example, in the first row of Table 3, ph0 is 1 and ph1 is 0, indicating that the phase logic value corresponding to the first multi-phase clock signal ph0 is 1, and the phase logic value corresponding to the second multi-phase clock signal ph1 is 0. Therefore, the code bit generation unit generates a first logic code of 1 based on ph0 and ph1, while the logic codes of the other bits are 0. The one-hot code generated by the decoding unit based on these logic codes is 1000000000. Of course, in other implementations, the logic codes corresponding to the two phase logic values ​​that meet predetermined requirements may be set to 0, and the other logic codes may be set to 1.

[0080] When the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirements are: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

[0081] For example, in the last row of Table 3, phb4 is 1 and ph0 is 0, indicating that the phase logic value corresponding to the last multi-phase clock signal phb4 is 1, and the phase logic value corresponding to the first multi-phase clock signal ph0 is 0. Therefore, the code bit generation unit generates a last bit logic code of 1 based on phb4 and ph0, while the logic codes of the other bits are 0. The one-hot code generated by the decoding unit based on these logic codes is 0000000001.

[0082] The decoding unit may include: a one-hot decoder; an input end of the one-hot decoder is adapted to input the set of logic codes, and an output end of the one-hot decoder is adapted to output the first code.

[0083] Combined with the above analysis, the code bit generation unit of this embodiment finds the phase logic value that meets the phase logic value

[10] combination through logical judgment, and generates a set of one-hot codes based on the phase logic value that meets this combination. The position of 1 in the one-hot code can represent which multi-phase clock signal is undergoing a rising edge flip, thereby knowing which multi-phase clock signal is sampled, that is, the position of the sampling moment in the delay, and thus obtaining the quantized fine time. For example, when the logic code generated by the code bit generation unit is 0100000000, it indicates that the second multi-phase clock signal is undergoing a rising edge flip, so the refined time is 2*ΔT. The sampling position is identified based on the rising edge and is not affected by the falling edge. Therefore, the quantization result deviation of the quantization time obtained thereby is at most 1 LSB, and is not affected by the clock signal duty cycle, thereby reducing the complexity of the design.

[0084] Optionally, the first code may also be a binary code, and the decoding unit obtains a corresponding binary code based on a set of one-hot codes, and uses the binary code as the first code.

[0085] Figure 5 Schematic diagram of the decoding circuit structure of an embodiment of the present invention, as Figure 1 Decoder 17 in.

[0086] like Figure 5 As shown, the code bit generating unit of this embodiment may include: multiple groups of sub-generating units, and the sub-generating units include: inverters and NAND gates.

[0087] The first input terminal of the NAND gate and the input terminal of the inverter are suitable for respectively inputting two phase logic values ​​corresponding to one bit of logic code, the output terminal of the inverter is connected to the second input terminal of the NAND gate, and the output terminal of the NAND gate is suitable for outputting the logic code.

[0088] When the two phase logic values ​​corresponding to one bit of logic code are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the first input end of the NAND gate is suitable for inputting the phase logic value corresponding to the previous multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the next multi-phase clock signal.

[0089] For example, the first input terminal of the NAND gate in the first sub-generation unit inputs the first multi-phase clock signal ph0, and the input terminal of the inverter inputs the second multi-phase clock signal ph1; the first input terminal of the NAND gate in the second sub-generation unit inputs the second multi-phase clock signal ph1, and the input terminal of the inverter inputs the third multi-phase clock signal ph2; the first input terminal of the NAND gate in the third sub-generation unit inputs the third multi-phase clock signal ph2, and the input terminal of the inverter inputs the fourth multi-phase clock signal ph3; the first input terminal of the NAND gate in the fourth sub-generation unit inputs the fourth multi-phase clock signal ph3, and the input terminal of the inverter inputs the fifth multi-phase clock signal ph4; the first input terminal of the NAND gate in the fifth sub-generation unit inputs the fifth multi-phase clock signal ph5. h4, the sixth multi-phase clock signal phb0 is input to the input end of the inverter; the sixth multi-phase clock signal phb0 is input to the first input end of the NAND gate in the sixth sub-generation unit, and the seventh multi-phase clock signal phb1 is input to the input end of the inverter; the seventh multi-phase clock signal phb1 is input to the first input end of the NAND gate in the seventh sub-generation unit, and the eighth multi-phase clock signal phb2 is input to the input end of the inverter; the eighth multi-phase clock signal phb2 is input to the first input end of the NAND gate in the eighth sub-generation unit, and the ninth multi-phase clock signal phb3 is input to the input end of the inverter; the ninth multi-phase clock signal phb3 is input to the first input end of the NAND gate in the ninth sub-generation unit, and the tenth multi-phase clock signal phb4 is input to the input end of the inverter.

[0090] When the two phase logic values ​​corresponding to one bit of logic code are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the first input end of the NAND gate is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

[0091] For example, the first input terminal of the NAND gate in the tenth sub-generation unit is input with the tenth multi-phase clock signal ph4, and the input terminal of the inverter is input with the first multi-phase clock signal ph0.

[0092] from Figure 5 As can be seen from the circuit structure, the NAND gate outputs a low level (logical value 0) only when the first input of the NAND gate is inputted with a high level (logical value 1) and the input of the inverter is inputted with a low level (logical value 0). In all other cases, the NAND gate outputs a high level (logical value 1). The decoding unit can include an inverter to invert the output value of the NAND gate and then arrange them in sequence to obtain a set of one-hot codes.

[0093] Refer to Table 4. When the phase logic value corresponding to a multi-phase clock signal is 0, and the phase logic value of the subsequent multi-phase clock signal is 1, a phase logic value combination of [0 1] appears in the table. Based on the phase logic value combination of [0 1], it can be determined which multi-phase clock signal has a falling edge flip. In the result of a phase sampling, the phase logic value combination of [0 1] appears only once and is not affected by the phase logic value combination of [1 0] caused by the rising edge.

[0094] Table 4

[0095]

[0096]

[0097] Based on the above analysis, this embodiment can also perform decoding based on falling edges. Specifically, when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is that the phase logic value corresponding to the first multi-phase clock signal is 0, and the phase logic value corresponding to the second multi-phase clock signal is 1.

[0098] For example, in the first row of Table 4, phb0 is 0 and phb1 is 1, indicating that the phase logic value corresponding to the sixth multi-phase clock signal phb0 is 0, and the phase logic value corresponding to the seventh multi-phase clock signal phb1 is 1. Therefore, the code bit generation unit generates a logic code of 1 for the sixth bit based on phb0 and phb1, while the logic codes for the other bits are 0. The one-hot code generated by the decoding unit based on these logic codes is 0000010000. Of course, in other implementations, the logic codes corresponding to the two phase logic values ​​that meet predetermined requirements may be set to 0, and the other logic codes may be set to 1.

[0099] When the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirements are: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

[0100] For example, in the last row of Table 4, ph4 is 0 and phb0 is 1, indicating that the phase logic value corresponding to the last multi-phase clock signal ph4 is 0, and the phase logic value corresponding to the first multi-phase clock signal phb0 is 1. Therefore, the code bit generation unit generates a logic code of 1 for the fifth bit based on ph4 and phb0, while the logic codes for the other bits are 0. The one-hot code generated by the decoding unit based on these logic codes is 0000100000.

[0101] The code bit generation unit uses logical judgment to find the phase logic value that matches the phase logic value combination of [0 1], and generates a set of one-hot codes based on the phase logic value that matches this combination. The position of 1 in the one-hot code can indicate which multi-phase clock signal is undergoing a falling edge flip. From this, it is possible to know which multi-phase clock signal is sampled, that is, the position of the sampling moment in the delay, and thus obtain the quantized fine time. For example, when the logic code generated by the code bit generation unit is 0000001000, it indicates that the second multi-phase clock signal is undergoing a rising edge flip, so the refined time is 2*ΔT. The sampling position is identified based on the falling edge and is not affected by the rising edge. Therefore, the quantization result deviation obtained thereby is at most 1 LSB and is not affected by the duty cycle, reducing the complexity of the design.

[0102] Figure 6 Schematic diagram of the decoding circuit structure of another embodiment of the present invention, as Figure 1 Decoder 17 in.

[0103] like Figure 6 As shown, in the code bit generating unit, when the two phase logic values ​​corresponding to one bit of logic code are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the previous multi-phase clock signal, and the second input end of the NAND gate is suitable for inputting the phase logic value corresponding to the next multi-phase clock signal.

[0104] For example, the first multi-phase clock signal ph0 is input to the input end of the inverter, and the second input end of the NAND gate in the first sub-generation unit is input to the second multi-phase clock signal ph1; the second multi-phase clock signal ph1 is input to the input end of the inverter, and the third multi-phase clock signal ph2 is input to the second input end of the NAND gate in the second sub-generation unit; the third multi-phase clock signal ph2 is input to the input end of the inverter, and the fourth multi-phase clock signal ph3 is input to the second input end of the NAND gate in the third sub-generation unit; the fourth multi-phase clock signal ph3 is input to the input end of the inverter, and the fifth multi-phase clock signal ph4 is input to the second input end of the NAND gate in the fourth sub-generation unit; the fifth multi-phase clock signal ph4 is input to the input end of the inverter, and the fifth multi-phase clock signal ph4 is input to the input end of the NAND gate in the fifth sub-generation unit. The sixth multi-phase clock signal phb0 is input to the second input terminal of the NAND gate of the sixth sub-generation unit; the sixth multi-phase clock signal phb0 is input to the input terminal of the inverter, and the seventh multi-phase clock signal phb1 is input to the second input terminal of the NAND gate of the sixth sub-generation unit; the seventh multi-phase clock signal phb1 is input to the input terminal of the inverter, and the eighth multi-phase clock signal phb2 is input to the second input terminal of the NAND gate of the seventh sub-generation unit; the eighth multi-phase clock signal phb2 is input to the input terminal of the inverter, and the ninth multi-phase clock signal phb3 is input to the second input terminal of the NAND gate of the eighth sub-generation unit; the ninth multi-phase clock signal phb3 is input to the input terminal of the inverter, and the tenth multi-phase clock signal phb4 is input to the second input terminal of the NAND gate of the ninth sub-generation unit.

[0105] When the two phase logic values ​​corresponding to one bit of logic code are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the second input end of the NAND gate is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

[0106] For example, the input terminal of the inverter inputs the tenth multi-phase clock signal ph4, and the second input terminal of the NAND gate in the tenth sub-generation unit inputs the first multi-phase clock signal ph0.

[0107] from Figure 6 As can be seen from the circuit structure, the NAND gate outputs a low level (logical value 0) only when the inverter input is low (logical value 0) and the second input of the NAND gate is high (logical value 1). In all other cases, the NAND gate outputs a high level (logical value 1). The decoding unit can include an inverter to invert the NAND gate output value and then arrange it in sequence to obtain a set of one-hot codes.

[0108] Continue to refer Figure 1The present invention also provides a TDC circuit, comprising the decoding circuit of the above embodiment, as well as a phase sampling circuit and a processing circuit (not shown in the figure).

[0109] The phase sampling circuit is adapted to sample the phase of the multi-phase clock signal at a sampling instant to generate a set of phase logic values. The processing circuit is adapted to obtain a quantized fine time based on at least the first encoding. The phase sampling circuit can be implemented by a phase sampler 12.

[0110] Specifically, the processing circuit obtains a quantized fine time based on the delay difference between the multi-phase clock signals and the first code. As explained above, the first code determines which multi-phase clock signal is experiencing a rising or falling edge transition, thereby obtaining the quantized fine time. For example, based on the first code 0000001000, the processing circuit obtains a quantized fine time of 2*ΔT.

[0111] The TDC circuit of this embodiment further includes a clock signal generating unit adapted to generate the multi-phase clock signal. The clock signal generating unit includes a plurality of delay units, each of whose outputs is adapted to output the multi-phase clock signal; the output of each delay unit is connected to the input of the next delay unit, and the output of the last delay unit is connected to the input of the first delay unit. The clock signal generating unit may be implemented by a voltage-controlled oscillator 18.

[0112] The TDC circuit further includes a counting unit configured to count and output the number of cycles of a multi-phase clock signal before the sampling instant. The processing circuit is further configured to obtain a quantized coarse time based at least on the number of cycles. Specifically, the processing circuit obtains the quantized coarse time based on the cycle time of the multi-phase clock signal and the number of cycles of the cycle.

[0113] The counting unit may include a first counter, a second counter, and a selection unit. The first counter is configured to count the number of cycles of one multi-phase clock signal before the sampling moment. The second counter is configured to count the number of cycles of another multi-phase clock signal before the sampling moment. The selection unit is configured to select a counter that is not in a jump state between the first counter and the second counter, and use the number of cycles counted by the counter as the output of the counting unit.

[0114] The first counter and the second counter are both in a jump state when a sudden edge of the multi-phase clock signal occurs. The selection unit includes a judgment unit adapted to determine, based on the phase logic value, which of the first counter and the second counter is not in the jump state. The judgment unit is further adapted to output a flag bit indicating which of the first counter and the second counter is to be used to calculate the number of cycles as the output of the counting unit.

[0115] The first counter can be implemented by a first counter counter and a counter sampler 13, and the second counter can be implemented by a second counter counter_b and a counter sampler 14. The judgment unit can be implemented by a logic circuit 15. The function of selecting the output value in the selection unit is implemented by a selector 16. For the method of calculating the number of cycles and the method of calculating the quantized coarse time, please refer to the above description.

[0116] In the design of high-throughput TDC circuits, the delay of the decoding circuit becomes one of the important factors limiting the TDC throughput. Combined with the above description, it can be seen that the decoding circuit provided by the embodiment of the present invention is a simple and parallel topology structure. Compared with the existing technology that increases the complexity of the design and decoding logic, it greatly reduces the delay of the decoding circuit and can effectively improve the throughput of the TDC.

[0117] like Figure 7 As shown, an embodiment of the present invention further provides a data processing chip, comprising the TDC circuit of the above embodiment, wherein the TDC circuit is suitable for cooperating with one or more photodetectors.

[0118] The photodetector may include a SPAD array. The SPAD array includes multiple rows and multiple columns, each row and each column is provided with multiple photoelectric conversion units, and each photoelectric conversion unit includes one or more SPADs. When a photoelectric conversion unit includes multiple SPADs, the multiple SPADs can be connected to the same TDC circuit and used as a pixel. In the application of tof measurement, the signal readout circuit includes a TDC, and the TDC outputs the SPAD trigger time and the number of SPADs triggered simultaneously in the same time to the synchronization circuit for generating a histogram and subsequent ToF time determination.

[0119] For example, each photodetection unit 1000 includes four SPADs, namely, SPAD 1001A, SPAD 1001B, SPAD 1001C, and SPAD 1001D. Output terminals of all the SPADs are coupled to the same TDC.

[0120] like Figure 8As shown, an embodiment of the present invention further provides an optical system 110 including: a light emitting module 111, a light detection module 112, and a control module 113. The light emitting module 111 refers to the portion of the optical detection system used for laser emission (which may include circuits, devices, structures, etc.); the light detection module 112 refers to the portion of the optical detection system used for detecting the laser echo signal (which may include circuits, devices, structures, etc.).

[0121] The light emitting module 111 includes a light emitting array 1111, such as a vertical-cavity surface-emitting laser (VCSEL) array. The light emitting array 1111 includes multiple rows and multiple columns. Each row and column is provided with multiple light emitting units 11111, each light emitting unit 11111 including at least one light emitter. The light emitting array 1111 is also configured with a corresponding emission array driver circuit, coupled to each light emitter, for driving the light emitter to operate.

[0122] The light detection module 112 includes a photoelectric detection array 1121. The photoelectric detection array 1121 can be, for example, Figure 7 The photodetection array 1121 is configured to receive the optical echo signal after the detection beam reaches the target object 114. In addition, the optical detection module 112 may further include a signal readout circuit (not shown) for reading out the signal generated by the photodetection array 1121 and transmitting it to the control module 113.

[0123] In the optical detection system, an emitting lens group 1114 may be provided, located on the outgoing light path of the light emitting array 1111; in the optical detection system, a receiving lens group 1122 may be provided, and the photoelectric detection array 1121 may be located on the focal plane of the receiving lens group 1122.

[0124] The control module 113 is coupled to the light emitting array 1111 and the photodetection array 1121 ; it controls the light emitting array to emit detection beams in a certain order and power, and the corresponding photodetection array receives echo signals.

[0125] The optical detection module 112 further includes a data processing chip 1123 and a front-end circuit (not shown). The data processing chip 1123 includes the TDC circuit of the above embodiment. The data processing chip of the embodiment of the present invention can be Figure 7 The data processing chip shown. The front-end circuit is adapted to generate a trigger signal based on the pulse signal, wherein the trigger signal includes a trigger pulse, the sudden edge of the trigger pulse corresponds to the sudden edge of the first pulse. The sudden edge of the trigger signal occurs at a time corresponding to the sampling time of the multi-phase clock signal.

[0126] An embodiment of the present invention also provides a decoding method, comprising: generating a set of logic codes based on a set of phase logic values, wherein every two phase logic values ​​correspond to one logic code, and the logic code corresponding to the two phase logic values ​​that meet predetermined requirements is different from other logic codes in the set of logic codes, and is used to indicate a phase signal at a sudden edge in the set of phases; the two phase logic values ​​represent the phase of a pair of multi-phase clock signals at a sampling moment; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals; and obtaining a first code based on the set of logic codes.

[0127] Optionally, the phase logic value is 0 or 1, the phase logic value 0 represents a phase of 0, and the phase logic value 1 represents a phase of π.

[0128] Optionally, when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the previous multi-phase clock signal is 1, and the phase logic value corresponding to the next multi-phase clock signal is 0; when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirement includes: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

[0129] Optionally, when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is: the phase logic value corresponding to the previous multi-phase clock signal is 0, and the phase logic value corresponding to the next multi-phase clock signal is 1; when the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirement includes: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

[0130] Optionally, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 1, and the other logic codes in the group of logic codes are 0; or, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 0, and the other logic codes in the group of logic codes are 1.

[0131] Optionally, obtaining the first code according to the set of logical codes includes: arranging the set of logical codes in order to obtain a set of one-hot codes, obtaining binary codes corresponding to the set of one-hot codes according to the set of one-hot codes, and using the binary codes as the first code.

[0132] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A decoding circuit, characterized in that: include: A code bit generating unit is adapted to generate a set of logic codes according to a set of phase logic values, Wherein, every two phase logic values ​​correspond to one logic code, and the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is different from other logic codes in the set of logic codes, and is used to mark the phase signal at the sudden edge in the set of phases; the two phase logic values ​​represent the phases of a pair of multi-phase clock signals at the sampling time; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals; a decoding unit, adapted to obtain a first code according to the set of logical codes; The decoding unit is adapted to sequentially arrange the set of logical codes to obtain a set of one-hot codes, obtain binary codes corresponding to the set of one-hot codes according to the set of one-hot codes, and use the binary codes as the first encoding.

2. The decoding circuit according to claim 1, wherein: The phase logic value is 0 or 1, where the phase logic value 0 represents a phase of 0, and the phase logic value 1 represents a phase of π.

3. The decoding circuit according to claim 2, wherein: When the two phase logic values ​​that meet the predetermined requirement are phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is that the phase logic value corresponding to the previous multi-phase clock signal is 1, and the phase logic value corresponding to the next multi-phase clock signal is 0; When the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirements include: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

4. The decoding circuit according to claim 2, wherein: When the two phase logic values ​​that meet the predetermined requirement are phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is that the phase logic value corresponding to the previous multi-phase clock signal is 0, and the phase logic value corresponding to the next multi-phase clock signal is 1; When the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirements include: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

5. The decoding circuit according to any one of claims 1 to 4, characterized in that: The logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 1, and the other logic codes in the set of logic codes are 0; or, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 0, and the other logic codes in the set of logic codes are 1.

6. The decoding circuit according to claim 1, wherein: The code bit generating unit includes: a plurality of groups of sub-generating units, each of which includes: an inverter and a NAND gate; One input end of the NAND gate and the input end of the inverter are suitable for respectively inputting two phase logic values ​​corresponding to one bit of logic code, the output end of the inverter is connected to the other input end of the NAND gate, and the output end of the NAND gate is suitable for outputting the logic code.

7. The decoding circuit according to claim 6, wherein: When the two phase logic values ​​corresponding to one bit of logic code are phase logic values ​​corresponding to two adjacent multi-phase clock signals, one input end of the NAND gate is adapted to input the phase logic value corresponding to the previous multi-phase clock signal, and the input end of the inverter is adapted to input the phase logic value corresponding to the next multi-phase clock signal; When the two phase logic values ​​corresponding to one bit of logic code are the phase logic values ​​corresponding to the last and first multi-phase clock signals, one input end of the NAND gate is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and the input end of the inverter is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

8. The decoding circuit according to claim 6, wherein: When the two phase logic values ​​corresponding to one bit of logic code are phase logic values ​​corresponding to two adjacent multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the previous multi-phase clock signal, and one input end of the NAND gate is suitable for inputting the phase logic value corresponding to the next multi-phase clock signal; When the two phase logic values ​​corresponding to one bit of logic code are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the input end of the inverter is suitable for inputting the phase logic value corresponding to the last multi-phase clock signal, and one input end of the NAND gate is suitable for inputting the phase logic value corresponding to the first multi-phase clock signal.

9. The decoding circuit according to claim 1, wherein: The decoding unit includes: a one-hot decoder; The input end of the one-hot decoder is suitable for inputting the set of logical codes, and the output end of the one-hot decoder is suitable for outputting the first code.

10. A TDC circuit, characterized in that: include: The decoding circuit according to any one of claims 1 to 9, and a phase sampling circuit, adapted to sample the phase of the multi-phase clock signal at a sampling moment to generate a set of phase logic values; The processing circuit is adapted to obtain a quantized fine time according to at least the first encoding.

11. The TDC circuit according to claim 10, wherein: Also includes: a clock signal generating unit, adapted to generate the multi-phase clock signal; The clock signal generating unit includes: a plurality of delay units, wherein the output ends of the plurality of delay units are suitable for outputting the multi-phase clock signal; The output end of the previous delay unit is connected to the input end of the next delay unit, and the output end of the last delay unit is connected to the input end of the first delay unit.

12. The TDC circuit according to claim 10, wherein: Also includes: a counting unit, adapted to count and output the number of cycles of a multi-phase clock signal before the sampling moment; The processing circuit is further adapted to obtain a quantized coarse time at least according to the number of cycles.

13. The TDC circuit according to claim 12, wherein: The processing circuit is adapted to obtain the quantized coarse time according to the period time of the multi-phase clock signal and the number of periods of the cycle.

14. The TDC circuit according to claim 12, wherein: The counting unit comprises: a first counter, adapted to count the number of cycles of a multi-phase clock signal before the sampling instant; a second counter adapted to count the number of cycles of another multi-phase clock signal before the sampling instant; The selection unit is adapted to select a counter that is not in a jump state from the first counter and the second counter, and use the number of cycles calculated by the counter as the output of the counting unit.

15. The TDC circuit according to claim 14, wherein: The first counter and the second counter are both in a jump state when a sudden edge of the multi-phase clock signal occurs; the selection unit includes: The judgment unit is adapted to determine which of the first counter or the second counter is not in a jump state according to the phase logic value.

16. The TDC circuit according to claim 15, wherein: The judgment unit is further adapted to output a flag bit, wherein the flag bit indicates which counter of the first counter and the second counter is used to calculate the number of cycles as the output of the counting unit.

17. The TDC circuit according to claim 10, wherein: The processing circuit is adapted to obtain a quantized fine time according to the delay difference between the multi-phase clock signals and the first code.

18. A data processing chip, characterized in that: include: The TDC circuit of any one of claims 10 to 17, adapted to cooperate with one or more photodetectors.

19. An optical system, characterized in that include: The TDC circuit according to any one of claims 10 to 17, as well as the front-end circuit and at least one photoelectric conversion unit, The photoelectric conversion unit is adapted to generate a first pulse in response to a laser pulse; The front-end circuit is adapted to generate a trigger signal according to the pulse signal, wherein the trigger signal includes a trigger pulse, and a sudden change edge of the trigger pulse corresponds to a sudden change edge of the first pulse; The moment when the sudden edge of the trigger signal occurs corresponds to the sampling moment of the multi-phase clock signal.

20. A decoding method, characterized in that: include: A set of logic codes is generated based on a set of phase logic values, wherein every two phase logic values ​​correspond to one logic code, and the logic codes corresponding to the two phase logic values ​​that meet predetermined requirements are different from other logic codes in the set of logic codes, and are used to indicate a phase signal at a sudden edge in the set of phases; the two phase logic values ​​represent the phases of a pair of multi-phase clock signals at a sampling time; the pair of multi-phase clock signals are two adjacent multi-phase clock signals, or the last and first multi-phase clock signals; Obtain a first code according to the set of logical codes; Obtaining the first code according to the set of logical codes includes: arranging the set of logical codes in order to obtain a set of one-hot codes, obtaining binary codes corresponding to the set of one-hot codes according to the set of one-hot codes, and using the binary codes as the first code.

21. The decoding method according to claim 20, wherein: The phase logic value is 0 or 1, where the phase logic value 0 represents a phase of 0, and the phase logic value 1 represents a phase of π.

22. The decoding method according to claim 21, wherein: When the two phase logic values ​​that meet the predetermined requirement are phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is that the phase logic value corresponding to the previous multi-phase clock signal is 1, and the phase logic value corresponding to the next multi-phase clock signal is 0; When the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirements include: the phase logic value corresponding to the last multi-phase clock signal is 1, and the phase logic value corresponding to the first multi-phase clock signal is 0.

23. The decoding method according to claim 21, wherein: When the two phase logic values ​​that meet the predetermined requirement are phase logic values ​​corresponding to two adjacent multi-phase clock signals, the predetermined requirement is that the phase logic value corresponding to the previous multi-phase clock signal is 0, and the phase logic value corresponding to the next multi-phase clock signal is 1; When the two phase logic values ​​that meet the predetermined requirements are the phase logic values ​​corresponding to the last and first multi-phase clock signals, the predetermined requirements include: the phase logic value corresponding to the last multi-phase clock signal is 0, and the phase logic value corresponding to the first multi-phase clock signal is 1.

24. The decoding method according to any one of claims 20 to 23, wherein: The logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 1, and the other logic codes in the set of logic codes are 0; or, the logic code corresponding to the two phase logic values ​​that meet the predetermined requirements is 0, and the other logic codes in the set of logic codes are 1.

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