Memory, memory control method and memory system

Abstract

The disclosed embodiment provides a memory and a control method thereof. The memory includes: a memory array, which includes a plurality of memory planes, each of which includes a memory block composed of memory cells; and a peripheral circuit, which is connected to the memory array and configured to control the plurality of memory planes to perform asynchronous operations; wherein the peripheral circuit includes at least one state machine; each of the state machines is arranged corresponding to at least one of the plurality of memory planes, the state machine is connected to a memory interface and can receive control commands related to the asynchronous operations of the corresponding memory planes from the memory interface in parallel, and each of the state machines can independently process the control commands received to obtain control information of the corresponding memory plane.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a memory, a control method for a memory, and a memory system. Background Art

[0002] Semiconductor memory devices have been increasingly widely used in various electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and various other electronic devices. With the development of informatization, the amount of data used by these devices is also increasing rapidly, which drives a larger flash memory storage capacity and promotes a faster speed. To meet market demands, NAND flash memory technology is developing rapidly, and NAND flash memory chips often encapsulate multiple NAND die at the package level to increase the capacity of the NAND flash memory chips. In addition, an operation supporting asynchronous multi-plane independent (AMPI) read has also been proposed to achieve independent read control of different memory planes.

[0003] However, in order to avoid conflicts in control command processing resources, control commands for different memory planes need to be processed serially, resulting in a slow overall processing rate, redundant waiting time, and thus low access efficiency of the entire memory. Summary of the Invention

[0004] Embodiments of the present disclosure provide a memory, a control method for a memory, and a memory system.

[0005] In a first aspect, embodiments of the present disclosure provide a memory, including:

[0006] A storage array including a plurality of memory planes, each of the memory planes including memory blocks composed of memory cells; and

[0007] A peripheral circuit connected to the storage array and configured to be able to control the plurality of memory planes to perform asynchronous operations;

[0008] wherein at least one state machine (STM) is included in the peripheral circuit;

[0009] Each of the state machines is provided corresponding to at least one of the plurality of memory planes, the state machine is connected to a memory interface and is capable of receiving control commands related to asynchronous operations of the corresponding memory planes in parallel from the memory interface, and each of the state machines is capable of independently processing the control commands it receives to obtain control information for the corresponding memory plane.

[0010] In some embodiments, the peripheral circuit is configured to control the plurality of memory planes to perform asynchronous operations according to the control information of the plurality of state machines.

[0011] In some embodiments, the state machine is further configured to perform parameter configuration according to the control command;

[0012] Wherein, at least a part of the time periods occupied by at least two of the state machines for processing the control command and performing the parameter configuration overlap.

[0013] In some embodiments, the peripheral circuit further includes:

[0014] A sequence operation module, connected to the plurality of state machines and configured to determine the processing order of the control information of the peripheral circuit according to the control information of the plurality of state machines.

[0015] In some embodiments, the state machine is specifically configured to:

[0016] Send a processing request to the sequence operation module according to the control command;

[0017] The sequence operation module is specifically configured to:

[0018] Determine the processing order according to the processing requests sent by the plurality of state machines.

[0019] In some embodiments, the peripheral circuit further includes:

[0020] A hardware operation module, connected to the sequence operation module and configured to sequentially determine the control parameters corresponding to the control information according to the processing order;

[0021] A plurality of microprocessing units respectively corresponding to each memory plane, connected to the hardware operation module and respectively connected to the corresponding memory plane, and the plurality of microprocessing units are configured to perform asynchronous operations on each memory plane according to the control parameters.

[0022] In some embodiments, the at least one state machine is further respectively connected to the corresponding microprocessing unit and configured to provide an enable signal to the microprocessing unit when receiving the control command.

[0023] In some embodiments, the plurality of microprocessing units are further configured to:

[0024] After ending the control operation of the memory plane based on one control command, send status information to the corresponding state machine;

[0025] The state machine is further configured to: receive the next control command after receiving the state information sent by the corresponding microprocessing unit.

[0026] In some embodiments, the peripheral circuit further includes:

[0027] A main processor, connected to the memory interface and the plurality of microprocessing units, configured to receive the state information sent by the plurality of microprocessing units, and send the total state information determined according to the plurality of state information to the memory interface; wherein, the total state information is used to indicate that the plurality of microprocessing units have all ended the control operations based on a set of control commands.

[0028] In some embodiments, the general microprocessor is further configured to receive a reset command; wherein, the reset command is used to reset the operations of each storage plane in the memory.

[0029] In some embodiments, the at least one state machine is further respectively connected to the plurality of storage planes, and is configured to send address information to the corresponding storage plane according to the control command.

[0030] In some embodiments, the asynchronous operation includes an asynchronous multi-plane independent read operation.

[0031] In some embodiments, the memory array is a three-dimensional flash memory array.

[0032] In some embodiments, the number of the storage planes includes at least 4.

[0033] In a second aspect, an embodiment of the present disclosure further provides a control method for a memory, which is executed by a peripheral circuit in the memory; the peripheral circuit includes at least one state machine; the method includes:

[0034] At least one state machine in the memory receives in parallel control commands related to asynchronous operations for each storage plane in the memory; wherein, each of the state machines is set corresponding to at least one of the plurality of storage planes;

[0035] The respective state machines independently process the received control commands to obtain control information for the corresponding storage planes.

[0036] In some embodiments, the method further includes:

[0037] The peripheral circuit controls the plurality of storage planes to perform asynchronous operations based on the control information obtained by the state machine.

[0038] In some embodiments, the method further includes:

[0039] The state machine performs parameter configuration according to the control command; wherein, at least part of the time periods occupied by at least two state machines in the state machine for processing the control command and performing the parameter configuration overlap.

[0040] In some embodiments, the peripheral circuit controls the plurality of memory planes to perform asynchronous operations based on the control information, including:

[0041] Determine the processing order of the control information according to the control information obtained by the state machine;

[0042] Process the control information in sequence according to the processing order;

[0043] Control the plurality of memory planes to perform asynchronous operations according to the processed control information.

[0044] In some embodiments, the determining the processing order of the control information according to the control information provided by the state machine includes:

[0045] The sequence operation module in the peripheral circuit receives the processing requests sent by the plurality of state machines based on the control command;

[0046] The sequence operation module determines the processing order of the control information based on the processing requests.

[0047] In some embodiments, the processing the control information in sequence according to the processing order includes:

[0048] The hardware operation module in the peripheral circuit determines the control parameters corresponding to the control information in sequence according to the control information provided by the state machine.

[0049] In some embodiments, the controlling the plurality of memory planes to perform asynchronous operations according to the processed control information includes:

[0050] The plurality of microprocessing units in the peripheral circuit control the corresponding memory planes to perform asynchronous operations according to the control parameters; wherein, the plurality of microprocessing units respectively correspond to the plurality of memory planes.

[0051] In some embodiments, the method further includes:

[0052] When receiving the control command, the state machine provides an enable signal to the microprocessing unit.

[0053] In some embodiments, the method further includes:

[0054] After the microprocessing unit finishes the control operation on the storage surface based on one piece of the control information, it sends status information to the corresponding state machine.

[0055] After receiving the status information sent by the corresponding microprocessing unit, the state machine receives the next control command.

[0056] In some embodiments, the method further includes:

[0057] The main processor in the peripheral circuit receives the status information sent by the multiple microprocessing units and sends total status information to the memory interface; wherein, the total status information is used to indicate that the multiple microprocessing units have all finished the control operations based on a set of control commands.

[0058] In some embodiments, the method further includes:

[0059] The main processor receives a reset command;

[0060] According to the reset command, reset the operations of each storage surface in the memory.

[0061] In some embodiments, the method further includes:

[0062] The state machine respectively sends address information to the corresponding storage surface according to the control command.

[0063] In a third aspect, an embodiment of the present disclosure further provides a memory system, including:

[0064] Any one of the above memories;

[0065] A controller, connected to the memory; the controller is configured to send control commands to the memory through the memory interface of the memory.

[0066] In some embodiments, the memory system is a solid state drive (SSD, Solid State Drive) or a memory card. Description of the Drawings

[0067] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0068] Figure 1A A schematic structural diagram of a system provided by an embodiment of the present disclosure;

[0069] Figure 1B A schematic structural diagram of a memory card provided by an embodiment of the present disclosure;

[0070] Figure 1CSchematic diagram of the structure of a solid-state drive provided by an embodiment of the present disclosure;

[0071] Figure 1D and Figure 1E Schematic diagram of the structure of a memory including a memory cell array and a peripheral circuit provided by an embodiment of the present disclosure;

[0072] Figure 1F Schematic diagram of the structure of a control logic unit in the peripheral circuit of a memory provided by an embodiment of the present disclosure;

[0073] Figure 2A Schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0074] Figure 2B Schematic diagram of the principle of separating queues between a memory interface and a state machine in a memory provided by an embodiment of the present disclosure;

[0075] Figure 3 Schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0076] Figure 4 Schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0077] Figure 5 Schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0078] Figure 6 Flowchart of a control method for a memory provided by an embodiment of the present disclosure;

[0079] Figure 7 Schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0080] Figure 8 Schematic diagram of the principle of a control method for a memory in an embodiment;

[0081] Figure 9 Timing diagram of a control method for a memory in an embodiment;

[0082] Figure 10 Schematic diagram of the principle of a control method for a memory in an embodiment;

[0083] Figure 11 Schematic diagram of the structure of a memory provided by an embodiment of the present disclosure;

[0084] Figure 12 Signal timing diagram in a control method for a memory provided by an embodiment of the present disclosure;

[0085] Figure 13Schematic diagram of the principle of a control method for a memory provided by an embodiment of the present disclosure;

[0086] Figure 14 Principle of path-level processing of a control command queue in a control method for a memory provided by an embodiment of the present disclosure;

[0087] Figure 15 For Figure 14 Based on the timing diagram of each signal;

[0088] Figure 16 Principle of information interaction between multiple state machines, a sequence operation module, and a hardware operation module in a control method for a memory provided by an embodiment of the present disclosure;

[0089] Figure 17 For Figure 16 Based on the schematic diagram of the time period required for each processing process shown;

[0090] Figure 18 Timing diagram of a control method for a memory provided by an embodiment of the present disclosure. Detailed implementation manners

[0091] To facilitate the understanding of the present disclosure, the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present disclosure more thorough and comprehensive.

[0092] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0093] As Figure 1A shown, an exemplary system 10 is shown in an embodiment of the present disclosure. The exemplary system 10 may include a host 20 and a storage system 30. Among them, the exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 34; the host 20 may be a processor (e.g., a central processing unit (CPU)) of an electronic device or a system on a chip (SoC) (e.g., an application processor (AP)).

[0094] In an embodiment of the present disclosure, the host 20 may be configured to send data to or receive data from the storage system 30. Here, the storage system 30 may include a controller 32 and one or more memories 34. Among them, the memories 34 may include, but are not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetoresistive random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc.

[0095] On the other hand, the controller 32 may be coupled to the memory 34 and the host 20 and is used to control the memory 34. Exemplarily, the controller may be designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller may also be designed to operate in a high-duty-cycle environment such as a Solid State Drive (SSD) or an embedded multimedia card (eMMC), where the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays. Further, the controller may manage the data in the memory and communicate with the host. The controller may be configured to control operations such as memory reading, erasing, and programming; may also be configured to manage various functions regarding the data stored in or to be stored in the memory, including but not limited to bad block management, garbage collection, logical-to-physical address conversion, wear leveling, etc.; may also be configured to process the error correction code (ECC) regarding the data read from or written to the memory. In addition, the controller may also perform any other suitable functions, such as formatting the memory, or communicating with external devices according to a specific communication protocol (for example, Figure 1Acommunicate with the host 20). Exemplarily, the controller can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.

[0096] In the embodiments of the present disclosure, the controller and one or more memories can be integrated into various types of storage devices. For example, they can be included in the same package (such as Universal Flash Storage (UFS) package or eMMC package). That is to say, the storage system can be implemented and packaged into different types of terminal electronic products. As Figure 1B shown, the controller 32 and a single memory 34 can be integrated into the memory card 40. The memory card 40 can include PC Card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 40 can also include a memory card connector 42 that couples the memory card 40 to a host (such as, Figure 1A the host 20 in Figure 1C In another embodiment shown in Figure 1A the controller 32 and multiple memories 34 can be integrated into the SSD 50. The SSD 50 can also include an SSD connector 52 that couples the SSD 50 to a host (such as,

[0097] It should be noted that the memories involved in the embodiments of the present disclosure can be semiconductor memories, which are solid-state electronic devices for storing data information made by semiconductor integrated circuit processes. Exemplarily, Figure 1D is a schematic diagram of an optional memory 60 in the embodiments of the present disclosure. Among them, the memory 60 can be Figures 1A to 1C the memory 34 in Figure 1DAs shown, the memory 60 may be composed of a storage array 110, a peripheral circuit 120 coupled to the storage array 110, etc. Here, the storage array 110 may be a NAND flash memory cell array, where the memory cells are provided in the form of an array of NAND memory strings 66, and each NAND memory string 66 extends vertically above a substrate (not shown). In some embodiments, each NAND memory string 66 may include a plurality of memory cells coupled in series and vertically stacked. Among them, each memory cell holds a continuous analog value, e.g., voltage or charge, which depends on the number of electrons captured within the memory cell region. Additionally, each memory cell in the above storage array 110 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0098] In an embodiment of the present disclosure, the above memory cell may be a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some other embodiments, each memory cell is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)). Each MLC may be programmed to assume a range of possible nominal storage values. Exemplarily, if each MLC stores two bits of data, the MLC may be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values into the memory cell. Among them, the fourth nominal storage value may be used for the erased state.

[0099] In an embodiment of the present disclosure, the above-mentioned peripheral circuit 120 can be coupled to the memory cell array through bit lines (BL), word lines (WL), source lines, source select gates (SSG), and drain select gates (DSG). Here, the peripheral circuit can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array by applying voltage signals and / or current signals to each target memory cell via the bit lines, word lines, source lines, SSG, and DSG and sensing voltage signals and / or current signals from each target memory cell. In addition, the peripheral circuit 120 can also include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. Exemplarily, as Figure 1E shown. The peripheral circuit 120 includes a page buffer / sense amplifier 71, a column decoder / bit line driver 72, a row decoder / word line driver 73, a voltage generator 74, a control logic unit 75, a register 76, an interface 77, and a data bus 78. It should be understood that the above-mentioned peripheral circuit 120 can be the same as the peripheral circuit 120 in Figure 1D , and in some other embodiments, the peripheral circuit 120 can also include Figure 1E additional peripheral circuits not shown in

[0100] In an embodiment of the present disclosure, the control logic unit included in the above-mentioned peripheral circuit can be used to receive control commands sent by an external host device, process the control commands accordingly, obtain signals required to execute the control commands, and transmit them to the row decoder / word line driver, column decoder / bit line driver, page buffer / sense amplifier, etc., ultimately implementing the operations corresponding to the control commands. As Figure 1F shown, the control logic unit 80 in the peripheral circuit 120 of the embodiment of the present disclosure can include a general microprocessing unit 81 (MP MCU), a hardware processing module 82, and multiple core microprocessing units 83 (core mcu), etc. The control logic unit 80 can communicate with an external host (e.g., the host 20 in Figure 1A ) through the interface 77. Exemplarily, the above-mentioned control logic unit 80 can be the same as the control logic unit 75 in Figure 1E , and in some other embodiments, the control logic unit 80 can also include Figure 1E and 1F other circuit structures and connection interfaces not shown in

[0101] Specifically, Figure 2A FIG. Figure 2A is a structural block diagram of a memory provided by an embodiment of the present disclosure. The memory 100 includes:

[0102] A storage array 110, which includes a plurality of storage planes 111, and each of the storage planes 111 includes storage blocks composed of storage units; and

[0103] A peripheral circuit 120, which is connected to the storage array 110 and is configured to be able to control the plurality of storage planes 111 to perform asynchronous operations;

[0104] Wherein, at least one state machine 121 is included in the peripheral circuit 120;

[0105] Each of the plurality of state machines 121 is correspondingly arranged with at least one of the plurality of storage planes 111. The plurality of state machines 121 are connected to a memory interface I / F and can receive control commands related to asynchronous operations of the corresponding storage planes 111 in parallel from the memory interface I / F. Each of the plurality of state machines 121 can independently process the received control commands to obtain control information of the corresponding storage plane 111.

[0106] In the embodiment of the present disclosure, the memory 100 can be a volatile memory or a non-volatile memory, including a read-only memory, a random access memory, and the like. The memory 100 can be the memory 34 in the above Figures 1A to 1C or Figure 1D the memory 60 in the above. The memory in the embodiment of the present disclosure can independently perform operations of the memory, including multiple storage planes such as reading, programming, and erasing. Hereinafter, a flash memory (NAND) is taken as an example for illustration.

[0107] One or more NAND die can be included in the memory 100 and packaged in a flash chip together with the peripheral circuit 120. The NAND die can include an array composed of storage units, and each storage unit can store data by the stored charge. During a read operation, the control gate voltage can be applied to the word line where the selected storage unit is located, and then the conduction state of the corresponding storage unit can be sensed through a sensing circuit, thereby realizing data reading. The write operation can be realized by storing charge in the floating gate of the storage unit, adjusting the conduction voltage of the storage unit, and further realizing the storage of different data.

[0108] In the memory 100, the distribution structure of each memory cell can be arranged as multiple memory blocks, and a memory block can be the smallest unit that can be erased simultaneously. In addition, the memory cells are also arranged as multiple memory planes 111, and each memory plane 111 includes a plurality of memory blocks and associated row / column control circuits. Each memory plane 111 can include a two-dimensional (2D) or three-dimensional (3D) memory structure.

[0109] In an embodiment of the present disclosure, the peripheral circuit 120 of the memory 100 can at least include: a plurality of state machines 121 and other logic circuits 122 connected to the state machines. Here, the other logic circuits 122 are part or all of the logic circuits other than the state machines 121 in the peripheral circuit 120. For example, it can include a microprocessing unit, a hardware processing module, and so on. The other logic circuits 122 are connected to each memory plane 111 in the memory 100 and are used to control each memory plane 111 to perform asynchronous operations based on the control commands processed by the state machines. Here, the peripheral circuit 120 of the memory 100 can be part or all of the peripheral circuit 70 described above. Exemplarily, the peripheral circuit 120 can at least include the control logic unit 75 in the peripheral circuit 70 described above, or include the control logic unit 80 described above. And the function of the memory interface I / F in the embodiment of the present disclosure is to transfer the control commands provided by an externally connected host (such as the host 20 shown) to each state machine 121 for processing. The memory interface I / F can be part or all of the interface 77 in the above or 1F, or can be an independent interface different from the above interface 77, which is not limited here. Figure 1E part or all of the peripheral circuit 70. Exemplarily, the peripheral circuit 120 can at least include the control logic unit 75 in the peripheral circuit 70 described above, or include the control logic unit 80 described above. And the function of the memory interface I / F in the embodiment of the present disclosure is to transfer the control commands provided by an externally connected host (such as the host 20 shown) to each state machine 121 for processing. The memory interface I / F can be part or all of the interface 77 in the above or 1F, or can be an independent interface different from the above interface 77, which is not limited here. Figure 1E part or all of the peripheral circuit 70. Exemplarily, the peripheral circuit 120 can at least include the control logic unit 75 in the peripheral circuit 70 described above, or include the control logic unit 80 described above. And the function of the memory interface I / F in the embodiment of the present disclosure is to transfer the control commands provided by an externally connected host (such as the host 20 shown) to each state machine 121 for processing. The memory interface I / F can be part or all of the interface 77 in the above or 1F, or can be an independent interface different from the above interface 77, which is not limited here. Figure 1F The function of the memory interface I / F in the embodiment of the present disclosure is to transfer the control commands provided by an externally connected host (such as the host 20 shown) to each state machine 121 for processing. The memory interface I / F can be part or all of the interface 77 in the above or 1F, or can be an independent interface different from the above interface 77, which is not limited here. Figure 1A The function of the memory interface I / F in the embodiment of the present disclosure is to transfer the control commands provided by an externally connected host (such as the host 20 shown) to each state machine 121 for processing. The memory interface I / F can be part or all of the interface 77 in the above or 1F, or can be an independent interface different from the above interface 77, which is not limited here. Figure 1E The memory interface I / F can be part or all of the interface 77 in the above or 1F, or can be an independent interface different from the above interface 77, which is not limited here.

[0110] The other logic circuits 122 can be connected to each memory plane 111 through corresponding interfaces to perform read, write, or erase operations on the memory blocks in the memory plane 111. For example, it controls multiple memory planes to perform asynchronous operations such as AMPI operations, asynchronous programming operations, asynchronous erase operations, etc. In addition to providing clock signals for performing different asynchronous operations, the other logic circuits 122 also need to provide various voltage or current signals and provide functions such as sensing. To support fast read operations, the other logic circuits 122 can also be configured to support asynchronous multi-plane independent (AMPI, Async Multi-plane Independent) read operations. AMPI read is an enhanced read operation that can support independent asynchronous read operations to be performed simultaneously between different memory planes 111. In addition, the other logic circuits 122 can also be configured to support mixed operations such as asynchronous multi-plane programming operations, asynchronous multi-plane erase operations, and other various asynchronous operations.

[0111] Taking the AMPI read operation as an example, the command processing of other logic circuits 122 is generally also an asynchronous operation, and the asynchronous control commands for each storage surface 111 are queued and processed in sequence. This will lead to too long processing time. After receiving the control commands, they are processed in sequence, resulting in too long waiting time for the storage surface 111 corresponding to the later processed control commands, thus making the overall processing time of the memory 100 relatively long.

[0112] Therefore, in the embodiments of the present disclosure, multiple state machines 121 corresponding to the storage surfaces 111 are adopted to process the control commands. Here, the number of the multiple state machines 121 can be the same as the number of the storage surfaces 111, and each state machine 121 corresponds to a storage surface 111 one by one. In another embodiment, the number of the multiple state machines 121 can also be less than the number of the storage surfaces 111, and one state machine 121 can correspond to one or more storage surfaces 111. Here, the correspondence between the state machine 121 and the storage surface 111 means that the state machine 121 is used to process the control commands for the specified storage surface 111. If a state machine 121 only corresponds to one storage surface 111, then the state machine 121 is only used to process the control commands for the corresponding storage surface 111. Exemplarily, the storage surfaces of the memory in the embodiments of the present disclosure can include 4, 6, 8 or more.

[0113] In the embodiments of the present disclosure, the state machine 121 is connected to the memory interface I / F and can receive the control commands for the corresponding storage surface 111. The state machine 121 parses and processes the control commands through a hardware circuit, or configures the parameters required to execute the operations corresponding to the control commands, etc.

[0114] Here, the memory interface I / F can be connected to an external host device (such as Figure 1A the host 20 shown). The memory interface I / F can include a bus interface such as some control signal lines, clock signal lines, and data signal lines. The host device can control the memory 100 by sending control commands. Exemplarily, as Figure 1A shown, the host 20 performs command interaction with the storage system 30 through a communication interface. The controller 32 in the storage system 30 can transfer the control commands sent by the host 20 to the memory 34 (i.e., the memory 100 shown in the above embodiments Figure 2A ), and send them to other logic circuits 122 through the memory interface I / F described in the above embodiments. The control commands can carry some address information, for example, which storage surface 111 the control command is for. According to these address information, the corresponding state machine 121 can receive the control commands and can feedback response messages, etc. Then, after the state machine 121 processes the control commands, other logic circuits 122 provide corresponding signals to realize the control of the storage surface 111.

[0115] Since the above-mentioned multiple state machines 121 are separately and independently arranged hardware structures, parallel processing of control commands can be performed. If multiple control commands for different storage surfaces 111 are received simultaneously or within the same time period, the multiple state machines 121 can perform parallel processing and transfer them to other logic circuits 122. Then, the other logic circuits 122 perform control in sequence. The purpose of this is to divide the original control command queue into multiple small queues for parallel processing through the multiple state machines 121. The control commands in each queue can be queued separately, thereby improving the overall queuing efficiency. In the embodiments of the present disclosure, the more the number of storage surfaces 111, the more obvious the effect of the state machines 121 performing asynchronous processing to shorten the overall processing duration.

[0116] In addition, in the embodiments of the present disclosure, the multiple state machines 121 can be respectively connected to the memory interface I / F, as Figure 2A shown. The memory interface I / F may include multiple connection terminals, each connection terminal is respectively connected to the state machine 121, and each connection terminal can respectively transmit different control commands to the state machine 121 to which it is connected.

[0117] Figure 2B illustrates the principle of the memory interface I / F separating the command queue and transmitting it to the state machines. Specifically, the multiple state machines 121 are respectively connected to the memory interface I / F. The memory interface I / F can divide the received control command queue into multiple queues according to the number of state machines 121 and transmit them to the state machines 121 in sequence according to the queue order. Figure 2B In, if the current state of each state machine 121 is to process a control command, then in the next state, it receives and processes the next control command waiting in the corresponding queue of the memory interface I / F.

[0118] Through the above solution, the control commands can be separated according to the paths and processed by different state machines in the form of multiple queues, so as to achieve path-level (way-level) processing. In contrast, in some other embodiments, a general-purpose microprocessor (MP MCU) performs chip-level (chip-level) serial processing on all control commands, that is, directly performs serial processing on the control logic of the memory chip through a total queue.

[0119] It can be understood that the path-level processing of control commands in the embodiments of the present disclosure can effectively reduce the processing duration of control commands and reduce the waiting or idle duration of each storage surface compared with the method of performing chip-level serial processing on all control commands through a general-purpose microprocessor, thereby improving the overall operation rate of the memory.

[0120] In some embodiments, the peripheral circuit 120 is configured to control the plurality of memory planes 111 to perform asynchronous operations according to control information from the plurality of state machines 121. In the embodiments of the present disclosure, after the plurality of state machines 121 obtain control information by processing control commands related to the asynchronous operations of the corresponding memory planes 111, the peripheral circuit 120 can control each memory plane 111 to perform asynchronous operations according to this control information.

[0121] Here, the processing of each control information by the peripheral circuit 120 can be serial processing. For example, other logic circuits 122 in the peripheral circuit 120 receive the control information provided by the plurality of state machines 121, process it in a certain order, and transmit it to different memory planes 111 to achieve the control of different memory planes 111. Exemplarily, the processing of the control information by the peripheral circuit 120 may include sending signals such as voltage and current required for asynchronous operations to each memory plane 111 according to the control information to achieve the asynchronous operations of each memory plane 111.

[0122] In the embodiments of the present disclosure, the peripheral circuit 120 performs hardware processing based on the control information, thereby executing the asynchronous operations corresponding to the control commands.

[0123] In some embodiments, the state machine 121 is further configured to perform parameter configuration according to the control command;

[0124] Wherein, at least part of the time periods occupied by at least two of the plurality of state machines 121 for processing the control command and performing the parameter configuration overlap.

[0125] In the embodiments of the present disclosure, the state machine 121 can also be used for parameter configuration. Based on different control commands, corresponding parameter configurations can be performed. Since the plurality of state machines 121 can perform parallel processing, therefore, the times for the above-mentioned plurality of state machines 121 to parse the control commands and perform parameter configuration can overlap with each other, that is, different state machines 121 can perform their respective parsing and configuration processes simultaneously.

[0126] In this way, the time difference between the start times of operations between different memory planes 111 can be reduced, thereby reducing the overall processing duration of the memory 100.

[0127] In some embodiments, as Figure 3 shown, the peripheral circuit 120 further includes:

[0128] A sequence operation module 131, connected to the plurality of state machines 121 and configured to determine the processing order of the control information according to the control information of the plurality of state machines 121.

[0129] Since the peripheral circuit 120 still needs to serially process the control information corresponding to each control command, in the embodiments of the present disclosure, a sequence operation module 131 is added to sort the control information obtained after the state machine 121 processes it, and determine the processing order of each control information.

[0130] That is to say, after multiple state machines 121 perform shunting queuing and related processing on the control commands, the sequence operation module 131 is used to queue the control information.

[0131] After the sequence operation module 131 determines the processing order of the control information, it sequentially instructs the peripheral circuit 120 to execute the corresponding control commands based on the control information, which can facilitate the reasonable utilization of control resources in the peripheral circuit 120 and reduce resource conflicts.

[0132] In some embodiments, the state machine 121 is specifically configured to:

[0133] Send a processing request to the sequence operation module 131 according to the control command;

[0134] The sequence operation module 131 is specifically configured to:

[0135] Determine the processing order of the control information for the peripheral circuit 120 according to the processing requests sent by multiple state machines 121.

[0136] In the embodiments of the present disclosure, the state machine 122 can send a processing request to the sequence operation module 131 according to the control command, and this processing request is to request the sequence operation module 131 to perform sorting processing.

[0137] The processing request may include storage surface information corresponding to the control command to be processed, such as storage surface number, address and other information, and may also include some operation type and other information. The sequence operation module 131 sorts the received control information through these information, and the peripheral circuit 120 can process the control information according to this sorting, and then perform asynchronous operations on each storage surface.

[0138] In some embodiments, as Figure 4 shown, the peripheral circuit 120 further includes:

[0139] A hardware operation module 132, connected to the sequence operation module 131 and configured to sequentially determine the control parameters corresponding to the control information according to the processing order;

[0140] Multiple microprocessing units 133 respectively corresponding to each storage surface 111, connected to the hardware operation module 132 and respectively connected to the corresponding storage surface 111, and the multiple microprocessing units 133 are configured to perform asynchronous operations on each storage surface 111 according to the control parameters.

[0141] In an embodiment of the present disclosure, the hardware operation module 132 in the peripheral circuit 120 is used to determine various signals required for asynchronously operating on the storage surface 111 according to control information, including voltages, currents required for various operations, and corresponding timing changes, etc. Since the hardware operation module 132 performs serial processing, the hardware operation module 132 can perform corresponding processing according to the processing sequence provided by the sequence operation module 131.

[0142] In addition, the hardware operation module 132 needs to provide control parameters to the microprocessing unit 133 (Core MCU). The microprocessing unit 133 is connected to each storage surface 111, and each microprocessing unit 133 can independently control one storage surface 111. In some embodiments, one microprocessing unit 133 can also control multiple storage surfaces 111.

[0143] The hardware operation module 132 transfers the control parameters to the corresponding microprocessing unit 133, and then the microprocessing unit 133 realizes the control of the storage surface 111. The microprocessing unit 133 can be connected to the storage surface 111 through a control bus, and the control bus can include connections to various logic circuits of the storage surface 111, including word lines, bit lines, selection lines, and control lines connected to each storage unit, etc.

[0144] In some embodiments, the multiple state machines 121 are also respectively connected to the corresponding microprocessing units 133 and are configured to provide an enable signal to the microprocessing unit 133 when receiving the control command.

[0145] In an embodiment of the present disclosure, the working states of the respective microprocessing units 133 and the working states of the state machine 121 can be synchronized through communication therebetween. In this way, when the state machine 121 receives a new control command, it can enable the microprocessing unit 133 through the enable signal, so that the microprocessing unit 133 makes corresponding preparations for the upcoming control operation. At the same time, it can also achieve functions such as clock synchronization.

[0146] In some embodiments, the state machines 121 can correspond one-to-one with the microprocessing units 133, so as to communicate with each microprocessing unit 133 separately and enable the corresponding microprocessing unit 133. In other embodiments, the state machines 121 can also correspond to multiple microprocessing units 133, communicate with the multiple microprocessing units 133, and enable the multiple microprocessing units 133.

[0147] In some embodiments, the multiple microprocessing units 133 are further configured to:

[0148] After ending the control operation on the storage surface 111 based on one of the control commands, send status information to the corresponding state machine 121;

[0149] The state machine 121 is further configured to: after receiving the state information sent by the corresponding microprocessing unit 133, receive the next control command.

[0150] In addition, the communication connection between each microprocessing unit 133 and the state machine 121 can also be used for the microprocessing unit 133 to inform the state machine 121 of its own processing state. If the microprocessing unit 133 is in the working state, a type of state information can be provided, and the state machine will pause the processing of the next control command or not receive the next control command for the time being. If the microprocessing unit 133 is in the idle state, another type of state information can be provided, and the state machine 121 can receive the next control command and enable the microprocessing unit 133 to perform the next round of operations.

[0151] Exemplarily, the microprocessing unit 133 can output a signal to the state machine 121. If the signal is in the high-level state, it represents that the current microprocessing unit 133 is in the working state. If the signal is in the low-level state, it represents that the current microprocessing unit 133 is in the idle state.

[0152] In this way, resource conflicts can be further reduced, processing efficiency can be improved, and the possibility of operation errors caused by resource conflicts can be reduced.

[0153] In some embodiments, as Figure 5 shown, the peripheral circuit 120 further includes:

[0154] A main processor 134, connected to the memory interface I / F and the plurality of microprocessing units 133, and configured to receive the state information sent by the plurality of microprocessing units 133 and send the total state information determined according to the plurality of state information to the memory interface I / F; wherein, the total state information is used to indicate that the plurality of microprocessing units 133 have all ended the control operations based on a set of control commands.

[0155] Here, the main processor 134 is connected to the memory interface I / F and can directly receive some external control commands. Exemplarily, the main processor 134 can be implemented by a general microprocessor. In addition, the main processor 134 is connected to the plurality of microprocessing units 133 and can control each storage surface 111 in the memory 100 through software. Therefore, using the main processor 134 in cooperation with the state machine 121 can flexibly control the storage surface 111. Some functions can be implemented using the main processor 134 during some function expansions or debugging, or the main processor 134 can also be used when serial processing of each control command is required.

[0156] In an embodiment of the present disclosure, each micro - processing unit 133 may send its respective status information to the main processor 134. If all micro - processing units 133 are in an idle state, the main processor 134 may send the total status information to the memory interface I / F to indicate that the memory 100 is in an idle state. In this way, it is convenient for an external host to perform some other overall controls on the memory 100, or operations such as resetting and refreshing the memory 100 can be carried out.

[0157] Here, the total status information may include the status information provided by each micro - processing unit 133, or may be information generated based on the status information provided by each micro - processing unit 133 for indicating that the memory status is an idle state.

[0158] In some embodiments, the main processor is further configured to receive a reset command; wherein, the reset command is used to reset the operations of each memory plane 111 in the memory 100.

[0159] In an embodiment of the present disclosure, if it is necessary to reset the memory 100, a reset command may be sent to the main processor 134 through the memory 100 interface. When the main processor 134 receives the reset command, it may perform a reset operation on each memory plane 111.

[0160] It should be noted that the reset operation can be performed at any time. For example, when each memory plane 111 is in an idle state, a reset operation can be performed on each memory plane 111. Another example is that when a memory plane 111 is performing read - write operations, if a reset command is received, the current read - write operations can be stopped and a reset operation can be performed. Here, the reset operation may include discharging the charges of each node, resetting the signals on each signal line to zero or to a certain value, etc.

[0161] In some embodiments, the multiple state machines 121 are also respectively connected to the multiple memory planes 111 and are configured to send address information to the corresponding memory plane 111 according to the control command.

[0162] In an embodiment of the present disclosure, the multiple state machines 121 may also be respectively connected to the multiple memory planes 111. For example, they are connected to the multiple memory planes 111 through an address bus. The state machine 121 may send address information to the memory plane 111 through the address bus, including row address information and column address information to be operated, or information such as a memory block to be operated, etc. If the state machines 121 and the memory planes 111 are in one - to - one correspondence, then the address information sent by each state machine may only include the address information of the corresponding storage unit in the memory plane 111, and does not need to include the address information of the memory plane.

[0163] Such as Figure 6As shown, an embodiment of the present disclosure also provides a control method for a memory, which is executed by a peripheral circuit in the memory; the peripheral circuit includes at least one state machine; the method includes:

[0164] Step S101, the state machines in the memory receive in parallel control commands related to asynchronous operations for each storage plane in the memory; wherein, each of the state machines is correspondingly set for at least one of the multiple storage planes;

[0165] Step S102, the state machines independently process the received control commands to obtain control information for the corresponding storage planes.

[0166] In an embodiment of the present disclosure, the memory includes at least one state machine, and different state machines can correspond to different storage planes. Exemplarily, one state machine can correspond to one storage plane or multiple storage planes. Multiple state machines can be connected to the memory interface and receive control commands related to asynchronous operations for each storage plane transmitted by the memory interface. Multiple state machines can receive and process control commands in parallel. Compared with the method of serially processing control commands related to asynchronous operations, it can reduce the waiting time of related circuits, improve the utilization rate of processing resources, thereby improving processing efficiency and reducing processing delay.

[0167] In some embodiments, the method further includes:

[0168] The peripheral circuit controls the multiple storage planes to perform asynchronous operations based on the control information.

[0169] After receiving the control commands, the above-mentioned multiple state machines can perform parsing to obtain corresponding control information. The process of the multiple state machines performing control command parsing can also be parallel, so as to synchronously complete the parsing of control commands for multiple different storage planes.

[0170] After the multiple state machines complete the parsing of the control commands, they can respectively transfer the parsed control information to other logic circuits of the peripheral circuit. Then, the asynchronous operation of the storage plane is executed.

[0171] In some embodiments, the method further includes:

[0172] The state machine performs parameter configuration according to the control command; wherein, there is at least partial overlap in the time periods occupied by at least two of the state machines for processing the control command and performing the parameter configuration.

[0173] In the embodiments of the present disclosure, multiple state machines also perform parameter configuration according to control commands. Since the multiple state machines can process in parallel, the time for the multiple state machines to parse control commands and perform parameter configuration can overlap with each other, that is, different state machines can perform their respective parsing and configuration processes simultaneously.

[0174] Compared with the method of serially parsing and processing control commands related to asynchronous operations by a general-purpose processor and having the peripheral circuit wait for each control command and then perform control operations in sequence, the method in the embodiments of the present disclosure can reduce the time difference for starting to execute operations between different storage surfaces, thereby reducing the overall processing duration of the memory.

[0175] In some embodiments, the peripheral circuit controls the multiple storage surfaces to perform asynchronous operations based on the control information, including:

[0176] Determining the processing order of the control information by the peripheral circuit according to the control information provided by the multiple state machines;

[0177] Processing the control information in sequence according to the processing order;

[0178] Controlling the multiple storage surfaces to perform asynchronous operations according to the processed control information.

[0179] In the embodiments of the present disclosure, after the state machine parses and processes each control command and performs parameter configuration, the peripheral circuit can perform corresponding control operations on each storage surface. Since other logic circuits in the peripheral circuit can perform serial operations, the control commands of the multiple state machines can be sorted and then sequentially executed by these logic circuits. The peripheral circuit can process the corresponding control information according to the processing order of each control command, and then sequentially control the corresponding storage surfaces to perform asynchronous operations.

[0180] In some embodiments, the determining the processing order of the control information according to the control information provided by the multiple state machines includes:

[0181] The sequence operation module in the peripheral circuit receives the processing requests sent by the multiple state machines based on the control commands;

[0182] The sequence operation module determines the processing order of the control information based on the processing requests.

[0183] In the embodiments of the present disclosure, the sorting action can be performed by a sequence operation module in a controller. Multiple state machines can send processing requests to the sequence operation module according to the received and parsed control commands. The sequence operation module can then sort the control information corresponding to the control commands according to the processing requests, and process the control information according to the sorting to perform asynchronous operations on different control storage surfaces.

[0184] In some embodiments, the sequentially processing the control information according to the processing order includes:

[0185] A hardware operation module in the peripheral circuit determines control parameters corresponding to the control information in sequence according to the control information provided by the state machine according to the processing order.

[0186] In the embodiments of the present disclosure, the processing order determined by the sequence operation module can be provided to the hardware operation module. The hardware operation module is used to calculate control parameters such as required voltage, current, and corresponding time according to specific control commands. Since the hardware operation module is for serial processing, the hardware operation module can perform corresponding processing according to the processing order provided by the sequence operation module.

[0187] In some embodiments, the controlling the multiple storage surfaces to perform asynchronous operations according to the processed control information includes:

[0188] Multiple microprocessors in the peripheral circuit control the corresponding storage surfaces to perform asynchronous operations according to the control parameters; wherein, the multiple microprocessors respectively correspond to the multiple storage surfaces.

[0189] The hardware operation module can provide control parameters to the microprocessors. The microprocessors are connected to each storage surface, and each microprocessor can independently control one storage surface. Multiple microprocessors are used to perform asynchronous operations on multiple storage surfaces.

[0190] In some other embodiments, one microprocessor can also control multiple storage surfaces.

[0191] The hardware operation module transfers the control parameters to the corresponding microprocessors, and then the microprocessors implement the control of the storage surfaces. The microprocessors can be connected to the storage surfaces through a control bus, and the control bus can include connections to various logic circuits of the storage surfaces, including word lines, bit lines, selection lines, and control lines connected to each storage unit, etc.

[0192] In this way, the microprocessors can perform corresponding operations on each storage surface according to the control parameters provided by the hardware operation module, and thus achieve the result of executing the control commands.

[0193] In some embodiments, the method further includes:

[0194] When the multiple state machines receive the control command, they provide an enable signal to the microprocessing unit.

[0195] In the embodiments of the present disclosure, the working states of the microprocessing units and the state machines can be synchronized through communication therebetween. In this way, when the state machine receives a new control command, it can enable the microprocessing unit through the enable signal, so that the microprocessing unit makes corresponding preparations for the upcoming control operation. At the same time, it can also achieve functions such as clock synchronization.

[0196] In the embodiments of the present disclosure, the state machine can send an enable signal to the corresponding microprocessing unit after receiving the control command, causing the microprocessing unit to enter a waiting state. It can also send an enable signal to the corresponding microprocessing unit after completing operations such as parsing the control command, so that the microprocessing unit starts to receive corresponding control parameter information and perform operations on the storage surface.

[0197] In some embodiments, the method further includes:

[0198] After the microprocessing unit finishes the control operation on the storage surface based on one piece of the control information, it sends status information to the corresponding state machine.

[0199] After receiving the status information sent by the corresponding microprocessing unit, the state machine receives the next control command.

[0200] In the embodiments of the present disclosure, the microprocessing unit can be connected to the corresponding state machine. After the microprocessing unit finishes the control operation of one control command, it enters an idle state. At this time, it can send status information to the state machine. In this way, the state machine can continue to receive the next control command and continue with corresponding parsing processing.

[0201] In some embodiments, the method further includes:

[0202] The main processor in the peripheral circuit receives the status information sent by the multiple microprocessing units and sends total status information to the memory interface; wherein the total status information is used to indicate that the multiple microprocessing units have all finished the control operations based on a set of control commands.

[0203] The multiple microprocessing units can respectively send their own status information to the main processor, and the main processor can then perform overall management. When the status information of the multiple microprocessing units all indicates an idle state, it means that the memory as a whole is in an idle state. At this time, the total status information can be sent to the memory interface.

[0204] In this way, it is convenient for the host connected to the memory to determine the state of the memory and perform other control operations.

[0205] In some embodiments, the method further includes:

[0206] The main processor receives a reset command;

[0207] According to the reset command, the operations of each memory plane in the memory are reset.

[0208] The main processor can receive a reset command from the memory interface and perform a reset operation on each memory plane. The reset operation can be performed at any time. For example, when each memory plane is in an idle state, a reset operation can be performed on each memory plane. Also, when a memory plane is performing a read operation or a write operation, if a reset command is received, the current read operation or write operation can be stopped and a reset operation can be performed. Here, the reset operation can include discharging the charges of each node, resetting the signals on each signal line to zero or to a certain value, etc.

[0209] In some embodiments, the method further includes:

[0210] The multiple state machines respectively send address information to the corresponding memory planes according to the control command.

[0211] In the embodiments of the present disclosure, the multiple state machines can also directly send address information to the memory planes to indicate the specific addresses of the memory cells to be operated by the control command, thereby facilitating the controller to perform corresponding operations on the memory planes.

[0212] The embodiments of the present disclosure also provide the following examples:

[0213] In one embodiment, as Figure 7 shown, the memory 200 includes a general controller 201 (MP MCU), a hardware processing module 202 (HW Calc), and core microprocessing units 203a, 203b, 203c, and 203d corresponding to multiple memory planes. The microprocessing units 203 are connected to the memory planes through data buses (cbus0 - 3). In addition, a memory interface 205 (nand if) is connected to a synchronization module 206 (sync). In addition, the hardware processing module 202 and the general controller 201 can also be connected to each memory plane through address buses (mbus0 - 3) to provide address information.

[0214] After the control command (cmd) enters through the memory interface 205, it can be clock-synchronized by the synchronization module 206 and then transmitted to the command sequence processing module 207 (cmd_seq). The command sequence processing module 207 sequentially transmits each control command to the general controller 201 through serial processing. The required control parameters are obtained through the operation of the hardware processing module 202, and the general controller 201 can enable the microprocessing unit 203. Then, the microprocessing unit 203 can perform control operations on each storage surface.

[0215] However, since the general controller parses commands through software and can only perform serial processing, in order to avoid resource conflicts between the general controller and the hardware processing module 202, each control command needs to wait for each other. This method has low utilization, and only read or write operations can be performed at a time, and multiple storage surfaces cannot be read and / or written simultaneously. In addition, since the line width of the bus is 8 bits, the parallelism is relatively low.

[0216] As Figure 8 shown, the Y direction represents the multi-channel control commands for different storage surfaces, and the X direction represents the queue depth of the control commands for each storage surface. After each control command (w0~w3) enters, they need to be serially processed time-divisionally with each other. Only when the microprocessing unit corresponding to one control command is in the idle state can the operation be performed. For the microprocessing unit in the busy state, the corresponding control command needs to be in the waiting state. Each queue is processed in the order of priority from high to low. When it comes to processing the control command at a queue position, logical operation processing, such as "AND operation" processing, can be performed through the status value of the microprocessing unit corresponding to the queue. Exemplarily, when it comes to the control command at the position [0][1] of the queue, if there is a control command to be processed at this position and the status value is "1" (idle state), it can be processed; if the status value is "0" (busy state), it waits to be processed.

[0217] As Figure 9 shown, after the control commands (w0~w3) enter, they process the 4-way control commands (way0~way3) of the general controller respectively. The processing time interval between the control commands corresponding to every two different storage surfaces is tAsync. Correspondingly, the processing duration of each path is also tAsync. The subsequent commands need to wait for tRCBSY, and then the general controller continues to receive the next control command.

[0218] For different control commands, the corresponding read duration tR may also be different. And only after the read operation duration corresponding to the first group of control commands can the next waiting control command be processed. In this way, the control commands ranked behind need to wait longer, resulting in low overall operation efficiency. The processing order and status of each control command can be determined by Figure 10Shown.

[0219] In the above example, the read operation is for 4-channel AMPI. If a 6-channel AMPI is used for the read operation, greater latency will be generated and the command processing queue will be more complex.

[0220] Therefore, the embodiments of the present disclosure provide a method for parallel processing control commands and a memory structure. As Figure 11 shown, the 6-channel AMPI read operation can be parsed and processed in parallel through different state machines (STM0 to STM5), and by controlling one of the corresponding multiple microprocessing units (core mcu0 to 5), waveform information defined by the electrical design rules of the corresponding storage plane can be generated, such as the waveform information of the read operation. In addition, parameter configuration, etc. are implemented through the sequence operation unit and the hardware processing unit. In this way, by parallel processing control commands of different storage planes through multiple separate queues, the one-dimensional serial processing method becomes a two-dimensional parallel processing method. Thereby, the processing efficiency can be effectively improved and resource conflicts can be reduced.

[0221] As Figure 12 shown are the processing timings of each state machine and the state timings (core_done_grp) of the corresponding microprocessing units. The processing periods of each state machine can include overlapping periods, that is, different control commands are processed in parallel. The processing periods of each state machine include overlapping periods, so the time difference tAsync for each channel to process the control command is shorter than the case where the processing periods do not overlap each other.

[0222] The state of the main controller (MP MCU) can be triggered when a control command is received and enter the AMPI operation state. Then, since the state machine executes the processing of the control command, the main controller can enter the sleep state. After the multiple microprocessing units complete the operation, corresponding status information can be sent to the general controller. As Figure 12 shown, the rising edges of waveforms such as core_done_grp0 to 2 indicate that the corresponding microprocessing units have completed the operation. At this time, the main controller MP MCU can be awakened and send a total status information indicating that all microprocessing units have completed the operation. As Figure 12 shown by the rising edge of the all_core_done waveform in, at this time, the main controller MP MCU can end the current AMPI operation state.

[0223] In addition, the main controller can also be used to perform a reset operation. When a reset command (cmd_ff) is received, the main controller is awakened and the memory is controlled to interrupt the ongoing AMPI read operation, for example, terminate the parallel processing operations of each channel corresponding to each storage plane.

[0224] In the embodiments of the present disclosure, by separately processing the command queue and resource allocation, and implementing parallel processing of multiple command queues through a state machine, the processing time of road-level commands is reduced. The resource queue is queued by a sequence operation module to handle possible resource conflicts generated by the hardware processing module at the chip level. Since there is no need to wait for the parsing of control commands, the conflict time is very short, and the queue depth is also reduced, thereby improving the overall processing efficiency, as Figure 13 shown. Exemplarily, on the one hand, the command sequence can perform resource calculations at the chip level. On the other hand, the memory interface can be separated into multiple queues and provided to the corresponding state machines through road-level processing. As Figure 13 shown, the command sequence after chip-level resource calculation can be separated into queues and enter different queues of the memory interface. For example, there are a total of 6 queues: cmd_xx_grp0 to 5. Here, cmd_xx refers to different command types, such as the read instruction cmd_rd or the write instruction cmd_wr, etc. Multiple queues of the memory interface are respectively connected to different state machines (such as Figure 13 shown stm0 to 5), and each control command is transmitted to the state machine in the queue order.

[0225] Figure 14 This is the road-level processing principle of the control command queue, Figure 15 and Figure 14 the corresponding signal timings. As Figure 14 shown, queues of multiple control commands (cmd_30_grpX... cmd_3d_grpX) can determine the next set of command sequences to be processed through state selection. For example, determine the command sequence (ampi_cmd_read_grpX) to be subjected to the ampi read operation as the sequence to be processed for asynchronous processing (sync) and transmit it to the corresponding state machine stm_x in order. As Figure 15 shown, the period from when the state machine is enabled (stm_en_pulse_grpX signal) to before the ampi processing reset signal (ampi_rst_grpX signal) sent by the state machine is the period during which the state machine and the controller perform arithmetic processing on the control command. The processing time difference tAsync between each state machine is included in this period. The period from after the ampi processing reset to before the memory is ready (core_cache_rdy_grpX signal) is the waiting time tRCBSY required before executing the instruction. When the memory is ready, operations on the control instruction can be performed, such as a read operation, and its corresponding duration is tR. In addition, the cotr_done_grpX signal indicates that each microprocessing unit (mcuX) is in an available state, that is, the operation of the previous control command has been completed. Figure 15The mp_mcu_clk in the figure is the clock signal of the main processor. All the above signals can be triggered by the rising or falling edge of the clock signal; cache_rbn_grpX is used as the trigger signal for transmitting control commands.

[0226] Figure 16 Shows the information interaction process between multiple state machines (STMs) and the sequence calculation module (calc seq) and the hardware calculation module (hwcale). Figure 17 shows the time period required for the processing process. Figure 16 and Figure 17 As shown in , after the state machines STMs process the received control commands in parallel, they send processing requests (stm_request[x]) and the processing request types (stm_request_typ_grpX[1:0]) of each state machine to the operation processing module within one clock cycle (1clk) of the operation request phase. Next, the operation processing module processes the control commands in parallel within one clock cycle (1clk) based on Figure 16 The queue (queue[1:0][5:0]) in is used to calculate and confirm the next control information to be processed. If it is determined to process the current control information (seq_acknowledge[x]=1), the relevant control information is passed to the hardware calculation module (hwcale) for calculation and processing; if the current control information needs to wait for processing (seq_acknowledge[x]=0), it waits for a clock cycle (1clk) before making a judgment. The hardware processing module (hw cale) may need multiple clock cycles to process, such as 4clk serial processing. After that, the state machine is reset (set stm_request_rst[x]) and the state machine continues to move down the parallel processing of the control command.

[0227] Figure 18 is a schematic diagram of the state of controlling each storage surface in the embodiment of the present disclosure. Figure 18 As shown in , after the control commands (w0~w3) for each storage plane are input, different state machines receive the control commands in turn and perform corresponding processing. Figure 18 T1~T3 in represent different setting processes, covering the period required to read the settings. Figure 18 It can be seen that the time difference tAsync between the processing of control commands between the channels is only a part of the time required for the overall reading setting. Therefore, compared with Figure 9 The situation shown in the figure shortens the processing time overall.

[0228] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the magnitudes of the serial numbers of the above processes do not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0229] It should be noted that in this article, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0230] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the couplings, direct couplings, or communication connections between the components shown or discussed with each other can be through some interfaces, and the indirect couplings or communication connections of the devices or units can be electrical, mechanical or other forms.

[0231] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units; they can be located in one place or distributed to multiple network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0232] In addition, each functional unit in the embodiments of the present disclosure can be all integrated in one processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in one unit; the above integrated unit can be implemented in the form of hardware, or in the form of a hardware plus software functional unit.

[0233] As described above, it is only the implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claimed rights.

Claims

1. A memory, comprising: A storage array comprising a plurality of storage planes, each of the storage planes comprising a storage block composed of storage cells; as well as A peripheral circuit connected to the memory array and configured to control the plurality of memory planes to perform asynchronous operations; Wherein, the peripheral circuit includes at least two state machines; Each of the state machines is arranged corresponding to at least one of the plurality of storage planes, the state machine is connected to the memory interface and can receive control commands related to asynchronous operations of the corresponding storage planes from the memory interface in parallel, each of the state machines can independently process the control commands received to obtain control information of the corresponding storage plane, and perform parameter configuration according to the control commands; the time periods occupied by at least two of the state machines for processing the control commands and performing the parameter configuration are at least partially overlapped; The memory interface divides the received control command queue into multiple queues according to the number of state machines; the control commands in each queue are processed by the corresponding state machine; The peripheral circuit further includes: a sequence operation module connected to the multiple state machines and configured to determine the processing order of the control information by the peripheral circuit according to the control information of the multiple state machines.

2. The memory according to claim 1, wherein: The peripheral circuit is configured to control the plurality of memory planes to perform asynchronous operations according to control information of the plurality of state machines.

3. The memory according to claim 1, wherein: The state machine is specifically configured as follows: Sending a processing request to the sequence operation module according to the control command; The sequence operation module is specifically configured as follows: The processing order is determined according to the processing requests sent by multiple state machines.

4. The memory according to claim 1, wherein: The peripheral circuit also includes: a hardware operation module, connected to the sequence operation module and configured to sequentially determine the control parameters corresponding to the control information according to the processing sequence; A plurality of micro-processing units corresponding to each storage plane are connected to the hardware operation module and are respectively connected to the corresponding storage planes. The plurality of micro-processing units are configured to perform asynchronous operations on each storage plane according to the control parameters.

5. The memory according to claim 4, wherein: The at least one state machine is also respectively connected to the corresponding micro-processing unit and is configured to provide an enable signal to the micro-processing unit when receiving the control command.

6. The memory according to claim 5, wherein: The plurality of micro-processing units are further configured to: After completing the control operation on the storage plane based on one of the control commands, sending state information to the corresponding state machine; The state machine is further configured to receive a next control command after receiving the state information sent by the corresponding micro-processing unit.

7. The memory according to claim 4, wherein: The peripheral circuit also includes: A main processor is connected to the memory interface and the multiple micro-processing units, and is configured to receive status information sent by the multiple micro-processing units, and send total status information determined based on the multiple status information to the memory interface; wherein the total status information is used to indicate that the multiple micro-processing units have all ended control operations based on a set of control commands.

8. A method for controlling a memory, the method being executed by a peripheral circuit in the memory; The peripheral circuit includes at least one state machine; the method includes: The at least one state machine in the memory receives control commands related to asynchronous operations of each storage plane in the memory in parallel; wherein each of the state machines is arranged corresponding to at least one of the plurality of storage planes; The state machines independently process the received control commands to obtain control information of the corresponding storage planes; the state machines perform parameter configuration according to the control commands; wherein the time periods occupied by at least two of the state machines for processing the control commands and performing the parameter configurations are at least partially overlapped; The peripheral circuit controls the multiple storage planes to perform asynchronous operations based on the control information obtained by the state machine, including: determining a processing order for the control information according to the control information obtained by the state machine; processing the control information in sequence according to the processing order; and controlling the multiple storage planes to perform asynchronous operations according to the processed control information.

9. The method according to claim 8, wherein: The determining, according to the control information provided by the state machine, a processing order of the control information comprises: The sequence operation module in the peripheral circuit receives the processing requests sent by the multiple state machines based on the control command; The sequence operation module determines a processing order of the control information based on the processing request.

10. The method according to claim 9, wherein: The processing of the control information in sequence according to the processing order includes: The hardware operation module in the peripheral circuit determines the control parameters corresponding to the control information in sequence according to the control information provided by the state machine and in the processing order; The step of controlling the plurality of storage planes to perform asynchronous operations according to the processed control information includes: The plurality of micro-processing units in the peripheral circuit control the corresponding storage planes to perform asynchronous operations according to the control parameters; wherein the plurality of micro-processing units correspond to the plurality of storage planes respectively.

11. The method according to claim 10, wherein: The method further comprises: When receiving the control command, the state machine provides an enable signal to the microprocessing unit.

12. The method according to claim 11, wherein: The method further comprises: After the microprocessing unit completes the control operation on the storage plane based on the control information, sending state information to the corresponding state machine; After receiving the state information sent by the corresponding micro-processing unit, the state machine receives the next control command.

13. The method according to claim 10, wherein: The method further comprises: The main processor in the peripheral circuit receives the status information sent by the multiple micro-processing units and sends the total status information to the memory interface; wherein the total status information is used to indicate that the multiple micro-processing units have all ended the control operation based on a set of control commands.

14. A memory system comprising: The memory as claimed in any one of claims 1 to 7; A controller connected to the memory; The controller is configured to send a control command to the memory through a memory interface of the memory. 15 . The memory system according to claim 14 , the memory system being a solid state drive (SSD) or a memory card.

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