A spin logic device and a spin logic circuit

Abstract

A spin logic device relates to the field of circuit technology. The spin logic device includes a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a second ferromagnetic layer that are sequentially stacked. The first ferromagnetic layer and the second ferromagnetic layer include magnetic materials; the first barrier layer and the second barrier layer include metal oxide materials; the magnetization direction of the fixed layer is a fixed direction. This logic device realizes low current density, high operating speed, and low power consumption relying on magnetic tunnel junctions. Also disclosed are a spin logic circuit, a control method, and a processing device.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of circuit technologies, and in particular, to a spin logic device and a spin logic circuit. Background Art

[0002] A spin logic device is a type of logic device proposed based on the magnetic moment dynamics process of magnetic units. It can significantly improve the working efficiency while limiting the power consumption to a relatively low level, and thus has been widely studied.

[0003] A spin logic device in the prior art can achieve magnetic moment flipping based on the spin Hall effect. For example, a perpendicularly magnetized magnetic tunnel junction (MTJ) is placed on a cross-shaped heavy metal electrode, and two currents are passed through the electrode perpendicularly to each other, serving as two input channels respectively. By adjusting the input directions of the two currents and applying an auxiliary external magnetic field, 4 or more logic resistance states can be achieved.

[0004] However, for a logic device operating using this method, an external magnetic field needs to be introduced to flip the magnetic moment. In a complementary metal-oxide-semiconductor (CMOS) circuit, this may affect the normal functions of the working area around the device. The greater the degree of magnetic field dispersion, the more it affects the MTJ close packing and reduces the storage density. Moreover, when achieving magnetic moment flipping based on the spin Hall effect, the applied current density is relatively large, resulting in high thermal effects and power consumption. Summary of the Invention

[0005] Embodiments of the present application provide a spin logic device and a spin logic circuit, which can achieve magnetic moment flipping by utilizing the voltage controlled magnetization anisotropy (VCMA) effect and the spin transfer torque (STT) effect, effectively reducing power consumption, accelerating the operation speed, and improving the operation efficiency.

[0006] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0007] In the first aspect of the embodiments of the present application, a spin logic device is provided. The spin logic device includes a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a second ferromagnetic layer that are sequentially stacked, where: the first ferromagnetic layer and the second ferromagnetic layer include magnetic materials; the first barrier layer and the second barrier layer include metal oxide materials; the magnetization direction of the fixed layer is a fixed direction. Based on this solution, the first ferromagnetic layer, the first barrier layer, and the fixed layer in the spin logic device can form a first MTJ, and the fixed layer, the second barrier layer, and the second ferromagnetic layer can form a second MTJ. That is, the structure of the spin logic device includes two MTJs. Thus, when voltage pulses are input to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, the magnetic moment reversal of the first ferromagnetic layer and the second ferromagnetic layer can be realized based on the VCMA effect and the STT effect, so that the first MTJ and the second MTJ can exhibit different resistance values, and thus the spin logic device can exhibit different resistance states to realize logical operations. It can be understood that when the spin logic device realizes magnetic moment reversal based on the VCMA effect and the STT effect, no external magnetic field needs to be introduced. Therefore, it will not affect the normal functions of the working areas around the device. Moreover, when the magnetic moment reversal of the spin logic device is realized through the VCMA effect and the STT effect, the current is small and the power consumption is low, improving the operation efficiency.

[0008] Combined with the first aspect, in a possible implementation manner, the fixed layer includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer, and a fifth sub-layer that are sequentially stacked, where: the first sub-layer and the fifth sub-layer include magnetic materials; the second sub-layer and the fourth sub-layer include metal non-magnetic materials or alloy non-magnetic materials; the third sub-layer includes a magnetic multi-layer film [Ax / By]n, where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is the number of periods of [Ax / By]; the third sub-layer forms an antiferromagnetic coupling with the first sub-layer, and the third sub-layer forms an antiferromagnetic coupling with the fifth sub-layer. Based on this solution, the coercivity of the fixed layer can be significantly higher than that of the first ferromagnetic layer and the second ferromagnetic layer by sequentially stacking five sub-layers. Thus, the magnetic moment direction of the fixed layer is a fixed direction, while the magnetic moment directions of the first ferromagnetic layer and the second ferromagnetic layer will flip with different input voltages. It can be understood that once the magnetic moment direction of the fixed layer is determined to be upward or downward during thin film deposition, the magnetic moment direction of the fixed layer will not change again during the normal operation of the spin logic device.

[0009] Combined with the first aspect and the above possible implementation manner, in another possible implementation manner, A is one of cobalt, iron, and nickel, and B is one of platinum, palladium, ruthenium, and tantalum. Based on this solution, the third sub-layer can be a magnetic multi-layer film, and the ratio of x, y, and n can make the third sub-layer have perpendicular magnetic anisotropy.

[0010] Combined with the first aspect and the above possible implementation manners, in another possible implementation manner, the above spin logic device further includes a first electrode, which is in conductive contact with the above third sub-layer in the above fixed layer, and the above first electrode is isolated from the above first ferromagnetic layer, the above first barrier layer, the above second barrier layer, and the above second ferromagnetic layer by an insulating layer. Based on this solution, the first electrode is only in conductive contact with the third sub-layer and is isolated from the first sub-layer, the second sub-layer, the fourth sub-layer, the fifth sub-layer, the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer to prevent leakage.

[0011] Combined with the first aspect and the above possible implementation manners, in another possible implementation manner, the above magnetic material includes one or more combinations of cobalt, iron, cobalt iron, cobalt iron boron, iron boron, cobalt platinum, nickel iron, cobalt palladium, cobalt nickel, and cobalt ruthenium. Based on this solution, the thickness of the magnetic material can make the magnetic moments in the above first ferromagnetic layer, second ferromagnetic layer, first sub-layer, and fifth sub-layer have perpendicular magnetic anisotropy.

[0012] Combined with the first aspect and the above possible implementation manners, in another possible implementation manner, the above metal oxide material includes one of magnesium oxide, aluminum oxide, zinc oxide, magnesium aluminum oxide compound MgAlOx (for example, MgAl2Ox, MgAl2O4), and hafnium oxide. Based on this solution, the first barrier layer and the second barrier layer are insulating barrier layers.

[0013] Combined with the first aspect and the above possible implementation manners, in another possible implementation manner, the shape of the above spin logic device is cylindrical or ellipsoidal. Based on this solution, the shape of the spin logic device can be cylindrical or ellipsoidal.

[0014] In the second aspect of the embodiments of the present application, a spin logic circuit is provided. The spin logic circuit includes: a first controller, a spin logic device, and a reading circuit. The spin logic device includes: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, a second ferromagnetic layer, and a first electrode. Among them, the first ferromagnetic layer and the second ferromagnetic layer include magnetic materials; the first barrier layer and the second barrier layer include metal oxide materials; the magnetization direction of the fixed layer is a fixed direction; the first electrode is in conductive contact with the fixed layer, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer. The first controller is configured to ground the first electrode and input a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode, and input a third voltage pulse and a fourth voltage pulse between the second ferromagnetic layer and the first electrode. The first voltage pulse and the third voltage pulse are greater than the critical switching voltage, and the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage. The critical switching voltage is the voltage at which the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer flips. The reading circuit is configured to read the resistance value of the spin logic device and convert the resistance value of the spin logic device into a corresponding logic signal. Based on this solution, by inputting voltage pulses to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, and realizing the magnetic moment flipping of the first ferromagnetic layer and the second ferromagnetic layer based on the VCMA effect and the STT effect, the spin logic device can exhibit different resistance states to implement various logic operations. When this method realizes the magnetic moment flipping of the spin logic device based on the VCMA effect and the STT effect, the current is small, which can reduce power consumption, accelerate the operation speed, and improve the operation efficiency.

[0015] In combination with the second aspect, in a possible implementation, the reading circuit includes: a second controller and a comparator. The second controller is configured to turn off the grounding setting of the first electrode and input a reading voltage between the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device to read the resistance value of the spin logic device. The comparator is configured to compare the resistance value of the spin logic device with the resistance value of a preset reference resistor to output a corresponding logic signal. Based on this solution, by reading the resistance state of the spin logic device and comparing it with the comparator to output a corresponding logic signal, logical operations such as NOR operation, NAND operation, and NOT operation can be realized.

[0016] Combined with the second aspect and the above possible implementation manners, in another possible implementation manner, the above reading circuit further includes: an inverter, which is configured to invert the logic signal output by the above comparator. Based on this solution, by inverting the logic signal output by the comparator, logical operations such as logical OR operation, logical AND operation, and logical buffer (BUF) operation can be realized.

[0017] Combined with the second aspect and the above possible implementation manners, in another possible implementation manner, the resistance value of the above preset reference resistor is greater than the resistance value RMid of the spin logic device in the intermediate resistance state and less than the resistance value RHigh of the spin logic device in the high resistance state, or the resistance value of the above preset reference resistor is greater than the resistance value RLow of the spin logic device in the low resistance state and less than the resistance value RMid of the spin logic device in the intermediate resistance state; wherein, when the spin logic device is in the intermediate resistance state with the resistance value RMid, among the magnetic moment directions of the above first ferromagnetic layer and the fixed layer, and the magnetic moment directions of the above second ferromagnetic layer and the fixed layer, only one group is in the parallel state; when the spin logic device is in the high resistance state with the resistance value RHigh, the magnetic moment directions of the above first ferromagnetic layer, the fixed layer, and the above second ferromagnetic layer are in an anti-parallel state between adjacent layers; when the spin logic device is in the low resistance state with the resistance value RLow, the magnetic moment directions of the above first ferromagnetic layer, the fixed layer, and the above second ferromagnetic layer are in a parallel state between adjacent layers. Based on this solution, the resistance value of the preset reference resistor can be between RMid and RHigh, or between RLow and RMid. It can be understood that when the resistance value of the preset reference resistor is different, different logical operations can be realized according to different input second voltage pulses and / or fourth voltage pulses.

[0018] Combined with the second aspect and the above possible implementation manners, in another possible implementation manner, the spin logic circuit is configured to perform logical AND (AND), logical OR (OR), logical buffer (BUF), logical NAND (NAND), logical NOR (NOR), or logical NOT (NOT). Based on this solution, logical operations such as AND gate, OR gate, buffer gate, NAND gate, NOR gate, and NOT gate can be realized.

[0019] In a third aspect of the embodiments of the present application, a control method based on a spin logic device is provided. The spin logic device includes: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, a second ferromagnetic layer, and a first electrode; wherein, the first ferromagnetic layer and the second ferromagnetic layer include magnetic materials; the first barrier layer and the second barrier layer include metal oxide materials; the magnetization direction of the fixed layer is a fixed direction; the first electrode is in conductive contact with the fixed layer, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer; the method includes: grounding the first electrode, and inputting a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode respectively, and inputting a third voltage pulse and a fourth voltage pulse between the second ferromagnetic layer and the first electrode; the first voltage pulse and the third voltage pulse are greater than a critical switching voltage, the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage, and the critical switching voltage is the voltage at which the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer flips; reading the resistance value of the spin logic device and converting the resistance value of the spin logic device into a corresponding logic signal.

[0020] In combination with the third aspect, in a possible implementation manner, the reading the resistance value of the spin logic device and converting the resistance value of the spin logic device into a corresponding logic signal includes: turning off the grounding setting of the first electrode, and inputting a reading voltage between the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, and reading the resistance value of the spin logic device; comparing the resistance value of the spin logic device with the resistance value of a preset reference resistance to output a corresponding logic signal.

[0021] In combination with the third aspect and the above possible implementation manner, in another possible implementation manner, the method further includes: inverting the logic signal.

[0022] Combined with the third aspect and the above possible implementation manners, in another possible implementation manner, the resistance value of the preset reference resistor is greater than the resistance value RMid of the spin logic device in the intermediate resistance state and less than the resistance value RHigh of the spin logic device in the high resistance state, or the resistance value of the preset reference resistor is greater than the resistance value RLow of the spin logic device in the low resistance state and less than the resistance value RMid of the spin logic device in the intermediate resistance state; wherein, when the spin logic device is in the intermediate resistance state with the resistance value RMid, among the magnetic moment directions of the first ferromagnetic layer and the fixed layer, and the magnetic moment directions of the second ferromagnetic layer and the fixed layer, only one group is in the parallel state; when the spin logic device is in the high resistance state with the resistance value RHigh, the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in the anti-parallel state between adjacent layers; when the spin logic device is in the low resistance state with the resistance value RLow, the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in the parallel state between adjacent layers.

[0023] Combined with the third aspect and the above possible implementation manners, in another possible implementation manner, the spin logic device is configured to execute a logic AND gate (AND), a logic OR gate (OR), a logic buffer gate (BUF), a logic NAND gate (NAND), a logic NOR gate (NOR), or a logic NOT gate (NOT).

[0024] For the description of the effects of the third aspect and various implementation manners of the third aspect, reference can be made to the description of the corresponding effects of the second aspect and various implementation manners of the second aspect, which will not be elaborated herein.

[0025] In the fourth aspect of the embodiments of the present application, a processing device is provided. The processing device includes a memory, and at least one spin logic circuit as described in the second aspect above, and the at least one spin logic circuit is respectively coupled to the memory. Description of the Drawings

[0026] Figure 1 It is a schematic structural diagram of a spin logic device provided by an embodiment of the present application;

[0027] Figure 2 It is a schematic structural diagram of a fixed layer in a spin logic device provided by an embodiment of the present application;

[0028] Figure 3 It is a schematic structural diagram of another spin logic device provided by an embodiment of the present application;

[0029] Figure 4 It is a schematic diagram of the magnetic moment direction in a spin logic device provided by an embodiment of the present application;

[0030] Figure 5Schematic diagram of the magnetic moment direction in another spin logic device provided by the embodiment of the present application;

[0031] Figure 6 Schematic diagram of the correspondence between the magnetic moment direction of a spin logic device and the resistance state of the spin logic device provided by the embodiment of the present application;

[0032] Figure 7 Flow schematic diagram of a control method based on a spin logic device provided by the embodiment of the present application;

[0033] Figure 8 Application schematic diagram of a control method based on a spin logic device provided by the embodiment of the present application;

[0034] Figure 9 Another application schematic diagram of a control method based on a spin logic device provided by the embodiment of the present application;

[0035] Figure 10 Another flow schematic diagram of a control method based on a spin logic device provided by the embodiment of the present application;

[0036] Figure 11 Another application schematic diagram of a control method based on a spin logic device provided by the embodiment of the present application;

[0037] Figure 12 Schematic diagram of implementing a logic NOR gate by a control method based on a spin logic device provided by the embodiment of the present application;

[0038] Figure 13 Schematic diagram of implementing a logic NAND gate by a control method based on a spin logic device provided by the embodiment of the present application;

[0039] Figure 14 Schematic diagram of implementing a logic NOT gate by a control method based on a spin logic device provided by the embodiment of the present application;

[0040] Figure 15 Another schematic diagram of implementing a logic NOT gate by a control method based on a spin logic device provided by the embodiment of the present application;

[0041] Figure 16 Another application schematic diagram of a control method based on a spin logic device provided by the embodiment of the present application;

[0042] Figure 17 Schematic diagram of implementing a logic OR gate by a control method based on a spin logic device provided by the embodiment of the present application;

[0043] Figure 18 Schematic diagram of implementing a logic AND gate by a control method based on a spin logic device provided by the embodiment of the present application;

[0044] Figure 19 Schematic diagram of implementing a logic AND gate by a control method based on a spin logic device provided in an embodiment of the present application;

[0045] Figure 20 Schematic diagram of implementing a logic OR gate by another control method based on a spin logic device provided in an embodiment of the present application;

[0046] Figure 21 Schematic diagram of the structure of a spin logic circuit provided in an embodiment of the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. In the present application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, X and / or Y may represent: X exists alone, X and Y exist simultaneously, and Y exists alone, where X and Y may be singular or plural. "At least one (item)" or a similar expression thereof refers to any combination of these items, including any combination of single item (item) or plural items (items). For example, at least one (item) of a, b, or c may represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c may be single or multiple.

[0048] It should be noted that in the present application, words such as "exemplary" or "for example" are used to represent examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific manner.

[0049] It should be noted that in the embodiments of the present application, the magnetic moment directions of the ferromagnetic layer and the fixed layer are parallel (or, the magnetic moment directions of the ferromagnetic layer and the fixed layer are in a parallel state), which means that the magnetic moment directions of the ferromagnetic layer and the fixed layer are the same. The magnetic moment directions of the ferromagnetic layer and the fixed layer are antiparallel (or, the magnetic moment directions of the ferromagnetic layer and the fixed layer are in an antiparallel state) means that the magnetic moment directions of the ferromagnetic layer and the fixed layer are opposite.

[0050] First, the nouns involved in the embodiments of the present application are explained.

[0051] Magnetic Tunnel Junction MTJ: It is a "sandwich" structure in which two ferromagnetic layers are separated by an insulating barrier layer. When the magnetic moment directions of the two ferromagnetic layers are parallel to each other, the vertical tunneling resistance of the entire tunnel junction is in a lower state, while when the magnetic moment directions of the two ferromagnetic layers are antiparallel, it is in a higher resistance state. The high and low resistance states of the tunnel junction can achieve different logical operations.

[0052] Voltage-Controlled Magnetic Anisotropy VCMA Effect: It refers to the phenomenon that the magnetism of a substance changes with direction by applying a voltage. In an MTJ, if the magnetic moment of the ferromagnetic layer is to be flipped by 180 degrees (between the in-plane state and the antiparallel state), it needs to overcome the potential barrier Eb during the flipping process. This Eb is an important index for determining the thermal stability Δ of the MTJ. For an MTJ with perpendicular magnetization of the magnetic moment, when a voltage drop is introduced at both ends, due to the charge accumulation between the barrier layer and the ferromagnetic layer, the magnetic anisotropy of the ferromagnetic layer will gradually decrease until the magnetic moment forms an in-plane arrangement under the action of the voltage, and the perpendicular magnetic anisotropy completely disappears, that is, the VCMA effect. At this time, the potential barrier Eb for magnetic moment flipping is 0. It should be noted that the final action form of the VCMA effect is to make the magnetic moment of the ferromagnetic layer in the MTJ with perpendicular magnetization arranged in the plane, and it cannot achieve a deterministic 180° flip. The above action works by applying a voltage at both ends of the MTJ, thereby forming an electric field at both ends of the barrier layer inside the MTJ. The amplitude of the current passing through the MTJ can be very small, so it can significantly reduce the overall power consumption of the device operation, which is beneficial to the practical application of spin logic devices.

[0053] Spin Transfer Torque STT Effect: It refers to the phenomenon of current controlling the magnetic moment in magnetic multilayer thin films. The STT effect can rely on the current to control the magnetization direction of the magnetic thin film without an external magnetic field. Only by using the STT effect can the magnetic moment in the MTJ undergo a deterministic 180° flip. The voltage drop applied across the MTJ corresponding to the STT intensity required to make the magnetic moment undergo a deterministic 180° flip is called the critical flip voltage Vc. Different from the VCMA effect, the STT effect works by relying on the current passing through the MTJ. Therefore, for an MTJ that only works by the STT effect, its power consumption is relatively large. It should be particularly pointed out that the deterministic 180° flip of the magnetic moment driven by the STT effect is divided into two stages: the first stage, the magnetic moment flips from 0° to 90°; the second stage, the magnetic moment flips from 90° to 180°. The power consumption generated when the magnetic moment flips from 0° to 90° is much greater than the power consumption generated when the magnetic moment flips from 90° to 180°. Therefore, for the magnetic moment flip caused by the STT effect, its power consumption is mainly concentrated in the first stage. In the embodiments of the present application, the magnetic moment flips from 0° to 90° (the first stage) through the VCMA effect, and the magnetic moment flips from 90° to 180° through the STT effect. Therefore, when the VCMA effect and the STT effect are combined to achieve magnetic moment flipping, the power consumption is relatively low, which can improve the operation efficiency of spin logic devices.

[0054] It should be noted that the spin transfer torque STT effect in the embodiments of the present application can also be referred to as the spin transfer moment STT effect or the self-rotation moment STT effect.

[0055] Exemplarily, when a first voltage drop higher than the critical switching voltage Vc is applied to the MTJ, the direction of the magnetic moment is in-plane. Then, when the voltage drop is reduced to a second voltage drop below the critical switching voltage Vc, the in-plane oriented magnetic moment flips under the action of the STT current. For the process of reciprocating flipping between the parallel state and the antiparallel state, the polarity of the first voltage drop does not change, while the polarity of the second voltage drop is related to the flipping direction.

[0056] In order to reduce the power consumption of the spin logic device, accelerate the operation speed, and improve the operation efficiency, an embodiment of the present application provides a spin logic device. When implementing logical operations, the spin logic device has a low current density, a high operation speed, and low power consumption.

[0057] As Figure 1 shown, an embodiment of the present application provides a spin logic device, which includes a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a second ferromagnetic layer that are sequentially stacked. For example, as Figure 1 shown, the spin logic device includes, from top to bottom in sequence: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, and a second ferromagnetic layer.

[0058] Among them, the first ferromagnetic layer and the second ferromagnetic layer include magnetic materials. The magnetic materials may include one or more combinations of cobalt, iron, cobalt iron, cobalt iron boron, iron boron, cobalt platinum, nickel iron, cobalt palladium, cobalt nickel, and cobalt ruthenium. For example, the above-mentioned first ferromagnetic layer and second ferromagnetic layer can be made of magnetic materials with perpendicular anisotropy such as Co, Fe, CoFe, CoFeB, FeB, etc. or their combinations, and the thicknesses of the first ferromagnetic layer and the second ferromagnetic layer can support the magnetic moments in the first ferromagnetic layer and the second ferromagnetic layer to have perpendicular anisotropy.

[0059] The first barrier layer and the second barrier layer include metal oxide materials. Exemplarily, the metal oxide materials include one of magnesium oxide, aluminum oxide, zinc oxide, magnesium aluminum oxide compound MgAlOx (for example, MgAl2Ox, MgAl2O4), and hafnium oxide. For example, the first barrier layer and the second barrier layer can be made of metal oxides such as MgO, AlOx, and MgAlOx, and the first barrier layer and the second barrier layer are insulating barrier layers.

[0060] The magnetization direction of the above-mentioned fixed layer is a fixed direction. For example, the magnetization direction of the fixed layer is upward or downward. The coercivity of the fixed layer is significantly higher than that of the first ferromagnetic layer and the second ferromagnetic layer.

[0061] In one implementation, the fixed layer can be a composite layer of a multi-layer film, and its magnetic moment has perpendicular anisotropy. As Figure 2 shown, the fixed layer includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer, and a fifth sub-layer that are sequentially stacked.

[0062] Among them, the first sub-layer and the fifth sub-layer include magnetic materials. Exemplarily, the above-mentioned first sub-layer and fifth sub-layer can be made of magnetic materials with perpendicular anisotropy such as Co, Fe, CoFe, CoFeB, FeB, etc. or combinations thereof, and their thickness can support the magnetic moments in the first sub-layer and the fifth sub-layer to have perpendicular anisotropy.

[0063] The second sub-layer and the fourth sub-layer include metal non-magnetic materials or alloy non-magnetic materials. For example, the second sub-layer and the fourth sub-layer can be made of metal non-magnetic materials or alloy non-magnetic materials such as PtMn, IrMn, Ru, Ta, Pd, etc.

[0064] The third sub-layer includes a magnetic multi-layer film [Ax / By]n, where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is the number of periods of [Ax / By]. [Ax / By]n means that during the film preparation process, in the direction perpendicular to the film surface, A thin film with a thickness of x and B thin film with a thickness of y are alternately prepared. Exemplarily, A can be one of cobalt, iron, and nickel, and B can be one of platinum, palladium, ruthenium, and tantalum. For example, the third sub-layer can be a magnetic multi-layer film [Cox / Pty]n, and the ratio of x, y, and n can make the third sub-layer have perpendicular anisotropy.

[0065] Exemplarily, as Figure 3 shown, the above-mentioned spin logic device further includes a first electrode, which is in conductive contact with the third sub-layer in the fixed layer, isolated from other sub-layers in the fixed layer by an insulating layer, and the first electrode is also isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer. Combining Figure 3 shown, the first electrode is only in conductive contact with the third sub-layer, and is isolated from the first sub-layer, the second sub-layer, the fourth sub-layer, the fifth sub-layer, the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer to prevent leakage.

[0066] Exemplarily, the thickness and composition of the above-mentioned second sub-layer can form an antiferromagnetic coupling between the first sub-layer and the third sub-layer, and the thickness and composition of the fourth sub-layer can form an antiferromagnetic coupling between the third sub-layer and the fifth sub-layer. Due to the existence of antiferromagnetic coupling between the first sub-layer and the third sub-layer, and between the third sub-layer and the fifth sub-layer, the magnetic moment directions of the first sub-layer and the third sub-layer are anti-parallel, and the magnetic moment directions of the third sub-layer and the fifth sub-layer are also anti-parallel. The magnetic moment direction of the fixed layer is consistent with that of the first sub-layer and the fifth sub-layer.

[0067] For example, as Figure 4 shown, the magnetic moment direction of the third sub-layer is downward, the magnetic moment direction of the first sub-layer is upward, and the magnetic moment direction of the fifth sub-layer is also upward, that is, the magnetic moment directions of the first sub-layer and the third sub-layer are anti-parallel, and the magnetic moment directions of the third sub-layer and the fifth sub-layer are also anti-parallel. The magnetic moment direction of the fixed layer is consistent with that of the first sub-layer and the fifth sub-layer and is upward.

[0068] For another example, as Figure 5 shown, the magnetic moment direction of the third sub-layer is upward, the magnetic moment direction of the first sub-layer is downward, and the magnetic moment direction of the fifth sub-layer is also downward, that is, the magnetic moment directions of the first sub-layer and the third sub-layer are anti-parallel, and the magnetic moment directions of the third sub-layer and the fifth sub-layer are also anti-parallel. The magnetic moment direction of the fixed layer is consistent with that of the first sub-layer and the fifth sub-layer and is downward.

[0069] The above Figure 4 and Figure 5 V1 and V2 therein are input voltages. By respectively inputting voltages V1 and V2 to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, the magnetic moments of the first ferromagnetic layer and the second ferromagnetic layer can be flipped. As Figure 4 and Figure 5 shown, the magnetic moment directions of the first ferromagnetic layer and the second ferromagnetic layer may be upward or downward according to the polarity of the input voltage, while the magnetic moment direction of the fixed layer does not change.

[0070] It can be understood that the magnetic moment direction of the above fixed layer has been determined during the thin film deposition, or during the annealing after the thin film preparation, or during the annealing after the thin film is made into an MTJ device. As Figure 4 and Figure 5 shown, the magnetic moment direction of this fixed layer can be upward or downward. It should be noted that once the magnetic moment direction of the fixed layer is determined to be upward or downward during the thin film deposition (or during the annealing after the thin film preparation, or during the annealing after the thin film is made into an MTJ device), the magnetic moment direction of this fixed layer will not change during the normal operation of the spin logic device. That is to say, when the spin logic device is damaged, the orientation of its fixed layer may change and is inconsistent with the magnetic moment direction determined during the thin film deposition (or during the annealing after the thin film preparation, or during the annealing after the thin film is made into an MTJ device).

[0071] Exemplarily, the shape of the above spin logic device is cylindrical or ellipsoidal. The embodiments of the present application do not limit the specific shape of the spin logic device, and this is only an exemplary illustration here.

[0072] Combined with the above Figures 3 to 5As can be seen from the spin logic device shown, the first ferromagnetic layer, the first barrier layer, and the fixed layer in the spin logic device can form a first MTJ, and the fixed layer, the second barrier layer, and the second ferromagnetic layer can form a second MTJ. That is, the structure of the spin logic device can form two MTJs. Thus, when the magnetization directions of the first ferromagnetic layer and the second ferromagnetic layer in the spin logic device change, the first MTJ and the second MTJ can exhibit different resistance values, and thus the spin logic device can exhibit different resistance states.

[0073] Exemplarily, when the magnetization directions of the first ferromagnetic layer and the fixed layer are in a parallel state, and the magnetization directions of the second ferromagnetic layer and the fixed layer are in an anti-parallel state, the resistance value of the first MTJ is lower, and the resistance value of the second MTJ is higher. Therefore, the spin logic device is in an intermediate resistance state, and the resistance value of this intermediate resistance state can be denoted as RMid. When the magnetization directions of the first ferromagnetic layer and the fixed layer are in an anti-parallel state, and the magnetization directions of the second ferromagnetic layer and the fixed layer are in a parallel state, the resistance value of the first MTJ is higher, and the resistance value of the second MTJ is lower. Therefore, the spin logic device is also in an intermediate resistance state. That is, when only one of the magnetization directions of the first ferromagnetic layer and the fixed layer and the magnetization directions of the second ferromagnetic layer and the fixed layer is in a parallel state, the resistance value of the spin logic device is RMid.

[0074] For example, as Figure 6 shown in (a) of [reference], taking the magnetization direction of the fixed layer as downward as an example. When the magnetization direction of the first ferromagnetic layer (upward) and the magnetization direction of the fixed layer (downward) are anti-parallel, and the magnetization direction of the second ferromagnetic layer (downward) and the magnetization direction of the fixed layer (downward) are parallel, the resistance RTotal of the spin logic device is the intermediate resistance state RMid. When the magnetization direction of the first ferromagnetic layer (downward) and the magnetization direction of the fixed layer (downward) are parallel, and the magnetization direction of the second ferromagnetic layer (upward) and the magnetization direction of the fixed layer (downward) are anti-parallel, the resistance RTotal of the spin logic device is also the intermediate resistance state RMid.

[0075] For another example, as Figure 6 shown in (b) of [reference], taking the magnetization direction of the fixed layer as upward as an example. When the magnetization direction of the first ferromagnetic layer (upward) and the magnetization direction of the fixed layer (upward) are parallel, and the magnetization direction of the second ferromagnetic layer (downward) and the magnetization direction of the fixed layer (upward) are anti-parallel, the resistance RTotal of the spin logic device is the intermediate resistance state RMid. When the magnetization direction of the first ferromagnetic layer (downward) and the magnetization direction of the fixed layer (upward) are anti-parallel, and the magnetization direction of the second ferromagnetic layer (upward) and the magnetization direction of the fixed layer (upward) are parallel, the resistance RTotal of the spin logic device is also the intermediate resistance state RMid.

[0076] Exemplarily, when the magnetic moment directions of the first ferromagnetic layer and the fixed layer are in a parallel state, and the magnetic moment directions of the second ferromagnetic layer and the fixed layer are also in a parallel state, the resistance value of the first MTJ is low, and the resistance value of the second MTJ is also low. Therefore, the spin logic device is in a low-resistance state, and the resistance value of this low-resistance state can be denoted as RLow. That is, when the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in a parallel state between adjacent two layers, the resistance value of this spin logic device is RLow.

[0077] For example, as Figure 6 shown in (a) of

[0078] Taking the magnetic moment direction of the fixed layer being downward as an example. When the magnetic moment direction of the first ferromagnetic layer (downward) is parallel to the magnetic moment direction of the fixed layer (downward), and the magnetic moment direction of the second ferromagnetic layer (downward) is also parallel to the magnetic moment direction of the fixed layer (downward), the resistance RTotal of the spin logic device is in the low-resistance state RLow. Figure 6 shown in (b) of

[0079] Exemplarily, when the magnetic moment directions of the first ferromagnetic layer and the fixed layer are in an anti-parallel state, and the magnetic moment directions of the second ferromagnetic layer and the fixed layer are also in an anti-parallel state, the resistance value of the first MTJ is high, and the resistance value of the second MTJ is also high. Therefore, the spin logic device is in a high-resistance state, and the resistance value of this high-resistance state can be denoted as RHigh. That is, when the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in an anti-parallel state between adjacent two layers, the resistance value of this spin logic device is RHigh.

[0080] For example, as Figure 6 shown in (a) of

[0081] Taking the magnetic moment direction of the fixed layer being downward as an example. When the magnetic moment direction of the first ferromagnetic layer (upward) is anti-parallel to the magnetic moment direction of the fixed layer (downward), and the magnetic moment direction of the second ferromagnetic layer (upward) is also anti-parallel to the magnetic moment direction of the fixed layer (downward), the resistance RTotal of the spin logic device is in the high-resistance state RHigh. Figure 6 shown in (b) of

[0082] It can be understood that the structure of the spin logic device in the embodiments of the present application can form two MTJs, and the magnetization direction of the fixed layer in the spin logic device is fixed. Therefore, when the magnetic moment directions of the first ferromagnetic layer and the second ferromagnetic layer are different, the entire spin logic device can exhibit different resistance states to implement logical operations.

[0083] Combined with Figures 3 - 6 , such as Figure 7 shown, a control method based on a spin logic device provided by an embodiment of the present application, where the spin logic device in the control method is Figures 3 to 5 any of the spin logic devices shown. The method includes steps S701 - S702.

[0084] S701. Ground the first electrode, and input a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode respectively, and input a third voltage pulse and a fourth voltage pulse between the second ferromagnetic layer and the first electrode.

[0085] It can be understood that the above step S701 can be executed by a controller. For example, the controller can ground the first electrode through a switch.

[0086] Exemplarily, the above first voltage pulse and third voltage pulse are greater than the critical flip voltage, and the second voltage pulse and fourth voltage pulse are less than the critical flip voltage. The critical flip voltage is the voltage that can cause the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer to flip. This critical flip voltage can be denoted as Vc.

[0087] Optionally, the time interval between the above first voltage pulse and the second voltage pulse is less than a preset threshold, and the preset threshold is the time insufficient to change the magnetic moment of the first ferromagnetic layer. That is, when a second voltage pulse is input after an interval of a first duration after the first voltage pulse is input on the first ferromagnetic layer, the magnetic moment direction of the first ferromagnetic layer will not change, and the first duration is less than the preset threshold. Similarly, the time interval between the third voltage pulse and the fourth voltage pulse is also less than the preset threshold. In the following embodiments, only the case where the time interval between the first voltage pulse and the second voltage pulse is 0 and the time interval between the third voltage pulse and the fourth voltage pulse is 0 is taken as an example for illustration. That is, the first voltage pulse and the second voltage pulse are continuous in time, and the third voltage pulse and the fourth voltage pulse are continuous in time.

[0088] Exemplarily, after applying a first voltage pulse greater than the critical switching voltage to the first ferromagnetic layer, based on the VCMA effect, the magnetic moment of the first ferromagnetic layer is oriented in-plane. Then, after reducing the input voltage of the first ferromagnetic layer to a second voltage pulse less than the critical switching voltage, based on the STT effect, the magnetic moment of the first ferromagnetic layer flips. That is to say, the above-mentioned first voltage pulse is used to orient the magnetic moment of the first ferromagnetic layer in-plane, and the second voltage pulse is used to flip the magnetic moment of the first ferromagnetic layer.

[0089] The polarity of the above-mentioned second voltage pulse is related to the flipping direction of the first ferromagnetic layer. Taking the potential of the first ferromagnetic layer being higher than the potential of the fixed layer as a positive voltage and the potential of the first ferromagnetic layer being lower than the potential of the fixed layer as a negative voltage as an example. When the second voltage pulse is greater than 0 (the potential of the first ferromagnetic layer is higher than the potential of the fixed layer), the magnetic moment of the first ferromagnetic layer flips to the parallel state, that is, the magnetic moment directions of the first ferromagnetic layer and the fixed layer are in the parallel state. When the second voltage pulse is less than 0 (the potential of the first ferromagnetic layer is lower than the potential of the fixed layer), the magnetic moment of the first ferromagnetic layer flips to the antiparallel state, that is, the magnetic moment directions of the first ferromagnetic layer and the fixed layer are in the antiparallel state.

[0090] Exemplarily, after applying a third voltage pulse greater than the critical switching voltage to the second ferromagnetic layer, based on the VCMA effect, the magnetic moment of the second ferromagnetic layer is oriented in-plane. Then, after reducing the input voltage of the second ferromagnetic layer to a fourth voltage pulse less than the critical switching voltage, based on the STT effect, the magnetic moment of the second ferromagnetic layer flips. That is to say, the above-mentioned third voltage pulse is used to orient the magnetic moment of the second ferromagnetic layer in-plane, and the fourth voltage pulse is used to flip the magnetic moment of the second ferromagnetic layer.

[0091] The polarity of the above-mentioned fourth voltage pulse is related to the flipping direction of the second ferromagnetic layer. Taking the potential of the second ferromagnetic layer being higher than the potential of the fixed layer as a positive voltage and the potential of the second ferromagnetic layer being lower than the potential of the fixed layer as a negative voltage as an example. When the fourth voltage pulse is greater than 0 (the potential of the second ferromagnetic layer is higher than the potential of the fixed layer), the magnetic moment of the second ferromagnetic layer flips to the parallel state, that is, the magnetic moment directions of the second ferromagnetic layer and the fixed layer are in the parallel state. When the fourth voltage pulse is less than 0 (the potential of the second ferromagnetic layer is lower than the potential of the fixed layer), the magnetic moment of the second ferromagnetic layer flips to the antiparallel state, that is, the magnetic moment directions of the second ferromagnetic layer and the fixed layer are in the antiparallel state.

[0092] It should be noted that the amplitudes of the above-mentioned first voltage pulse and the third voltage pulse may be the same or different, and the amplitudes of the above-mentioned second voltage pulse and the fourth voltage pulse may be the same or different. The embodiments of the present application do not limit this.

[0093] Exemplarily, such as Figure 8As shown, the controller can ground the first electrode and input V1 (the first and second voltage pulses that are continuous in time) to the first ferromagnetic layer and input V2 (the third and fourth voltage pulses that are continuous in time) to the second ferromagnetic layer. The input times of V1 and V2 can be the same or different.

[0094] Combined with Figure 8 , as Figure 9 shown in (a) of Figure 9 , when the first and second voltage pulses that are continuous in time are input to the first ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the first ferromagnetic layer flips. Since the second voltage pulse is greater than 0, the direction of the magnetic moment of the first ferromagnetic layer is the same as that of the fixed layer. When the third and fourth voltage pulses that are continuous in time are input to the second ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer flips. Since the fourth voltage pulse is greater than 0, the direction of the magnetic moment of the second ferromagnetic layer is the same as that of the fixed layer. Therefore, the resistance RTotal of the spin logic device is in the low-resistance state RLow. As

[0095] Combined with Figure 8 , as Figure 9 shown in (b) of Figure 9 , when the first and second voltage pulses that are continuous in time are input to the first ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the first ferromagnetic layer flips. Since the second voltage pulse is greater than 0, the direction of the magnetic moment of the first ferromagnetic layer is the same as that of the fixed layer. When the third and fourth voltage pulses that are continuous in time are input to the second ferromagnetic layer, based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer flips. Since the fourth voltage pulse is less than 0, the direction of the magnetic moment of the second ferromagnetic layer is opposite to that of the fixed layer. Therefore, the resistance RTotal of the spin logic device is in the intermediate-resistance state RMid. As

[0096] Combined with Figure 8 , as Figure 9As shown in (c), a first voltage pulse and a second voltage pulse that are continuous in time are input to the first ferromagnetic layer. Based on the VCMA effect and the STT effect, the magnetic moment of the first ferromagnetic layer is reversed. Since the second voltage pulse is less than 0, the direction of the magnetic moment of the first ferromagnetic layer is opposite to the direction of the magnetic moment of the fixed layer. A third voltage pulse and a fourth voltage pulse that are continuous in time are input to the second ferromagnetic layer. Based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer is reversed. Since the fourth voltage pulse is greater than 0, the direction of the magnetic moment of the second ferromagnetic layer is the same as the direction of the magnetic moment of the fixed layer. Therefore, the resistance RTotal of the spin logic device is in the intermediate resistance state RMid. As Figure 9 As shown in (c), when the input second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is in the intermediate resistance state RMid.

[0097] Combined with Figure 8 , as Figure 9 As shown in (d), a first voltage pulse and a second voltage pulse that are continuous in time are input to the first ferromagnetic layer. Based on the VCMA effect and the STT effect, the magnetic moment of the first ferromagnetic layer is reversed. Since the second voltage pulse is less than 0, the direction of the magnetic moment of the first ferromagnetic layer is opposite to the direction of the magnetic moment of the fixed layer. A third voltage pulse and a fourth voltage pulse that are continuous in time are input to the second ferromagnetic layer. Based on the VCMA effect and the STT effect, the magnetic moment of the second ferromagnetic layer is reversed. Since the fourth voltage pulse is less than 0, the direction of the magnetic moment of the second ferromagnetic layer is opposite to the direction of the magnetic moment of the fixed layer. Therefore, the resistance RTotal of the spin logic device is in the high resistance state RHigh. As Figure 9 As shown in (d), when the input second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance RTotal of the spin logic device is in the high resistance state RHigh.

[0098] It can be understood that when different voltage pulses are input to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, the directions of the magnetic moments of the first ferromagnetic layer and the second ferromagnetic layer are different, and the spin logic device can exhibit different resistance states.

[0099] Optionally, the pulse widths of the above first voltage pulse and third voltage pulse can be less than (but not limited to) 2 ns, and the pulse widths of the above second voltage pulse and fourth voltage pulse can be less than (but not limited to) 10 ns to reduce the energy consumption of the spin logic device.

[0100] S702. Read the resistance value of the spin logic device and convert the resistance value of the spin logic device into a corresponding logic signal.

[0101] It can be understood that the above step S702 can be implemented by a reading circuit. The reading circuit can include a controller and a comparator.

[0102] Exemplarily, after the above step S701, the spin logic device will present different resistance states, and the resistance value of the spin logic device can be read and converted into corresponding logic signals to implement different logical operations.

[0103] Exemplarily, as Figure 10 shown, the above step S702 may include steps S7021 - S7022.

[0104] S7021. Turn off the grounding setting of the first electrode, and input a reading voltage between the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device to read the resistance value of the spin logic device.

[0105] It can be understood that the above step S7021 can be implemented by a controller in the reading circuit.

[0106] Exemplarily, as Figure 11 shown, the controller in the reading circuit can turn off the grounding setting of the first electrode in the spin logic device through a switch, input a reading voltage between the first ferromagnetic layer and the second ferromagnetic layer, and read the resistance value of the spin logic device. Figure 11 The reading circuit shown can implement logical NOR operation, logical NAND operation, and logical NOT operation.

[0107] Optionally, an inverter can also be added after the comparator in the above Figure 11 shown reading circuit to implement other logical operations. For example, logical OR operation, logical AND operation, logical buffer (BUF) operation.

[0108] It can be understood that the voltage value of the above input voltage is not sufficient to change the direction of the magnetic moment of the spin logic device, that is, the input of the above input voltage will not change the resistance value of the spin logic device, and the resistance value of the spin logic device read through step S7021 is still the resistance value presented after step S701.

[0109] Exemplarily, the controller in the above reading circuit can read the resistance value of the spin logic device based on Ohm's law.

[0110] S7022. Compare the resistance value of the spin logic device with the resistance value of a preset reference resistance to output corresponding logic signals.

[0111] It can be understood that the above step S7021 can be implemented by a comparator in the reading circuit.

[0112] Exemplarily, the resistance value of the above-mentioned preset reference resistor can be greater than the resistance value RMid of the spin logic device in the intermediate resistance state and less than the resistance value RHigh of the spin logic device in the high resistance state. The resistance value of this preset reference resistor is denoted as R1Ref; alternatively, the resistance value of the preset reference resistor is greater than the resistance value RLow of the spin logic device in the low resistance state and less than the resistance value RMid of the spin logic device in the intermediate resistance state. The resistance value of this preset reference resistor is denoted as R2Ref.

[0113] Exemplarily, when the resistance RTotal of the spin logic device of the input comparator is greater than the resistance value of the preset reference resistor, a high level is output, denoted as "1"; when the resistance RTotal of the spin logic device of the input comparator is less than the resistance value of the preset reference resistor, a low level is output, denoted as "0". That is, the logic signal processor of the input and output depends on the value of the preset reference voltage. Different logic operations can be achieved when the preset reference voltage is different.

[0114] For example, in combination with Figure 9 and Figure 11 , as Figure 12 shown, taking the resistance value of the preset reference resistor as R1Ref as an example. As Figure 9 shown, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RLow. Since RLow is less than R1Ref, a low level is output, denoted as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, a low level is output, denoted as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, a low level is output, denoted as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RHigh. Since RHigh is greater than R1Ref, a high level is output, denoted as "1". That is, as Figure 12 shown, when the resistance value of the preset reference resistor is R1Ref, according to the differences in the input second voltage pulse and fourth voltage pulse, the logic NOR (NOR) operation can be achieved.

[0115] For example, in combination with Figure 9 and Figure 11 , as Figure 13 shown, taking the resistance value of the preset reference resistor as R2Ref as an example. As Figure 9As shown, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is RLow. Since RLow is less than R2Ref, the output is a low level, denoted as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, the output is a high level, denoted as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, the output is a high level, denoted as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance RTotal of the spin logic device is RHigh. Since RHigh is greater than R2Ref, the output is a high level, denoted as "1". That is, as Figure 13 shown, when the resistance value of the preset reference resistor is R2Ref, according to the differences in the input second voltage pulse and fourth voltage pulse, the logic NAND operation can be achieved.

[0116] Exemplarily, in one implementation manner of implementing the logic NOT operation, it is achieved by setting the resistance value of the preset reference resistor to R1Ref, initializing any one of the second voltage pulse and the fourth voltage pulse to input "0", and only using the uninitialized end of the second voltage pulse and the fourth voltage pulse as the input, then the logic NOT operation can be achieved.

[0117] For example, taking the initialization of the second voltage pulse to "0" as an example. Combining Figure 9 and Figure 11 , as Figure 14 shown in (a) of Figure 9 , taking the resistance value of the preset reference resistor as R1Ref as an example. As Figure 14 shown, when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, the output is a low level, denoted as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance RTotal of the spin logic device is RHigh. Since RHigh is greater than R1Ref, the output is a high level, denoted as "1". That is, as

[0118] shown in (a) of Figure 9 and Figure 11 , when the resistance value of the preset reference resistor is R1Ref and the second voltage pulse is initialized to "0", according to the differences in the input fourth voltage pulse, the logic NOT operation can be achieved. Figure 14As shown in (b) therein, taking the resistance value of the preset reference resistor as R1Ref as an example. As Figure 9 shown, when the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RHigh. Since RHigh is greater than R1Ref, a high level is output, denoted as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, a low level is output, denoted as "0". That is, as Figure 14 shown in (b) therein, when the resistance value of the preset reference resistor is R1Ref and the fourth voltage pulse is initialized to "0", a logical NOT operation can be achieved according to the different input second voltage pulses.

[0119] Exemplarily, another implementation method when implementing the logical NOT operation is to set the resistance value of the preset reference resistor to R2Ref, initialize any one of the second voltage pulse and the fourth voltage pulse to input "1", and only use the uninitialized end of the second voltage pulse and the fourth voltage pulse as the input, then the logical NOT operation can be achieved.

[0120] For example, taking the second voltage pulse initialized to "1" as an example. Combining Figure 9 and Figure 11 , as Figure 15 shown in (a) therein, taking the resistance value of the preset reference resistor as R2Ref as an example. As Figure 9 shown, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RLow. Since RLow is less than R2Ref, a low level is output, denoted as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, a high level is output, denoted as "1". That is, as Figure 15 shown in (a) therein, when the resistance value of the preset reference resistor is R2Ref and the second voltage pulse is initialized to "1", a logical NOT operation can be achieved according to the different input fourth voltage pulses.

[0121] Again, for example, taking the fourth voltage pulse initialized to "1" as an example. Combining Figure 9 and Figure 11 , as Figure 15 shown in (b) therein, taking the resistance value of the preset reference resistor as R2Ref as an example. As Figure 9As shown, when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, a high level is output, denoted as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is RLow. Since RLow is less than R2Ref, a low level is output, denoted as "0". That is, as shown in (b) of Figure 15 , when the resistance value of the preset reference resistor is R2Ref and the fourth voltage pulse is initialized to "1", a logical NOT operation can be achieved according to the different input second voltage pulses.

[0122] Optionally, as shown in Figure 16 , when implementing logical OR operation, logical AND operation, and logical buffer (BUF) operation, an inverter can be added after the comparator shown in Figure 11 to swap the high and low levels of the output.

[0123] Exemplarily, as shown in Figure 16 , when implementing a logical OR operation, the resistance value of the preset reference resistor is set to R1Ref, and the OR logic can be achieved according to the different input second voltage pulses and fourth voltage pulses.

[0124] For example, as shown in Figure 9 and Figure 16 , as shown in Figure 17 , taking the resistance value of the preset reference resistor as R1Ref as an example. As shown in Figure 9 , when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is RLow. Since RLow is less than R1Ref, the output of the comparator is a low level, and after being inverted by the inverter, a high level is output, denoted as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, the output of the comparator is a low level, and after being inverted by the inverter, a high level is output, denoted as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, the output of the comparator is a low level, and after being inverted by the inverter, a high level is output, denoted as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance RTotal of the spin logic device is RHigh. Since RHigh is greater than R1Ref, the output of the comparator is a high level, and after being inverted by the inverter, a low level is output, denoted as "0". That is, as shown in Figure 16 and Figure 17As shown, when the resistance value of the preset reference resistor is R1Ref, logical OR gate (OR) operations can be achieved based on the differences between the input second voltage pulse and the fourth voltage pulse.

[0125] Exemplarily, in combination with Figure 16 As shown, when implementing logical AND gate (AND) operations, the resistance value of the preset reference resistor is set to R2Ref, and based on the differences between the input second voltage pulse and the fourth voltage pulse, AND logic can be achieved.

[0126] For example, in combination with Figure 9 and Figure 16 as Figure 18 shown, taking the resistance value of the preset reference resistor as R2Ref as an example. As Figure 9 shown, when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RLow. Since RLow is less than R2Ref, the output of the comparator is at a low level, and after being inverted by the inverter, the output is at a high level, denoted as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, the output of the comparator is at a high level, and after being inverted by the inverter, the output is at a low level, denoted as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, the output of the comparator is at a high level, and after being inverted by the inverter, the output is at a low level, denoted as "0". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RHigh. Since RHigh is greater than R2Ref, the output of the comparator is at a high level, and after being inverted by the inverter, the output is at a low level, denoted as "0". That is, in combination with Figure 16 and 18 shown, when the resistance value of the preset reference resistor is R2Ref, logical AND gate (AND) operations can be achieved based on the differences between the input second voltage pulse and the fourth voltage pulse.

[0127] Exemplarily, in combination with Figure 16 shown, one implementation method when implementing logical buffer (BUF) operations is to set the resistance value of the preset reference resistor to R1Ref, initialize either the second voltage pulse or the fourth voltage pulse as the input "0", and only use the uninitialized end of the second voltage pulse and the fourth voltage pulse as the input to achieve logical buffer (BUF) operations.

[0128] For example, taking the initialization of the second voltage pulse as "0" as an example. In combination with Figure 9 and Figure 16 asFigure 19 As shown in (a) therein, taking the resistance value of the preset reference resistor as R1Ref as an example. As Figure 9 shown, when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, the output of the comparator is at a low level, and after being inverted by the inverter, the output is at a high level, denoted as "1". When the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RHigh. Since RHigh is greater than R1Ref, the output of the comparator is at a high level, and after being inverted by the inverter, the output is at a low level, denoted as "0". That is, combining Figure 16 and Figure 19 as shown in (a) therein, with the resistance value of the preset reference resistor being R1Ref, when the second voltage pulse is initialized to "0", according to the different input fourth voltage pulses, the logic buffer (BUF) operation can be realized.

[0129] For another example, taking the fourth voltage pulse initialized to "0" as an example. Combining Figure 9 and Figure 16 as shown in Figure 19 as shown in (b) therein, taking the resistance value of the preset reference resistor as R1Ref as an example. As Figure 9 shown, when the second voltage pulse is "0" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RHigh. Since RHigh is greater than R1Ref, the output of the comparator is at a high level, and after being inverted by the inverter, the output is at a low level, denoted as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RMid. Since RMid is less than R1Ref, the output of the comparator is at a low level, and after being inverted by the inverter, the output is at a high level, denoted as "1". That is, combining Figure 16 and Figure 19 as shown in (b) therein, with the resistance value of the preset reference resistor being R1Ref, when the fourth voltage pulse is initialized to "0", according to the different input second voltage pulses, the logic buffer (BUF) operation can be realized.

[0130] Exemplarily, combining Figure 16 as shown, another implementation method when realizing the logic buffer (BUF) operation is to set the resistance value of the preset reference resistor to R2Ref, initialize any one of the second voltage pulse and the fourth voltage pulse as the input "1", and only use the uninitialized end of the second voltage pulse and the fourth voltage pulse as the input, then the logic buffer (BUF) operation can be realized.

[0131] For example, taking the second voltage pulse initialized to "1" as an example. Combining Figure 9 andFigure 16 , as shown in (a) of Figure 20 , taking the resistance value of the preset reference resistor as R2Ref as an example. As shown in Figure 9 , when the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RLow. Since RLow is less than R2Ref, the output of the comparator is at a low level. After being inverted by the inverter, the output is at a high level, denoted as "1". When the second voltage pulse is "1" and the fourth voltage pulse is "0", the resistance value RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, the output of the comparator is at a high level. After being inverted by the inverter, the output is at a low level, denoted as "0". That is, combining Figure 16 and Figure 20 as shown in (a) of , with the resistance value of the preset reference resistor being R2Ref, when the second voltage pulse is initialized to "1", according to the different input fourth voltage pulses, the logic buffer (BUF) operation can be achieved.

[0132] For another example, taking the fourth voltage pulse initialized to "1" as an example. Combining Figure 9 and Figure 16 , as shown in (b) of Figure 20 , taking the resistance value of the preset reference resistor as R2Ref as an example. As shown in Figure 9 , when the second voltage pulse is "0" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RMid. Since RMid is greater than R2Ref, the output of the comparator is at a high level. After being inverted by the inverter, the output is at a low level, denoted as "0". When the second voltage pulse is "1" and the fourth voltage pulse is "1", the resistance value RTotal of the spin logic device is RLow. Since RLow is less than R2Ref, the output of the comparator is at a low level. After being inverted by the inverter, the output is at a high level, denoted as "1". That is, combining Figure 16 and Figure 20 as shown in (b) of , with the resistance value of the preset reference resistor being R2Ref, when the fourth voltage pulse is initialized to "1", according to the different input second voltage pulses, the logic buffer (BUF) operation can be achieved.

[0133] It should be noted that in the embodiments of the present application, different logic operations can be achieved by combining the above solutions according to the different input second voltage pulses and / or fourth voltage pulses by selecting different resistance values as the resistance value of the preset reference resistor.

[0134] It can be understood that the control method based on spin logic devices provided by the embodiments of the present application inputs voltage pulses to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device, and realizes the magnetic moment reversal of the first ferromagnetic layer and the second ferromagnetic layer based on the VCMA effect and the STT effect, so that the spin logic device can exhibit different resistance states, and thus can realize various logic operations when comparing and outputting with a comparator. When this method realizes the magnetic moment reversal of the spin logic device based on the VCMA effect and the STT effect, the current is small, which can reduce power consumption, speed up the operation speed, and improve the operation efficiency.

[0135] As Figure 21 shown, a spin logic circuit 2100 provided by an embodiment of the present application includes a first controller 2101, a reading circuit 2102, and a spin logic device 2103. The spin logic device 2103 can be Figures 3 to 5 any of the spin logic devices shown.

[0136] The first controller 2101 is configured to ground the first electrode in the spin logic device 2103, and input a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode in the spin logic device 2103, and input a third voltage pulse and a fourth voltage pulse between the second ferromagnetic layer and the first electrode. The first voltage pulse and the third voltage pulse are greater than the critical switching voltage, and the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage. The critical switching voltage is the voltage that can cause the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer to reverse.

[0137] The reading circuit 2102 is configured to read the resistance value of the spin logic device 2103 and convert the resistance value of the spin logic device 2103 into a corresponding logic signal.

[0138] Exemplarily, the reading circuit 2102 may include a second controller 2102a and a comparator 2102b. The second controller 2102a is configured to turn off the grounding setting of the first electrode, and input a reading voltage between the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device 2103 to read the resistance value of the spin logic device 2103. The comparator 2102b is configured to compare the resistance value of the spin logic device 2103 with the resistance value of a preset reference resistance to output a corresponding logic signal. The reading circuit 2102 can be used to implement operations such as logic NOR operation, logic NAND operation, and logic NOT operation.

[0139] Optionally, the above reading circuit 2102 may further include an inverter 2102c, which is configured to invert the logic signal output by the comparator 2102b to implement, for example, logical OR operation, logical AND operation, and logical buffer (BUF) operation.

[0140] All relevant contents of the steps involved in the above method embodiments can be cited in the function descriptions of the corresponding circuit modules of the spin logic circuit 2100, and will not be elaborated here.

[0141] Exemplarily, an embodiment of the present application further provides a processing device, which includes a memory and at least one spin logic circuit 2100 as described above Figure 21 shown. The at least one spin logic circuit 2100 is respectively coupled to the memory.

[0142] The steps of the methods or algorithms described in connection with the disclosure of the present application may be implemented in hardware, or may be implemented by a processor executing software instructions. The software instructions may be composed of corresponding software modules, and the software modules may be stored in a random access memory (RAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), register, hard disk, removable hard disk, read-only optical disc (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and the storage medium may be located in an ASIC. Additionally, the ASIC may be located in a core network interface device. Of course, the processor and the storage medium may also exist as discrete components in the core network interface device.

[0143] Those skilled in the art should be able to realize that in the above one or more examples, the functions described in the present application can be implemented by hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transmission of a computer program from one place to another. The storage media can be any available medium accessible by a general-purpose or special-purpose computer.

[0144] The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present application. It should be understood that the above description is only the specific embodiments of the present application and is not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present application shall be included within the protection scope of the present application.

Claims

1. A spin logic device, characterized in that, the spin logic device includes a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, a second ferromagnetic layer, and a first electrode which are sequentially stacked, wherein: the first ferromagnetic layer and the second ferromagnetic layer include magnetic materials; the first barrier layer and the second barrier layer include metal oxide materials; the magnetization direction of the fixed layer is a fixed direction; the fixed layer includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer and a fifth sub-layer which are sequentially stacked, wherein: the first sub-layer and the fifth sub-layer include magnetic materials; the second sub-layer and the fourth sub-layer include metal non-magnetic materials or alloy non-magnetic materials; the third sub-layer includes a magnetic multilayer film [Ax / By]n, where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is the number of periods of [Ax / By]; the third sub-layer forms an antiferromagnetic coupling with the first sub-layer, and the third sub-layer forms an antiferromagnetic coupling with the fifth sub-layer; the first electrode is in conductive contact with the third sub-layer in the fixed layer, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer.

2. The spin logic device according to claim 1, characterized in that, A is one of cobalt, iron, and nickel, and B is one of platinum, palladium, ruthenium, and tantalum.

3. The spin logic device according to claim 1 or 2, characterized in that, the magnetic material includes one or a combination of cobalt, iron, cobalt iron, cobalt iron boron, iron boron, cobalt platinum, nickel iron, cobalt palladium, cobalt nickel, and cobalt ruthenium.

4. The spin logic device according to claim 1, characterized in that, the metal oxide material includes one of magnesium oxide, aluminum oxide, zinc oxide, MgAlOx, and hafnium oxide.

5. The spin logic device according to claim 1, characterized in that, the spin logic device is in a cylindrical or ellipsoidal shape.

6. A spin logic circuit, characterized in that, the spin logic circuit includes: a first controller, a spin logic device, and a reading circuit; the spin logic device includes: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, a second ferromagnetic layer, and a first electrode; wherein, the first ferromagnetic layer and the second ferromagnetic layer include magnetic materials; the first barrier layer and the second barrier layer include metal oxide materials; the magnetization direction of the fixed layer is a fixed direction; The fixed layer includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer, and a fifth sub-layer that are stacked in sequence, where: the first sub-layer and the fifth sub-layer include magnetic materials; the second sub-layer and the fourth sub-layer include metal non-magnetic materials or alloy non-magnetic materials; the third sub-layer includes a magnetic multi-layer film [Ax / By]n, where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is the number of periods of [Ax / By]; the third sub-layer forms an antiferromagnetic coupling with the first sub-layer, and the third sub-layer forms an antiferromagnetic coupling with the fifth sub-layer; The first electrode is in conductive contact with the third sub-layer in the fixed layer, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer; The first controller is configured to ground the first electrode, and input a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode, and input a third voltage pulse and a fourth voltage pulse between the second ferromagnetic layer and the first electrode; the first voltage pulse and the third voltage pulse are greater than the critical switching voltage, the second voltage pulse and the fourth voltage pulse are less than the critical switching voltage, and the critical switching voltage is the voltage at which the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer flips; The reading circuit is configured to read the resistance value of the spin logic device and convert the resistance value of the spin logic device into a corresponding logic signal.

7. The spin logic circuit according to claim 6, wherein, The reading circuit includes: a second controller and a comparator, The second controller is configured to turn off the grounding setting of the first electrode, and input a reading voltage between the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device to read the resistance value of the spin logic device; The comparator is configured to compare the resistance value of the spin logic device with the resistance value of a preset reference resistance to output a corresponding logic signal.

8. The spin logic circuit according to claim 7, wherein, The reading circuit further includes: an inverter, The inverter is configured to invert the logic signal output by the comparator.

9. The spin logic circuit according to claim 7 or 8, wherein, The resistance value of the preset reference resistor is greater than the resistance value RMid of the spin logic device in the intermediate resistance state and less than the resistance value RHigh of the spin logic device in the high resistance state, or the resistance value of the preset reference resistor is greater than the resistance value RLow of the spin logic device in the low resistance state and less than the resistance value RMid of the spin logic device in the intermediate resistance state; wherein, when the spin logic device is in the intermediate resistance state with the resistance value RMid, among the magnetic moment directions of the first ferromagnetic layer and the fixed layer, and the magnetic moment directions of the second ferromagnetic layer and the fixed layer, only one group is in the parallel state; when the spin logic device is in the high resistance state with the resistance value RHigh, the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in the anti-parallel state between adjacent layers; when the spin logic device is in the low resistance state with the resistance value RLow, the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in the parallel state between adjacent layers.

10. The spin logic circuit according to claim 6, wherein, the spin logic circuit is configured to execute a logic AND gate, a logic OR gate, a logic YES gate, a logic NAND gate, a logic NOR gate, or a logic NOT gate.

11. A control method based on a spin logic device, wherein, the spin logic device includes: a first ferromagnetic layer, a first barrier layer, a fixed layer, a second barrier layer, a second ferromagnetic layer, and a first electrode; wherein, the first ferromagnetic layer and the second ferromagnetic layer include magnetic materials; the first barrier layer and the second barrier layer include metal oxide materials; the magnetization direction of the fixed layer is a fixed direction; the fixed layer includes a first sub-layer, a second sub-layer, a third sub-layer, a fourth sub-layer, and a fifth sub-layer which are sequentially stacked, wherein: the first sub-layer and the fifth sub-layer include magnetic materials; the second sub-layer and the fourth sub-layer include metal non-magnetic materials or alloy non-magnetic materials; the third sub-layer includes a magnetic multi-layer film [Ax / By]n, where A is a ferromagnetic metal element, B is a heavy metal element, x is the thickness of A, y is the thickness of B, and n is the number of periods of [Ax / By]; the third sub-layer forms an antiferromagnetic coupling with the first sub-layer, and the third sub-layer forms an antiferromagnetic coupling with the fifth sub-layer; the first electrode is in conductive contact with the third sub-layer in the fixed layer, and the first electrode is isolated from the first ferromagnetic layer, the first barrier layer, the second barrier layer, and the second ferromagnetic layer by an insulating layer; the method includes: grounding the first electrode, and inputting a first voltage pulse and a second voltage pulse between the first ferromagnetic layer and the first electrode respectively, and inputting a third voltage pulse and a fourth voltage pulse between the second ferromagnetic layer and the first electrode; the first voltage pulse and the third voltage pulse are greater than the critical flip voltage, the second voltage pulse and the fourth voltage pulse are less than the critical flip voltage, and the critical flip voltage is the voltage at which the magnetic moment of the first ferromagnetic layer or the second ferromagnetic layer flips. Read the resistance value of the spin logic device and convert the resistance value of the spin logic device into a corresponding logic signal.

12. The method according to claim 11, wherein, the reading the resistance value of the spin logic device and converting the resistance value of the spin logic device into a corresponding logic signal includes: Turn off the grounding setting of the first electrode, and input a reading voltage to the first ferromagnetic layer and the second ferromagnetic layer of the spin logic device to read the resistance value of the spin logic device; Compare the resistance value of the spin logic device with the resistance value of a preset reference resistance to output a corresponding logic signal.

13. The method according to claim 12, wherein, the method further includes: Inverting the logic signal.

14. The method according to claim 12 or 13, wherein, the resistance value of the preset reference resistance is greater than the resistance value RMid of the spin logic device in the intermediate resistance state and less than the resistance value RHigh of the spin logic device in the high resistance state, or the resistance value of the preset reference resistance is greater than the resistance value RLow of the spin logic device in the low resistance state and less than the resistance value RMid of the spin logic device in the intermediate resistance state; wherein, when the spin logic device is in the intermediate resistance state with the resistance value RMid, only one of the magnetic moment directions of the first ferromagnetic layer and the fixed layer, and the magnetic moment directions of the second ferromagnetic layer and the fixed layer is in a parallel state; when the spin logic device is in the high resistance state with the resistance value RHigh, the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in an anti-parallel state between adjacent layers; when the spin logic device is in the low resistance state with the resistance value RLow, the magnetic moment directions of the first ferromagnetic layer, the fixed layer, and the second ferromagnetic layer are in a parallel state between adjacent layers.

15. The method according to claim 11, wherein, the spin logic device is configured to perform a logic AND gate, a logic OR gate, a logic YES gate, a logic NAND gate, a logic NOR gate, or a logic NOT gate.

16. A processing device, wherein, the processing device includes a memory, and at least one spin logic circuit according to any one of claims 6-10, and the at least one spin logic circuit is respectively coupled to the memory.

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