Magnetoresistive Random Access Memory

Abstract

The present invention discloses a magnetoresistive random access memory. Each memory unit in the magnetoresistive random access memory includes two non-volatile memory units, three N-type transistors, and three P-type transistors. Each N-type transistor is connected in parallel to a corresponding P-type transistor. A transmission gate formed by a parallel structure of the N-type transistor and the P-type transistor can provide a bidirectional current in a write operation to avoid source degradation.

Description

Technical Field

[0001] The invention relates to a magnetoresistive random access memory, and in particular to a spin transfer torque magnetoresistive random access memory which can avoid source degradation to increase writing speed and reduce writing voltage. Background Art

[0002] Compared to traditional memory that uses electric charge to store bit information, magnetoresistive random-access memory (MRAM) uses magnetic impedance effect to store data. It has the advantages of high-speed data transmission, high density, light size, low power consumption and impact resistance, and is therefore particularly suitable for use in high-end portable electronic products.

[0003] Spin torque transfer (STT) is an operation form of MRAM, which uses a multi-layer thin film structure (magnetic tunnel junction, MTJ) as a storage unit, uses the spin of electrons to generate torque, and then stores different data by changing the magnetization direction of each thin film.

[0004] Figure 1A and Figure 1B Schematic diagram of a spin transfer torque magnetoresistive random access memory (STT MRAM) 100 in the prior art. The spin transfer torque magnetoresistive random access memory 100 includes a memory cell 10, bit lines BL1 and BL2, a word line WL, and a source line SL. The memory cell 10 of the prior art adopts a 3T2M architecture, that is, it includes three N-type transistors N1-N3 and two non-volatile memory cells MTJ1 and MTJ2. When performing a write operation in a parallel state and an anti-parallel state, the write current I W All are provided by N-type transistors N1-P3. The carriers of N-type transistors N1-P3 are negative electrons. When electrons flow from the source terminal to the drain terminal of the N-type transistor, a positive current flowing from the drain terminal to the source terminal is provided.

[0005] Figure 1A 1 is a schematic diagram of the related operation of the prior art memory cell 10 when writing its memory cell to the parallel state. When writing the memory cell MTJ1 to the parallel state, the bit line BL1 is biased to a positive potential VDD (e.g., 0.8V), the source line SL is biased to a ground potential (e.g., 0V), and the bit line BL2 is floating. At this time, the write current I W will flow from the bit line BL1 to the source line SL, such as Figure 1AAs shown by the dashed arrow in []. When the prior art spin-transfer torque magnetoresistive random access memory 100 performs a write operation in the parallel state, the memory cell MTJ1 is located at the drain ends of the N-type transistors N1-N3, so it will not cause source degeneration to the N-type transistors N1-N3.

[0006] Figure 1B FIG. [] is a schematic diagram of related operations when the prior art memory cell 10 writes its memory cell to the antiparallel state. When writing the memory cell MTJ1 to the antiparallel state, the bit line BL1 is biased to the ground potential (e.g., 0V), the source line SL is biased to the positive potential VDD (e.g., 0.8V), and the bit line BL2 is floating. At this time, the write current I W flows from the source line SL to the bit line BL1, as Figure 1B shown by the dashed arrow in []. When the prior art spin-transfer torque magnetoresistive random access memory 100 performs a write operation in the antiparallel state, the memory cell MTJ1 is located at the source ends of the N-type transistors N1-N3, and its cross voltage will reduce the gate-source voltage of the N-type transistors N1-N3, thereby causing source degeneration and reducing the write current I W to become smaller.

[0007] As described above, under the same biasing conditions, the prior art spin-transfer torque magnetoresistive random access memory 100 will reduce the speed when writing the memory cell to the antiparallel state due to source degeneration. If a high write speed is to be maintained for the antiparallel state, the write voltage needs to be increased. Therefore, there is a need for a spin-transfer torque magnetoresistive random access memory that can avoid source degeneration to increase the write speed and reduce the write voltage. SUMMARY OF THE INVENTION

[0008] The present invention provides a magnetoresistive random access memory, which includes a first bit line, a second bit line, and a memory unit. The memory unit includes a first non-volatile memory unit, a second non-volatile memory unit, first to third N-type transistors, and first to third P-type transistors. The first end of the first non-volatile memory unit is coupled to the first bit line, and the first end of the second non-volatile memory unit is coupled to the second bit line. The first end of the first N-type transistor is coupled to the second end of the first non-volatile memory unit. The first end of the second N-type transistor is coupled to the second end of the second non-volatile memory unit. The first end of the third N-type transistor is coupled to the first end of the first N-type transistor, and the second end is coupled to the first end of the second N-type transistor. A first end of the first P-type transistor is coupled to the second end of the first N-type transistor, and the second end is coupled to the first end of the first N-type transistor. The first end of the second P-type transistor is coupled to the second end of the second N-type transistor, and the second end is coupled to the first end of the second N-type transistor. The first terminal of the third P-type transistor is coupled to the second terminal of the third N-type transistor, and the second terminal of the third P-type transistor is coupled to the first terminal of the third N-type transistor.

[0009] The present invention also provides a magnetoresistive random access memory, which includes an N-type doped region formed in a substrate; a P-type doped region formed in the substrate; a polysilicon layer formed on the substrate; a first metal layer formed on the substrate; a second metal layer formed above the first metal layer; a first non-volatile memory unit arranged above the second metal layer and located on a first reference line; a second non-volatile memory unit arranged above the second metal layer and located on a second reference line, wherein the second reference line is parallel to the first reference line; a third metal layer formed above the first non-volatile memory unit and the second non-volatile memory unit; and a fourth metal layer formed above the third metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and Figure 1B The figure is a schematic diagram of a spin transfer torque magnetoresistive random access memory in the prior art.

[0011] Figure 2A and Figure 2B Schematic diagram of a spin-transfer torque magnetoresistive random access memory according to an embodiment of the present invention.

[0012] Figure 3A and 3B It is a schematic diagram of the implementation method and data state of each storage unit in the memory unit according to an embodiment of the present invention.

[0013] Figure 4It is a schematic diagram of a write operation of a related memory unit in an embodiment of the present invention.

[0014] Figure 5 Schematic diagram of a spin transfer torque magnetoresistive random access memory according to an embodiment of the present invention.

[0015] Figure 6 FIG. 4 is a layout diagram of a spin-transfer torque magnetoresistive random access memory implementation according to an embodiment of the present invention.

[0016] Figure 7 FIG. 4 is a cross-sectional view of the spin-transfer torque magnetoresistive random access memory along the tangent line AA′ according to an embodiment of the present invention.

[0017] Figure 8 FIG. 4 is a cross-sectional view of the spin-transfer torque magnetoresistive random access memory along the tangent line BB′ according to an embodiment of the present invention.

[0018]

Main component symbol description

[0019] 10, 20, UC1-UC4: Memory unit

[0020] 32: Data magnetic layer

[0021] 34: Reference Magnetosphere

[0022] 36: Tunneling the Magnetosphere

[0023] 100, 200, 300: Magnetoresistive random access memory

[0024] BL1-BL4: bit lines

[0025] WL, WL1, WL2: word lines

[0026] SL, SL1, SL2: Source line

[0027] N1-N3: N-type transistor

[0028] P1-P3: P-type transistor

[0029] MTJ1, MTJ2: non-volatile storage cells

[0030] I W : Write current DETAILED DESCRIPTION

[0031] Figure 2A and Figure 2BSchematic diagram of a spin-transfer torque magnetoresistive random access memory 200 according to an embodiment of the present invention. The spin-transfer torque magnetoresistive random access memory 200 includes a memory cell 20, bit lines BL1 and BL2, word lines WL1-WL2, and a source line SL. The memory cell 20 adopts a 6T2M architecture, that is, it includes six transistors (N-type transistors N1-N3 and P-type transistors P1-P3) and two non-volatile memory cells MTJ1 and MTJ2.

[0032] The first terminals of the memory cell MTJ1 and the memory cell MTJ2 are coupled to the bit lines BL1 and BL2, respectively. The first terminal of the N-type transistor N1 is coupled to the second terminal of the memory cell MTJ1, the second terminal is coupled to the source line SL, and the control terminal is coupled to the word line WL1. The first terminal of the N-type transistor N2 is coupled to the second terminal of the memory cell MTJ2, the second terminal is coupled to the source line SL, and the control terminal is coupled to the word line WL1. The first terminal of the N-type transistor N3 is coupled to the first terminal of the N-type transistor N1, the second terminal is coupled to the first terminal of the N-type transistor N2, and the control terminal is coupled to the word line WL1. The first terminal of the P-type transistor P1 is coupled to the second terminal of the N-type transistor N1, the second terminal is coupled to the first terminal of the N-type transistor N1, and the control terminal is coupled to the word line WL2. The first terminal of the P-type transistor P2 is coupled to the second terminal of the N-type transistor N2, the second terminal is coupled to the first terminal of the N-type transistor N2, and the control terminal is coupled to the word line WL2. The first terminal of the P-type transistor P3 is coupled to the second terminal of the N-type transistor N3 , the second terminal of the P-type transistor P3 is coupled to the first terminal of the N-type transistor N3 , and the control terminal of the P-type transistor P3 is coupled to the word line WL2 .

[0033] Figure 3A and 3B Schematic diagram of the implementation and data state of each memory cell in the memory cell 20 of an embodiment of the present invention. The memory cells MTJ1 and MTJ2 each include a data magnetic layer 32, a reference magnetic layer 34, and a tunneling magnetic layer 36, wherein the magnetization directions of the data magnetic layer 32 and the reference magnetic layer 34 are indicated by arrows. The magnetization direction of the data magnetic layer 32 switches between two opposite magnetic states with an external magnetic field to store bit information. The reference magnetic layer 34 is composed of a magnetic material with a fixed magnetic state, so its magnetization direction will not be changed by an external magnetic field. The resistance value of the tunneling magnetic layer 36 is determined by the relative magnetization directions of the data magnetic layer 32 and the reference magnetic layer 34: when a switching pulse signal is applied to the memory cell MTJ1 or MTJ2 to make the magnetization direction of the data magnetic layer 32 and the magnetization direction of the reference magnetic layer 34 anti-parallel, the resistance value of the tunneling magnetic layer 36 is very high. At this time, the memory cells MTJ1 and MTJ2 are in a closed high impedance state (RH state), such as Figure 3AAs shown; when a switching pulse signal is applied to the storage unit MTJ1 or MTJ2 to make the magnetization direction of the data magnetic layer 32 parallel to the magnetization direction of the reference magnetic layer 34, the resistance value of the tunneling magnetic layer 36 is very low, and the storage unit MTJ1 or MTJ2 is in a low impedance state (RL state) of conduction, as shown Figure 3B shown.

[0034] The data stored in the memory cell 20 is determined by the states of its memory cells MTJ1 and MTJ2. In one embodiment, when the memory cell MTJ1 or MTJ2 is in an anti-parallel state, the memory data of the corresponding memory cell 20 can be regarded as logic 1; when the memory cell MTJ1 or MTJ2 is in a parallel state, the memory data of the corresponding memory cell 20 can be regarded as logic 0. In another embodiment, when the memory cell MTJ1 or MTJ2 is in a parallel state, the memory data of the corresponding memory cell 20 can be regarded as logic 1; when the memory cell MTJ1 or MTJ2 is in an anti-parallel state, the memory data of the corresponding memory cell 20 can be regarded as logic 0. However, the definition of the data stored in the memory cell 20 and the states of its memory cells MTJ1 / MTJ2 does not limit the scope of the present invention.

[0035] In the memory cell 20 of the present invention, each N-type transistor is connected in parallel to the corresponding P-type transistor. The carriers of the N-type transistors N1-P3 are negative electrons. When the electrons flow from the source end to the drain end of the N-type transistor, a positive current flowing from the drain end to the source end is provided. The carriers of the P-type transistors P1-P3 are positive holes. When the holes flow from the source end to the drain end of the P-type transistor, a positive current flowing from the source end to the drain end is provided. Through the transmission gate composed of the parallel structure of the N-type transistor and the P-type transistor, the memory cell 20 of the present invention can provide a bidirectional current in the write operation.

[0036] Figure 2A Schematic diagram of the operation of writing the memory cell 20 to the parallel state according to the embodiment of the present invention. When performing the parallel state writing operation, the bit line BL1 is biased to a positive potential VDD (e.g., 0.8V), the source line SL is biased to a ground potential (e.g., 0V), and the bit line BL2 is floating. At this time, the writing current I W will flow from the bit line BL1 to the source line SL, such as Figure 2A As shown by the dotted arrow in the figure. When performing a parallel write operation, the write current I W It is mainly provided by the N-type transistors N1 - N3 . At this time, the memory unit MTJ1 is located at the drain end of the N-type transistors N1 - N3 , so it will not cause source degradation to the N-type transistors N1 - N3 .

[0037] Figure 2BFIG. 1 is a schematic diagram of the related operations when the memory cell 20 is written into the anti-parallel state according to an embodiment of the present invention. When performing the anti-parallel state writing operation, the bit line BL1 is biased to the ground potential (e.g., 0V), the source line SL is biased to a positive potential VDD (e.g., 0.8V), and the bit line BL2 is floating. At this time, the write current I W will flow from the source line SL to the bit line BL1, such as Figure 2B As shown by the dotted arrow in the figure. When performing anti-parallel write operation, the write current I W It is mainly provided by the P-type transistors P1 - P3 . At this time, the non-volatile memory unit MTJ1 is located at the drain end of the P-type transistors P1 - P3 , so it will not cause source degradation to the P-type transistors P1 - P3 .

[0038] Figure 4 Schematic diagram of the write operation of the memory cell 20 in the embodiment of the present invention. The vertical axis is the switching voltage V required to change the magnetization direction of the memory cell in the memory cell 20. C_WL The horizontal axis is the cell size of the storage unit, in μm. 2 Curve 1 represents the characteristic curve of the memory cell 20 of the present invention using the 6T2M architecture when written to the anti-parallel state, Curve 2 represents the characteristic curve of the memory cell 20 of the present invention using the 6T2M architecture when written to the parallel state, Curve 3 represents the characteristic curve of the memory cell 10 of the prior art using the 3T2M architecture when written to the anti-parallel state, and Curve 4 represents the characteristic curve of the memory cell 10 of the prior art using the 3T2M architecture when written to the parallel state. As shown in Curve 1 and Curve 3, under the same device size, the present invention can use a smaller switching voltage V C_WL To switch the magnetization direction of the memory cell in the memory cell 20.

[0039] Figure 5 FIG. 3 is a schematic diagram of a spin transfer torque magnetoresistive random access memory 300 according to an embodiment of the present invention. The spin transfer torque magnetoresistive random access memory 300 includes M*N memory cells, a bit line BL 1 -BL 2M , word line WL 1 -WL N , and source line SL 1 -SL M , where M and N are positive integers. For illustration purposes, Figure 5 An embodiment where M=N=2 is shown, however the number of memory cells, bit lines, word lines, and source lines does not limit the scope of the present invention. Figure 5In the embodiment, the memory cells of the spin transfer torque magnetoresistive random access memory 300 are denoted by UC1-UC4, and each memory cell adopts the following Figure 2A and 2B The 6T2M architecture shown in .

[0040] In the spin-transfer torque magnetoresistive random access memory 300 of the present invention, memory cells adjacent to each other on the left and right (in the direction perpendicular to the bit lines) share two bit lines. For example, the first end of the memory cell MTJ1 in the memory cells UC1 and UC2 is coupled to the bit line BL1, the first end of the memory cell MTJ2 in the memory cells UC1 and UC2 is coupled to the bit line BL2, the first end of the non-volatile memory cell MTJ1 in the memory cells UC3 and UC4 is coupled to the bit line BL3, and the first end of the non-volatile memory cell MTJ2 in the memory cells UC3 and UC4 is coupled to the bit line BL4.

[0041] In the spin-transfer torque magnetoresistive random access memory 200 of the present invention, memory cells adjacent to each other (in the direction parallel to the bit lines) share the same word line. For example, the control terminals of the N-type transistors N1-N3 in the memory cells UC1-UC4 are coupled to the word line WL1, and the control terminals of the P-type transistors P1-P3 in the memory cells UC1-UC4 are coupled to the word line WL2.

[0042] Figure 6 FIG. 4 is a layout diagram of a spin-transfer torque magnetoresistive random access memory 300 according to an embodiment of the present invention. Figure 7 FIG. 4 is a cross-sectional view of the spin-transfer torque magnetoresistive random access memory 300 along the tangent line AA′ according to an embodiment of the present invention. Figure 8 1 is a cross-sectional view of the spin transfer torque magnetoresistive random access memory 300 along the cut line BB' in an embodiment of the present invention. Diff represents a doped region (P-type doped region or N-type doped region), GT represents a polysilicon layer used as a gate, CT represents a contact point, M1 represents a metal layer used as a word line, VIA represents a channel coupling each layer, M2 represents a metal layer used as a source line, MJT represents a non-volatile memory cell, and M4 and M5 represent metal layers used as bit lines.

[0043] In summary, the memory cell of the spin-transfer torque magnetoresistive random access memory of the present invention adopts a 6T2M structure, and each N-type transistor is connected in parallel to the corresponding P-type transistor. The transmission gate composed of the parallel structure of the N-type transistor and the P-type transistor can provide a bidirectional current in the write operation to avoid source degradation, wherein the write current is mainly provided by the N-type transistor when performing a parallel state write operation, and the write current is mainly provided by the P-type transistor when performing an anti-parallel state write operation. Therefore, the spin-transfer torque magnetoresistive random access memory of the present invention can increase the write speed and reduce the write voltage.

[0044] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A magnetoresistive random access memory, comprising: First line; a second bit line; and A first memory unit comprising: A first non-volatile storage unit comprising: A first end coupled to the first bit line; and The second end; A second non-volatile storage unit comprising: A first terminal coupled to the second bit line; and The second end; A first N-type transistor comprising: A first terminal coupled to the second terminal of the first non-volatile memory unit; The second end; as well as Control terminal; A second N-type transistor comprising: A first terminal coupled to the second terminal of the second non-volatile memory unit; The second end; as well as Control terminal; A third N-type transistor comprising: A first terminal coupled to the first terminal of the first N-type transistor; A second terminal coupled to the first terminal of the second N-type transistor; and Control terminal; A first P-type transistor comprising: A first terminal coupled to the second terminal of the first N-type transistor; A second terminal coupled to the first terminal of the first N-type transistor; and Control terminal; A second P-type transistor comprising: A first terminal coupled to the second terminal of the second N-type transistor; A second terminal coupled to the first terminal of the second N-type transistor; and Control terminal; and A third P-type transistor comprising: A first terminal coupled to the second terminal of the third N-type transistor; A second terminal coupled to the first terminal of the third N-type transistor; and Control end.

2. The magnetoresistive random access memory according to claim 1, in: The control terminals of the first N-type transistor, the second N-type transistor and the third N-type transistor are coupled to a first word line; and The control terminals of the first P-type transistor, the second P-type transistor and the third P-type transistor are coupled to a second word line.

3. The magnetoresistive random access memory of claim 1 , further comprising a second memory cell comprising: A third non-volatile storage unit, comprising: A first terminal coupled to the first bit line; and The second end; A fourth non-volatile storage unit, comprising: A first terminal coupled to the second bit line; and The second end; A fourth N-type transistor comprising: A first terminal coupled to the second terminal of the third non-volatile memory unit; The second end; as well as Control terminal; A fifth N-type transistor comprising: A first end coupled to the second end of the fourth non-volatile memory unit; The second end; as well as Control terminal; A sixth N-type transistor, comprising: A first terminal coupled to the first terminal of the fourth N-type transistor; A second terminal coupled to the first terminal of the fifth N-type transistor; and Control terminal; A fourth P-type transistor comprising: A first terminal coupled to the second terminal of the fourth N-type transistor; A second terminal coupled to the first terminal of the fourth N-type transistor; and Control terminal; A fifth P-type transistor comprising: A first terminal coupled to the second terminal of the fifth N-type transistor; A second terminal coupled to the first terminal of the fifth N-type transistor; and Control terminal; and A sixth P-type transistor, comprising: A first terminal coupled to the second terminal of the sixth N-type transistor; A second terminal coupled to the first terminal of the sixth N-type transistor; and Control end.

4. The magnetoresistive random access memory according to claim 3, in: The control terminals of the first N-type transistor, the second N-type transistor, the third N-type transistor, the fourth N-type transistor, the fifth N-type transistor and the sixth N-type transistor are coupled to a first word line; and The control terminals of the first P-type transistor, the second P-type transistor, the third P-type transistor, the fourth P-type transistor, the fifth P-type transistor and the sixth P-type transistor are coupled to a second word line.

5. The magnetoresistive random access memory as described in claim 3, wherein the second end of the first N-type transistor and the second end of the second N-type transistor are coupled to a first source line, and the second end of the fourth N-type transistor and the second end of the fifth N-type transistor are coupled to a second source line.

6. The magnetoresistive random access memory according to claim 1, further comprising: The third bit line; a fourth bit line; and A third memory unit comprising: A fifth non-volatile storage unit, comprising: A first terminal coupled to the third bit line; and The second end; A sixth non-volatile storage unit, comprising: A first terminal coupled to the fourth bit line; and The second end; A seventh N-type transistor, comprising: A first terminal coupled to the second terminal of the fifth non-volatile memory unit; The second end; as well as Control terminal; An eighth N-type transistor, comprising: A first terminal coupled to the second terminal of the sixth non-volatile memory unit; The second end; as well as Control terminal; A ninth N-type transistor, comprising: A first terminal coupled to the first terminal of the seventh N-type transistor; A second terminal coupled to the first terminal of the eighth N-type transistor; and Control terminal; A seventh P-type transistor, comprising: A first terminal coupled to the second terminal of the seventh N-type transistor; A second terminal coupled to the first terminal of the seventh N-type transistor; and Control terminal; An eighth P-type transistor, comprising: A first terminal coupled to the second terminal of the eighth N-type transistor; A second terminal coupled to the first terminal of the eighth N-type transistor; and Control terminal; and A ninth P-type transistor, comprising: A first terminal coupled to the second terminal of the ninth N-type transistor; A second terminal coupled to the first terminal of the ninth N-type transistor; and Control end.

7. The magnetoresistive random access memory according to claim 6, in: The control terminals of the first N-type transistor, the second N-type transistor, the third N-type transistor, the seventh N-type transistor, the eighth N-type transistor and the ninth N-type transistor are coupled to a first word line; and The control terminals of the first P-type transistor, the second P-type transistor, the third P-type transistor, the seventh P-type transistor, the eighth P-type transistor and the ninth P-type transistor are coupled to a second word line.

8. The magnetoresistive random access memory as claimed in claim 6, wherein the second end of the first N-type transistor, the second end of the second N-type transistor, the second end of the seventh N-type transistor, and the second end of the eighth N-type transistor are coupled to a source line.

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