Power chip packaging structure and its fabrication method

Abstract

This invention provides a power chip packaging structure and its fabrication method. The method includes: providing a power chip and fabricating a conductive interconnect structure on the active surface of the power chip; providing a packaging substrate and electrically connecting the power chip and the packaging substrate through the conductive interconnect structure to obtain a pre-package; molding the pre-package to obtain a molding layer and a base surface; fabricating a metal layer on the base surface; providing a heat dissipation base with heat dissipation fins on one side, and hot-pressing the heat dissipation base and the metal layer to obtain a power chip packaging structure with a metal welding layer. This invention solves the problem of poor heat dissipation in existing power chip packaging structures by connecting the heat dissipation base with heat dissipation fins and the power chip through the metal layer and the metal welding layer, utilizing the high thermal conductivity of the metal material to quickly disperse the heat generated by the power chip, thereby improving the heat dissipation effect of the power chip.

Description

Technical Field

[0001] This invention relates to the field of circuit packaging technology, and more specifically to a packaging structure suitable for power chips and its fabrication method. Background Technology

[0002] Power chips have high power density due to their wide operating voltage and current range. Furthermore, silicon-based semiconductor power chips inherently have high power consumption, making heat dissipation a major concern in the industry. In existing technologies, after packaging, the power chip is the primary heat source. The packaging materials surrounding the power chip typically include: (1) an EMC molding layer; (2) thermal grease; and (3) a packaging substrate. The structural characteristics of the power chip determine that its main heat dissipation channels are the top and bottom surfaces, which have the largest contact area with the external environment. In existing technologies, the thermal grease and packaging substrate have the largest contact areas with the power chip.

[0003] Currently, various technological improvements are being made to increase the thermal conductivity of the packaging substrate, thereby improving the heat dissipation of power chips. However, the packaging substrate is the only interconnection structure in the power chip package that interacts with the outside world for signal exchange and power supply. Therefore, there is limited room for improvement in the heat dissipation of power chips from the packaging substrate.

[0004] It is evident that the existing power chip packaging structure suffers from poor heat dissipation, which affects the stability and reliability of the power chip. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the power chip packaging structure and its fabrication method provided by this invention solve the problem of poor heat dissipation in existing power chip packaging structures. By connecting the heat dissipation base of the heat sink fins and the power chip through a metal layer and a metal welding layer, the high thermal conductivity of the metal material is used to quickly disperse the heat generated by the power chip, thereby improving the heat dissipation effect of the power chip.

[0006] In a first aspect, the present invention provides a method for fabricating a power chip package structure, the method comprising: providing a power chip and fabricating a conductive interconnect structure on the active surface of the power chip; providing a packaging substrate and electrically connecting the power chip and the packaging substrate through the conductive interconnect structure to obtain a pre-package, wherein the pre-package includes the power chip, the conductive interconnect structure, and the packaging substrate; molding the pre-package to obtain a molding layer and a base surface, wherein the base surface is a surface on which the top surface of the molding layer is coplanar with the passive surface of the power chip; fabricating a metal layer on the base surface; providing a heat sink with heat dissipation fins on one side, and hot-pressing the heat sink to fuse the metal layer to obtain a power chip package structure with a metal bonding layer.

[0007] Optionally, before fabricating a conductive interconnect structure on the active surface of the power chip, the method further includes: growing a crystalline silicon layer on the passive surface of the power chip; wherein the base surface is the surface on which the top surface of the molding compound is coplanar with the crystalline silicon layer.

[0008] Optionally, a conductive interconnect structure is fabricated on the active surface of the power chip, including: fabricating conductive pillars and tin-based alloy solder blocks on the active surface of the power chip; and electrically connecting the power chip and the packaging substrate through the conductive interconnect structure, including: melting the tin-based alloy solder blocks on the packaging substrate through a reflow soldering process to electrically connect the power chip and the packaging substrate.

[0009] Optionally, before encapsulating the pre-packaged body, the method further includes: underfilling the conductive interconnect structure to form an underfill layer.

[0010] Optionally, the heat sink base and the metal layer are hot-pressed together, including: grinding the bottom surface of the heat sink base to obtain a first metal mirror surface; grinding the side of the metal layer away from the power chip to obtain a second metal mirror surface; and hot-pressing the first metal mirror surface and the second metal mirror surface together to form the metal welding layer.

[0011] Optionally, after hot-pressing the first metal mirror and the second metal mirror to form the metal welding layer, the method further includes: preparing metal welding points on the surface of the packaging substrate away from the power chip; providing a PCB board, and interconnecting the packaging substrate with the PCB board through the metal welding points to obtain a power chip packaging structure with a PCB board.

[0012] Secondly, the present invention provides a power chip packaging structure, the packaging structure comprising: a power chip, a packaging substrate, a metal layer, a molding compound, and a heat sink with heat dissipation fins; the packaging substrate is electrically connected to the power chip through a conductive interconnection structure on the active surface of the power chip, and the molding compound surrounds the power chip; the metal layer is disposed between the heat sink and the passive surface of the power chip, and the metal layer and the heat sink are thermally pressed together to form a metal weld layer.

[0013] Optionally, the packaging structure further includes a crystalline silicon layer disposed between the metal layer and the passive surface of the power chip.

[0014] Optionally, the packaging structure further includes: a bottom filler layer formed between the conductive interconnect structure and the packaging substrate, such that the bottom filler layer surrounds the conductive interconnect structure; and / or a PCB board interconnected with the packaging substrate via metal solder joints.

[0015] Optionally, the metal layer, the heat dissipation fins, and / or the heat dissipation base may be made of copper.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The packaging substrate in this invention serves as the main interconnect structure for signal transmission and power supply, and is also one of the heat dissipation channels for the power chip. Furthermore, the heat dissipation base of the heat sink fins and the power chip are connected through a metal layer and a metal solder layer. The high thermal conductivity of the metal material is used to quickly disperse the heat generated by the power chip, thereby improving the heat dissipation effect of the power chip. Attached Figure Description

[0018] Figure 1 The diagram shown is a flowchart illustrating a method for fabricating a power chip packaging structure according to an embodiment of the present invention.

[0019] Figure 2 The diagram shown is a schematic diagram of a conductive interconnect structure fabricated on the active surface of a power chip according to an embodiment of the present invention.

[0020] Figure 3 The diagram shown is a structural schematic of a pre-packaged body provided in an embodiment of the present invention;

[0021] Figure 4 The diagram shown is a schematic representation of the structure of a pre-packaged body after plastic encapsulation according to an embodiment of the present invention.

[0022] Figure 5 The diagram shown is a schematic representation of the structure of a plastic sealant layer after grinding, according to an embodiment of the present invention.

[0023] Figure 6 The diagram shown is a schematic diagram of a structure for preparing a metal layer on a substrate according to an embodiment of the present invention;

[0024] Figure 7 The diagram shown is a schematic representation of a power chip packaging structure provided in an embodiment of the present invention.

[0025] Figure 8 The diagram shown is a flowchart illustrating another method for fabricating a power chip packaging structure according to an embodiment of the present invention.

[0026] Figure 9The diagram shown is a schematic diagram of a structure for growing a crystalline silicon layer on a passive surface of a power chip according to an embodiment of the present invention.

[0027] Figure 10 The diagram shown is a structural schematic of another power chip packaging structure provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0029] In a first aspect, the present invention provides a method for fabricating a power chip packaging structure, specifically including the following embodiments:

[0030] Example 1

[0031] Figure 1 The diagram shown is a flowchart illustrating a method for fabricating a power chip packaging structure according to an embodiment of the present invention; as follows: Figure 1 As shown, the fabrication method of the power chip packaging structure specifically includes the following steps:

[0032] Step S101: A power chip is provided, and a conductive interconnect structure is fabricated on the active surface of the power chip.

[0033] In this embodiment, the conductive interconnect structure is fabricated on the active surface of the power chip, including: fabricating conductive pillars and tin-based alloy solder blocks on the active surface of the power chip;

[0034] It should be noted that, as Figure 2 As shown, the power chip 10 includes a passive surface 10a and an active surface 10b. The conductive interconnect structure in this embodiment includes conductive pillars 12 and tin-based alloy solder blocks 13. Therefore, the conductive interconnect structure is prepared on the active surface of the power chip by electroplating the conductive pillars 12 and tin-based alloy solder blocks 13 on the active surface 10b of the power chip 10.

[0035] Step S102: A packaging substrate is provided, and the power chip and the packaging substrate are electrically connected through a conductive interconnection structure to prepare a pre-packaged body.

[0036] In this embodiment, the pre-packaged body includes a power chip, a conductive interconnect structure, and a packaging substrate.

[0037] In this embodiment, electrically connecting the power chip and the packaging substrate through a conductive interconnect structure specifically includes: melting the tin-based alloy solder block on the packaging substrate using a reflow soldering process to electrically connect the power chip and the packaging substrate.

[0038] In this embodiment, before encapsulating the pre-packaged body, the method further includes: bottom filling the conductive interconnect structure to form a bottom filling layer.

[0039] It should be noted that, as Figure 3 As shown, in the high-temperature reflow soldering process, the tin-based alloy solder block 13 melts and interconnects with the packaging substrate 3, and fills the conductive interconnect structure of the power chip 10 to form a bottom fill layer 14. The bottom fill layer 14 can reduce the degree of warpage caused by the CTE mismatch between the silicon substrate of the power chip 10 and the packaging substrate 3.

[0040] Step S103: The pre-packaged body is encapsulated to prepare an encapsulation layer and a base surface, wherein the base surface is the surface on which the top surface of the encapsulation layer is coplanar with the passive surface of the power chip.

[0041] It should be noted that the molding layer includes a bottom surface and a top surface, wherein the surface in contact with the encapsulation substrate is the bottom surface, and the surface opposite to the bottom surface is the top surface.

[0042] like Figure 4 As shown, the pre-packaged body is encapsulated to obtain a power chip 10 covered by a molding compound 15; wherein, the molding compound 15 is preferably made of an EMC series material.

[0043] like Figure 5 As shown, the molding layer 15 is ground until the passive surface 10a of the power chip is exposed, resulting in a base surface with high flatness where the top surface of the molding layer 15 is coplanar with the passive surface of the power chip.

[0044] Step S104: Prepare a metal layer on the substrate.

[0045] like Figure 6 As shown, a metal layer 20 is prepared on the substrate, wherein the metal layer 20 is preferably prepared by an electroplating copper process.

[0046] Step S105: Provide a heat sink base with heat dissipation fins, and heat-press the heat sink base to the metal layer to obtain a power chip packaging structure with a metal welding layer.

[0047] In this embodiment, the heat sink base and the metal layer are hot-pressed together, including: grinding the bottom surface of the heat sink base to obtain a first metal mirror surface; grinding the side of the metal layer away from the power chip to obtain a second metal mirror surface; and hot-pressing the first metal mirror surface and the second metal mirror surface together to form the metal welding layer.

[0048] like Figure 7 As shown, the first metal mirror 22a obtained by grinding the heat sink 22 and the second metal mirror 20a obtained by grinding the metal layer 20 are hot-pressed together. The welding of the first metal mirror 22a and the second metal mirror 20a is achieved by the mutual diffusion of metal atoms under high temperature and high pressure conditions, forming a metal welding layer 21. A metal welding layer 21 is constructed between the heat sink fins 23 and the pre-packaged body. A metal material with high thermal conductivity is used as the connection layer. In the prior art, thermal grease with poor thermal conductivity is used as the connection layer between the heat sink fins 23 and the power chip 10. In this invention, a metal material with high thermal conductivity is used as the connection layer between the heat sink fins 23 and the power chip 10, thereby improving the heat dissipation effect of the power chip 10.

[0049] Compared with the prior art, this embodiment has the following beneficial effects:

[0050] The packaging substrate in this invention serves as the main interconnect structure for signal transmission and power supply, and is also one of the heat dissipation channels for the power chip. Furthermore, the heat dissipation base of the heat sink fins and the power chip are connected through a metal layer and a metal solder layer. The high thermal conductivity of the metal material is used to quickly disperse the heat generated by the power chip, thereby improving the heat dissipation effect of the power chip.

[0051] Example 2

[0052] Figure 8 The diagram shown is a flowchart illustrating another method for fabricating a power chip packaging structure according to an embodiment of the present invention; as shown Figure 8 As shown, the fabrication method of the power chip packaging structure specifically includes the following steps:

[0053] Step S201: A power chip is provided, and a crystalline silicon layer is grown on the passive surface of the power chip.

[0054] like Figure 9 As shown, the passive surface 10a of the power chip 10 is chemically polished, and an ordered crystalline silicon layer 11 is epitaxially grown on the passive surface 10a of the power chip 10. Since the crystalline silicon layer 11 is prepared by epitaxial growth and does not have other elements doped, its resistivity is very high, and it serves as an electrical barrier layer between the transistor circuit in the power chip 10 and the external circuit.

[0055] Step S202: A conductive interconnect structure is fabricated on the active surface of the power chip;

[0056] Step S203: Provide a packaging substrate, and electrically connect the power chip and the packaging substrate through a conductive interconnection structure to prepare a pre-packaged body;

[0057] Step S204: The pre-packaged body is encapsulated to prepare an encapsulation layer and a base surface, wherein the base surface is the surface on which the top surface of the encapsulation layer is coplanar with the crystalline silicon layer;

[0058] Step S205: Prepare a metal layer on the substrate surface;

[0059] Step S206: Provide a heat sink base with heat dissipation fins, and heat-press the heat sink base to the metal layer to obtain a power chip packaging structure with a metal welding layer.

[0060] It should be noted that, as Figure 10 As shown, the specific preparation method of steps S202 to S206 in this embodiment differs from the preparation method of steps S101 to S105 in the above embodiment in that: the base surface in this embodiment is the surface on which the top surface of the molding layer and the crystalline silicon layer are coplanar, while the base surface in the first embodiment is the surface on which the top surface of the molding layer and the passive surface of the power chip are coplanar; therefore, the other preparation methods are the same, and will not be described again here.

[0061] Compared with the prior art, this embodiment has the following beneficial effects:

[0062] 1. The packaging substrate in this invention serves as the main interconnection structure for signal transmission and power supply, and is also one of the heat dissipation channels for the power chip. Furthermore, the heat dissipation base of the heat sink fins and the power chip are connected through a metal layer and a metal welding layer. The high thermal conductivity of the metal material is used to quickly disperse the heat generated by the power chip, thereby improving the heat dissipation effect of the power chip.

[0063] 2. In this invention, a crystalline silicon layer is epitaxially grown on the passive surface of the power chip. The crystalline silicon layer serves as an electrical barrier between the transistor circuit of the power chip and the external circuit. Furthermore, the high thermal conductivity of crystalline silicon, combined with the metal layer and the metal bonding layer, further improves the heat dissipation effect of the power chip.

[0064] In this embodiment, after the first metal mirror and the second metal mirror are hot-pressed together to form the metal welding layer, the method further includes: preparing metal welding points on the surface of the packaging substrate away from the power chip; providing a PCB board, and interconnecting the packaging substrate with the PCB board through the metal welding points to obtain a power chip packaging structure with a PCB board.

[0065] Secondly, the present invention provides a power chip packaging structure, specifically including the following embodiments:

[0066] Example 3

[0067] Figure 7 The diagram shown is a schematic representation of a power chip packaging structure according to an embodiment of the present invention. The power chip packaging structure includes:

[0068] Power chip, packaging substrate, metal layer, molding layer and heat sink with heat dissipation fins;

[0069] The packaging substrate is electrically connected to the power chip through a conductive interconnect structure on the active surface of the power chip. The molding layer surrounds the power chip. The metal layer is disposed between the heat sink and the passive surface of the power chip, so that the metal layer and the heat sink are thermo-pressed and fused to form a metal weld layer.

[0070] It should be noted that the active surface 10b of the power chip 10 is interconnected with the packaging substrate 3 through a conductive interconnection structure, wherein the conductive interconnection structure includes conductive pillars 12 and tin-based alloy solder blocks 13 on the conductive pillars; a molding compound is filled around the power chip 10 to form a molding layer 15, providing reliability protection for the power chip; the molding layer 15 is ground, and a metal layer 20 is prepared on the ground molding layer 15 and the passive surface of the power chip, and the metal layer 20 is finely ground to obtain a metal mirror surface 20a with high surface flatness; similarly, the heat sink base 22 is also finely ground to obtain a metal mirror surface 22a with high surface flatness; the metal mirror surface of the heat sink base 22 and the metal mirror surface of the metal layer 20 are hot-pressed together, so that the mirror surface of the heat sink base 22 and the mirror surface of the metal layer 20 achieve mutual diffusion of metal atoms under high temperature and high pressure conditions, and a metal solder layer is prepared.

[0071] The packaging substrate in this invention serves as the main interconnect structure for signal transmission and power supply, and is also one of the heat dissipation channels for the power chip. Furthermore, the heat dissipation base of the heat sink fins and the power chip are connected through a metal layer and a metal solder layer. The high thermal conductivity of the metal material is used to quickly disperse the heat generated by the power chip, thereby improving the heat dissipation effect of the power chip.

[0072] Example 4

[0073] Figure 10 The diagram shown is a structural schematic of another power chip packaging structure provided in an embodiment of the present invention. Figure 10 As shown, compared to Embodiment 3, the power chip packaging structure provided in this embodiment further includes: a crystalline silicon layer, wherein the crystalline silicon layer is disposed between the metal layer and the passive surface of the power chip.

[0074] It should be noted that a crystalline silicon layer 11 is prepared on the passive surface 10a of the power chip 10. The crystalline silicon layer 11 can be prepared by deposition, magnetron sputtering, epitaxial growth, etc. It is composed of high-purity crystalline silicon material without any doping, and therefore has a high resistivity, which is used to achieve electrical insulation between the circuit layout in the power chip 10 and other external conductive components.

[0075] This invention epitaxially grows a crystalline silicon layer on the passive surface of a power chip. The crystalline silicon layer serves as an electrical barrier between the transistor circuit of the power chip and the external circuit. Furthermore, crystalline silicon has a high thermal conductivity, and by combining the crystalline silicon layer with a metal layer and a metal bonding layer, the heat dissipation effect of the power chip is further improved.

[0076] In Embodiments 3 and 4, the packaging structure further includes a bottom filler layer, which is formed between the conductive interconnect structure and the packaging substrate, so that the bottom filler layer surrounds the conductive interconnect structure; wherein, the bottom filler layer 14 fills between the conductive pillar 12, the tin-based alloy solder block 13, and the packaging substrate 3, which can reduce the warping problem caused by CTE mismatch between packaging materials.

[0077] In Embodiments 3 and 4, the packaging structure further includes a PCB board, which is interconnected with the packaging substrate via metal solder joints.

[0078] It should be noted that the molding compound 15 is preferably made of EMC series molding compound; the metal layer 20 is preferably made of copper, and the preparation of the metal layer 20 is preferably made of electroplating process; the heat sink base 22 is preferably made of copper; and the heat sink fins 23 are preferably made of copper.

[0079] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for fabricating a power chip packaging structure, characterized in that, The method comprises: providing a power chip, growing a crystalline silicon layer on a passive surface of the power chip by epitaxy; preparing a conductive interconnection structure on an active surface of the power chip; providing a packaging substrate, electrically connecting the power chip and the packaging substrate through the conductive interconnection structure to obtain a pre-packaging body, wherein the pre-packaging body comprises the power chip, the conductive interconnection structure and the packaging substrate; encapsulating the pre-packaging body to obtain an encapsulation layer and a base surface, wherein the base surface is a surface of the encapsulation layer which is coplanar with the crystalline silicon layer; preparing a metal layer on the base surface; 2. The method for fabricating the power chip packaging structure as described in claim 1, characterized in that, providing a heat dissipation base with heat dissipation fins, and hot-pressing and fusing the heat dissipation base and the metal layer to obtain a power chip packaging structure with a metal welding layer. The method for preparing the conductive interconnection structure on the active surface of the power chip comprises: preparing a conductive column and a tin-based alloy solder block on the active surface of the power chip; electrically connecting the power chip and the packaging substrate through the conductive interconnection structure comprises:

3. The method of claim 1 or 2, wherein the method further comprises: electrically connecting the power chip and the packaging substrate by melting the tin-based alloy solder block on the packaging substrate through a reflow soldering process. Before encapsulating the pre-packaging body, the method further comprises:

4. The method for fabricating the power chip packaging structure as described in claim 3, characterized in that, bottom filling the conductive interconnection structure to form a bottom filling layer. Hot-pressing and fusing the heat dissipation base and the metal layer comprises: grinding a bottom surface of the heat dissipation base to obtain a first metal mirror surface; grinding a surface of the metal layer away from the power chip to obtain a second metal mirror surface; 5. The method for fabricating the power chip packaging structure as described in claim 4, characterized in that, hot-pressing and fusing the first metal mirror surface and the second metal mirror surface to form the metal welding layer. After hot-pressing and fusing the first metal mirror surface and the second metal mirror surface to form the metal welding layer, the method further comprises: preparing a metal welding point on a surface of the packaging substrate away from the power chip; 6. A power chip package structure, characterized by, providing a PCB board, and interconnecting the packaging substrate and the PCB board through the metal welding point to obtain a power chip packaging structure with a PCB board. The packaging structure comprises: a power chip, a packaging substrate, a metal layer, an encapsulation layer and a heat dissipation base with heat dissipation fins; a crystalline silicon layer, which is arranged between the passive surface of the power chip and the metal layer and is formed by epitaxy; the packaging substrate is electrically connected with the power chip through the conductive interconnection structure on the active surface of the power chip, and the encapsulation layer surrounds the power chip; 7. The power chip package structure of claim 6, wherein, the metal layer is arranged between the heat dissipation base and the passive surface of the crystalline silicon layer, and the metal layer is hot-pressed and fused with the heat dissipation base to form a metal welding layer. The packaging structure further comprises: a bottom filling layer, which is formed between the conductive interconnection structure and the packaging substrate and wraps around the conductive interconnection structure; 8. The power chip package structure of claim 7, wherein, or / and a PCB board, which is interconnected with the packaging substrate through a metal welding point. The material of the metal layer, the heat dissipation fins or / and the heat dissipation base comprises copper.

Images