Three-dimensional memory and methods of forming the same, metrology methods for three-dimensional memory

Abstract

The present application relates to a kind of three-dimensional memory and its forming method, the measurement method of three-dimensional memory.The three-dimensional memory includes: device structure, including stack layer, multiple channel holes are in the stack layer, each described channel hole includes first channel hole and second channel hole with first preset relative offset amount;Measurement structure is located outside the device structure, the measurement structure includes multiple measurement subarrays, with a pitch between adjacent measurement subarrays, multiple measurement holes in each described measurement subarray are arranged in array, and the measurement hole includes first measurement hole and second measurement hole with second preset relative offset amount, there is a preset difference between the first preset offset and the second preset offset.The present application improves the reliability and accuracy of the channel hole in the registration measurement result.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a three-dimensional memory and a method for forming the same, as well as a method for measuring the three-dimensional memory. Background Technology

[0002] With the development of planar flash memory, semiconductor manufacturing processes have made tremendous progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, limitations of existing development technologies, and limits of storage electron density. Against this backdrop, in order to solve the difficulties encountered by planar flash memory and to pursue lower production costs per unit of storage cell, various three-dimensional (3D) flash memory structures have emerged, such as 3D NOR (3D NAND) flash memory and 3D NAND (3D NAND) flash memory.

[0003] Among them, 3D NAND memory, with its small size and large capacity, adopts the design concept of highly integrated storage cells stacked in a three-dimensional pattern to produce memory with high storage density per unit area and high efficiency of storage cell performance. It has become the mainstream process for the design and production of emerging memory.

[0004] With the continuous increase in memory demand, the need for high-capacity memory is becoming increasingly prominent. Increasing the number of stacked layers in 3D NAND flash memory increases the etching difficulty when etching structures such as vias. Dual-deck technology can effectively solve the problem of the inability to increase the number of stacked layers indefinitely. However, achieving precise alignment between the upper and lower layers is crucial in the dual-deck process. Current measurement methods cannot accurately reflect the overlay accuracy of the upper and lower vias, thus limiting improvements in the yield of 3D NAND flash memory products.

[0005] Therefore, improving the reliability of the measurement results of the upper and lower channel holes, thereby improving the yield of 3D memory products, is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] This invention provides a three-dimensional memory and a method for forming the same, as well as a method for measuring the three-dimensional memory, to solve the problem of low reliability of the measurement results of the upper and lower channel holes in the prior art, so as to improve the yield of three-dimensional memory products.

[0007] To address the above problems, the present invention provides a three-dimensional memory, comprising:

[0008] Substrate;

[0009] A device structure is located on the substrate, and includes a stack layer having a plurality of channel holes arranged in an array, each of the channel holes including a first channel hole and a second channel hole located above the first channel hole and in communication with the first channel hole, and a first preset relative offset between the first channel hole and the second channel hole in communication therewith in a direction parallel to a top surface of the substrate;

[0010] A metrology structure is located on the substrate and distributed outside the device structure, and includes a plurality of metrology sub-arrays with a pitch between adjacent metrology sub-arrays, each of the metrology sub-arrays including a plurality of metrology holes arranged in an array, each of the metrology holes including a first metrology hole and a second metrology hole located above the first metrology hole and in communication with the first metrology hole, and a second preset relative offset between the first metrology hole and the second metrology hole in communication therewith in a direction parallel to a top surface of the substrate, the first preset offset and the second preset offset having a preset difference.

[0011] Optionally, the stack layer includes a first stack layer and a second stack layer located above the first stack layer, the first channel hole penetrates the first stack layer in a direction perpendicular to the substrate, and the second channel hole penetrates the second stack layer in the direction perpendicular to the substrate.

[0012] The metrology structure includes a first dielectric layer and a second dielectric layer located above the first dielectric layer, the first metrology hole is located in the first dielectric layer, and the second metrology hole is located in the second dielectric layer.

[0013] Optionally, the first metrology hole has the same shape and / or size as the first channel hole.

[0014] The second metrology hole has the same shape and / or size as the second channel hole.

[0015] Optionally, the pitch has a width greater than an inner diameter of one of the metrology holes.

[0016] Optionally, the device structure further includes a gate line slot.

[0017] The pitch has a width greater than or equal to a width of the gate line slot.

[0018] Optionally, the first metrology hole, the second metrology hole, the first channel hole, and the second channel hole have the same aperture.

[0019] The preset difference is less than or equal to half of the aperture of the first metrology hole.

[0020] Optionally, the substrate includes a plurality of streets, the streets separating the substrate into a plurality of chips, the device structures being located within the chips, the metrology structures being located in the streets.

[0021] Optionally, the substrate includes a plurality of streets, the streets separating the substrate into a plurality of chips, the device structures and the metrology structures being located within the chips.

[0022] Optionally, the plurality of the trench holes in the stack layer correspond to the plurality of the metrology holes in the metrology structures one-to-one.

[0023] Optionally, the plurality of the metrology sub-arrays in the metrology structures are arranged in an array along a first direction and a second direction, forming a metrology array, the first direction and the second direction being parallel to a top surface of the substrate, and the first direction intersecting the second direction.

[0024] Optionally, all the trench holes in the stack layer are arranged in a trench hole array, the trench hole array including a plurality of trench hole sub-arrays, the plurality of the trench hole sub-arrays being arranged in parallel along the second direction.

[0025] Each row in the metrology array corresponds to one of the trench hole sub-arrays.

[0026] Optionally, the substrate has a plurality of the device structures and a plurality of the metrology structures thereon, and one of the device structures corresponds to one or more of the metrology structures.

[0027] To solve the above problems, the present application further provides a forming method of a three-dimensional memory, comprising the following steps:

[0028] A substrate is provided, and a first region and a second region outside the first region are defined on the substrate, the second region including a plurality of metrology sub-regions arranged in an array, and there is a spacing between adjacent metrology sub-regions;

[0029] A plurality of first trench holes arranged in an array are formed on the first region of the substrate, and a plurality of first metrology holes are formed on each of the metrology sub-regions of the substrate;

[0030] A second trench hole in communication with each of the first trench holes is formed above each of the first trench holes, and a second metrology hole in communication with each of the first metrology holes is formed above each of the first metrology holes, in a direction parallel to a top surface of the substrate, there is a first preset relative offset between the first trench hole and the second trench hole in communication therewith, and there is a second preset relative offset between the first metrology hole and the second metrology hole in communication therewith, and a difference between the first preset relative offset and the second preset relative offset is within a preset range.

[0031] To solve the above problems, the application further provides a three-dimensional memory metrology method, comprising the following steps:

[0032] Providing a three-dimensional memory as described in any one of the above;

[0033] Measuring the actual offset of the first metrology hole and the second metrology hole in the metrology hole along the direction parallel to the top surface of the substrate as a first actual relative offset;

[0034] According to the preset difference and the first actual relative offset, a second actual relative offset is calculated, which is the actual offset of the first channel hole and the second channel hole in the channel hole along the direction parallel to the top surface of the substrate.

[0035] Optionally, the specific step of measuring the actual offset of the first metrology hole and the second metrology hole in the metrology hole along the direction parallel to the top surface of the substrate comprises:

[0036] The optical method is used to measure the actual offset of the first metrology hole and the second metrology hole in the metrology hole along the direction parallel to the top surface of the substrate.

[0037] Optionally, the specific step of measuring the actual offset of the first metrology hole and the second metrology hole in the metrology hole along the direction parallel to the top surface of the substrate comprises:

[0038] Emitting a detection light signal to the metrology structure;

[0039] Collecting and analyzing the diffraction light signal of the metrology structure to obtain the actual offset of the first metrology hole and the second metrology hole in the metrology hole along the direction parallel to the top surface of the substrate.

[0040] The three-dimensional memory and the forming method thereof, and the measurement method of the three-dimensional memory are provided, the measurement structure is arranged outside the device structure, the measurement structure comprises a plurality of measurement sub-arrays, there is a spacing between adjacent measurement sub-arrays, and in the direction parallel to the top surface of the substrate, the second preset relative offset between the first measurement hole and the second measurement hole in the measurement hole and the first preset relative offset between the first channel hole and the second channel hole in the channel hole have a preset difference value. The existence of the spacing between adjacent measurement arrays in the measurement structure can enhance the measurement signal, so that the first actual relative offset between the first measurement hole and the second measurement hole in the measurement hole can be accurately and reliably measured, and finally the second actual relative offset between the first channel hole and the second channel hole in the channel hole can be accurately and reliably obtained, thereby improving the reliability and accuracy of the channel hole and the second channel hole in the channel hole. The alignment measurement result of the first channel hole and the second channel hole improves the yield of the three-dimensional memory product. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a schematic cross-sectional view of a three-dimensional memory according to an embodiment of the present application; Figure 1 Figure 2 is a schematic top view of a device structure according to an embodiment of the present application;

[0042] Figure 3 is a schematic top view of a measurement structure according to an embodiment of the present application; Figure 2 Figure 4 is a schematic layout of a measurement structure on a substrate according to an embodiment of the present application;

[0043] Figure 5 is a flowchart of a forming method of a three-dimensional memory according to an embodiment of the present application; Figure 3 Figure 6 is a flowchart of a measurement method of a three-dimensional memory according to an embodiment of the present application.

[0044] Figure 7 is a schematic cross-sectional view of a three-dimensional memory according to another embodiment of the present application; Figure 4 Figure 8 is a schematic top view of a device structure according to another embodiment of the present application; Figure 9 is a schematic top view of a measurement structure according to another embodiment of the present application;

[0045] Figure 10 is a schematic layout of a measurement structure on a substrate according to another embodiment of the present application; Figure 5 Figure 11 is a flowchart of a forming method of a three-dimensional memory according to another embodiment of the present application;

[0046] Figure 12 is a flowchart of a measurement method of a three-dimensional memory according to another embodiment of the present application. Figure 6 The specific embodiments of the three-dimensional memory and the forming method thereof, and the measurement method of the three-dimensional memory provided by the present application will be described in detail below with reference to the accompanying drawings.

[0047] The specific embodiments of the three-dimensional memory and the forming method thereof, and the measurement method of the three-dimensional memory provided by the present application will be described in detail below with reference to the accompanying drawings.

[0048] The three-dimensional memory with double stack structure includes a lower stack structure with a lower channel hole and an upper stack structure above the lower stack structure and with an upper channel hole. Before forming the upper stack structure, a sacrificial carbon layer is filled in the lower channel hole of the lower stack structure. Then, after depositing the upper stack structure, the sacrificial carbon layer is removed synchronously in the process of etching the upper stack structure to form the upper channel hole, so that the upper channel hole and the lower channel hole are both filled with air. When the overlay accuracy between the upper channel hole and the lower channel hole is measured by using an optical method, because the materials in the upper channel hole and the lower channel hole are the same (both are air), the measurement signal is weak, and thus the accuracy and reliability of the measurement result of the overlay accuracy between the upper channel hole and the lower channel hole are reduced.

[0049] To improve the accuracy and reliability of the measurement result of the overlay accuracy between the upper channel hole and the lower channel hole in the double stack structure, the embodiment provides a three-dimensional memory, which comprises Figure 1 is a schematic cross-sectional view of the three-dimensional memory in the embodiment of the present application, which shows that Figure 2 is a schematic top view of the device structure in the embodiment of the present application, which shows that Figure 3 is a schematic top view of the measurement structure in the embodiment of the present application. As shown in the figure, Figures 1-3 the three-dimensional memory provided by the embodiment comprises:

[0050] The present application provides a three-dimensional memory, which comprises:

[0051] a substrate 10;

[0052] a device structure 17 on the substrate 10, the device structure comprising a stack layer 11, the stack layer 11 having a plurality of channel holes 12 arranged in an array, each of the channel holes 12 comprising a first channel hole 121 and a second channel hole 122 above the first channel hole 121 and in communication with the first channel hole 121, the first channel hole 121 and the second channel hole 122 in communication therewith having a first preset relative offset in a direction parallel to the top surface of the substrate 10;

[0053] A metrology structure 18 is disposed on the substrate 10 and is distributed outside the device structure 17. The metrology structure 18 includes a plurality of metrology sub-arrays 30 with a pitch 31 between adjacent metrology sub-arrays 30. Each metrology sub-array 30 includes a plurality of metrology holes 16 arranged in an array. The metrology holes 16 include a first metrology hole 161 and a second metrology hole 162 disposed above and in communication with the first metrology hole 161. The first metrology hole 161 and the second metrology hole 162 in communication therewith have a second preset relative offset in a direction parallel to the top surface of the substrate 10. The first preset relative offset and the second preset relative offset have a preset difference.

[0054] In particular, the substrate 10 can be a Si substrate, a Ge substrate, a SiGe substrate, a SOI (Silicon On Insulator) or a GOI (Germanium On Insulator), etc. In the specific embodiment, the substrate 10 is preferably a silicon substrate for supporting the device structure thereon. The stack layer 11 includes gate layers 14 and interlayer insulating layers 13 alternately stacked in a direction perpendicular to the top surface of the substrate 10 (e.g. the Z-axis direction in FIG. 1). Figure 1 The total number of the gate layers 14 and the interlayer insulating layers 13 alternately stacked can be 32, 64 or other number of layers, which can be set according to actual needs by those skilled in the art. The more the number of layers of the stack layer 11, the higher the integration of the corresponding three-dimensional memory. The material of the interlayer insulating layer 13 can be, but is not limited to, an oxide material such as silicon dioxide. The gate layer 14 can be a gate layer in the final three-dimensional memory product (e.g. the material is doped polysilicon or tungsten); or a dummy gate layer (e.g. the material is nitride).

[0055] The specific embodiment adds the metrology structure outside the device structure 17. The metrology structure 18 includes a plurality of metrology sub-arrays 30 with a pitch 31 between adjacent metrology sub-arrays 30, so that when the metrology structure 18 is measured by optical or other methods, the first metrology hole 161 and the second metrology hole 162 in communication therewith are in the direction parallel to the top surface of the substrate 10 (e.g. the Z-axis direction in FIG. 1). Figure 1 , Figure 2 and Figure 3When the first measurement hole 161 and the second measurement hole 162 have a second preset relative offset in the X-axis direction and / or the Y-axis direction, the measurement sub-array 30 and the pitch 31 have different structures, and the diffraction intensity of light rays between the measurement sub-array 30 and the pitch 31 is different, which means that the size of each measurement sub-array 30 in the measurement structure 18 is closer to the wavelength of measurement light, and the diffraction effect inside the measurement sub-array 30 (including the inside of the measurement hole 16) is enhanced, so as to improve the accuracy and reliability of the measurement result of the overlay accuracy of the first measurement hole 161 and the second measurement hole 162 inside the measurement hole 16. In addition, since the difference between the second preset relative offset between the first measurement hole 161 and the second measurement hole 162 in the measurement hole 16 and the first preset relative offset between the first channel hole 121 and the second channel hole 122 in the channel hole 12 is fixed (i.e., the preset difference), the actual relative offset between the first channel hole 121 and the second channel hole 122 in the channel hole 12 (i.e., the second actual relative offset) can be obtained according to the actual relative offset between the first measurement hole 161 and the second measurement hole 162 (i.e., the first actual relative offset).

[0056] The embodiment reflects the relative offset between the first channel hole 121 and the second channel hole 122 in the device structure 17 by measuring the relative offset between the first measurement hole 161 and the second measurement hole 162 in the measurement structure 18, which can improve the accuracy and reliability of the measurement result of the overlay accuracy of the first channel hole 121 and the second channel hole 122, and avoid damaging the channel hole 12, which is helpful to improve the yield of the device structure 17.

[0057] Optionally, the stack layer 11 includes a first stack layer 111 and a second stack layer 112 located above the first stack layer 111, the first channel hole 121 penetrates the first stack layer 111 in a direction perpendicular to the substrate 10, and the second channel hole 122 penetrates the second stack layer 112 in a direction perpendicular to the substrate 10.

[0058] The measurement structure 18 includes a first dielectric layer 151 and a second dielectric layer 152 located above the first dielectric layer 151, the first measurement hole 161 is located in the first dielectric layer 151, and the second measurement hole 162 is located in the second dielectric layer 152.

[0059] For example, the first channel hole 121 may be along a direction perpendicular to the top surface of the substrate 10 (e.g., Figure 1 The first measurement hole 161 can penetrate the first dielectric layer 151 in a direction perpendicular to the top surface of the substrate 10, and the second measurement hole 162 can penetrate the second dielectric layer 152 in a direction perpendicular to the top surface of the substrate 10. The top surface of the substrate 10 refers to the surface of the substrate 10 on which the first stacked layer 111 is formed. The first measurement hole 161 can penetrate the first dielectric layer 151 in a direction perpendicular to the top surface of the substrate 10, and the second measurement hole 162 can penetrate the second dielectric layer 152 in a direction perpendicular to the top surface of the substrate 10. The height of the first dielectric layer 151 can be the same as the height of the first stacked layer 111, so that the height of the first measurement hole 161 is the same as the height of the first channel hole 121. The height of the second dielectric layer 152 can be the same as the height of the second stacked layer 112, so that the height of the second measurement hole 162 is the same as the height of the second channel hole 122.

[0060] In other specific embodiments, the measurement structure may further include a first measurement layer and a second measurement layer located above the first measurement layer. The structure of the first measurement layer is the same as that of the first stacked layer 111 (for example, the first measurement layer includes gate layers 14 and interlayer insulating layers 13 alternately stacked along a direction perpendicular to the top surface of the substrate 10), and the structure of the second measurement layer is the same as that of the second stacked layer 112 (for example, the second measurement layer also includes gate layers 14 and interlayer insulating layers 13 alternately stacked along a direction perpendicular to the top surface of the substrate 10). In this case, the shape and size of the first measurement hole 161 are closer to the shape and size of the first channel hole 121, and the shape and size of the second measurement hole 162 are closer to the shape and size of the second channel hole 122. This simplifies the three-dimensional memory manufacturing process and further improves the accuracy and reliability of the refitting measurement results of the first channel hole 121 and the second channel hole 122.

[0061] To reduce the number of masking operations and lower the manufacturing cost of the three-dimensional memory, optionally, the shape and / or size of the first measuring hole 161 is the same as the shape and / or size of the first channel hole 121.

[0062] The shape and / or size of the second measuring hole 162 is the same as the shape and / or size of the second channel hole 122.

[0063] Optionally, the diameters of the first measuring hole 161, the second measuring hole 162, the first channel hole 121, and the second channel hole 122 are all equal.

[0064] The preset difference is less than or equal to half of the diameter of the first measurement hole 161.

[0065] The diameter in the embodiment refers to the inner diameter of the hole. By setting the preset difference to be less than or equal to half of the diameter of the first measurement hole 161, the actual offset between the first measurement hole 161 and the second measurement hole 162 can be measured without being affected by the preset difference.

[0066] In an embodiment, the preset difference can be 0, i.e., the first preset relative offset and the second preset relative offset are equal. In this case, the offset between the first channel hole and the second channel hole can be directly obtained by measuring the offset between the first measurement hole and the second measurement hole, without additional calculation, which is simple to operate.

[0067] In another embodiment, the diameters of the first measurement hole 161, the second measurement hole 162, the first channel hole 121 and the second channel hole 122 are equal, and the preset difference is one fifth, one fourth or one third of the diameter of the first measurement hole. In this case, the offset between the first channel hole and the second channel hole can be calculated according to the preset difference after measuring the offset between the first measurement hole and the second measurement hole.

[0068] Optionally, the width of the interval 31 is greater than the inner diameter of one measurement hole 16.

[0069] Specifically, the width of the interval 31 should not be too large, otherwise the size of the measurement structure 18 as a whole will be too large, occupying too much area on the surface of the substrate 10. The width of the interval 31 should also not be too small, otherwise it will be difficult to achieve the effect of enhancing the diffraction effect. For example, the width of the interval 31 can be greater than the inner diameter of the plurality of measurement holes 16. For another example, the device structure 17 further includes a gate line slot 21. The width of the interval 31 can be the same as the width of the gate line slot 21. Firstly, the measurement structure 18 occupies less area on the surface of the substrate 10, reducing the size of the measurement structure as a whole. Secondly, the mask plate used to etch the gate line slot 21 in the device structure 17 can be directly used, which helps to save costs. Thirdly, the arrangement of the plurality of measurement sub-arrays can be the same as the arrangement of the plurality of channel hole sub-arrays 20 (as shown in the figure) separated by the gate line slot 21 in the device structure, thereby simplifying the manufacturing process of the measurement structure. The plurality in the embodiment refers to two or more. Figure 2

[0070] Attached Figure 4 ​is a layout diagram of a measurement structure on a substrate in the embodiments of the present application. In order to avoid occupying the area of the chip region on the substrate 10, the substrate 10 can optionally include a plurality of cutting lanes 41, which separate the substrate 10 into a plurality of chips 40, the device structure 17 is located in the chip 40, and the measurement structure 18 is located in the cutting lane 41.

[0071] Optionally, the substrate 10 includes a plurality of cutting lanes 41, which separate the substrate 10 into a plurality of chips 40, and the device structure 17 and the measurement structure 18 are both located in the chip 40.

[0072] In other embodiments, the measurement structure 18 includes a plurality of measurement structures, and part of the measurement structures 18 are distributed in the chip 40, and part of the measurement structures 18 are distributed in the cutting lane 41.

[0073] In order to more comprehensively reflect the internal overlay accuracy of the channel hole 12 in the device structure 17, optionally, a plurality of channel holes 12 in the stack layer 11 correspond one-to-one to a plurality of measurement holes 16 in the measurement structure 18.

[0074] Optionally, a plurality of measurement sub-arrays 30 in the measurement structure 18 are arranged in an array along a first direction and a second direction to form a measurement array, the first direction and the second direction are both parallel to the top surface of the substrate 10, and the first direction intersects the second direction.

[0075] Optionally, all the channel holes 12 in the stack layer 11 are arranged in a channel hole array, and the channel hole array includes a plurality of channel hole sub-arrays 20, and a plurality of channel hole sub-arrays 20 are arranged in parallel along the second direction.

[0076] Each row in the measurement array corresponds to one channel hole sub-array.

[0077] Specifically, as shown in Figure 3 The measurement structure 18 includes a plurality of measurement sub-arrays 30 arranged in a two-dimensional array along the X-axis direction and the Y-axis direction. Any two adjacent measurement sub-arrays 30 in the measurement array have the pitch 31. As shown in Figure 2As shown, the stack layer 11 includes a plurality of channel hole sub-arrays 20 arranged in one-dimensional array along the Y-axis direction, and the adjacent channel hole sub-arrays 20 have the gate line separation groove 21. In order to intuitively reflect the overlay accuracy in each channel hole 12 of the device structure 17, each row of the measurement array corresponds to one channel hole sub-array. In the embodiment, each row of the measurement array corresponds to one channel hole sub-array 20, which means that the total number of rows and columns of the measurement holes 16 in all the measurement sub-arrays 30 in the same row of the measurement array is equal to the number of rows and columns of the channel holes 12 in one channel hole sub-array 20, i.e., each row of the measurement array has all the measurement holes 16 corresponding to all the channel holes 12 in one channel hole sub-array 20.

[0078] Optionally, the substrate 10 has a plurality of device structures 17 and a plurality of measurement structures 18, and one device structure 17 corresponds to one or more measurement structures 18.

[0079] For example, the device structure 17 can be divided into a plurality of regions, and each region corresponds to one or more measurement structures 18.

[0080] Furthermore, the embodiment also provides a forming method of a three-dimensional memory. As shown in Figure 5 is a flowchart of the forming method of the three-dimensional memory in the embodiment. The structure of the three-dimensional memory formed by the embodiment can be seen from Figures 1-4 . As shown in Figures 1-5 , the forming method of the three-dimensional memory includes the following steps:

[0081] Step S51, providing a substrate 10, and defining a first region and a second region outside the first region on the substrate 10, the second region including a plurality of measurement sub-regions arranged in an array, and the adjacent measurement sub-regions have a spacing 31;

[0082] Step S52, forming a plurality of first channel holes 121 arranged in an array on the first region of the substrate 10, and forming a plurality of first measurement holes 161 on each measurement sub-region of the substrate 10;

[0083] Step S53, forming a second via hole 122 in communication with each of the first via holes 121 and a second measurement hole 162 in communication with each of the first measurement holes 161, the first via hole 121 and the second via hole 122 in communication therewith having a first preset relative offset in a direction parallel to the top surface of the substrate 10, the first measurement hole 161 and the second measurement hole 162 in communication therewith having a second preset relative offset, the difference between the first preset relative offset and the second preset relative offset being within a preset range.

[0084] Specifically, the device structure 17 is formed on the first region of the substrate 10, and the measurement structure 18 is formed on the second region. The device structure 17 includes a stack layer 11 having a plurality of via holes 12 arranged in an array, each of the via holes 12 including a first via hole 121 and a second via hole 122 located above and in communication with the first via hole 121. The measurement structure 18 is distributed outside the device structure 17, and each of the measurement sub-arrays 30 is formed above each of the measurement sub-regions. Each of the measurement sub-arrays 30 includes a plurality of measurement holes 16 arranged in an array, the measurement holes 16 including a first measurement hole 161 and a second measurement hole 162 located above and in communication with the first measurement hole 161.

[0085] Optionally, the specific steps of forming a plurality of first via holes 121 arranged in an array on the first region of the substrate 10 and forming a plurality of first measurement holes 161 on each of the measurement sub-regions of the substrate 10 include:

[0086] forming a first stack layer 111 on the first region of the substrate 10 and a first dielectric layer 151 on the second region of the substrate 10;

[0087] forming the first via holes 121 in the first stack layer 111 in a direction perpendicular to the substrate 10 and simultaneously forming the first measurement holes 161 in the first dielectric layer 151 above the measurement sub-regions.

[0088] Optionally, the specific steps of forming a second via hole 122 in communication with each of the first via holes 121 and a second measurement hole 162 in communication with each of the first measurement holes 161 include:

[0089] forming a second stack layer 112 above the first stack layer 111 and a second dielectric layer 152 above the first dielectric layer 151;

[0090] forming a second via hole 122 in the second stack layer 112, the second via hole 122 penetrating the second stack layer 112 in a direction perpendicular to the substrate 10 and communicating with the first via hole 121, and simultaneously forming a second measurement hole 162 in the second dielectric layer 152, the second measurement hole 162 communicating with the first measurement hole 161.

[0091] Furthermore, the embodiment also provides a measurement method of a three-dimensional memory. Figure 6 is a flow chart of the measurement method of the three-dimensional memory in the embodiment. The structure of the three-dimensional memory in the embodiment can be referred to Figures 1-4 , and the forming method of the three-dimensional memory can be referred to Figure 5 . As shown in Figures 1-6 , the measurement method of the three-dimensional memory comprises the following steps:

[0092] Step S61, providing the three-dimensional memory according to any one of the above.

[0093] Step S62, measuring the actual offset of the first measurement hole 161 and the second measurement hole 162 in the measurement hole 16 in a direction parallel to the top surface of the substrate 10 as a first actual relative offset.

[0094] Step S63, calculating a second actual relative offset according to the preset difference and the first actual relative offset, the second actual relative offset being the actual offset of the first via hole 121 and the second via hole 122 in the via hole 12 in a direction parallel to the top surface of the substrate 10.

[0095] Optionally, the specific step of measuring the actual offset of the first measurement hole 161 and the second measurement hole 162 in the measurement hole 16 in a direction parallel to the top surface of the substrate 10 comprises:

[0096] measuring the actual offset of the first measurement hole 161 and the second measurement hole 162 in the measurement hole 16 in a direction parallel to the top surface of the substrate 10 by an optical method.

[0097] Optionally, the specific step of measuring the actual offset of the first measurement hole 161 and the second measurement hole 162 in the measurement hole 16 in a direction parallel to the top surface of the substrate 10 by an optical method comprises:

[0098] emitting a detection light signal to the measurement structure 18;

[0099] The diffraction light signal of the measurement structure 18 is collected and analyzed to obtain the actual offset between the first measurement hole 161 and the second measurement hole 162 in the measurement hole 16 along the direction parallel to the top surface of the substrate 10.

[0100] To further enhance the diffraction effect of the measurement structure 18, in an example, the wavelength of the detection light signal can be the same as the size of the measurement sub-array 30 along the direction parallel to the top surface of the substrate 10 (for example, the length along the X-axis direction and / or the width along the Y-axis direction).

[0101] The three-dimensional memory and the forming method thereof, and the measurement method of the three-dimensional memory provided by the specific embodiment can accurately and reliably measure the actual relative offset between the first measurement hole and the second measurement hole in the measurement hole, and finally accurately and reliably obtain the actual relative offset between the first channel hole and the second channel hole in the channel hole, thereby improving the reliability and accuracy of the overlay measurement result of the first channel hole and the second channel hole in the channel hole, and improving the yield of the three-dimensional memory product.

[0102] The above description is only the preferred embodiment of the present application, and it should be noted that those skilled in the art can make several improvements and refinements without departing from the principles of the present application, and these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A three-dimensional memory, comprising: The application relates to a device structure and a metrology structure. The device structure comprises a substrate and a device structure on the substrate, the device structure comprising a stack layer having a plurality of channel holes arranged in an array, each of the channel holes comprising a first channel hole and a second channel hole above the first channel hole and in communication with the first channel hole, the first channel hole and the second channel hole in communication with the first channel hole having a first preset relative offset in a direction parallel to a top surface of the substrate. The metrology structure comprises a plurality of metrology sub-arrays, each of the metrology sub-arrays comprising a plurality of metrology holes arranged in an array, each of the metrology holes comprising a first metrology hole and a second metrology hole above the first metrology hole and in communication with the first metrology hole, the first metrology hole, the second metrology hole, the first channel hole and the second channel hole having equal diameters, the first metrology hole and the second metrology hole in communication with the first metrology hole having a second preset relative offset in a direction parallel to the top surface of the substrate, the first preset relative offset and the second preset relative offset having a preset difference, the preset difference being less than or equal to half of the diameter of the first metrology hole. The stack layer comprises a first stack layer and a second stack layer above the first stack layer, the first channel hole penetrating the first stack layer in a direction perpendicular to the substrate, the second channel hole penetrating the second stack layer in a direction perpendicular to the substrate.

2. The three-dimensional memory of claim 1, wherein, The metrology structure comprises a first dielectric layer and a second dielectric layer above the first dielectric layer, the first metrology hole being in the first dielectric layer, the second metrology hole being in the second dielectric layer. The first metrology hole has the same shape and / or size as the first channel hole.

3. The three-dimensional memory of claim 1, wherein, The second metrology hole has the same shape and / or size as the second channel hole. The width of the interval is greater than the inner diameter of one of the metrology holes.

4. The three-dimensional memory of claim 1, wherein, The device structure further comprises a gate line slot.

5. The three-dimensional memory of claim 1, wherein, The width of the interval is greater than or equal to the width of the gate line slot. The substrate comprises a plurality of scribe lines, the scribe lines separating the substrate into a plurality of chips, the device structure being in the chips, the metrology structure being in the scribe lines.

6. The three-dimensional memory of claim 1, wherein, The substrate comprises a plurality of scribe lines, the scribe lines separating the substrate into a plurality of chips, the device structure and the metrology structure being in the chips.

7. The three-dimensional memory of claim 1, wherein, The plurality of channel holes in the stack layer correspond to the plurality of metrology holes in the metrology structure one by one.

8. The three-dimensional memory of claim 1, wherein, The plurality of metrology sub-arrays in the metrology structure are arranged in an array in a first direction and a second direction, the first direction and the second direction being parallel to the top surface of the substrate, and the first direction intersecting the second direction.

9. The three-dimensional memory of claim 1, wherein, ​ 10. The three-dimensional memory as recited in claim 9, further comprising: All of the channel holes in the stack layer are arranged in a channel hole array, and the channel hole array includes a plurality of channel hole sub-arrays, and the plurality of channel hole sub-arrays are arranged in parallel along the second direction. Each row in the metrology array corresponds to one channel hole sub-array.

11. The three-dimensional memory as recited in claim 1, further comprising: The substrate has a plurality of device structures and a plurality of metrology structures thereon, and one device structure corresponds to one or more metrology structures.

12. A method of forming a three-dimensional memory, comprising: The method comprises the following steps: providing a substrate, and defining a first region and a second region outside the first region on the substrate, the second region including a plurality of metrology sub-regions arranged in an array, and there is a spacing between adjacent metrology sub-regions; forming a plurality of first channel holes arranged in an array on the first region of the substrate, and forming a plurality of first metrology holes on each metrology sub-region of the substrate; forming a second channel hole communicating with each first channel hole above the first channel hole, and forming a second metrology hole communicating with each first metrology hole above the first metrology hole, the aperture of the first metrology hole, the aperture of the second metrology hole, the aperture of the first channel hole and the aperture of the second channel hole are equal, in a direction parallel to the top surface of the substrate, there is a first preset relative offset between the first channel hole and the second channel hole communicating with the first channel hole, and there is a second preset relative offset between the first metrology hole and the second metrology hole communicating with the first metrology hole, the first preset relative offset and the second preset relative offset have a preset difference, and the preset difference is less than or equal to half of the aperture of the first metrology hole.

13. A method of metrology of a three-dimensional memory, characterized in that, The method comprises the following steps: providing a three-dimensional memory as claimed in any one of claims 1-11; measuring the actual offset of the first metrology hole and the second metrology hole in the metrology hole in the direction parallel to the top surface of the substrate as a first actual relative offset; calculating a second actual relative offset according to the preset difference and the first actual relative offset, and the second actual relative offset is the actual offset of the first channel hole and the second channel hole in the channel hole in the direction parallel to the top surface of the substrate.

14. The method of claim 13, wherein: The specific step of measuring the actual offset of the first metrology hole and the second metrology hole in the metrology hole in the direction parallel to the top surface of the substrate comprises: measuring the actual offset of the first metrology hole and the second metrology hole in the metrology hole in the direction parallel to the top surface of the substrate by an optical method.

15. The method of claim 14, wherein: The specific step of measuring the offset of the first metrology hole and the second metrology hole in the metrology hole in the direction parallel to the top surface of the substrate by an optical method comprises: emitting a detection light signal to the metrology structure; collecting and analyzing the diffraction light signal of the metrology structure to obtain the actual offset of the first metrology hole and the second metrology hole in the metrology hole in the direction parallel to the top surface of the substrate.

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