Semiconductor device and semiconductor module

Abstract

A semiconductor device capable of improving heat dissipation characteristics is provided. When a first surface of a first member is viewed in plan, a plurality of circuit modules are arranged in an inner region of the first surface. A second member is joined in surface contact with the first surface of the first member. The second member includes at least one circuit module. A conductor protrusion protrudes from the second member toward a side opposite to the first member side. One of the circuit modules of the second member constitutes a first amplification circuit including a plurality of first transistors connected in parallel with each other. At least one of the plurality of circuit modules of the first member overlaps at least one of the circuit modules of the second member when viewed in plan.

Description

Technical Field

[0001] This invention relates to semiconductor devices and semiconductor modules. Background Technology

[0002] Electronic devices used for mobile communications, satellite communications, etc., include RF front-end modules that integrate high-frequency signal transmission and reception. RF front-end modules consist of monolithic microwave integrated circuits (MMICs) with high-frequency amplification capabilities, control ICs for controlling the high-frequency amplification circuit, switching ICs, duplexers, etc.

[0003] Patent Document 1 discloses a high-frequency module miniaturized by stacking a control IC on an MMIC. The high-frequency module disclosed in Patent Document 1 includes an MMIC mounted on a module substrate and a control IC stacked on the MMIC. The electrodes of the MMIC, the electrodes of the control IC, and the electrodes on the module substrate are electrically connected by wire bonding.

[0004] Patent Document 1: U.S. Patent Application Publication No. 2015 / 0303971

[0005] High-frequency amplifier circuits, for example, use heterojunction bipolar transistors (HBTs). HBTs generate heat due to collector losses during operation. This temperature rise caused by heating acts in a direction that further increases the collector current. If this positive feedback condition is met, the HBT will reach thermal runaway. To avoid thermal runaway of the HBT, the upper limit of its output power is limited.

[0006] To achieve high output in high-frequency amplifier circuits, it is desirable to improve the heat dissipation characteristics from semiconductor devices, including HBTs. However, the high-frequency module disclosed in Patent Document 1 fails to meet the demands for high output in recent years' high-frequency amplifier circuits. Summary of the Invention

[0007] The purpose of this invention is to provide a semiconductor device and a semiconductor module that can improve heat dissipation characteristics.

[0008] According to one aspect of the present invention, a semiconductor device is provided, comprising:

[0009] The first component has a first surface and includes a plurality of circuit modules disposed in the internal region of the first surface when viewed from above;

[0010] The second component is in contact with the first surface of the first component and includes at least one circuit module; and

[0011] The conductor protrusion extends from the second component to the side opposite to the first component.

[0012] One of the circuit modules in the second component constitutes a first amplifier circuit, which includes a plurality of first transistors connected in parallel with each other.

[0013] When viewed from above, at least one circuit module of the first component overlaps with at least one circuit module of the second component.

[0014] According to another aspect of the present invention, a semiconductor module is provided, comprising:

[0015] The first component has a first surface and includes a plurality of circuit modules disposed in the internal region of the first surface when viewed from above;

[0016] The second component is in contact with the first surface of the first component and includes at least one circuit module.

[0017] The first conductor protrusion protrudes from the first surface of the first component;

[0018] The second conductor protrusion protrudes from the second component in the same direction as the first conductor protrusion; and

[0019] The module substrate is equipped with the first component and the second component described above.

[0020] One of the circuit modules in the second component constitutes a first amplifier circuit, which includes a plurality of first transistors connected in parallel with each other.

[0021] When viewed from above, at least one circuit module of the first component overlaps with at least one circuit module of the second component.

[0022] When viewed from above, the circuit modules of the first component and the second component, which overlap each other, are interconnected via the first conductor protrusion, the second conductor protrusion, and wiring disposed on the module substrate.

[0023] The heat generated in the first transistor is conducted through two heat conduction paths: one from the first transistor to the first component, and the other via a conductor protrusion. Therefore, the heat dissipation characteristics of the first transistor can be improved. Attached Figure Description

[0024] Figure 1 This is a block diagram of a high-frequency module including the semiconductor device of the first embodiment.

[0025] Figure 2 This is a diagram showing the positional relationship of the circuit components of the high-frequency module in the first embodiment when viewed from above.

[0026] Figure 3This is a schematic cross-sectional view of the semiconductor device of the first embodiment.

[0027] Figure 4A These are the equivalent circuit diagrams of the plurality of units constituting the first amplifier circuit of the semiconductor device of the first embodiment. Figure 4B It is a schematic cross-sectional view of a unit that constitutes a first amplifier circuit formed in the second component.

[0028] Figure 5A This is a schematic diagram showing the in-plane distribution of each circuit module when viewed from above on the first surface of the semiconductor device of the first embodiment. Figure 5B This is a top view showing the arrangement of the multiple transistors that make up the first amplifier circuit.

[0029] Figures 6A to 6F The accompanying drawing is a cross-sectional view of a semiconductor device during an intermediate stage of manufacturing.

[0030] Figures 7A to 7C The attached figure is a cross-sectional view of a semiconductor device during an intermediate stage of manufacturing. Figure 7D This is a cross-sectional view of the completed semiconductor device.

[0031] Figure 8 This is a cross-sectional view of a semiconductor module, a variation of the first embodiment.

[0032] Figure 9 This is a schematic diagram showing the in-plane distribution of each circuit module when viewed from above the first surface of the semiconductor device of the second embodiment.

[0033] Figure 10A This is a schematic diagram showing the in-plane distribution of each circuit module when viewed from above on the first surface of the semiconductor device of the third embodiment. Figure 10B This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0034] Figure 11 This is a schematic diagram showing the in-plane distribution of each circuit module when viewed from above the first surface of the semiconductor device of the fourth embodiment. Detailed Implementation

[0035] [First Embodiment]

[0036] Reference Figures 1 to 7D The semiconductor device of the first embodiment will be described with reference to the accompanying drawings. The semiconductor device of the first embodiment described below is a high-frequency power amplifier.

[0037] Figure 1This is a block diagram of a high-frequency module 20 including the semiconductor device 30 of the first embodiment. The high-frequency module 20 includes the semiconductor device 30 of the first embodiment, an output matching circuit 76, multiple duplexers 70, an antenna switch 72, two receiving band selection switches 73, two low-noise amplifiers 71, a receiving output terminal selection switch 74, and a second control circuit 75. These circuit components are flip-chip mounted on a module substrate. The high-frequency module 20 has the function of transmitting and receiving in frequency division duplex (FDD) mode.

[0038] Semiconductor device 30 includes a first component 31 and a second component 32 coupled to the first component 31. For example, the first component 31 is constructed of an elemental semiconductor system, and the second component 32 is constructed of a compound semiconductor. An input switch 43, a first control circuit 42, and a frequency band selection switch 41 are formed in the first component 31. A two-stage high-frequency amplifier circuit 50, consisting of a first amplifier circuit 51 and a second amplifier circuit 52, and a bias circuit 53 are formed in the second component 32. The second amplifier circuit 52 is a primary amplifier circuit, and the first amplifier circuit 51 is a final stage amplifier circuit. Figure 1 In the diagram, the circuit modules located in the first component 31 are marked with relatively light shading lines, while the circuit modules located in the second component 32 are marked with relatively dark shading lines. The bias circuit 53 supplies bias current to the first amplifier circuit 51 and the second amplifier circuit 52 according to the control signal from the first control circuit 42.

[0039] The two input contacts of input switch 43 are respectively connected to high-frequency signal input terminals IN1 and IN2 provided on the module substrate. High-frequency signals are input from the two high-frequency signal input terminals IN1 and IN2. Input switch 43 selects one of the two input contacts and inputs the high-frequency signal input to the selected contact to the high-frequency amplifier circuit 50.

[0040] The high-frequency signal amplified in the high-frequency amplifier circuit 50 is input to one input contact of the frequency band selection switch 41 through the output matching circuit 76. The frequency band selection switch 41 selects one contact from multiple output contacts and outputs the high-frequency signal amplified in the high-frequency amplifier circuit 50 from the selected output contact.

[0041] Two of the multiple output contacts of the frequency band selection switch 41 are connected to auxiliary output terminals PAAUX1 and PAAUX2 respectively, which are provided on the module substrate. The other six contacts are connected to the transmit input ports of multiple duplexers 70 prepared for each frequency band. The frequency band selection switch 41 has the function of selecting one duplexer 70 from the multiple duplexers 70 prepared for each frequency band.

[0042] Antenna switch 72 has multiple contacts on the circuit side and two contacts on the antenna side. Two of the multiple contacts on the circuit side of antenna switch 72 are connected to the transmit signal input terminals TRX1 and TRX2, respectively. The other six contacts on the circuit side are connected to the input / output shared ports of multiple duplexers 70. The two contacts on the antenna side are connected to antenna terminals ANT1 and ANT2, respectively. Antenna terminals ANT1 and ANT2 are connected to the antenna.

[0043] Antenna switch 72 connects two antenna-side contacts to two contacts selected from a plurality of contacts on the circuit side. When communicating using a single frequency band, antenna switch 72 connects one contact on the circuit side and one contact on the antenna side. The high-frequency signal, amplified in high-frequency amplifier circuit 50 and transmitted via duplexer 70 for the corresponding frequency band, is transmitted from the antenna connected to the selected antenna-side contact.

[0044] Each of the two receiving band selection switches 73 has four input contacts and one output contact. Three of the four input contacts of each of the two band selection switches 73 are connected to the receiving output port of the duplexer 70. The remaining contact of each of the two band selection switches 73 is connected to the auxiliary input terminals LNAAUX1 and LNAAUX2.

[0045] The output contacts of the two receiver band selection switches 73 are respectively connected to the two low-noise amplifiers 71. The two receiver band selection switches 73 respectively enable the received signal through the duplexer 70 to be input to the low-noise amplifier 71.

[0046] The contacts on the two circuit sides of the output terminal selection switch 74 are connected to the output ports of the two low-noise amplifiers 71, respectively. The contacts on the three terminal sides of the output terminal selection switch 74 are connected to the receive signal output terminals LNAOUT1, LNAOUT2, and LNAOUT3, respectively. The received signal, amplified in the low-noise amplifier 71, is output from the receive signal output terminal selected by the output terminal selection switch 74.

[0047] Power supply voltages are applied to the first amplifier circuit 51 and the second amplifier circuit 52 respectively from the power supply terminals VCC1 and VCC2 located on the module substrate.

[0048] The first control circuit 42 is connected to the power supply terminal VIO1, the control signal terminal SDATA1, and the clock terminal SCLK1. The first control circuit 42 controls the bias circuit 53, the input switch 43, and the frequency band selection switch 41 based on the control signal given to the control signal terminal SDATA1.

[0049] The second control circuit 75 is connected to the power supply terminal VIO2, the control signal terminal SDATA2, and the clock terminal SCLK2. The second control circuit 75 controls the low-noise amplifier 71, the receiver band selection switch 73, and the output terminal selection switch 74 based on the control signal given to the control signal terminal SDATA2.

[0050] The module substrate also includes a power supply terminal VBAT and a drain voltage terminal VDD2. Power is supplied from the power supply terminal VBAT to the bias circuit of the high-frequency amplifier circuit 50 and the first control circuit 42. The power supply voltage is applied to the low-noise amplifier 71 from the drain voltage terminal VDD2.

[0051] Figure 2 This diagram shows the positional relationship of the circuit components of the high-frequency module 20 in the first embodiment when viewed from above. A semiconductor device 30, multiple duplexers 70, a low-noise amplifier 71, an antenna switch 72, and other surface-mount passive components are mounted on the module substrate 21. In top view, the first component 31 of the semiconductor device 30 is larger than the second component 32 and includes the second component 32.

[0052] The first component 31 includes a frequency band selection switch 41, a first control circuit 42, and an input switch 43. Figure 2 In the diagram, the area enclosed by dashed lines shows the circuit modules, including the frequency band selection switch 41, the first control circuit 42, and the input switch 43. Here, a "circuit module" refers to a collection of multiple circuit elements, such as semiconductor elements and passive components, constructed to achieve a specific function, as well as the wiring connecting these circuit elements. Generally, circuits are designed and laid out on a semiconductor substrate according to each circuit module.

[0053] The output matching circuit 76 is composed of passive components such as inductors disposed within the module substrate and capacitors surface-mounted on the module substrate. The inductors constituting the output matching circuit 76 are positioned to overlap with the semiconductor device 30 when viewed from above. In this specification, the state of "two components overlapping when viewed from above" includes a state in which one component includes another component, a state in which a part of one component overlaps with a part of another component, and a state in which the outer perimeters of the two components coincide.

[0054] Figure 3 This is a schematic cross-sectional view of the semiconductor device 30 according to the first embodiment. The first component 31 includes a substrate 311, a multilayer wiring structure 312 disposed on the substrate 311, and a first component protective film 313 covering the surface of the multilayer wiring structure 312. The substrate 311 includes the semiconductor portion of an elemental semiconductor system. For example, a silicon substrate or a silicon-on-insulator (SOI) substrate is used as the substrate 311. Band selection switch 41 ( Figure 1), First control circuit 42 ( Figure 1 ) and input switch 43 ( Figure 1 It is composed of semiconductor elements formed on the surface layer of substrate 311 and wiring within multilayer wiring structure 312. Figure 3 In the diagram, the area forming the input switch 43 is shown enclosed by a dashed line. The outermost surface of the first component 31 is referred to as the first surface 31A. The upper surface of the first component protective film 313 corresponds to the first surface 31A.

[0055] The second component 32 contacts and engages with the first surface 31A of the first component 31. A first amplifier circuit 51 is formed on the second component 32. Figure 1 ), second amplifier circuit 52 ( Figure 1 ) and bias circuit 53 ( Figure 1 ).exist Figure 3 In the image, the area where the second amplifier circuit 52 is located is shown, enclosed by a dashed line.

[0056] An interlayer insulating film 67 is disposed on the first surface 31A to cover the second component 32. Multiple openings are provided at predetermined locations on the interlayer insulating film 67. Multiple pads 62 and 63 and multiple traces 61 are disposed on the interlayer insulating film 67. There is a case where the wiring layer with multiple pads 62 and 63 and multiple traces 61 is referred to as a rewiring layer. There is a case where the traces 61 within the rewiring layer are referred to as rewiring.

[0057] Wiring 61 connects to the input switch 43 via wiring 315 within the multilayer wiring structure 312 through an opening in the interlayer insulating film 67, and is connected to the second amplifier circuit 52 via other openings in the interlayer insulating film 67. That is, the input switch 43 formed in the first component 31 and the second amplifier circuit 52 formed in the second component 32 are directly electrically connected via wiring 61 in the rewiring layer. Here, "direct electrical connection" means electrical connection without via active components such as transistors. For example, the case of connection via a circuit composed only of passive components such as impedance matching circuits is included in the case of "direct electrical connection". Other wiring included in the rewiring layer is used, for example, for the first control circuit 42 (…). Figure 1 ) and bias circuit 53 ( Figure 1 (connections, etc.)

[0058] In top view, pad 62 is included in the second component 32 and connected to the circuitry formed in the second component 32. In addition to pad 62, other pads are also included in the second component 32 in top view. In top view, pad 63 is disposed on the outer side of the second component 32 and connected to the input switch 43 formed in the first component 31 via wiring 316 within the multilayer wiring structure 312 through an opening provided in the interlayer insulating film 67. In addition to pad 63, other pads are disposed on the outer side of the second component 32 in top view.

[0059] A protective film 68 is disposed on the interlayer insulating film 67 to cover the redistribution layer. The protective film 68 has openings that expose portions of the upper surfaces of the pads 62 and 63, respectively. Conductor protrusions 82 and 83 are disposed on the pads 62 and 63, respectively. The conductor protrusion 82 includes a Cu pillar 82A connected to the pad 62 and a solder layer 82B disposed on the upper surface of the Cu pillar 82A. This type of conductor protrusion 82 is referred to as a Cu pillar bump.

[0060] Alternatively, a bump under-metal layer can be placed on the bottom surface of the Cu pillar 82A to improve adhesion. Other conductor protrusions 83 also have the same stacked structure as conductor protrusions 82. Furthermore, conductor protrusions 82, 83, etc., can replace Cu pillar bumps with Au bumps, solder ball bumps, conductor pillars erected on pads, etc. Like Au bumps, bumps without a solder layer are also called pillars. Conductor pillars erected on pads are also called posts.

[0061] Conductor protrusion 82, for example, is used for Figure 1 The diagram shows the connection between power terminal VCC1 and the first amplifier circuit 51, the connection between power terminal VCC2 and the second amplifier circuit 52, and the connection between the first amplifier circuit 51 and the output matching circuit 76. Furthermore, the conductor protrusion 82 is used to connect the grounding conductor within the second component 32 to the grounding conductor of the module substrate.

[0062] Conductor protrusion 83, for example, is used for Figure 1 The connection shown includes the input switch 43 to the high-frequency signal input terminals IN1 and IN2, the connection of the first control circuit 42 to the power supply terminal VIO1, the control signal terminal SDATA1 and the clock terminal SCLK1, the connection of the frequency band selection switch 41 to the output matching circuit 76, and the connection of multiple duplexers 70.

[0063] Figure 4A The first amplifier circuit 51 constituting the semiconductor device of the first embodiment ( Figure 1 The equivalent circuit diagram of each unit in the multiple units of the amplifier circuit 51. The first amplifier circuit 51 is composed of multiple units connected in parallel. In addition, the second amplifier circuit 52 ( Figure 1It also has the same circuit structure as the first amplifier circuit 51. However, the number of units constituting the second amplifier circuit 52 is less than the number of units constituting the first amplifier circuit 51.

[0064] Each unit includes a transistor Q, an input capacitor Cin, and a ballast resistor Rb. The base of transistor Q is connected to the high-frequency signal input wiring 105RF via the input capacitor Cin. Furthermore, the base of transistor Q is connected to the base bias wiring 104BB via the ballast resistor Rb. The emitter of transistor Q is grounded. The collector of transistor Q is connected to the collector wiring 104C. A power supply voltage is applied to the collector of transistor Q via collector wiring 104C, and the amplified high-frequency signal is output from the collector.

[0065] Figure 4B It constitutes the first amplifier circuit 51 formed in the second component 32. Figure 1 This is a schematic cross-sectional view of one unit of the first component 31. The second component 32 includes a substrate semiconductor layer 101. The second component 32 is bonded to the first component 31 through surface contact between the substrate semiconductor layer 101 and the first component 31. The substrate semiconductor layer 101 is divided into a conductive region 101A and a device separation region 101B. The substrate semiconductor layer 101 is, for example, made of GaAs. The conductive region 101A is formed of n-type GaAs, and the device separation region 101B is formed by ion implantation of insulating impurities into the n-type GaAs layer.

[0066] A transistor Q is disposed on the conductive region 101A. The transistor Q comprises a collector layer 102C, a base layer 102B, and an emitter layer 102E, sequentially stacked starting from the conductive region 101A. The emitter layer 102E is disposed on a portion of the base layer 102B. As an example, the collector layer 102C is formed of n-type GaAs, the base layer 102B is formed of p-type GaAs, and the emitter layer 102E is formed of n-type InGaP. That is, the transistor Q is a heterojunction bipolar transistor.

[0067] A base electrode 103B is disposed on the base layer 102B and is electrically connected to the base layer 102B. An emitter electrode 103E is disposed on the emitter layer 102E and is electrically connected to the emitter layer 102E. A collector electrode 103C is disposed on the conductive region 101A. The collector electrode 103C is electrically connected to the collector layer 102C via the conductive region 101A.

[0068] A first interlayer insulating film 111 is disposed on the substrate semiconductor layer 101 to cover the transistor Q, collector electrode 103C, base electrode 103B, and emitter electrode 103E. The first interlayer insulating film 111 is formed, for example, by an inorganic insulating material such as SiN. Multiple openings are provided at predetermined positions on the interlayer insulating film 111.

[0069] A first layer of emitter wiring 104E, base wiring 104B, collector wiring 104C, and base bias wiring 104BB are disposed on the interlayer insulating film 111. A ballast resistor element Rb is also disposed on the interlayer insulating film 111. Emitter wiring 104E is connected to emitter electrode 103E through an opening in the interlayer insulating film 111. Base wiring 104B is connected to base electrode 103B through other openings in the interlayer insulating film 111. Collector wiring 104C is connected to collector electrode 103C through other openings in the interlayer insulating film 111.

[0070] The base wiring 104B extends into the region where no transistor Q is configured, and the leading end of the base wiring 104B overlaps with one end of the ballast resistor element Rb. In the overlapping portion, the base wiring 104B is electrically connected to the ballast resistor element Rb. The other end of the ballast resistor element Rb overlaps with the base bias wiring 104BB. In the overlapping portion, the ballast resistor element Rb is electrically connected to the base bias wiring 104BB.

[0071] A second interlayer insulating film 112 is disposed on the interlayer insulating film 111 to cover the first layer of emitter wiring 104E, base wiring 104B, base bias wiring 104BB, and ballast resistor element Rb. The second interlayer insulating film 112 is also formed of an inorganic insulating material such as SiN.

[0072] A second emitter wiring 105E and a high-frequency signal input wiring 105RF are disposed on the interlayer insulating film 112. The second emitter wiring 105E is connected to the first emitter wiring 104E through an opening in the interlayer insulating film 112. In top view, a portion of the high-frequency signal input wiring 105RF overlaps with the first base wiring 104B. An input capacitor Cin is formed in the overlapping area.

[0073] A third interlayer insulating film 67 is provided to cover the second emitter wiring 105E and the high-frequency signal input wiring 105RF. The third interlayer insulating film 67 is formed, for example, of an organic insulating material such as polyimide. Furthermore, such as Figure 3 As shown, the third interlayer insulating film 67 extends onto the first component 31.

[0074] A pad 62 is disposed on the third interlayer insulating film 67. The pad 62 is connected to the second layer emitter wiring 105E through an opening provided in the interlayer insulating film 67.

[0075] Figure 5A This refers to the first surface 31A of the semiconductor device 30 in the first embodiment, viewed from above. Figure 3 This is a schematic diagram showing the in-plane arrangement of each circuit module at the time of the circuit's formation. The multiple circuit modules formed in the first component 31 respectively constitute... Figure 1 The frequency band selection switch 41, the first control circuit 42, and the input switch 43 are shown. When viewed from above, these circuit modules are located within the interior region of the first surface 31A. Figure 5A The diagram shows the circuit module constituting the input switch 43 and the circuit module constituting the first control circuit 42. Figure 5A In the image, the circuit module formed in the first component 31 is marked with a shading line that slopes downwards to the right.

[0076] The multiple circuit modules formed in the second component 32 respectively constitute the final stage first amplifier circuit 51, the primary second amplifier circuit 52, and the bias circuit 53.

[0077] Figure 5B This represents the plurality of transistors Q that constitute the first amplifier circuit 51. Figure 4A , Figure 4B This is a top-view diagram of the configuration of transistors Q. Multiple transistors Q each comprise a collector layer 102C and a base layer 102B. In top view, the outer periphery of the collector layer 102C is almost flush with the outer periphery of the base layer 102B. In top view, the emitter layer 102E (… Figure 4B The transistors Q are contained in the base layer 102B. The transistors Q have a shape that, when viewed from above, in one direction (in... Figure 5B The shape is relatively long (vertical). Multiple transistors Q have parallel long sides, and are arranged in a configuration orthogonal to their long sides (in...). Figure 5B (The center represents the left and right directions).

[0078] Multiple transistors Q are distributed within region 55. Region 55, in which the multiple transistors Q are distributed, can be defined, for example, as the smallest convex polygon containing the multiple transistors Q when viewed from above.

[0079] Alternatively, multiple columns of transistors Q can be arranged in a direction orthogonal to the direction in which the transistors Q are arranged. In this case, the smallest convex polygon containing all the transistors Q included in the multiple transistor columns is defined as the region 55 in which the multiple transistors Q are distributed.

[0080] like Figure 5AAs shown, within the circuit module constituting the first amplifier circuit 51, a region 55 is provided where multiple transistors Q are distributed. Conductor protrusions 82E and 82C are respectively connected to the emitters and collectors of the multiple transistors Q. Viewed from above, the conductor protrusion 82E for the emitters encompasses the region 55 where multiple transistors Q are distributed. Within the circuit module constituting the first amplifier circuit 51, there is also... Figure 4A and Figure 4B The input capacitor Cin and the ballast resistor element Rb are shown.

[0081] When viewed from above, the circuit module constituting the second amplifier circuit 52 overlaps with the circuit module constituting the input switch 43. When viewed from above, the circuit module constituting the bias circuit 53 overlaps with a portion of the multiple circuit modules constituting the first control circuit 42. For example, the first control circuit 42 includes a circuit module that outputs control of the bias current supplied to the first amplifier circuit 51, a circuit module constituting a fuse array, etc. In this embodiment, when viewed from above, the circuit module that outputs control of the bias current supplied to the first amplifier circuit 51 overlaps with the circuit module constituting the bias circuit 53. In this specification, the state of "two circuit modules overlapping when viewed from above" includes a state where the area occupied by one circuit module includes the area occupied by another circuit module, a state where a portion of the area occupied by one circuit module overlaps with a portion of the area occupied by another circuit module, and a state where the outer perimeters of the areas occupied by each of the two circuit modules are aligned. Furthermore, a circuit module may include multiple semiconductor elements, multiple passive elements, and wiring connecting these elements as constituent elements; a state where only the wiring of a constituent element overlaps with another circuit module can also be considered a state of two circuit modules overlapping.

[0082] Input switch 43 and second amplifier circuit 52 are connected via wiring 61 in the rewiring layer. Figure 3 Direct electrical connection. The first control circuit 42 and the bias circuit 53 are directly electrically connected via other wiring 64 within the redistribution layer. In top view, wiring 61, 64 intersects the edge of the second component 32.

[0083] Next, refer to Figures 6A to 7D The accompanying drawings illustrate a method for manufacturing the semiconductor device 30 of the first embodiment. Figures 6A to 7C The attached figure is a cross-sectional view of the semiconductor device 30 during the manufacturing process. Figure 7D This is a cross-sectional view of the completed semiconductor device 30.

[0084] like Figure 6A As shown, a release layer 201 is epitaxially grown on a single-crystal mother substrate 200 of a compound semiconductor such as GaAs, and a device forming layer 202 is formed on the release layer 201. A device forming layer 202 is formed on the device forming layer 202. Figure 4BThe second component 32 shown includes transistor Q, a first wiring layer, a second wiring layer, etc. These circuit elements and wiring layers are formed using conventional semiconductor processes. Figure 6A The element structure formed on the element forming layer 202 is omitted from the description. At this stage, the element forming layer 202 is not separated into a separate second component 32.

[0085] Next, as Figure 6B As shown, a resist pattern (not shown) is used as an etching mask to pattern the element formation layer 202. Figure 5A ) and release layer 201. In this stage, element forming layer 202 ( Figure 5A ) is separated into each second component 32.

[0086] Next, as Figure 6C As shown, a connecting support 204 is attached to the separated second component 32. Thus, multiple second components 32 are interconnected via the connecting support 204. Furthermore, it is also possible to... Figure 6B The patterning process leaves a resist pattern used as an etching mask, so that the second component 32 and the connecting support 204 are sandwiched between the resist pattern.

[0087] Next, as Figure 6D As shown, the release layer 201 is selectively etched onto the mother substrate 200 and the second component 32. As a result, the second component 32 and the connecting support 204 are peeled off from the mother substrate 200. To selectively etch the release layer 201, a compound semiconductor with an etching resistance different from both the mother substrate 200 and the second component 32 is used as the release layer 201.

[0088] like Figure 6E As shown, a structure is prepared to be formed on the first component 31 ( Figure 3 The input switch 43 and the multi-layer wiring structure 312 () Figure 3 The substrate 210, etc. At this stage, the substrate 210 is not separated into a separate first component 31.

[0089] like Figure 6F As shown, the second component 32 is bonded to the substrate 210. The bonding between the second component 32 and the substrate 210 is achieved through van der Waals bonds or hydrogen bonds. Alternatively, the second component 32 can also be bonded to the substrate 210 by electrostatic force, covalent bonds, eutectic alloy bonds, etc. For example, if a portion of the surface of the substrate 210 is formed of Au, the two can be bonded by pressing the second component 32 tightly against the Au region.

[0090] Next, as Figure 7A As shown, the connecting support 204 is peeled off from the second component 32. After peeling off the connecting support 204, as... Figure 7BAs shown, an interlayer insulating film 67 and a redistribution layer are formed on the substrate 210 and the second component 32. The redistribution layer includes wiring 61, pads 62, and 63. Figure 3 )wait.

[0091] Next, as Figure 7C As shown, a protective film 68 is formed on the redistribution layer, and an opening is formed at a predetermined position on the protective film 68. Then, conductor protrusions 82 are formed within the openings and on the protective film 68. Simultaneously with the formation of the conductor protrusions 82, other conductor protrusions 83 are also formed. Figure 3 )wait.

[0092] Finally, as Figure 7D As shown, substrate 210 is cut. This yields semiconductor device 30.

[0093] Next, the superior effects of the first embodiment will be explained.

[0094] In the semiconductor device 30 of the first embodiment, the transistor Q of the first amplifier circuit 51 ( Figure 5B This becomes the largest heat source. Therefore, the temperature of the region 55, where multiple transistors Q are configured, rises. In the first embodiment, as... Figure 3 As shown, the second component 32 is in surface contact with and bonded to the first component 31, forming a heat conduction path that intersects the interface between the first component 31 and the second component 32 and extends from the second component 32 toward the first component 31. Heat generated in the multiple transistors Q is conducted to the first component 31 through this heat conduction path. A protective film 313 of the first component (which may also be present in the area overlapping the second component 32 when viewed from above) is also present. Figure 3 An opening is provided, and metal is filled into the opening. According to this structure, since the second component 32 is in contact with the metal portion, the thermal resistance of the heat conduction path can be reduced.

[0095] Heat conducted from the second component 32 to the first component 31 diffuses into the first component 31. The heat diffused into the first component 31 is dissipated to the outside from the surface of the first component 31. When the semiconductor device 30 is mounted on the module substrate and covered by molding resin, heat is conducted from the first component 31 to the molding resin.

[0096] Furthermore, conductor protrusion 82 ( Figure 3This serves as a heat conduction path from the second component 32 to the module substrate. Thus, two paths are formed: a heat conduction path from the second component 32 towards the module substrate and a heat conduction path from the second component 32 towards the first component 31. Therefore, the heat dissipation characteristics of the second component 32 can be improved. To achieve a sufficiently improved heat dissipation characteristic, it is preferable that the semiconductor portion of the substrate 311 of the first component 31 uses a semiconductor with a thermal conductivity higher than that of the compound semiconductor formed on the semiconductor element disposed in the second component 32, such as elemental semiconductors like Si or Ge. Furthermore, as the semiconductor element formed on the second component 32, to amplify high-frequency signals, it is preferable to use a semiconductor element of a compound semiconductor system with a higher electron mobility than that of the semiconductor portion of the substrate 311 of the first component 31.

[0097] In the first embodiment, as Figure 3 as well as Figure 5A As shown, the circuit modules constituting the direct electrical connection between the input switch 43 and each of the second amplifier circuit 52 via wiring 61 within the rewiring layer overlap each other when viewed from above. Similarly, as Figure 5A As shown, the circuit modules that constitute each of the first control circuit 42 and bias circuit 53, which are directly connected via wiring 64 in the redistribution layer, overlap each other when viewed from above.

[0098] Generally, if the circuit modules of the first component 31 and the second component 32 are overlapped, the electronic circuit formed by the two overlapping circuit modules is prone to electromagnetic interference. Between two directly electrically connected circuits, even if electromagnetic interference occurs, the impact of the interference on the operation of the electronic circuit is relatively small. For example, even if the circuit module constituting the input switch 43 and the circuit module constituting the second amplifier circuit 52 are overlapped, the impact of electromagnetic interference is relatively small. Similarly, even if the circuit module constituting the first control circuit 42 and the circuit module constituting the bias circuit 53 are overlapped, the impact of electromagnetic interference is relatively small. In the first embodiment, since the circuit modules constituting two directly electrically connected circuits are arranged to overlap when viewed from above, the impact of electromagnetic interference on the overall circuit is mitigated.

[0099] Furthermore, by configuring the circuit modules of the first component 31 and the second component 32 to overlap when viewed from above, the size of the semiconductor device 30 when viewed from above can be reduced. Thus, in the first embodiment, the effects caused by electromagnetic interference between the two circuit modules can be suppressed to a lesser extent, and miniaturization of the semiconductor device 30 can be achieved.

[0100] Next, a variation of the first embodiment will be described.

[0101] In the first embodiment, the impedance matching circuit between the input switch 43 and the second amplifier circuit 52 is not specifically described, but it is also possible to insert an impedance matching circuit between them. This impedance matching circuit can be formed in the first component 31 or the second component 32. The impedance matching circuit is typically composed of passive components such as capacitors and inductors, and does not contain active components such as transistors. Therefore, even when the input switch 43 and the second amplifier circuit 52 are connected via an impedance matching circuit, they can still be considered to be directly electrically connected.

[0102] Alternatively, there is a case where the impedance matching circuit inserted between the input switch 43 and the second amplifier circuit 52 is configured together with the second amplifier circuit 52 in a single circuit module. In this case, the circuit module constituting the impedance matching circuit and the second amplifier circuit 52 can be configured to overlap with the circuit module constituting the input switch 43 when viewed from above.

[0103] Next, refer to Figure 8 Other variations of the first embodiment will be described.

[0104] Figure 8 This is a cross-sectional view of the semiconductor module 20 in this modified example. In the first embodiment ( Figure 3 In this circuit, input switch 43 and second amplifier circuit 52 are directly electrically connected via wiring 61 within the redistribution layer. In contrast, in... Figure 8 In the variant shown, the input switch 43 and the second amplifier circuit 52 are directly electrically connected via wiring 26 within the module substrate 21.

[0105] Specifically, a first conductor protrusion 84 protrudes from the first surface 31A of the first component 31. A second conductor protrusion 85 protrudes from the second component 32 in the same direction as the first conductor protrusion 84. The semiconductor device 30 is mounted on the module substrate 21 in an orientation that aligns the first conductor protrusion 84 and the second conductor protrusion 85 with respect to the module substrate 21. The first conductor protrusion 84 is connected to the input switch 43, and the second conductor protrusion 85 is connected to the second amplifier circuit 52.

[0106] Furthermore, the first conductor protrusion 84 and the second conductor protrusion 85 are respectively fixed to the pads 24 and 25 disposed on the surface of the module substrate 21 by solder. The two pads 24 and 25 are interconnected via wiring 26 within the module substrate 21.

[0107] like Figure 8 As shown in the modified example, the circuit modules of the first component 31 and the second component 32, which overlap when viewed from above, can also be directly electrically connected via wiring 26 within the module substrate 21.

[0108] In the first embodiment, the semiconductor device 30 is mounted on a high-frequency module 20 in a frequency division duplex (FDD) configuration. Figure 1 However, it can also be used in high-frequency modules with time-division duplex (TDD) mode.

[0109] When the semiconductor device 30 is mounted in a TDD-type high-frequency module, the frequency band selection switch 41 is replaced. Figure 1 A transmit / receive switch is used. The transmit / receive switch has two contacts and one common terminal. One of the two contacts is connected via an output matching circuit 76. Figure 1 One contact is connected to the first amplifier circuit 51, and the other contact is connected to the low-noise amplifier 71 used to amplify the received signal. Figure 1 ), or via the receiving band selection switch 73 ( Figure 1 It is connected to the low-noise amplifier 71. The common terminal is connected to the antenna terminal via a filter.

[0110] [Second Embodiment]

[0111] Next, refer to Figure 9 The semiconductor device of the second embodiment will be described. Hereinafter, the semiconductor device will be described in relation to the referenced semiconductor device. Figures 1 to 7D The description of the common structure of the semiconductor device in the first embodiment of the accompanying drawings is omitted.

[0112] Figure 9 This refers to the first surface 31A of the semiconductor device 30 in the second embodiment, viewed from above. Figure 3 This is a schematic diagram showing the in-plane configuration of each circuit module. In the second embodiment, the first component 31 includes a fuse array 44, a fuse write / read circuit 45, and a component characteristic measurement circuit 46. Figure 9 In the image, the circuit module formed in the first component 31 is marked with a shading line that slopes downwards to the right.

[0113] The fuse array 44 is composed of multiple fuses. The fuse write-read circuit 45 performs writing (fuse disconnection) to each fuse in the fuse array 44 and reading the on / off state of the fuses. The on / off state of the fuse array 44 is set after the semiconductor process is completed, for example, to compensate for manufacturing deviations in the characteristics of the semiconductor device 30. The writing to the fuse array 44 is performed before the product is shipped. In addition, the reading of the on / off state of the fuse array 44 is performed after the power supply to the semiconductor device 30 is started, and the reading result is held by the lock-in circuit of each circuit using the reading result. Therefore, during the amplification operation of the first amplifier circuit 51 and the second amplifier circuit 52, the fuse array 44 and the fuse write-read circuit 45 do not operate.

[0114] The component characteristic measurement circuit 46 is configured to measure the characteristics of each component of the semiconductor device 30. The component characteristic measurement circuit 46 is used, for example, to evaluate the characteristics of each component constituting the semiconductor device 30 and to check for defects. Therefore, the component characteristic measurement circuit 46 does not operate during the amplification operation of the first amplifier circuit 51 and the second amplifier circuit 52.

[0115] In this second embodiment, when viewed from above, the circuit modules constituting the first amplifier circuit 51 overlap with the circuit modules of the plurality of circuit modules of the first component 31 that are not activated during the operation of the first amplifier circuit 51.

[0116] Next, the superior effects of the second embodiment will be explained.

[0117] The circuit module of the first component 31, which overlaps with the circuit module constituting the first amplifier circuit 51 when viewed from above, does not operate during the operation of the first amplifier circuit 51. Therefore, the circuit module of the first component 31, which overlaps with the first amplifier circuit 51 when viewed from above, does not affect the operation of the first amplifier circuit 51. Conversely, the first amplifier circuit 51 does not affect the operation of the circuit module of the first component 31, which overlaps with the circuit module constituting the first amplifier circuit 51 when viewed from above. Therefore, in the second embodiment, as in the first embodiment, the effects of electromagnetic interference between the circuit module of the first component 31 and the circuit module of the second component 32 can be suppressed to a lesser extent, and miniaturization of the semiconductor device 30 can be achieved.

[0118] [Third Embodiment]

[0119] Next, refer to Figure 10A as well as Figure 10B The semiconductor device of the third embodiment will be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figures 1 to 7D The description of the common structure of the semiconductor device in the first embodiment of the accompanying drawings is omitted.

[0120] Figure 10A This refers to the first surface 31A of the semiconductor device 30 in the third embodiment, viewed from above. Figure 3 This is a schematic diagram showing the in-plane arrangement of each circuit module. In the third embodiment, a digital circuit 47 is formed in the first component 31. Figure 10A In the diagram, the circuit modules formed in the first component 31 are marked with a slanted shaded line pointing downwards to the right. The digital circuit 47 decodes digital signals input from external circuits, such as command signals and data, converts them into analog signals, and assigns them to the first control circuit 42. Figure 1 The first control circuit 42 controls the bias circuit 53, the input switch 43, and the frequency band selection switch 41 based on the analog signal input from the digital circuit 47.

[0121] When viewed from above, the circuit modules constituting digital circuit 47 overlap with the circuit modules constituting first amplifier circuit 51.

[0122] Figure 10B This is a schematic cross-sectional view showing the semiconductor device 30 of the third embodiment. The digital circuit 47 is constructed from semiconductor elements formed on the surface layer of the substrate 311 of the first component 31 and multiple wirings within the multilayer wiring structure 312. In a top view, the first amplifier circuit 51 of the second component 32 overlaps with the digital circuit 47. A metal film 317 is disposed between the circuit modules constituting the first amplifier circuit 51 and the circuit modules constituting the digital circuit 47. The metal film 317 is, for example, disposed in any wiring layer within the multilayer wiring structure 312.

[0123] The metal film 317 is connected to the ground conductor of the second component 32 via wiring 318 within the multilayer wiring structure 312 and wiring 65 within the rewiring layer. Alternatively, the metal film 317 can be connected to the ground conductor of the second component 32 via wiring within the module substrate. The metal film 317 functions as an electromagnetic shielding conductor, providing electromagnetic shielding between the digital circuit 47 and the first amplifier circuit 51.

[0124] Next, the superior effects of the third embodiment will be explained.

[0125] In the third embodiment, the digital circuit 47 and the first amplifier circuit 51 are shielded from each other by a metal film 317. Therefore, even if the circuit modules constituting the digital circuit 47 and the circuit modules constituting the first amplifier circuit 51 are arranged to overlap when viewed from above, electromagnetic interference between them is unlikely to occur. Therefore, in the third embodiment, similar to the first embodiment, the effects of electromagnetic interference between the circuit modules of the first component 31 and the circuit modules of the second component 32 can be suppressed to a lesser extent, and miniaturization of the semiconductor device 30 can be achieved.

[0126] Furthermore, when the circuit modules constituting the analog circuit within the first component 31 and the circuit modules constituting the first amplifier circuit 51 are configured to overlap when viewed from above, the operating speed of the analog circuit is reduced due to the parasitic capacitance between the metal film 317, which is given a ground potential, and the analog circuit. In the third embodiment, since the circuit modules overlapping with the metal film 317 when viewed from above constitute the digital circuit 47, no reduction in the operating speed of the analog circuit occurs.

[0127] In order to avoid reducing the operating speed of the first amplifier circuit 51 of the second component 32, it is preferable to keep the metal film 317, which has dropped to ground potential, away from the second component 32. For example, it is preferable to make the spacing between the metal film 317 and the second component 32 in the thickness direction wider than the minimum spacing between the wiring in the multilayer wiring structure 312 constituting the digital circuit 47 and the metal film 317 in the thickness direction.

[0128] [Fourth Embodiment]

[0129] Next, refer to Figure 11 The semiconductor device of the fourth embodiment will be described. Hereinafter, the device will be described in relation to the referenced semiconductor device. Figures 1 to 7D The description of the common structure of the semiconductor device in the first embodiment of the accompanying drawings is omitted.

[0130] Figure 11 This refers to the first surface 31A of the semiconductor device 30 in the fourth embodiment, viewed from above. Figure 3 This is a schematic diagram showing the in-plane arrangement of each circuit module. In the fourth embodiment, a periodic signal operation circuit 48 is formed in the first component 31. Figure 11 In the diagram, the circuit modules formed in the first component 31 are marked with a shaded line sloping downwards to the right. When viewed from above, the circuit modules of the first amplifier circuit 51 constituting the second component 32 overlap with the circuit modules of the periodic signal operation circuit 48 constituting the first component 31. The periodic signal operation circuit 48 includes, for example, a digital circuit that operates according to a periodically changing clock signal, and a charge pump circuit that performs a boost operation by periodically switching on and off.

[0131] The circuit modules of the second amplifier circuit 52 constituting the second component 32 do not overlap with any circuit modules of the first component 31.

[0132] Next, the superior effects of the fourth embodiment will be explained.

[0133] The periodic signal operating circuit 48, which operates based on periodically changing signals, is prone to generating noise. The noise generated in the periodic signal operating circuit 48 can easily couple with the circuit module of the second component 32, which overlaps with the circuit module constituting the periodic signal operating circuit 48 when viewed from above. Generally, in a two-stage high-frequency amplifier circuit, the gain of the primary amplifier circuit is increased, while the gain is suppressed in the final amplifier stage to obtain a large output.

[0134] If clutter couples with the primary second amplifier circuit 52, the clutter is amplified in the high-gain second amplifier circuit 52, and further amplified in the first amplifier circuit 51. Therefore, the clutter component of the output signal of the first amplifier circuit 51 increases. In the fourth embodiment, since the circuit modules constituting the second amplifier circuit 52 and the circuit modules constituting the periodic signal operation circuit 48 do not overlap when viewed from above, clutter components are prevented from being amplified and output in both the primary second amplifier circuit 52 and the final first amplifier circuit 51.

[0135] Because the circuit modules constituting the periodic signal operation circuit 48 overlap with the circuit modules constituting the first amplifier circuit 51 when viewed from above, there is a possibility that clutter generated in the periodic signal operation circuit 48 may couple with the first amplifier circuit 51. The signal input to the first amplifier circuit 51 is amplified by the second amplifier circuit 52, thus increasing the signal level to a certain extent. Therefore, even if clutter couples to the first amplifier circuit 51, the clutter component has a relatively small impact on the high-frequency signal of the amplified object. Furthermore, the clutter component coupled to the first amplifier circuit 51 will not be amplified by the primary second amplifier circuit 52, which has a higher gain.

[0136] By overlapping the circuit modules constituting the first amplifier circuit 51 and the circuit modules constituting the periodic signal operation circuit 48 when viewed from above, the influence of noise can be reduced and the semiconductor device 30 can be miniaturized.

[0137] Next, a variation of the fourth embodiment will be described.

[0138] In the fourth embodiment, the circuit module of the periodic signal operation circuit 48 constituting the first component 31 overlaps with the circuit module constituting the first amplifier circuit 51 when viewed from above. However, other circuit modules of the first component 31 may also overlap with the circuit module constituting the first amplifier circuit 51. In this case, the circuit module constituting the second amplifier circuit 52 does not overlap with any circuit module constituting the first component 31. In this structure, even if noise generated in the circuit module of the first component 31 is coupled to the first amplifier circuit 51, the noise component has a smaller impact on the output signal. Therefore, similar to the fourth embodiment, the impact of noise can be reduced, and miniaturization of the semiconductor device 30 can be achieved.

[0139] [Fifth Embodiment]

[0140] Next, the semiconductor device of the fifth embodiment will be described. Hereinafter, the semiconductor device will be described in relation to the referenced... Figures 1 to 7D The description of the common structure of the semiconductor device in the first embodiment of the accompanying drawings is omitted.

[0141] In the first embodiment, the overlap of the circuit modules when viewed from top was described. The semiconductor device of the fifth embodiment is characterized not only by the circuit modules, but also by the overlap of the wiring connecting the different circuit modules when viewed from top.

[0142] A circuit module, including the circuit modules that constitute a certain circuit and the wiring within the same component that is directly connected to that circuit, is called an amplifier circuit module. In the fifth embodiment, when viewed from above, the amplifier circuit modules, which respectively include the circuits of the first component 31 and the circuits of the second component 32 that are directly connected to each other, overlap each other.

[0143] For example, in the first embodiment, when viewed from above, the circuit modules of each of the input switch 43 and the second amplifier circuit 52 that constitute a direct electrical connection overlap each other. In contrast, in the fifth embodiment, when viewed from above, at least one of the circuit module constituting the input switch 43 and the wiring within the first component 31 directly connected to the input switch 43 overlaps with at least one of the circuit module constituting the second amplifier circuit 52 and the wiring within the second component 32 directly connected to the second amplifier circuit 52.

[0144] Next, the superior effects of the fifth embodiment will be explained.

[0145] Similar to the first embodiment, the fifth embodiment can suppress the effects of electromagnetic interference between the two circuit modules to a lesser extent, and achieve miniaturization of the semiconductor device 30. Furthermore, it can increase the freedom of wiring configuration.

[0146] Next, a variation of the fifth embodiment will be described.

[0147] In the fifth embodiment, the amplifier circuit modules, each containing a circuit of the first component 31 and a circuit of the second component 32 that are directly connected to each other, overlap each other when viewed from above. Alternatively, as in the second embodiment, the amplifier circuit module containing the first amplifier circuit 51 may overlap with an amplifier circuit module containing a circuit that is not activated during the operation of the first amplifier circuit 51, one of the plurality of amplifier circuit modules of the first component 31, when viewed from above. As in the third embodiment, the amplifier circuit module containing the digital circuit 47 and the amplifier circuit module containing the first amplifier circuit 51 may be configured to overlap when viewed from above, with a metal film disposed between them. As in the fourth embodiment, the amplifier circuit module containing the first amplifier circuit 51 and the amplifier circuit module containing the periodic signal operation circuit 48 may overlap when viewed from above.

[0148] Next, other variations of the fifth embodiment will be described.

[0149] In the fifth embodiment and the above-described modifications, the amplifier circuit modules, including circuitry that minimizes the impact of electromagnetic interference on circuit operation, overlap each other when viewed from above. Alternatively, the circuit modules of the first component 31 and the wiring connected to any circuit module of the second component 32 may overlap when viewed from above. Conversely, the circuit modules of the second component 32 and the wiring connected to any circuit module of the first component 31 may overlap when viewed from above. In this case, excellent effects such as miniaturization of the semiconductor device and improved heat dissipation characteristics can be achieved. Furthermore, the freedom of wiring configuration can be increased.

[0150] The above embodiments are illustrative, and of course, partial substitutions or combinations of the structures shown in different embodiments are possible. The same effects achieved by the same structures in multiple embodiments are not mentioned sequentially in each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, those skilled in the art will certainly be able to make various changes, improvements, combinations, etc.

[0151] Explanation of reference numerals in the attached figures

[0152] 20…High-frequency module; 21…Module substrate; 24, 25…Pads; 26…Wiring; 30…Semiconductor device; 31…First component; 31A…First surface; 32…Second component; 41…Band selection switch; 42…First control circuit; 43…Input switch; 44…Fuse array; 45…Fuse write / read circuit; 46…Component characteristic measurement circuit; 47…Digital circuit; 48…Periodic signal operation circuit; 50…High-frequency amplifier circuit; 51…Final stage first amplifier circuit; 52…Primary stage second amplifier circuit; 61…Wiring; 62, 63…Pads; 64, 65…Wiring; 67…Interlayer insulating film; 68…Protective film; 70…Duplexer; 71…Low-noise amplifier; 72…Antenna switch; 73…Band selection switch for receiver; 74…Output terminal selection switch; 75… Second control circuit; 76… Output matching circuit; 82… Conductor protrusion; 82A… Cu pillar; 82B… Solder layer; 83… Conductor protrusion; 84… First conductor protrusion; 85… Second conductor protrusion; 101… Substrate semiconductor layer; 101A… Conductive region; 101B… Component separation region; 103B… Base layer; 103C… Collector layer; 103E… Emitter layer; 104B… Base electrode; 104BB… Base bias wiring; 104C… Collector electrode; 104E… Emitter electrode; 105E… Emitter wiring; 105RF… High-frequency signal input wiring; 311… Substrate; 312… Multilayer wiring structure; 313… First component protective film; 315, 316… Wiring within the multilayer wiring structure; 317… Metal film; 318… Wiring within the multilayer wiring structure.

Claims

1. A semiconductor device comprising: The first component has a first surface and includes a plurality of circuit modules disposed in the internal region of the first surface when viewed from above; The second component is in contact with the first surface of the first component and includes at least one circuit module; and The conductor protrusion extends from the second component to the side opposite to the first component. One of the circuit modules in the second component constitutes a first amplifier circuit, which includes a plurality of first transistors connected in parallel with each other. When viewed from above, at least one circuit module of the first component overlaps with at least one circuit module of the second component.

2. The semiconductor device according to claim 1, wherein, It also includes wiring that connects the circuit modules of the first component and the second component, which overlap when viewed from above.

3. The semiconductor device according to claim 1, wherein, The circuit module of the second component, which overlaps with the circuit module of the first component when viewed from above, constitutes the first amplifier circuit. When viewed from above, the circuit modules constituting the first amplifier circuit overlap with the circuit modules of the first component that are not activated during the operation of the first amplifier circuit.

4. The semiconductor device according to claim 1, wherein, The circuit module of the first component that overlaps with the circuit module of the second component when viewed from above is a digital circuit. Between the circuit modules of the first component and the second component, which overlap when viewed from above, the first component includes a metal film connected to ground.

5. The semiconductor device according to claim 1, wherein, The second component further includes a second amplifier circuit, which is connected to the front end of the first amplifier circuit. When viewed from above, the circuit module of the second component that overlaps with the circuit module of the first component constitutes the first amplifier circuit. When viewed from above, the circuit module that constitutes the second amplifier circuit does not overlap with any circuit module of the first component.

6. A semiconductor module, comprising: The first component has a first surface and includes a plurality of circuit modules disposed in the internal region of the first surface when viewed from above; The second component is in contact with the first surface of the first component and includes at least one circuit module. The first conductor protrusion protrudes from the first surface of the first component; The second conductor protrusion protrudes from the second component in the same direction as the first conductor protrusion. as well as The module substrate is equipped with the first component and the second component described above. One of the circuit modules in the second component constitutes a first amplifier circuit, which includes a plurality of first transistors connected in parallel with each other. When viewed from above, at least one circuit module of the first component overlaps with at least one circuit module of the second component. The circuit module of the above first component and the circuit module of the above second component, which overlap each other in plan view, are connected to each other via the above first conductor protrusion, the above second conductor protrusion, and a wiring provided on the above module substrate. The circuit module of the above first component and the circuit module of the above second component, which overlap each other in plan view, are connected to each other via the above first conductor protrusion, the above second conductor protrusion, and a wiring provided on the above module substrate.

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