Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, including a substrate and a plurality of fins protruding from the substrate; forming an interlayer dielectric layer on the substrate; forming a gate opening in the interlayer dielectric layer that spans the fins and exposes a portion of the top and sidewalls of the fins; forming source and drain doped regions within the fins on both sides of the gate opening; the substrate includes adjacent first and second regions for forming transistors, respectively; the gate opening located in either the first or second region extends into the other region and exposes the fins of the other region; the location of the exposed fins in the other region serves as an interconnect location; forming a conformally conformally gate dielectric layer covering the bottom and sidewalls of the gate opening and the fins within the gate opening; removing the gate dielectric layer from the surface of the fins at the interconnect location to expose the surface of the fins at the interconnect location; and forming a gate structure in the gate opening after exposing the surface of the fins at the interconnect location. This invention increases the process window for electrical connections.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid growth of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity. This also promotes the development of three-dimensional design, such as FinFET.

[0003] Whether it's a planar device or a three-dimensional device, current conduction is typically achieved through metal interconnect structures, thereby enabling the specific functions of the semiconductor device. Generally, different semiconductor devices are electrically connected through metal plugs, which can be connected to the gate structure or to the source / drain regions. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure that increases the process window for electrical connections.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, including a base and a plurality of fins protruding from the substrate, the substrate including adjacent first and second regions along the arrangement direction of the plurality of fins, the first and second regions being respectively used to form transistors; a gate structure, spanning the fins and covering a portion of the top and a portion of the sidewalls of the fins, wherein the gate structure located in either the first or second region extends to another region and covers the fins of the other region, and the location of the covered fins in the other region serves as an interconnect location, at which the gate structure and the fins are directly electrically connected; source and drain doped regions located within the fins on both sides of the gate structure; a gate dielectric layer located between the gate structure and the substrate, the gate dielectric layer being exposed on the surface of the fins at the interconnect location; and an interlayer dielectric layer located on the substrate on the side of the gate structure and covering the sidewalls of the gate structure.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of fins protruding from the substrate, an interlayer dielectric layer formed on the substrate, a gate opening formed in the interlayer dielectric layer, the gate opening spanning the fins and exposing a portion of the top and a portion of the sidewalls of the fins, and source / drain doped regions formed in the fins on both sides of the gate opening, wherein the substrate includes adjacent first and second regions along the arrangement direction of the plurality of fins, the first and second regions being respectively used to form transistors, wherein the gate opening located in either the first or second region extends to the other region and exposes the fins of the other region, and the location of the exposed fins of the other region is used as an interconnect location; forming a gate dielectric layer conformally covering the bottom and sidewalls of the gate opening and the fins in the gate opening; removing the gate dielectric layer from the surface of the fins at the interconnect location to expose the surface of the fins at the interconnect location; and after exposing the surface of the fins at the interconnect location, forming a gate structure in the gate opening.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] In the semiconductor structure provided by this invention, the fins on both sides of the gate structure have source / drain doped regions. The substrate includes adjacent first and second regions along the arrangement direction of the plurality of fins. The first and second regions are respectively used to form transistors. The gate structure located in either the first or second region extends to the other region and covers the fins of the other region. The location of the covered fins in the other region is used as an interconnect location. The gate dielectric layer exposes the surface of the fins at the interconnect location, so that the gate structure and the fins are directly electrically connected at the interconnect location. This achieves a direct electrical connection between the gate structure and the source / drain doped regions in the fins corresponding to the interconnect location, thus meeting actual wiring requirements. Compared with the scheme of using a plug to achieve the electrical connection between the gate structure and the source / drain doped regions in the fins corresponding to the interconnect location, this invention increases the process window for achieving the electrical connection between the gate structure and the source / drain doped regions in the fins corresponding to the interconnect location, and also helps to save photomasks.

[0009] In an optional embodiment, the semiconductor structure is an SRAM device, and the first region and the second region are used to form a first pull-up transistor and a second pull-up transistor, respectively. In this embodiment of the invention, it is not necessary to use a shared connector to achieve electrical connection between the gate structure and the source / drain doped regions in the fin corresponding to the interconnect location. By exposing the gate dielectric layer on the surface of the fin at the interconnect location, the fin at the interconnect location and the gate structure are directly electrically connected to achieve normal operation of the SRAM device. This correspondingly expands the process window for electrical connection and saves photomasks, thereby reducing process costs.

[0010] In the semiconductor structure formation method provided by this invention, active and drain doped regions are formed in the fins on both sides of the gate opening. The substrate includes adjacent first and second regions along the arrangement direction of the plurality of fins. The first and second regions are respectively used to form transistors. A gate opening located in either the first or second region extends into the other region, exposing the fins of that other region. The location of the exposed fins in the other region is used as an interconnect location. A conformally conformal gate dielectric layer is formed covering the bottom and sidewalls of the gate opening, as well as the fins in the gate opening. The gate dielectric layer on the surface of the fins at the interconnect location is removed, exposing the surface of the fins at the interconnect location. After the fin surface is exposed, a gate structure is formed in the gate opening. In this embodiment of the invention, after removing the gate dielectric layer on the surface of the fin at the interconnect position to expose the surface of the fin at the interconnect position, a gate structure is formed in the gate opening. Then, the fin at the interconnect position and the gate structure are directly electrically connected, thereby realizing the direct electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect position, so as to meet the actual wiring requirements. Compared with the scheme of using plugs to realize the electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect position, this embodiment of the invention increases the process window for realizing the electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect position, and is also beneficial to save photomasks.

[0011] In an optional embodiment, the semiconductor structure is an SRAM device, and the first region and the second region are used to form the first pull-up transistor and the second pull-up transistor, respectively. In this embodiment, it is not necessary to form a shared connector to achieve the electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect location. By removing the gate dielectric layer on the surface of the fin at the interconnect location, the surface of the fin at the interconnect location is exposed, and the fin at the interconnect location and the gate structure are directly electrically connected to achieve normal operation of the SRAM device. This correspondingly expands the process window of the electrical connection process and can save photomasks, thereby reducing the process cost. Attached Figure Description

[0012] Figure 1 This is a top view corresponding to a method for forming a semiconductor structure;

[0013] Figures 2 to 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figure 5 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention;

[0015] Figures 6 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0016] Figure 25 This is a schematic diagram of another embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0017] The process window for electrical connections in semiconductor structures still needs to be expanded. This paper analyzes the reasons why the process window for electrical connections still needs to be expanded, using a semiconductor structure formation method as an example.

[0018] refer to Figure 1 The diagram shows a top view corresponding to a method for forming a semiconductor structure.

[0019] refer to Figure 1 A substrate (not shown) is provided, including a substrate (not shown) and a plurality of fins 11 protruding from the substrate. An interlayer dielectric layer (not shown) is formed on the substrate, and a gate opening (not shown) is formed in the interlayer dielectric layer. The gate opening spans the fins 11 and exposes a portion of the top and a portion of the sidewalls of the fins 11. Source and drain doped regions (not shown) are formed within the fins 11 on both sides of the gate opening. The substrate is aligned with the arrangement direction of the plurality of fins 11 (e.g., ...). Figure 1 The image (shown in the X direction) includes an adjacent first region 10F and a second region 10S, which are used to form transistors. A gate opening located in either the first region 10F or the second region 10S extends into the other region and exposes a fin 11 of the other region. The location of the fin 11 exposed by the gate opening of the other region is used as an interconnect location (not shown). A gate structure 50 is formed in the gate opening. A shared plug 60 is formed on top of the gate structure 50 at the interconnect location. The shared plug 60 is also connected to the source / drain doped regions in the fin 11 at the interconnect location.

[0020] Specifically, taking the semiconductor structure as an SRAM device as an example, the SRAM device includes multiple SRAM cells (such as... Figure 1 (As shown in the dashed box in the middle), in the SRAM cell, the first region 10F is used to form a first pull-up transistor, and the second region 10S is used to form a second pull-up transistor.

[0021] Along the arrangement direction of the plurality of fins 11, the substrate further includes: a third region 10A located on the side of the first region 10F away from the second region 10S, the third region 10A being used to form a first pull-down transistor; and a fourth region 10B located on the side of the second region 10S away from the first region 10F, the fourth region 10B being used to form a second pull-down transistor.

[0022] In the SRAM cell, the first pull-up transistor and the first pull-down transistor constitute a first inverter, and the second pull-up transistor constitutes a second inverter. The input terminal of the first inverter and the output terminal of the second inverter are connected to form a latch, and the input terminal of the second inverter and the output terminal of the first inverter are connected to form a latch. That is, the gate structure 50 of the first pull-up transistor and the source / drain doped region of the second pull-up transistor are electrically connected through a shared plug 60.

[0023] As semiconductor structures continue to shrink, the gap between the first pull-up transistor and the second pull-up transistor becomes smaller and smaller, resulting in a smaller process window for forming the shared plug 60. At the same time, when the gap between two adjacent shared plugs 60 is small, the two adjacent shared plugs 60 need to be formed separately using different photomasks, which requires more photomasks to form the interconnect plugs 60, increasing the process cost.

[0024] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of fins protruding from the substrate, an interlayer dielectric layer formed on the substrate, a gate opening formed in the interlayer dielectric layer, the gate opening spanning the fins and exposing a portion of the top and sidewalls of the fins, and source / drain doped regions formed within the fins on both sides of the gate opening, wherein the substrate includes adjacent first and second regions along the arrangement direction of the plurality of fins, the first and second regions being respectively used to form transistors, wherein a gate opening located in either the first or second region extends into the other region and exposes the fins of the other region, and the location of the exposed fins of the other region is designated as an interconnect location; forming a conformally conformally covering the bottom and sidewalls of the gate opening and the fins in the gate opening; removing the gate dielectric layer from the surface of the fins at the interconnect location to expose the surface of the fins at the interconnect location; and after exposing the surface of the fins at the interconnect location, forming a gate structure in the gate opening.

[0025] In the formation method provided by this embodiment of the invention, active and drain doped regions are formed in the fins on both sides of the gate opening. The substrate includes adjacent first and second regions along the arrangement direction of the plurality of fins. The first and second regions are respectively used to form transistors. The gate opening located in either the first or second region extends into the other region and exposes the fins of the other region. The location of the exposed fins of the other region is used as an interconnect location. A conformal gate dielectric layer is formed to cover the bottom and sidewalls of the gate opening and the fins in the gate opening. The gate dielectric layer on the surface of the fins at the interconnect location is removed to expose the surface of the fins at the interconnect location. After surface treatment, a gate structure is formed in the gate opening. In this embodiment of the invention, after removing the gate dielectric layer on the surface of the fin at the interconnect position to expose the surface of the fin at the interconnect position, a gate structure is formed in the gate opening. Then, the fin at the interconnect position and the gate structure are directly electrically connected, thereby realizing the direct electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect position, so as to meet the actual wiring requirements. Compared with the scheme of using plugs to realize the electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect position, this embodiment of the invention increases the process window for realizing the electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect position, and also helps to save photomasks.

[0026] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] refer to Figures 2 to 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. Figure 2 This is a top view of the fin and gate structure. Figure 3 Based on Figure 2 Sectional view along the AA direction. Figure 4 Based on Figure 2 A sectional view along the BB direction. For ease of illustration, ... Figure 2 Only the fins and gate structure are shown in the diagram.

[0028] The semiconductor structure includes: a substrate (not shown), comprising a substrate 101 and a plurality of fins 111 protruding from the substrate 101, wherein the substrate 101 is arranged along the direction of the plurality of fins 111 (e.g., Figure 2 The structure (shown in the X direction) includes an adjacent first region 101F and a second region 101S, which are respectively used to form transistors; a gate structure 501 extends across the fin 111 and covers part of the top and part of the sidewalls of the fin 111, wherein the gate structure 501 located in either the first region 101F or the second region 101S extends into the other region and covers the fin 111 of the other region, and the fin 111 of the covered other region is located in... The location is designated as interconnect location 161, at which the gate structure 501 and the fin 111 are directly electrically connected; source / drain doped regions 151 are located within the fins 111 on both sides of the gate structure 501; a gate dielectric layer 301 is located between the gate structure 501 and the substrate, and the gate dielectric layer 301 is exposed on the surface of the fins 111 at the interconnect location 161; an interlayer dielectric layer 211 is located on the substrate 101 on the side of the gate structure 501 and covers the sidewall of the gate structure 501.

[0029] In the semiconductor structure provided in this embodiment of the invention, the fins 111 on both sides of the gate structure 501 have source / drain doped regions 151. The substrate 101 includes adjacent first regions 101F and second regions 101S along the arrangement direction of the plurality of fins 111. The first regions 101F and second regions 101S are respectively used to form transistors. The gate structure 501 located in either the first region 101F or the second region 101S extends to the other region and covers the fins 111 of the other region. The location of the covered fins 111 of the other region serves as an interconnect location 161. The gate dielectric layer 301 is exposed. The surface of the fin 111 at the interconnect location 161 is configured such that the gate structure 501 and the fin 111 are directly electrically connected at the interconnect location 161. This achieves a direct electrical connection between the gate structure 501 and the source / drain doped region 151 in the fin 111 corresponding to the interconnect location 161, thus meeting actual wiring requirements. Compared with the scheme of using plugs to achieve electrical connection between the gate structure and the source / drain doped region in the fin corresponding to the interconnect location, this embodiment increases the process window for achieving electrical connection between the gate structure 501 and the source / drain doped region 151 in the fin 111 corresponding to the interconnect location 161, and also helps to save on photomasks.

[0030] The substrate provides the basis for the process operation of forming the semiconductor structure.

[0031] In this embodiment, the substrate includes a substrate 101, which is made of silicon. In other embodiments, the substrate may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0032] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the fin 111 is used to provide the channel of the fin field-effect transistor.

[0033] In this embodiment, the fin 111 and the substrate 101 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0034] In this embodiment, the material of the fin 111 is the same as the material of the substrate 101, and the material of the fin 111 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0035] In this embodiment, the substrate 101 includes an adjacent first region 101F and a second region 101S along the arrangement direction of the plurality of fins 111, and the first region 101F and the second region 101S are respectively used to form transistors.

[0036] In this embodiment, the semiconductor structure includes an SRAM device, and the SRAM device includes multiple SRAM cells (such as...). Figure 2 (As shown in the dashed box). As an example, Figure 2 Two SRAM cells are shown, but an SRAM device may contain more than two SRAM cells.

[0037] Accordingly, both the first region 101F and the second region 101S are PMOS regions used to form P-type transistors. Specifically, the first region 101F and the second region 101S are used to form the first pull-up transistor and the second pull-up transistor, respectively.

[0038] The interlayer dielectric layer 211 serves to isolate adjacent devices.

[0039] The material of the interlayer dielectric layer 211 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0040] As an example, a gate opening (not shown) is formed in the interlayer dielectric layer 211, and the gate structure 501 is located in the gate opening.

[0041] The gate opening is used to provide space for the gate structure 501. During the formation of the semiconductor structure, a dummy gate structure is first used to occupy the position of the gate structure 501. Therefore, the gate opening is formed in the interlayer dielectric layer 211, that is, the gate opening is formed by removing the dummy gate structure. The position of the gate opening corresponds to the position of the gate structure 501.

[0042] In this embodiment, the gate structure 501 located in either the first region 101F or the second region 101S extends to the other region and exposes the fin 111 of the other region, and the location of the fin 111 of the other region that is covered is used as the interconnect location 161.

[0043] The fin 111 of the interconnection position 161 in either the first region 101F or the second region 101S is used for direct electrical connection with the gate structure 501 in the other region.

[0044] Specifically, active drain doped regions 151 are formed in the fins 111 on both sides of the gate structure 501, that is, active drain doped regions 151 are formed in the fins 111 corresponding to the interconnect position 161. Therefore, by directly electrically connecting the gate structure 501 in any region of the first region 101F and the second region 101S with the fins 111 of the interconnect position 161 in the other region, the gate structure 501 in any region is electrically connected with the source drain doped regions 151 in the fins 111 corresponding to the interconnect position 161 in the other region.

[0045] In this embodiment, the semiconductor structure includes an SRAM device. The first region 101F and the second region 101S are used to form a first pull-up transistor and a second pull-up transistor, respectively. Therefore, the gate structure 501 in the first region 101F extends into the second region 101S and covers the fin 111 of the second region 101S. In the second region 101S, the location of the fin 111 covered by the gate structure 501 of the first region 101F is used as the interconnect location 161. Similarly, the gate structure 501 in the second region 101S extends into the first region 101F and covers the fin 111 of the first region 101F. In the first region 101F, the location of the fin 111 covered by the gate structure 501 of the second region 101S is used as the interconnect location 161.

[0046] The source / drain doped regions 151 are located in the fins 111 on both sides of the gate structure 501, and the source / drain doped regions 151 are used as the source or drain regions of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped regions 151 is the same as the channel conductivity type of the corresponding transistor.

[0047] The gate dielectric layer 301 is used to achieve electrical isolation between the fin 111 and the gate structure 501.

[0048] In this embodiment, the gate dielectric layer 301 is made of a high-k dielectric material, where a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the gate dielectric layer 301 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the gate dielectric layer 301 is HfO2.

[0049] In this embodiment, the gate dielectric layer 301 exposes the surface of the fin 111 at the interconnect location 161.

[0050] The gate structure 501 located in either the first region 101F or the second region 101S extends into the other region and covers the fin 111 of the other region. The location of the fin 111 in the covered other region serves as an interconnect location 161. Therefore, by exposing the surface of the fin 111 at the interconnect location 161, the gate structure 501 is directly electrically connected to the fin 111 at the interconnect location 161.

[0051] In this embodiment, the semiconductor structure includes an SRAM device. The first region 101F and the second region 101S are used to form the first pull-up transistor and the second pull-up transistor, respectively. Therefore, it is not necessary to use a shared plug to achieve the electrical connection between the gate structure 501 of either region 101F or the second region 101S and the source / drain doped region 151 in the fin 111 corresponding to the interconnect position 161 in the other region. By exposing the gate dielectric layer 301 to the surface of the fin 111 of the interconnect position 161, the fin 111 of the interconnect position and the gate structure 501 are directly electrically connected. This allows the source / drain doped region 151 of the first pull-up transistor and the gate structure 501 of the second pull-up transistor to be directly electrically connected, and the source / drain doped region 151 of the second pull-up transistor and the gate structure 501 of the first pull-up transistor to be directly electrically connected, so as to achieve normal operation of the SRAM device without the need to form a shared plug. This expands the process window of the electrical connection process and saves photomasks, thereby reducing the process cost.

[0052] In this embodiment, the semiconductor structure further includes a capping layer 311, which is located between the gate structure 501 and the gate dielectric layer 301 and exposes the surface of the fin 111 at the interconnect location.

[0053] The capping layer 311 is used to protect the gate dielectric layer 301, reduce damage to the gate dielectric layer 301 during the process, and also helps to reduce the diffusion of easily diffusing ions in the gate structure 501 into the gate dielectric layer 301.

[0054] The capping layer 311 exposes the surface of the fin 111 at the interconnect location 161. This means that during the formation of the semiconductor structure, after the capping layer 311 covering the gate dielectric layer 301 is formed, the capping layer 311 and the gate dielectric layer 301 at the interconnect location 161 are etched again in sequence to expose the fin 111 at the interconnect location 161. Thus, during the etching of the gate dielectric layer 301, the capping layer 311 protects the gate dielectric layer 301.

[0055] Furthermore, by exposing the surface of the fin 111 of the interconnect location 161 to the capping layer 311, the effect of direct electrical connection between the gate structure 501 and the fin 111 of the interconnect location 161 is improved.

[0056] In this embodiment, the capping layer 311 is a single-layer structure or a multi-layer structure. The material of the capping layer 311 includes one or both of TaN and TiN.

[0057] It should be noted that in other embodiments, the capping layer may also cover the fins at the interconnect locations. Since the capping layer is a conductive material, even if the capping layer covers the fins at the interconnect locations, direct electrical connection between the gate structure in one region and the fins at the interconnect locations in another region can still be achieved.

[0058] In this embodiment, the semiconductor structure further includes: a metal silicide layer 141, the metal silicide layer 141 covering the surface of the fin 111 at the interconnect location; or, the material of the fin 111 at the interconnect location 161 is a metal silicide material.

[0059] The metal silicide layer 141 has a low resistivity and is in direct contact with the gate structure 501, thereby reducing the contact resistance of the interconnect location 161.

[0060] Since the metal silicide layer 141 is formed by consuming the material of the fins 111, depending on different process requirements (e.g., the thickness requirement of the metal silicide layer 141) and the width of the fins 111, if a portion of the width of the fins 111 at the interconnect location 161 is consumed, then the metal silicide layer 141 covers the surface of the fins 111 at the interconnect location; if all the fins 111 at the interconnect location 161 are consumed, then the material of the fins 111 at the interconnect location is a metal silicide material.

[0061] In this embodiment, the metal silicide layer 141 is shown to cover the surface of the fin 111 of the interconnect location 161.

[0062] In this embodiment, the metal silicide layer 141 is in contact with the adjacent source / drain doped region 151 in the fin 111 corresponding to the interconnect location 161.

[0063] In the semiconductor structure, a source / drain plug is typically included, located on top of and electrically connected to the source / drain doped region 151. Since the gate structure 501 and the fin 111 are directly electrically connected at the interconnect location 161, a direct electrical connection is achieved between the gate structure 501 and the source / drain doped region 151 in the fin 111 corresponding to the interconnect location 161. Correspondingly, the gate structure 501 at the interconnect location 161 is electrically connected to the source / drain plug through the source / drain doped region 151 and the metal silicide layer 141. Therefore, by making the metal silicide layer 141 at the interconnect location 161 contact the adjacent source / drain doped region 151 in the fin 111 corresponding to the interconnect location 161, the resistance between the gate structure 501 and the source / drain plug at the interconnect location 161 is reduced, thereby further improving the performance of the semiconductor structure.

[0064] The material of the metal silicide layer 141 includes titanium silicon compound, cobalt silicon compound, or nickel silicon compound.

[0065] In this embodiment, the gate structure 501 includes a metal gate structure for controlling the opening or closing of the channel of the fin field-effect transistor.

[0066] In this embodiment, the metal gate structure includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0067] The work function layer is used to adjust the threshold voltage of the fin field-effect transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0068] The gate electrode layer is used to bring out the electrical properties of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0069] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0070] In this embodiment, the semiconductor structure further includes a sidewall 221 located on the sidewall of the gate structure 501.

[0071] The sidewall 221 is used to protect the sidewalls of the gate structure 501. The sidewall 221 can be a single-layer structure or a multilayer structure, and the material of the sidewall 221 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 221 is a single-layer structure, and the material of the sidewall 221 is silicon nitride.

[0072] In this embodiment, the semiconductor structure further includes an isolation layer 121, which is located on the substrate 101 exposed by the fin 111 and covers part of the sidewall of the fin 111.

[0073] The isolation layer 121 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 121 is usually formed between NMOS transistors and PMOS transistors.

[0074] The insulating layer 121 is made of an insulating material. As an example, the insulating layer 121 is made of silicon oxide.

[0075] Figure 5 This is a schematic diagram of another embodiment of the semiconductor structure of the present invention. For ease of illustration, only a top view of the fins and gate structure is shown.

[0076] The similarities between the embodiments of the present invention and the foregoing embodiments will not be repeated here. The difference between the embodiments of the present invention and the foregoing embodiments is that: the substrate (not shown in the figure) is arranged along the direction of the plurality of fins 112 (e.g., Figure 5 The region (shown in the X direction) includes an adjacent first region 102F and a second region 102S. A gate opening (not shown) located in either the first region 102F or the second region 102S extends into the other region and exposes the fin 112 of the other region. The location of the exposed fin 112 of the other region is used as an interconnect location 162. The transistor in the region where the fin 112 of the interconnect location 162 is located is disabled, and the fin of the other region is used to form a transistor.

[0077] In this embodiment, the gate opening of the first region 102F extends into the second region 102S and exposes the fin 112 of the second region 102S. The location of the fin 112 exposed by the gate opening of the first region 102F in the second region 102S is used as the interconnect location 162.

[0078] If the gate structure 502 of the first region 102F extends to the second region 102S and is directly electrically connected to the fin 112 at the interconnect location 162, then the first region 102F is used to form a transistor, and the transistor in the second region 102S is disabled.

[0079] Specifically, the transistor in the second region 102S fails, and the fins 112 on both sides of the gate structure 502 in the second region 102S also have source / drain doped regions. Therefore, the gate structure 502 of the first region 102F is electrically connected to the source / drain doped regions (not shown) in the fins 112 corresponding to the interconnection position 162 in the second region 102S. Accordingly, the gate structure 502 of the first region 102F can be electrically connected to the external circuit through the source / drain doped regions of the second region 102S to meet the actual wiring requirements. In other words, for the transistor in the first region 102F, the plug for electrical connection with the gate structure 502 can be set at the location of the source / drain doped regions of the second region 102S, thereby increasing the process window for electrical connection.

[0080] For a detailed description of the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0081] Figures 6 to 24 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0082] Reference Figures 6 to 8 ,in, Figure 6 This is a top view of the fins and gate openings. Figure 7 Based on Figure 6 Sectional view along the AA direction. Figure 8 Based on Figure 6 A cross-sectional view along the BB direction shows a substrate (not shown), including a substrate 100 and a plurality of fins 110 protruding from the substrate 100. An interlayer dielectric layer 210 is formed on the substrate 100, and a gate opening 210 is formed in the interlayer dielectric layer 210. The gate opening 210 spans the fins 110 and exposes a portion of the top and sidewalls of the fins 110. Active and drain doped regions 150 are formed within the fins 110 on both sides of the gate opening 210. The substrate 100 is aligned with the arrangement direction of the plurality of fins 110 (e.g., ...). Figure 6 The image (shown in the X direction) includes an adjacent first region 100F and a second region 100S, which are used to form transistors. A gate opening 200 located in either the first region 100F or the second region 100S extends into the other region and exposes the fin 110 of the other region. The location of the exposed fin 110 of the other region is used as an interconnect location 160.

[0083] The substrate provides the basis for the process operation of forming the semiconductor structure.

[0084] In this embodiment, the substrate includes a substrate 100, the material of which is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium bismuth. The substrate may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0085] In this embodiment, the semiconductor structure is a fin field-effect transistor, and the fin portion 110 is used to provide the channel of the fin field-effect transistor.

[0086] In this embodiment, the fin 110 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, thereby achieving precise control over the height of the fin.

[0087] In this embodiment, the material of the fin 110 is the same as the material of the substrate 100, and the material of the fin 110 is silicon. In other embodiments, the material of the fin may also be one or more of germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ide, and the material of the fin may also be different from the material of the substrate.

[0088] In this embodiment, the substrate 100 includes an adjacent first region 100F and a second region 100S along the arrangement direction of the plurality of fins 110, and the first region 100F and the second region 100S are respectively used to form transistors.

[0089] In this embodiment, the forming method is used to form an SRAM device, the SRAM device including multiple SRAM cells (such as...). Figure 6 (As shown in the dashed box). As an example, Figure 6 Two SRAM cells are shown, but an SRAM device may contain more than two SRAM cells.

[0090] Accordingly, both the first region 100F and the second region 100S are PMOS regions used to form P-type transistors. Specifically, the first region 100F and the second region 100S are used to form the first pull-up transistor and the second pull-up transistor, respectively.

[0091] The interlayer dielectric layer 210 serves to isolate adjacent devices.

[0092] The material of the interlayer dielectric layer 210 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbon oxynitride.

[0093] The gate opening 200 is used to provide space for the subsequent formation of the gate structure.

[0094] During the formation of the semiconductor structure, a dummy gate structure is first used to occupy the position of the gate structure. Therefore, the gate opening 200 is formed in the interlayer dielectric layer 210, that is, the gate opening 200 is formed by removing the dummy gate structure.

[0095] Therefore, in this embodiment, before forming the interlayer dielectric layer 210, the method further includes: forming a pseudo-gate structure (not shown) on the substrate, the pseudo-gate structure spanning the fin 110 and covering part of the top and part of the sidewalls of the fin 110.

[0096] The pseudo-gate structure occupies space for the subsequent formation of the gate structure.

[0097] The pseudo-gate structure can be a single-layer structure or a multilayer structure, and the material of the pseudo-gate structure includes one or both of amorphous silicon and polycrystalline silicon. In other embodiments, the material of the pseudo-gate structure can also be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon nitride, silicon carbonitride, or amorphous carbon.

[0098] In this embodiment, the interlayer dielectric layer 210 is formed on the substrate on the side of the pseudo-gate structure, and the interlayer dielectric layer 210 is exposed above the top of the pseudo-gate layer.

[0099] The interlayer dielectric layer 210 also serves as a platform base for forming the gate opening 200.

[0100] In this embodiment, the step of forming the gate opening 200 includes: removing the dummy gate layer.

[0101] The pseudo-gate structure is removed to form the gate opening 200, which prepares for the subsequent formation of the gate structure.

[0102] In this embodiment, the gate opening 200 located in either the first region 100F or the second region 100S extends to the other region and exposes the fin 110 of the other region, and the location of the exposed fin 110 of the other region is used as the interconnect location 160.

[0103] The fin 110 of the interconnection position 160 in either the first region 100F or the second region 100S is used for direct electrical connection with the gate structure in the other region.

[0104] Specifically, active drain doped regions 150 are formed in the fins 110 on both sides of the gate opening 200, that is, active drain doped regions 150 are formed in the fins 110 corresponding to the interconnect positions 160. Therefore, by directly electrically connecting the gate structure of any region in the first region 100F and the second region 100S with the fins 110 of the interconnect positions 160 in the other region, the gate structure in any region is electrically connected to the source drain doped regions 150 in the fins 110 corresponding to the interconnect positions in the other region.

[0105] In this embodiment, the formation method is used to form an SRAM device. The first region 100F and the second region 100S are used to form a first pull-up transistor and a second pull-up transistor, respectively. Therefore, the gate opening 200 in the first region 100F extends into the second region 100S and exposes the fin 110 of the second region 100S. In the second region 100S, the location of the fin 110 exposed by the gate opening 200 of the first region 100F is used as the interconnect location 160. Similarly, the gate opening 200 in the second region 100S extends into the first region 100F and exposes the fin 110 of the first region 100F. In the first region 100F, the location of the fin 110 exposed by the gate opening 200 of the second region 100S is used as the interconnect location 160.

[0106] The source / drain doped regions 150 are located on both sides of the fins 110 of the gate opening 200, and the source / drain doped regions 150 are used as the source or drain regions of the formed fin field-effect transistor. Specifically, the doping type of the source / drain doped regions 150 is the same as the channel conductivity type of the corresponding transistor.

[0107] In this embodiment, after forming the pseudo-gate structure and before forming the interlayer dielectric layer 210, the method further includes: forming a sidewall 220 on the sidewall of the pseudo-gate structure.

[0108] The sidewall 220 is used to protect the sidewalls of the gate structure. The sidewall 220 can be a single-layer structure or a multilayer structure, and the material of the sidewall 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 220 is a single-layer structure, and the material of the sidewall 220 is silicon nitride.

[0109] In this embodiment, the substrate further includes an isolation layer 120.

[0110] The isolation layer 120 is used to achieve insulation between different devices. For example, in CMOS manufacturing processes, an isolation layer 120 is usually formed between NMOS transistors and PMOS transistors.

[0111] The insulating layer 120 is made of an insulating material. As an example, the insulating layer 120 is made of silicon oxide.

[0112] Reference Figures 9 to 11 ,in, Figure 9 Based on Figure 6 Top view, Figure 10 Based on Figure 9 Sectional view along the AA direction. Figure 11 Based on Figure 9 A BB-direction cross-sectional view shows a conformally formed gate dielectric layer 300 covering the bottom and sidewalls of the gate opening 200, as well as the fins 110 in the gate opening 200.

[0113] The gate dielectric layer 300 is used to achieve electrical isolation between the fin 110 and the subsequently formed gate structure.

[0114] In this embodiment, the gate dielectric layer 300 is formed using atomic layer deposition (ALD). The gate dielectric layer 300 formed by ALD has good thickness uniformity and excellent step coverage, enabling it to conformally cover the bottom and sidewalls of the gate opening 200, as well as the fins 110 within the gate opening 200.

[0115] In other embodiments, the gate dielectric layer may also be formed using a chemical vapor deposition process.

[0116] In this embodiment, the gate dielectric layer 300 is made of a high-k dielectric material, where a high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the gate dielectric layer 300 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the gate dielectric layer 300 is HfO2.

[0117] It should be noted that the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160 needs to be removed subsequently.

[0118] In this embodiment, after the gate dielectric layer 300 is formed at the bottom and sidewall of the gate opening 200, and before the gate dielectric layer 300 on the surface of the fin 110 of the interconnect location 160 is removed, the embodiment further includes: forming a capping layer 310, which conformally covers the gate dielectric layer 300.

[0119] The capping layer 310 is used to protect the gate dielectric layer 300, reduce damage to the gate dielectric layer 300 during the process, and after the gate structure is formed, it also helps to reduce the diffusion of easily diffusing ions in the gate structure into the gate dielectric layer 300.

[0120] In this embodiment, the capping layer 310 is formed using atomic layer deposition (ALD).

[0121] The capping layer 310 formed by atomic layer deposition has good thickness uniformity and good step coverage ability, which enables the capping layer 310 to cover the gate dielectric layer 300 in good conformal manner.

[0122] In this embodiment, the capping layer 310 is a single-layer structure or a multi-layer structure. The material of the capping layer 310 includes one or both of TaN and TiN.

[0123] Reference Figures 12 to 18 Remove the gate dielectric layer 300 from the surface of the fin 110 at the interconnect location 160 to expose the surface of the fin 110 at the interconnect location 160.

[0124] In this embodiment, after removing the gate dielectric layer 300 from the surface of the fin 110 at interconnect location 160 to expose the surface of the fin 110 at interconnect location 160, a gate structure is subsequently formed in the gate opening 200. This allows the fin 110 at interconnect location 160 and the gate structure to be directly electrically connected, thereby achieving a direct electrical connection between the gate structure and the source / drain doped regions 150 in the fin 110 corresponding to interconnect location 160, thus meeting actual wiring requirements. Furthermore, compared to the scheme of using plugs to achieve electrical connection between the gate structure and the source / drain doped regions in the fin corresponding to interconnect location 160, this embodiment of the invention increases the process window for achieving electrical connection between the gate structure and the source / drain doped regions 150 in the fin 110 corresponding to interconnect location 160.

[0125] In this embodiment, a dry etching process is used to remove the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160, exposing the surface of the fin 110 at the interconnect location.

[0126] The dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate. Therefore, by selecting the dry etching process, it is beneficial to improve the accuracy of pattern conversion and reduce the damage to the gate dielectric layer 300 on the surface of the fin 110 at other locations when removing the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160.

[0127] Reference Figure 12 and Figure 13 ,in, Figure 12 Based on Figure 10 sectional view, Figure 13 Based on Figure 11 The cross-sectional view, after the gate dielectric layer 300 is formed at the bottom and sidewalls of the gate opening 200 and before the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160 is removed, further includes: forming a planarization layer 400 within the gate opening 200.

[0128] The planarization layer 400 is formed to transfer patterns and to serve as an etching mask when etching the gate dielectric layer 300.

[0129] In this embodiment, the planarization layer 400 is made of spin-on carbon (SOC). Spin-on carbon is formed by a spin coating process, which has a low processing cost. Moreover, by using spin-on carbon, the flatness of the top surface of the planarization layer 400 is improved, thereby providing a good interface for the formation of mask openings.

[0130] In this embodiment, the forming method further includes forming a patterned photoresist layer 410 on the planarization layer 400.

[0131] The patterned photoresist layer 410 is used to transfer patterns into the planarization layer 400.

[0132] Reference Figure 14 and Figure 15 ,in, Figure 14 Based on Figure 12 sectional view, Figure 15 Based on Figure 13 A cross-sectional view of the planarization layer 400 is shown, in which an opening 420 is formed in the planarization layer 400 at the interconnection location 160.

[0133] An opening 420 is formed in the planarization layer 400 of the interconnect location 160 to expose the gate dielectric layer 300 of the interconnect location 160, in preparation for removing the gate dielectric layer 300 from the surface of the fin 110 of the interconnect location 160.

[0134] It should be noted that, in order to facilitate the removal of the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160 and to enlarge the process window, the opening 420 also exposes the gate dielectric layer 300 on the top of the isolation layer 120 on both sides of the fin 110 at the interconnect location 160.

[0135] Reference Figures 16 to 18 ,in, Figure 16 This is a top view. Figure 17 Based on Figure 16 Sectional view along the AA direction. Figure 18 Based on Figure 16 A sectional view along the BB direction, along the opening 420 (e.g. Figure 15 As shown), the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160 is removed.

[0136] The gate opening 200 located in either the first region 100F or the second region 100S extends into the other region and exposes the fin 110 of the other region. The location of the exposed fin 110 of the other region is used as the interconnect location 160. Therefore, by removing the gate dielectric layer 300 from the surface of the fin 110 of the interconnect location 160, the surface of the fin 110 of the interconnect location 160 is exposed, thereby enabling the subsequent gate structure to be directly electrically connected to the fin 110 of the interconnect location 160.

[0137] In this embodiment, the formation method is used to form an SRAM device. The first region 100F and the second region 100S are used to form the first pull-up transistor and the second pull-up transistor, respectively. Therefore, it is not necessary to use a shared plug to achieve the electrical connection between the gate structure of either region 100F or the second region 100S and the source / drain doped region 150 in the fin 110 corresponding to the interconnect position 160 in the other region. By removing the gate dielectric layer 300 on the surface of the fin 110 of the interconnect position 160, the surface of the fin 110 of the interconnect position 160 is exposed, so that the fin 110 of the subsequent interconnect position and the gate structure are directly electrically connected. This allows the source / drain doped region 150 of the first pull-up transistor and the gate structure of the second pull-up transistor to be directly electrically connected, and the source / drain doped region 150 of the second pull-up transistor and the gate structure of the first pull-up transistor to be directly electrically connected, so as to achieve normal operation of the SRAM device. Moreover, it is not necessary to form a shared plug, which expands the process window of the electrical connection process and can save photomasks, thereby reducing the process cost.

[0138] It should be noted that during the process of removing the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160, the gate dielectric layer 300 exposed at the top of the isolation layer 120 and the sidewall of the interlayer dielectric layer 300 at the opening 420 is also removed.

[0139] In this embodiment, before removing the gate dielectric layer 300 on the surface of the fin 110 at the interconnect location 160, the method further includes removing the capping layer 310 on the surface of the fin 110 at the interconnect location 160.

[0140] Remove the capping layer 310 on the surface of the fin 110 at interconnect location 160 to prepare for removing the gate dielectric layer 300 on the surface of the fin 110 at interconnect location 160.

[0141] During the etching of the gate dielectric layer 300 at the interconnect location 160, the capping layer 310 protects the gate dielectric layer 300.

[0142] Furthermore, by exposing the surface of the fin 110 at the interconnect location 160 with the capping layer 310, the effect of direct electrical connection between the subsequently formed gate structure and the fin 110 at the interconnect location is improved.

[0143] It should be noted that, in other embodiments, a capping layer may be formed after etching away the gate dielectric layer at the interconnect location. Accordingly, the capping layer may also cover the fins at the interconnect location. Since the capping layer is a conductive material, even if the capping layer covers the fins at the interconnect location, direct electrical connection between the gate structure in any region and the fins at the interconnect location in an adjacent region can still be achieved.

[0144] In this embodiment, a dry etching process is used to remove the capping layer 310 on the surface of the fin 110 at the interconnect location 160.

[0145] The dry etching process has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate. Therefore, by selecting the dry etching process, it is beneficial to improve the accuracy of pattern conversion. When removing the capping layer 310 on the surface of the fin 110 at interconnect position 160, the damage to the capping layer 310 on the surface of the fin 110 at other positions is reduced. At the same time, the gate dielectric layer 300 on the surface of the fin 110 at interconnect position 160 is also removed by dry etching. Therefore, the capping layer 310 and the gate dielectric layer 300 can be etched sequentially by dry etching.

[0146] In this embodiment, after removing the gate dielectric layer 300 from the surface of the fin 110 at the interconnect location 160, the method further includes: removing the planarization layer 400 (e.g., Figure 15 (As shown).

[0147] The planarization layer 400 is removed to provide a process basis for subsequent process steps.

[0148] Reference Figures 19 to 21 ,in, Figure 19 This is a top view. Figure 20 Based on Figure 19 Sectional view along the AA direction. Figure 21 Based on Figure 19 A cross-sectional view along the BB direction, with the gate dielectric layer 300 removed from the surface of the fin 110 at interconnect location 160, exposing the surface of the fin 110 at interconnect location 160 (e.g., Figure 18(As shown) After that, before the gate structure is formed in the gate opening 200, the method further includes: performing a metal silicide treatment on the surface of the fin 110 exposed at the interconnect location 160 to form a metal silicide layer 140.

[0149] The metal silicide layer 140 has a low resistivity and is in direct contact with the gate structure, thereby reducing the contact resistance of the interconnect site 160.

[0150] In this embodiment, the metal silicide layer 140 is formed using a self-aligned metal silicide process.

[0151] It should be noted that, since the self-aligned metal silicide process forms the metal silicide layer 140 by consuming the material of the fins 110, depending on different process requirements (e.g., the thickness requirement of the metal silicide layer 140) and the width of the fins 110, if a portion of the width of the fins 110 at the interconnect location 160 is consumed, the metal silicide layer 140 covers the surface of the fins 110 at the interconnect location 160; if all the fins 110 at the interconnect location 160 are consumed, the material of the fins 110 at the interconnect location 160 is a metal silicide material. Therefore, in this embodiment, the metal silicide layer 140 covers the surface of the fins 110 at the interconnect location 160; or, the material of the fins 110 at the interconnect location 160 is a metal silicide material.

[0152] In this embodiment, the metal silicide layer 140 is shown to cover the surface of the fin 110 at the interconnect location 160.

[0153] In this embodiment, the metal silicide layer 140 is in contact with the adjacent source / drain doped region 150 in the fin 110 corresponding to the interconnect location 160.

[0154] Subsequently, a source / drain plug is typically formed on top of and electrically connected to the source / drain doped region 150. Since the gate structure is formed subsequently, the gate structure and the fin 110 are directly electrically connected at the interconnect location 160, thereby achieving a direct electrical connection between the gate structure and the source / drain doped region 150 in the fin 110 corresponding to the interconnect location 160. Correspondingly, the gate structure at the interconnect location 160 is electrically connected to the source / drain plug through the source / drain doped region 150 and the metal silicide layer 140. Therefore, by making the metal silicide layer 140 of the interconnect location 160 contact the adjacent source / drain doped region 150 in the fin 110 corresponding to the interconnect location 160, the resistance between the gate structure and the source / drain plug at the interconnect location 160 is reduced, which is beneficial to further improve the performance of the semiconductor structure.

[0155] The material of the metal silicide layer 140 includes titanium silicon compound, cobalt silicon compound, or nickel silicon compound.

[0156] Reference Figures 22 to 24 ,in, Figure 22 This is a top view of the fin and gate structure. Figure 23 Based on Figure 22 Sectional view along the AA direction. Figure 24 Based on Figure 22 A cross-sectional view in the BB direction, showing the gate opening 200 (e.g. Figure 21 A gate structure 500 is formed in the (shown).

[0157] In this embodiment, the gate structure 500 includes a metal gate structure for controlling the opening or closing of the channel of the fin field-effect transistor.

[0158] In this embodiment, the metal gate structure includes a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer.

[0159] The work function layer is used to adjust the threshold voltage of the fin field-effect transistor. When forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0160] The gate electrode layer is used to bring out the electrical properties of the metal gate structure. In this embodiment, the material of the gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0161] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0162] Figure 25 This is a schematic diagram of another embodiment of the semiconductor structure formation method of the present invention.

[0163] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that: the substrate (not shown in the figure) is arranged along the direction of the plurality of fins 113 (e.g., Figure 25The region (shown in the X direction) includes an adjacent first region 103F and a second region 103S. A gate opening (not shown) located in either the first region 103F or the second region 103S extends into the other region and exposes the fin 113 of the other region. The location of the exposed fin 113 of the other region is used as an interconnect location 163. The transistor in the region where the fin 112 of the interconnect location 163 is located is disabled, and the fin of the other region is used to form a transistor.

[0164] In this embodiment, the gate opening of the first region 103F extends into the second region 103S and exposes the fin 113 of the second region 103S. The location of the fin 113 exposed by the gate opening of the first region 103F in the second region 103S is used as the interconnect location 163.

[0165] If the gate structure 503 of the first region 103F extends to the second region 103S and is directly electrically connected to the fin 113 at the interconnect location 163, then the first region 103F is used to form a transistor, and the transistor in the second region 103S is disabled.

[0166] Specifically, the transistor in the second region 103S fails, and the fins 113 on both sides of the gate structure 503 in the second region 103S also have source / drain doped regions. Therefore, the gate structure 503 of the first region 103F and the source / drain doped regions (not shown) in the fins 113 corresponding to the interconnection position 163 in the second region 103S are electrically connected. Accordingly, the gate structure 503 of the first region 103F can be electrically connected to the external circuit through the source / drain doped regions of the second region 103S to meet the actual wiring requirements. In other words, for the transistor in the first region 103F, the plug for electrical connection with the gate structure 503 can be set at the location of the source / drain doped regions of the second region 103S, thereby increasing the process window for electrical connection.

[0167] For a detailed description of the method for forming the semiconductor structure described in this embodiment, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0168] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate comprising a plurality of fins standing on the substrate, the substrate comprising a first region and a second region adjacent to each other along the arrangement direction of the plurality of fins, the first region and the second region being used for forming transistors respectively; a gate structure across the fins and covering part of the top and part of the sidewall of the fins, wherein the gate structure in any one of the first region and the second region extends to the other region and covers the fins of the other region, and the position where the fins of the other region covered by the gate structure is located is an interconnection position at which the gate structure and the fins are directly electrically connected; source-drain doped regions in the fins on both sides of the gate structure; a gate dielectric layer between the gate structure and the substrate, and the gate dielectric layer exposing the fin surface of the interconnection position; an interlayer dielectric layer on the substrate on the side of the gate structure and covering the sidewall of the gate structure.

2. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a cap layer between the gate structure and the gate dielectric layer, and exposing the fin surface of the interconnection position.

3. The semiconductor structure of claim 1, wherein, The semiconductor structure further comprises: a metal silicide layer covering the fin surface of the interconnection position. Alternatively, the material of the fins at the interconnection position is a metal silicide material, which is used as a metal silicide layer.

4. The semiconductor structure of claim 3, wherein, The metal silicide layer is in contact with adjacent source-drain doped regions in the fins corresponding to the interconnection position.

5. The semiconductor structure of claim 1, wherein, The semiconductor structure comprises an SRAM device, and the first region and the second region are used for forming a first pull-up transistor and a second pull-up transistor respectively. The gate structure in the first region extends to the second region and covers the fins of the second region, and in the second region, the position where the fins covered by the gate structure of the first region is located is the interconnection position. The gate structure in the second region extends to the first region and covers the fins of the first region, and in the first region, the position where the fins covered by the gate structure of the second region is located is the interconnection position.

6. The semiconductor structure of claim 1, wherein, The gate structure comprises a metal gate structure.

7. A method of forming a semiconductor structure, characterized by, The semiconductor structure comprises: providing a substrate comprising a plurality of fins standing on the substrate, forming an interlayer dielectric layer on the substrate, forming a gate opening in the interlayer dielectric layer, the gate opening across the fins and exposing part of the top and part of the sidewall of the fins, and forming source-drain doped regions in the fins on both sides of the gate opening, wherein the substrate comprises a first region and a second region adjacent to each other along the arrangement direction of the plurality of fins, the first region and the second region being used for forming transistors respectively, wherein the gate opening in any one of the first region and the second region extends to the other region and exposes the fins of the other region, and the position where the fins of the other region exposed by the gate opening is located is an interconnection position; forming a gate dielectric layer conformally covering the bottom and sidewall of the gate opening and the fins in the gate opening; removing the gate dielectric layer on the fin surface of the interconnection position to expose the fin surface of the interconnection position; After the fin surface of the interconnect location is exposed, a gate structure is formed in the gate opening.

8. The method of forming a semiconductor structure of claim 7, wherein, After a gate dielectric layer is formed on the bottom and sidewall of the gate opening, before the gate dielectric layer of the fin surface of the interconnect location is removed, further comprising: forming a planarization layer in the gate opening; Patterning the planarization layer to form an opening in the planarization layer of the interconnect location; Along the opening, the gate dielectric layer of the fin surface of the interconnect location is removed; After the gate dielectric layer of the fin surface of the interconnect location is removed, further comprising: removing the planarization layer.

9. The method of forming a semiconductor structure of claim 7, wherein, After a gate dielectric layer is formed on the bottom and sidewall of the gate opening, before the gate dielectric layer of the fin surface of the interconnect location is removed, further comprising: forming a cap layer conformally covering the gate dielectric layer; Before the gate dielectric layer of the fin surface of the interconnect location is removed, further comprising: removing the cap layer of the fin surface of the interconnect location.

10. The method of forming a semiconductor structure of claim 7, wherein, After the gate dielectric layer of the fin surface of the interconnect location is removed to expose the fin surface of the interconnect location, before a gate structure is formed in the gate opening, further comprising: performing a metal silicide process on the exposed fin surface of the interconnect location to form a metal silicide layer.

11. The method of forming a semiconductor structure of claim 10, wherein, In the step of forming the metal silicide layer, the metal silicide layer is in contact with adjacent source / drain doped regions in the fin corresponding to the interconnect location.

12. The method of forming a semiconductor structure of claim 7, wherein, Before the interlayer dielectric layer is formed, further comprising: forming a dummy gate layer on the substrate, the dummy gate layer crossing the fins and covering part of the top and sidewall of the fins; The interlayer dielectric layer is formed on the substrate at the side of the dummy gate layer, and the interlayer dielectric layer exposes the top of the dummy gate layer. The step of forming the gate opening comprises: removing the dummy gate layer.

13. The method of forming a semiconductor structure of claim 7, wherein, The gate dielectric layer of the fin surface of the interconnect location is removed by a dry etching process to expose the fin surface of the interconnect location.

14. The method of forming a semiconductor structure of claim 9, wherein, The cap layer of the fin surface of the interconnect location is removed by a dry etching process.

15. The method of forming a semiconductor structure of claim 7, wherein, The semiconductor structure is an SRAM device, and the first region and the second region are used to form a first pull-up transistor and a second pull-up transistor, respectively. The gate opening in the first region extends to the second region and exposes the fin of the second region, and the position of the fin of the second region exposed by the gate opening of the first region is the interconnect location. The gate opening in the second region extends to the first region and exposes the fin of the first region, and the position of the fin of the first region exposed by the gate opening of the second region is the interconnect location.

16. The method of forming a semiconductor structure of claim 7, wherein, The gate structure comprises a metal gate structure.

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