Integrated assembly and method of forming an integrated assembly

Abstract

This application relates to integrated assemblies and methods of forming integrated assemblies. Some embodiments include an integrated assembly having a first memory region, a second memory region, and an intermediate region between the first and second memory regions. The intermediate region has a first edge adjacent the first memory region and has a second edge adjacent the second memory region. A column of channel material is disposed within the first and second memory regions. A conductive column is disposed within the intermediate region. A doped semiconductor material is within the intermediate region and is configured to have a generally H-shaped structure with a first leg region along the first edge, a second leg region along the second edge, and a strip region adjacent the panel. Some embodiments include methods of forming integrated assemblies.

Description

Technical Field

[0001] The present invention relates to a method for forming an integrated assembly (e.g., an integrated memory device) and the integrated assembly itself. Background Technology

[0002] Memory provides data storage devices for electronic systems. Flash memory is a type of memory widely used in modern computers and devices. For example, modern personal computers store the BIOS on flash memory chips. As another example, it is increasingly common for computers and other devices to use flash memory, in the form of solid-state drives, instead of traditional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and allows manufacturers to provide the ability to remotely upgrade devices for enhanced features.

[0003] NAND can be the basic architecture of flash memory and can be configured to include vertically stacked memory cells.

[0004] Before specifically describing NAND, it may be helpful to describe the relationships of memory arrays within an integrated arrangement more generally. Figure 1 shows a block diagram of a prior art device 1000 including: a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns; access lines 1004 (e.g., word lines for conducting signals WL0 to WLm); and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). Access lines 1004 and first data lines 1006 are used to transmit information to and from the memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells in the memory cells 1003 will be accessed. Sensing amplifier circuitry 1015 operates to determine the value of the information read from the memory cells 1003. I / O circuitry 1017 transmits the value of the information between the memory array 1002 and the input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 represent values ​​of information read from or to be written to memory cell 1003. Other devices can communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 controls memory operations to be performed on memory cell 1003 and uses signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuitry 1040 and input / output (I / O) circuitry 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013, the signals representing values ​​of information to be read from or programmed into memory cell 1003. Column decoder 1008 can selectively activate CSEL1 to CSELn signals based on address signals A0 to AX on address line 1009. Selection circuit 1040 can select signals on first data line 1006 and second data line 1013 to enable communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0005] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked one on top of the other, where each charge storage device corresponds to, for example, one of thirty-two rows (e.g., row 0 to row 31). The charge storage devices in the corresponding strings may share a common channel region, for example, a common channel region formed in pillars of a corresponding semiconductor material (e.g., polysilicon), around which the charge storage device strings are formed. In a second direction (X-X'), each first group of the multiple strings, for example, sixteen first groups, may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines," also referred to as word lines WL). Each of the access lines may couple a charge storage device within a layer. When each charge storage device includes a cell capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same layer) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each second group in the multiple strings, for example, eight second groups, may include sixteen strings coupled by corresponding data lines of eight data lines. The size of the memory block may include 1024 pages and approximately 16 MB in total (e.g., 16WL × 32 rows × 2 bits = 1024 pages / block, block size = 1024 pages × 16KB / page = 16 MB). The number of strings, layers, access lines, data lines, first groups, second groups, and / or pages may be larger or smaller than those shown in Figure 2.

[0006] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 in the X-X' direction. The memory block 300 contains fifteen strings of charge storage devices in one of the sixteen first groups of strings described in Figure 2. The multi-string memory block 300 can be divided into multiple subsets 310, 320, 330 (e.g., tile columns), such as tile column I, tile column j, and tile column K, where each subset (e.g., tile column) includes a “partial block” (sub-block) of the memory block 300. A global drain-side selected gate (SGD) line 340 can be coupled to the SGDs of multiple strings. For example, the global SGD line 340 can be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding sub-SGD drivers of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, and 336 can simultaneously couple or disconnect the SGD of the corresponding sub-block (e.g., a tile array) of strings, independent of the SGD of strings in other sub-blocks. A global source-side select gate (SGS) line 360 ​​can be coupled to the SGS of multiple strings. For example, the global SGS line 360 ​​can be coupled to multiple sub-SGS lines 362, 364, and 366 via corresponding sub-SGS drivers among the multiple sub-SGS drivers 322, 324, and 326, where each sub-SGS line corresponds to a corresponding subset (e.g., a tile array). Each of the sub-SGS drivers 322, 324, and 326 can simultaneously couple or disconnect the SGS of the corresponding sub-block (e.g., a tile array) of strings, independent of the SGS of strings in other sub-blocks. A global access line (e.g., a global CG line) 350 can couple to a charge storage device corresponding to a corresponding row of each of the multiple strings. Each global CG line (e.g., global CG line 350) can be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding sub-string driver among a plurality of sub-string drivers 312, 314, and 316. Each sub-string driver among the sub-string drivers can simultaneously couple or disconnect the charge storage device corresponding to the corresponding sub-block and / or row, independent of the charge storage devices of other sub-blocks and / or other rows. The charge storage devices corresponding to the corresponding subset (e.g., sub-block) and the corresponding row may include charge storage devices of a “sub-row” (e.g., a single “patch”). The string corresponding to the corresponding subset (e.g., sub-block) can be coupled to a corresponding sub-source among sub-sources 372, 374, and 376 (e.g., “patch source”), wherein each sub-source is coupled to a corresponding power source.

[0007] Alternatively, the NAND memory device 200 is described with reference to the schematic illustration of FIG4.

[0008] Memory array 200 includes word lines 2021 to 202 NAnd bit lines 2281 to 228 M .

[0009] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. N Charge storage transistors can store charge using floating gate materials (e.g., polysilicon) or charge trapping materials (e.g., silicon nitride, metal nanodots, etc.).

[0010] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side select gate SGS) 210 and a drain select device (e.g., drain-side select gate SGD) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated by the boxes in FIG4.

[0011] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select device 210 is connected to the source select line 214.

[0012] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N The drain electrode.

[0013] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The control gate 236 of the charge storage transistor 208 is coupled to a word line 202. Columns of the charge storage transistor 208 are those transistors coupled to a given positioning line 228 within a NAND string 206. Rows of the charge storage transistor 208 are those transistors typically coupled to a given word line 202.

[0014] Block erasure of vertically stacked memory cells in a three-dimensional NAND architecture can be performed by generating hole carriers below them and then using an electric field to sweep the hole carriers upward along the memory cells.

[0015] A gate-controlled structure of a transistor can be used to provide gate-induced drain leakage (GIDL), which generates holes for block erasure of memory cells. The transistor can be a source-side selected (SGS) device as described above. The channel material associated with the memory cell string can be configured as channel material pillars, and regions of such pillars can be gated and coupled to the SGS device. The gatedly coupled portion of the channel material pillar is the portion overlapping the gate of the SGS device.

[0016] It is desirable that at least some of the gated coupling portions of the heavily doped channel material be used. In some applications, it is desirable that the gated coupling portions comprise both a heavily doped lower region and a lightly doped upper region; wherein both regions overlap with the gate of the SGS device. Specifically, overlapping with the lightly doped region provides the SGS device with non-drain "off" characteristics, and overlapping with the heavily doped region provides the SGS device with drain GIDL characteristics. The terms "heavily doped" and "lightly doped" are used relative to each other rather than relative to a particular conventional meaning. Thus, a "heavily doped" region is more heavily doped than the adjacent "lightly doped" region and may or may not include heavy doping in the conventional sense. Similarly, a "lightly doped" region is less doped than the adjacent "heavily doped" region and may or may not include light doping in the conventional sense. In some applications, the term "lightly doped" refers to having a doping density of less than or equal to about 10. 18 Semiconductor materials with dopant concentrations of 10 atoms per cubic centimeter, and the term "heavily doped" refers to semiconductor materials with dopant concentrations greater than or equal to about 10 atoms per cubic centimeter. 22 Semiconductor materials with dopants of 1 atom / cubic centimeter.

[0017] The channel material can be initially doped to a light doping level, and then a heavily doped region can be formed by diffusion from the bottom doped semiconductor material outward.

[0018] It is desirable to develop improved methods for forming integrated memories (e.g., NAND memory). It is also desirable to develop improved memory devices. Summary of the Invention

[0019] According to one aspect of this application, an integrated assembly is provided. The integrated assembly includes: a memory region and another region adjacent to the memory region; channel material pillars disposed in the memory region and pillars disposed in the other region; a source structure coupled to a lower region of the channel material pillars; at least some of the pillars are conductive pillars and have a lower region coupled to a logic circuit system; a panel extending across the memory region and the other region, and separating a first memory block region from a second memory block region; a first doped semiconductor material adjacent to the panel in the other region; a second doped semiconductor material adjacent to the panel in the memory region; the first doped semiconductor material is not electrically coupled to the conductive pillars; and the second doped semiconductor material is electrically coupled to the channel material pillars.

[0020] According to another aspect of this application, an integrated assembly is provided. The integrated assembly includes: a first memory region, a second memory region offset from the first memory region, and an intermediate region located between the first and second memory regions; the intermediate region having a first edge adjacent to the first memory region and a second edge adjacent to the second memory region; a first channel material pillar disposed within the first memory region; a second channel material pillar disposed within the second memory region; a conductive pillar disposed within the intermediate region; a panel extending across the first memory region, the intermediate region, and the second memory region; the panel being laterally positioned between the first and second memory block regions; and a doped semiconductor material located within the intermediate region and configured as having a generally H-shaped structure having a first foot region along the first edge, a second foot region along the second edge, and a strip region adjacent to the panel.

[0021] According to another aspect of this application, a method for forming an integrated assembly is provided. The method includes: forming a configuration comprising a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first and second memory regions; the configuration includes a first stack extending across the first memory region, the second memory region, and the intermediate region; the first stack includes alternating semiconductor-containing regions and intermediate regions; at least three of the semiconductor-containing regions are present, wherein one of the semiconductor-containing regions is a central semiconductor-containing region and is vertically located between the other two semiconductor-containing regions; the configuration further includes a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein... The second stack is positioned above the first stack; the second stack comprises alternating first and second levels, wherein the first level comprises a sacrificial material and the second level comprises an insulating material; the intermediate region has a first edge adjacent to the first memory region and a second edge adjacent to the second memory region; the central semiconductor material region has a relatively doped portion and a relatively undoped portion; the relatively undoped portion is located within the memory region and the intermediate region; the relatively doped portion is located only within the intermediate region and is configured to have a generally H-shaped region having a first foot region along the first edge, a second foot region along the second edge, and a strip region extending from the first foot region to the second foot region. The structure includes: forming pillars extending through the first memory region and the second memory region and at least partially entering the first stack of the first memory region and the second memory region, the pillars comprising cell material and channel material; forming pillars extending through the second stack of the intermediate region and entering the first stack of the intermediate region; forming a slit opening through the second stack and reaching the central semiconductor material region of the first stack; the slit opening extending across the first memory region, the intermediate region and the second memory region, and situated above and along the strip region; and using one or more etchants flowing into the slit opening to etch material from the first memory region... The process involves removing the central semiconductor material region within the first memory region and the second memory region, wherein the relatively doped portion of the central semiconductor material region is resistant to one or more etchants; the removal of the central semiconductor material region forms a conduit in the first stack within the first memory region and the second memory region; extending the conduit through the cell material and to the channel material of the pillar; forming a doped semiconductor material within the extended conduit; diffusing a dopant from the doped semiconductor material outward into the channel material, the outwardly diffusing dopant extending upward to at least one of the first layers; and replacing at least some of the sacrificial materials in the first layers with a conductive material. Attached Figure Description

[0022] Figure 1 shows a block diagram of a prior art memory device with a memory array having memory cells.

[0023] Figure 2 shows a schematic diagram of the prior art memory device of Figure 1 in the form of a 3D NAND memory device.

[0024] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 along the X-X' direction.

[0025] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0026] Figure 5-5B This is a schematic top view of a region of the instance integrated assembly during the instance processing stage of an instance embodiment method for forming an instance memory device. Figure 5 ) and a pair of schematic cross-sectional side views ( Figure 5A and 5B ). Figure 5A and 5B The cross-sectional side views are respectively along Figure 5 Lines AA and BB. Figure 5 Top view along Figure 5A and 5B The line CC.

[0027] Figure 6A and 6B Is Figure 5-5B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 6A and 6B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0028] Figure 7A and 7B Is Figure 6A and 6B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 7A and 7B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0029] Figure 8A and 8B Is Figure 7A and 7BThe instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 8A and 8B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0030] Figure 9A and 9B Is Figure 8A and 8B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 9A and 9B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section.

[0031] Figure 10A and 10B Is Figure 9A and 9B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 10A and 10B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section. Figure 10A-1 In relation to Figure 10A The alternative instance processing phase shown in the instance processing phase. Figure 10A A schematic cross-sectional side view of the area.

[0032] Figure 11A and 11B Is Figure 10A and 10B The instance processing phase after the instance processing phase Figure 5-5B A schematic cross-sectional side view of the area of ​​an example integrated assembly. Figure 11A and 11B The cross-sectional side views are respectively along with Figure 5A and 5B Same cross-section. Figure 11A-1 In relation to Figure 11A The alternative instance processing phase shown in the instance processing phase. Figure 11A A schematic cross-sectional side view of the area.

[0033] Figure 12A and 12B yes Figure 11A and 11BA schematic cross-sectional side view of a region of an example integrated assembly, and showing the components of such an assembly, excluding... Figure 11A and 11B Additional vertical extension areas beyond those shown in the diagram. Figure 12A-1 In relation to Figure 12A The alternative instance processing phase shown in the instance processing phase. Figure 12A A schematic cross-sectional side view of the area.

[0034] Figure 12C yes Figure 12A and 12B A schematic top view of the assembly. Figure 12A and 12B The cross-sectional side views are respectively along Figure 12C Lines AA and BB. Figure 12C Top view along Figure 12A and 12B The line CC. Figure 12C-1 In relation to Figure 12C The alternative instance processing phase shown in the instance processing phase. Figure 12C A schematic cross-sectional side view of the area. Detailed Implementation

[0035] Some embodiments include protecting regions of the integrated assembly with doped semiconductor material during the formation of conduits and / or other openings. Some embodiments include integrated assemblies having doped semiconductor material adjacent to some regions of a panel but not adjacent to other regions of the panel, wherein the panel separates one memory block region from another memory block. Reference Figure 5 -12 describes example implementations.

[0036] Figure 5 A top view is shown along several instance regions of the instance integrated assembly 10. The illustrated region of assembly 10 includes a pair of memory regions (memory array regions) 12a and 12b (array-1 and array-2), and includes an intermediate region 14 located between the memory regions. In some embodiments, memory regions 12a and 12b may be referred to as a first region laterally displaced (laterally offset) relative to each other, and intermediate region 14 may be referred to as another region (or a second region) located between the laterally displaced (laterally offset) first regions.

[0037] Unit material pillars 16 are arranged within memory regions 12a and 12b. Pillars 16 may be substantially identical to each other, where "substantially identical" means identical within reasonable manufacturing and measurement tolerances. Pillars 16 may be configured in a compact arrangement within each of memory regions 12a and 12b, such as a hexagonal close-packed (HCP) arrangement. Hundreds, thousands, millions, or even hundreds of thousands of pillars 16 may exist within each of memory regions 12a and 12b.

[0038] Each of the pillars 16 includes an outer region 18 containing memory cell material, a channel material 20 adjacent to the outer region 18, and an insulating material 22 surrounded by the channel material 20.

[0039] The cell material within the outer region 18 may include a tunneling material, a charge storage material, and a charge blocking material. The tunneling material (also referred to as the gate dielectric material) may include any suitable composition; and in some embodiments, it may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc. The charge storage material may include any suitable composition; and in some embodiments, it may include a floating gate material (e.g., polycrystalline silicon) or a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.). The charge blocking material may include any suitable composition; and in some embodiments, it may include one or more of silicon dioxide, alumina, hafnium oxide, zirconium oxide, etc.

[0040] The channel material 20 includes a semiconductor material. The semiconductor material may include any suitable composition; and in some embodiments, it may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., primarily composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., or composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term III / V semiconductor material refers to a semiconductor material comprising elements selected from Groups III and V of the periodic table (where Groups III and V are older nomenclature and are now referred to as Groups 13 and 15). In some embodiments, the semiconductor material may include suitably doped silicon, primarily composed of suitably doped silicon, or composed of suitably doped silicon.

[0041] The channel material 20 can be considered as configured as channel material pillars 24. In the illustrated embodiment, the channel material pillars 24 are... Figure 5In a top view, the channel material pillars are configured as loops, with such loops surrounding the insulating material 22. This configuration of the channel material pillars can be considered as corresponding to a “hollow” channel configuration, where the insulating material 22 is disposed within the hollow body of the channel material pillar. In other embodiments, the channel material pillars 24 may be configured as solid pillars. In some embodiments, the channel material pillars within the first memory region 12a may be referred to as first channel material pillars, and the channel material pillars within the second memory region 12b may be referred to as second channel material pillars. The channel material pillars may be arranged in any suitable configuration within the first memory region 12a and the second memory region 12b. In some embodiments, the channel material pillars may be arranged in a compact configuration, such as a close-packed hexagonal configuration.

[0042] The insulating material 22 may include any suitable composition; and in some embodiments, it may include silicon dioxide, consisting primarily of silicon dioxide, or consisting of silicon dioxide.

[0043] Posts 26 are arranged within the intermediate zone 14. Each of the described posts 26 comprises conductive material 28 transversely surrounded by an insulating liner 30. Posts 26 can be arranged in any suitable configuration, and their size and composition may be the same or different from each other.

[0044] The conductive material 28 may include any suitable conductive composition; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). In some embodiments, the conductive material 28 may include one or more of tungsten, titanium nitride, and tungsten nitride. For example, the conductive material 28 may include a conductive liner and may include tungsten filler laterally surrounded by the conductive liner, which includes one or both of titanium nitride and tungsten nitride along the insulating liner 30.

[0045] The insulating liner 30 may include any suitable composition; and in some embodiments, it may include silicon dioxide, consisting primarily of silicon dioxide, or consisting of silicon dioxide.

[0046] The column 26 is shown to be laterally surrounded by a first material 34 and a second material 36, wherein the second material 36 is configured as a loop 35 surrounding the first material 34.

[0047] The first material 34 may include undoped semiconductor materials, such as undoped silicon. The term "undoped" does not necessarily mean that there are absolutely no dopants present in the semiconductor material, but rather that the amount of any dopants present in such semiconductor materials is generally understood to be negligible. For example, depending on the context, undoped silicon can be understood to include less than about 10 16 atoms per cubic centimeter, less than approximately 10 15The dopant concentration is expressed as atoms per cubic centimeter, etc. In some embodiments, the first material 34 may include silicon, be composed primarily of silicon, or be composed of silicon.

[0048] In the illustrated embodiment, the first material 34 extends around the pillar 16 within the memory regions 12a and 12b, and extends outward from the insulating liner 30 within the intermediate region 14. In some embodiments, the first material 34 is a sacrificial material within the memory regions 12a and 12b (as referenced below). Figure 7B The process described is discussed in more detail), and therefore, the first material 34 may include any suitable sacrificial material, including but not limited to undoped semiconductor materials (e.g., undoped silicon).

[0049] The second material 36 may include any suitable composition, and may include, for example, silicon dioxide, consisting primarily of silicon dioxide, or composed of silicon dioxide.

[0050] In some embodiments, the conductive material 28 of the pillar 26 may be referred to as the conductive pillar 32. Such a conductive pillar may be "live" and therefore can be used as an electrical interconnect. Alternatively, the pillar may be "dummy" and may be used solely to provide structural support.

[0051] Hundreds, thousands, or millions of columns 26 can be set within the central area 14.

[0052] Intermediate region 14 may include numerous regions associated with the integrated memory, including, for example, stepped regions, peak regions, bridging regions, etc. If the conductive pillar 32 is energized, such pillars can be used to interconnect components associated with memory regions 12a and 12b to the circuitry below the illustrated regions of the integrated assembly 10. For example, conductive pillars can be used to connect bit lines to sensing circuitry (e.g., sensing amplifier circuitry), to connect SGD devices to control circuitry, etc.

[0053] Figure 5 The top view schematically shows that the intermediate region 14 has a first boundary edge 37 adjacent to the first memory region 12a and a second boundary edge 39 adjacent to the second memory region 12b. Boundary edges 37 and 39 can be considered as being along a first side and a second side of the intermediate region 14, respectively; wherein such first and second sides are in an opposing relationship to each other.

[0054] Boundary edges 37 and 39 can be considered to extend along the first direction (the x-axis direction as described).

[0055] exist Figure 5The slit opening orientation 38 is schematically shown in dashed lines. The slit opening orientation 38 extends along a second direction (the illustrated y-axis direction) intersecting the first direction (the illustrated x-axis direction). In the illustrated embodiment, the second direction (y-axis direction) is orthogonal to the first direction (the illustrated x-axis direction), or at least substantially orthogonal to the first direction; wherein the term "substantially orthogonal" means orthogonal within reasonable manufacturing and measurement tolerances. In other embodiments, the slit opening orientation 38 may extend along a direction intersecting but not substantially orthogonal to the first direction of the boundary edges 37 and 39.

[0056] A doped semiconductor material 40 is disposed within the intermediate region 14. The doped semiconductor material 40 is illustrated using a dotted diagram to aid the reader in observing this type of material.

[0057] The doped semiconductor material 40 is configured to include a first portion 42 along the boundary edge 37 of the intermediate region, a second portion 46 along the slit opening orientation 38, and a third portion 44 along the boundary edge 39 of the intermediate region. In some embodiments, portions 42 and 44 may be referred to as the first portion and the second portion, and portion 46 may be referred to as a strip extending between the first portion 42 and the second portion 44. In the illustrated embodiment, the doped semiconductor material 40 is configured as a generally H-shaped structure 48. Portions 42, 44, and 46 may be considered as a first leg region (first leg portion), a second leg region (second leg portion), and a strip region (strip portion) of such a generally H-shaped structure, respectively. The term "generally H-shaped" means that the shape generally conveys an H-shaped configuration to an observer. The lengths of the first leg and the second leg may be the same or different from each other, and the strip region may or may not be centered relative to one or both of the first leg and the second leg.

[0058] The H-shaped structure 48 described may be a much larger segment of the doped semiconductor material 40. For example, in addition to orientation 38, there may be multiple slit opening orientations, wherein such slit opening orientations are laterally offset relative to each other. Multiple strip-shaped portions extending between the first portion 42 and the second portion 44 may be present, wherein each of the strip-shaped portions is below one of the slit opening orientations.

[0059] Figure 5A and 5B Cross-sectional side views of the intermediate region 14 and the first memory region 12a are shown respectively. Figure 5A The view along Figure 5 Line AA, and Figure 5B The view along Figure 5 BB line. Figure 5 The view along Figure 5A and 5B The line CC. Figure 5A and5B The view is schematically illustrated. Figure 5 The instance structure shown in the top view, but not with Figure 5 Provide the same proportion.

[0060] Figure 5A and 5B An example configuration is shown in which insulating material 50 forms a support structure for the first stack 52.

[0061] The insulating material 50 may include any suitable composition, and in some embodiments may include silicon dioxide, consisting primarily of silicon dioxide, or composed of silicon dioxide.

[0062] In the illustrated embodiment, the conductive structure 54 is located within the insulating material 50. The conductive structure 54 may include any suitable conductive material; such as one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.) and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.).

[0063] One or more of the conductive structures 54 may be coupled to a logic circuit system (e.g., CMOS) disposed beneath the insulating material 50. Figure 5A A logic circuit system is shown, which may include components 56a and 56b corresponding to, for example, a control circuit system and / or a sensing circuit system (e.g., a sense amplifier circuit system, a driver circuit system, etc.). Figure 5B A logic circuit system is shown that is configured to include a component 56c (e.g., a control circuit system) coupled to the source structure.

[0064] The logic circuit system 56 may be supported by a semiconductor material (not shown). Such semiconductor materials may include, for example, monocrystalline silicon (Si), consist primarily of monocrystalline silicon (Si), or consist entirely of monocrystalline silicon (Si). The semiconductor material may be referred to as a semiconductor substrate or a semiconductor base. The term "semiconductor substrate" means any construction that includes semiconductor material, including but not limited to bulk semiconductor material, such as a semiconductor wafer (alone or in a combination including other materials), and a layer of semiconductor material (alone or in a combination including other materials). The term "substrate" refers to any support structure that includes (but is not limited to) the semiconductor substrate described above. The configuration described herein may be referred to as an integrated configuration supported by a semiconductor substrate and therefore may be considered as an integrated assembly.

[0065] The first stack 52 can be referred to as the first stack, and can be considered as a cross-stack. Figure 5The memory regions (12a and 12b) and intermediate region (14) extend from each other. The first stack 52 contains conductive material 58 (which can be considered as conductive structures configured within regions 12a, 12b and 14) and includes regions 60 and 62 above the conductive material 58. Region 60 can be referred to as a semiconductor material-containing region.

[0066] In the illustrated embodiment, three regions are present in region 60, and these regions are labeled 60a, 60b, and 60c. Regions 60a and 60c contain semiconductor material 64. Such semiconductor material may include conductive doped semiconductor material, such as conductive doped silicon. In some embodiments, the silicon may be n-type doped, and therefore may be doped with one or both of phosphorus and arsenic. The conductive doped silicon in regions 60a and 60c may be doped to at least about 10⁻⁶ using one or more suitable conductivity-enhancing dopants. 22 The concentration is atoms per cubic centimeter. The semiconductor material in region 60a may be the same as the semiconductor material in region 60c, as shown, or may be different from the semiconductor material in region 60c.

[0067] Section 60b includes the above reference. Figure 5 Materials 34 and 40 are described. In some embodiments, materials 34 and 40 may comprise the same semiconductor material, wherein the doped semiconductor material 40 corresponds to a relatively doped portion of such a semiconductor material, and wherein the first material 34 corresponds to a relatively undoped portion of such a material. The doped semiconductor material 40 comprises a higher concentration of dopant compared to any dopant concentration present in the first material 34. In some embodiments, the doped semiconductor material 40 of region 60b comprises from about 10 15 From one atom per cubic centimeter to about 10 25 Within the range of atoms per cubic centimeter, from approximately 10 18 From one atom per cubic centimeter to about 10 22 The total dopant concentration is in the range of atoms per cubic centimeter. In subsequent processing stages (see below for reference) Figure 7A and 7B The etching characteristics (described) are achieved by using dopants within the doped semiconductor material 40 to modify those etching properties of the doped semiconductor material 40 relative to the first material 34. The dopants disposed within the doped semiconductor material 40 can be any suitable dopant, and in some embodiments may include one or more of carbon, phosphorus, arsenic, boron, nitrogen, oxygen, and gallium. In some embodiments, the doped semiconductor material 40 may include boron-doped silicon, be primarily composed of boron-doped silicon, or be composed of boron-doped silicon.

[0068] Regions 60a-c can be considered as vertically stacked one on top of the other, where region 60b is the central semiconductor material region located vertically between regions 60a and 60c.

[0069] Intermediate region 62 alternates with semiconductor material-containing region 60 within the first stack 52. Region 62 includes material 66. Material 66 may be insulating, conductive, etc. In some embodiments, material 66 may be insulating and may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride, etc., primarily composed of one or more of silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride, etc., or composed of one or more of silicon dioxide, aluminum oxide, hafnium oxide, silicon nitride, silicon oxynitride, etc. Regions 62a and 62b may include the same composition as each other (as shown), or may include compositions different from each other. One or both of regions 62 may include a homogeneous composition (as shown) or may include a laminate of two or more different compositions.

[0070] Although the first stack 52 is shown as including three of the semiconductor material-containing regions 60 and two of the intermediate regions 62, it should be understood that the stack may include any suitable number of regions 60 and 62. In some embodiments, the first stack 52 may include at least three of the semiconductor material-containing regions 60 and at least two of the intermediate regions 62.

[0071] Region 60 can be formed to any suitable thickness, and in some embodiments, it can be formed to a thickness ranging from about 100 nanometers (nm) to about 300 nm. Region 62 can be formed to any suitable thickness, and in some embodiments, it can be formed to a thickness ranging from about 5 nm to about 20 nm.

[0072] A second stack 68 is formed over a first stack 52. The second stack 68 has alternating first levels 70 and second levels 72. The first level 70 includes material 74, and the second level 72 includes material 76. Materials 74 and 76 may include any suitable composition. In some embodiments, material 74 may include silicon nitride, and is composed primarily of silicon nitride, or is composed of silicon nitride; and material 76 may include silicon dioxide, and is composed primarily of silicon dioxide, or is composed of silicon dioxide. Material 74 may be referred to as a sacrificial material, and material 76 may be referred to as an insulating material.

[0073] Stacks 52 and 68 can be considered together as part of construction 78. In the illustrated embodiment, such a construction also includes a second material 36 configured as loops 35. These loops subdivide the conductive material 58 into islands 80, some of which are connected to the conductive material 78 in the concrete. Figure 5A In the illustrated embodiment, the CMOS circuit system 56 is coupled.

[0074] like Figure 5AAs shown, pillar 26 is formed to extend through the second stack 68, through regions 60 and 62 of the first stack 52, and to reach the conductive material 58. Pillar 26 includes conductive pillars 32, and in the illustrated embodiment, such conductive pillars are electrically coupled to conductive islands 80 formed of the conductive material 58. In embodiments where the conductive pillars 32 are “charged” pillars, the conductive pillars 32 may be coupled to the CMOS circuit system 56. Alternatively, in embodiments where the conductive pillars are in a “simulated” configuration for structural support rather than for electrical connection, at least some of the conductive pillars 32 may not be coupled to the CMOS circuit system.

[0075] In the illustrated embodiment, each of the islands 80 supports one of the conductive posts 32. In other embodiments, at least one of the islands 80 may support two or more of the conductive posts. Moreover, in the illustrated embodiment, each of the posts 26 comprises a conductive post 32. In other embodiments, one or more of the posts 26 may comprise only insulating material, especially where such posts are provided solely for structural support.

[0076] The second material 36 has a ring 35 that laterally surrounds the lower region of the conductive post 32. In some embodiments, the ring 35 can be considered as an outer ring and can be considered as an inner ring 81 laterally surrounding the first material 34 (wherein... Figure 5A Cross-sectional side view and Figure 5 The top view of these two inner rings (marked as such) is shown. The ring 35 is shown as a square, but in other embodiments, it may have any suitable shape, including, for example, a circular shape, an elliptical shape, a rectangular shape, etc.

[0077] The cell material pillar 16 is formed to extend through the second stack 68 and partially into the first stack 52, as shown in 5B. In the illustrated embodiment, the cell material pillar 16 extends into the lower region 60a of the first stack 52 but not into the conductive material 58. The cell material pillar 16 includes cell material within the outer region 18, channel material pillar 24, and insulating material 22.

[0078] In some embodiments, memory regions 12a and 12b (containing Figure 5B A portion of the first stack 52 within the region described above may ultimately correspond to a source structure similar to the prior art source structure described above with reference to Figures 1-4.

[0079] Figure 5A and 5B A slit opening 82 is shown formed along the slit opening orientation 38. The slit opening passes through the second stack 68 and enters the first stack 52. In the illustrated embodiment, the slit opening terminates on a doped semiconductor material 40 (e.g., Figure 5B (as shown in the diagram). In other embodiments, the slit opening may extend into the doped semiconductor material 40.

[0080] In the illustrated embodiment, the slit opening has a generally vertically straight sidewall surface; wherein the term "generally vertically straight" means that it is vertically straight within reasonable manufacturing and measurement tolerances. In other embodiments, the sidewall surface of the slit opening may be tapered.

[0081] A protective material 84 is formed within the slit opening 82 and along the sidewall surface of the slit opening. The protective material 84 may include any suitable composition. In some embodiments, the protective material 84 may include silicon, be primarily composed of silicon, or be composed of silicon; and specifically may include virtually undoped material (e.g., including an inherent dopant concentration, and in some embodiments, including less than or equal to about 10). 16 Silicon with a dopant concentration of atoms per cubic centimeter. In some embodiments, the protective material 84 may include one or more of the following: metals (e.g., tungsten, titanium, etc.), metal-containing materials (e.g., metal silicides, metal nitrides, metal carbides, metal borides, etc.), and semiconductor materials (e.g., silicon, germanium, etc.).

[0082] Figure 5A and 5B The area described for assembly 10 shown is the lower part of the assembly, and it should be understood that the assembly may include... Figure 5A and 5B The layers described herein are compared to the second stack 68, which has more layers.

[0083] refer to Figure 6A and 6B One or more etchings are used to penetrate the protective material 84 at the bottom of the slit opening 82 to expose region 60b of the first stack 52. The slit opening 82 spans... Figure 5 The memory area and intermediate area (areas 12a, 12b and 14) extend. Therefore, removing the protective material 84 from the bottom of the slit opening 82 exposes the memory area (e.g., Figure 6B The first memory region 12a) contains the first material (relative to the undoped portion) 34 and also exposes the intermediate region 14. Figure 6A The doped semiconductor material 40 (relative to the doped portion) is located within the H-shaped structure 48 of the doped semiconductor material 40. In the illustrated embodiment, the slit opening 82 is positioned above the strip portion (strip region) 46 of the H-shaped structure 48 of the doped semiconductor material 40, as shown in the reference. Figure 5 Understandable.

[0084] refer to Figure 7B Remove the first material 34 from zone 60b. Figure 6B To form conduit 86. Conduit 86 is formed within memory regions 12a and 12b (in Figure 7BThe cross-sectional view shows the first memory region 12a. The conduit 86 can be formed by any suitable process, and in some embodiments, it can be formed using one or more etchants containing hydrofluoric acid. In the illustrated embodiment, intermediate regions 62a and 62b are retained after the conduit 86 is formed. In other embodiments, depending on the composition of the intermediate regions and the composition of the etchant used to remove the first material 34, such intermediate regions can be removed during conduit formation.

[0085] Figure 7A Showing with Figure 7B The first memory region 12a is located in the intermediate region 14 at the same processing stage, and shows pairs of doped semiconductor materials 40 for use in the memory region (e.g., Figure 7B The etchant forming the conduit 86 in the first memory region 12a) is resistant. In some embodiments, the first material 34 exposed within the slit 82 can be considered as being selectively removed relative to the doped semiconductor material 40 exposed within the slit 82. For the purposes of interpreting this disclosure and the appended claims, if the first material is removed more rapidly than the second material, then the first material is considered to be selectively removed relative to the second material; this may include, but is not limited to, a condition that the first material is 100% selective relative to the second material.

[0086] H-shaped configuration of doped semiconductor material 40 (in) Figure 5 (As shown in the top view) Materials 30, 34, and 36 protect the intermediate region 14 from exposure to the etchant used to remove the first material 34 from memory regions 12a and 12b. Thus, materials 30, 34, and 36 remain intact in the intermediate region 14 to provide isolation between the conductive pillars 32.

[0087] refer to Figure 8B The conduit 86 extends through the cell material within the outer region 18 to expose the sidewall surface of the semiconductor material (channel material) 20. Figure 8A This shows that no significant changes occur in the intermediate zone 14 during the extension of the conduit 86 through the unit material within the outer zone 18.

[0088] refer to Figure 9A and 9B The conductive doped semiconductor material 88 is formed inside the conduit 86. Figure 8BThe conductive doped semiconductor material 88 may include any suitable composition; and in some embodiments, it may include one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., primarily composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc., or composed of one or more of silicon, germanium, III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc. In some embodiments, the conductive doped semiconductor material 88 may include heavily doped (e.g., doped to at least about 10) n-type dopant (e.g., doped to at least about 10). 22 Silicon with a concentration of atoms per cubic centimeter (A / C). The conductive doped semiconductor material 88 can be considered as a source structure assembly 90 configured to be coupled to the lower region of the channel material pillar 24. In some embodiments, Figure 9B The material within the first stack 52 can all be considered as part of the conductive electrode structure. This can be achieved in the formation of... Figure 7B During catheter 86, areas 62a and 62b were removed (as referenced above). Figure 7B (as discussed), such that these regions are not part of the source structure including the first stack 52. In some embodiments, regions 62a and 62b may be conductive so as not to adversely affect the conductivity along the source structure including the first stack 52, or may be insulating and kept thin enough so as not to problematically affect the conductivity along the source structure including the first stack 52.

[0089] The conductive doped semiconductor material 88 is used to form memory regions 12a and 12b (in Figure 9B The diagram shows region 60b of the first stack 52 within the first memory region 12a), and channel material 20 directly contacting the channel material pillar 24.

[0090] In some embodiments, one of the doped semiconductor materials 40 and 88 may be referred to as a first doped semiconductor material, and the other may be referred to as a second doped semiconductor material. Doped semiconductor materials 40 and 88 may comprise the same semiconductor components as each other (e.g., both may comprise doped silicon, be primarily composed of doped silicon, or be composed of doped silicon), but may be doped in different ways relative to each other. For example, in some embodiments, doped semiconductor material 40 may comprise p-type doped silicon (e.g., boron-doped silicon), and conductive doped semiconductor material 88 may comprise n-type doped silicon (e.g., one or both of phosphorus-doped silicon and arsenic-doped silicon).

[0091] refer to Figure 10A , 10BAnd 10A-1, material 84 and 88 are removed from the opening (slit) 82 by one or more suitable etching methods. The material can be removed by any suitable etchant. The slit opening 82 can be stamped to any suitable depth within the source structure of the first stack 52. Figure 10A An embodiment is shown in which the etching extends the slit 82 into the doped semiconductor material 40, and Figure 10A-1 An alternative embodiment is shown in which the etching does not extend into the doped semiconductor material 40.

[0092] The dopant diffuses outward from the conductive doped semiconductor material 88 into the semiconductor material (channel material) 20 to form a heavily doped region 92 in the lower portion of the channel material pillar 24. The approximate upper boundary of the dopant within the heavily doped region 92 is indicated by line 93.

[0093] Outward diffusion from the conductive doped semiconductor material 88 to the semiconductor material 20 can be achieved by any suitable process, including, for example, a suitable heat treatment (e.g., heat treatment at a temperature exceeding about 300°C for a duration of at least about two minutes).

[0094] Remove 74 sacrificial materials from Tier 1, Level 70. Figure 9A and 9B And replaced with conductive material 94. Although conductive material 94 is shown as completely filling the first layer 70, in other embodiments, at least some of the materials disposed within the first layer 70 may be insulating materials (e.g., dielectric barrier materials).

[0095] The conductive material 94 may include a suitable composition; and in some embodiments, it may include a tungsten core at least partially surrounded by titanium nitride. The dielectric barrier material may include any suitable composition; and in some embodiments, it may include one or more of alumina, hafnium oxide, zirconium oxide, etc.

[0096] Figure 10A , 10B The first layer 70 of 10A-1 is a conductive layer, and the second stack 68 can be considered as being in... Figure 10A , 10B The processing stage of 10A-1 includes alternating insulating layers (intermediate layers) 72 and conductive layers 70.

[0097] refer to Figure 11A , 11BIn 11A-1, panel material 96 is formed within slit opening 82. Panel material 96 may include any suitable composition; and in some embodiments, it may include silicon dioxide, be primarily composed of silicon dioxide, or be composed of silicon dioxide. Although panel material 96 is shown as a single homogeneous composition, in other embodiments, panel material may include a laminate of two or more different compositions.

[0098] Panel material 96 forms across memory regions (e.g., Figure 11B First memory region 12a) and intermediate region ( Figure 11A and 11A-1 The middle area 14) extends to the panel 98.

[0099] Figure 11B The assembly 10 can be considered as a memory device including memory cell 100 and select device (SGS device) 102. The lowermost part of conductive layer 70 is designated 70a and extends through doped region 92 to conductive layer 70a. Conductive layer 70a includes SGS device 102. In the illustrated embodiment, the dopant extends partially across layer 70a to achieve a desired balance between the non-drain "off" characteristics and drain GIDL characteristics of the SGS device.

[0100] Although only one of the conductive layers is shown as being incorporated into the SGS device, in other embodiments, multiple conductive layers may be incorporated into the SGS device. The conductive layers may be electrically coupled (joined together) to be incorporated into the long-channel SGS device. If multiple conductive layers are incorporated into the SGS device, then outwardly diffusing dopant may extend upward across two or more of the conductive layers 70 incorporated into the SGS device.

[0101] Memory cells 100 (e.g., NAND memory cells) are stacked vertically on top of each other. Each memory cell includes a region of semiconductor material (channel material) 20 and a region of conductive layer 70 (control gate region). Regions of conductive layer 70 not included in memory cell 100 can be considered as word line regions (routing regions) coupling the control gate region to driver circuitry and / or other suitable circuitry. Memory cell 100 includes cell material (e.g., tunneling material, charge storage material, and charge blocking material) within an outer region 18.

[0102] In some embodiments, the conductive level 70 associated with memory cell 100 may be referred to as a word line / control gate level (or memory cell level) because it contains word lines and control gates associated with the vertically stacked memory cells of the NAND string. The NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0103] The source structure including the first stack 52 may be similar to the source structure 216 described in the "Background Art" section. As shown, the source structure is shown coupled to a control circuitry system (e.g., CMOS) 56c. The control circuitry system may be below the source structure (as shown) or may be in any other suitable orientation. The source structure may be coupled to the control circuitry system 56c at any suitable processing stage.

[0104] In some embodiments, the channel material column 24 can be considered as representing the span Figure 11B The first memory region 12a extends from a plurality of substantially identical channel material pillars; wherein the term “substantially identical” means identical within reasonable tolerances for manufacturing and measurement. Panel 98 may divide the pillars between a first memory block region 104 and a second memory block region 106. Thus, a memory cell 100 on one side of panel 98 may be considered within the first memory block region 104, and a memory cell 100 on the other side of panel 98 may be considered within the second memory block region 106. Memory block regions 104 and 106 may be analogous to the memory block (or memory sub-block) described above in the “Background” section of this disclosure.

[0105] Figure 12A and 12B Show Figure 11A and 11B The configuration is shown, and the individual structures (e.g., panel 98, conductive pillar 32, and unit material pillar 16) extend vertically and are coupled to additional circuit elements. The second stack 68 may extend vertically to extend along a large portion of panel 98, conductive pillar 32, and unit material pillar 16.

[0106] Figure 12B The unit material column 16 extends upward to the bit line 108. The SGD device 110 is schematically illustrated as being adjacent to the upper region of the column 16 and below the bit line 108.

[0107] Bit line 108 can extend into and out relative to Figure 12B The page with a cross-sectional view.

[0108] Pillar 16, bit line 108, SGD device 110, SGS device 102 and memory cell 100 can be considered together as forming a NAND-type configuration similar to those described above with reference to Figures 1-4.

[0109] exist Figure 12B In the view, bit line 108 is indicated as coupled to conductive post 32, and in Figure 12A In the view, the conductive post 32 is indicated to be coupled to the bit line 108. Therefore, in some embodiments, the bit line 108 associated with the first memory region 12a can be coupled to the sensing circuitry (e.g., 56a and 56b) via the conductive post 32 associated with the intermediate region 14.

[0110] Bit line 108 is an example of a component that can be associated with cell material pillar 16 and coupled to a logic circuit system via conductive pillar 32. In other embodiments, as an alternative to or supplement to the bit line, other components may be coupled to the logic circuit system via one or more of the conductive pillars 32. For example, SGD device 110 may be coupled to the logic circuit system via conductive pillar 32, and in such embodiments, the logic circuit system may include a control circuit system for controlling the SGD device. Typically, one or more components may be operatively located near cell material pillar 16 (and / or channel material pillar 24) and coupled to the logic circuit system 56 via conductive pillar 32.

[0111] Figure 12A Showing something similar to Figure 11A The configuration of the panel 98 is through a doped semiconductor material 40. Figure 12A-1 A similar configuration is shown, but Figure 12A-1 The configuration is similar to Figure 11A-1 The configuration includes a panel 98 that stops at the upper surface of the doped semiconductor material 40.

[0112] Figure 12C Show along Figure 12A and 12B A top view of section CC. Panel 98 is located within the slit opening orientation 38 and extends across memory regions 12a and 12b, and across intermediate region 14. Panel 98 is laterally positioned between the first memory block region 104 and the second memory block region 106, and subdivides the first memory block region 104 and the second memory block region 106 (i.e., separates the first memory block region from the second memory block region).

[0113] In some embodiments, the doped semiconductor material 40 may be considered as a first doped semiconductor material adjacent to the panel 98 within the intermediate region 14, and the conductive doped semiconductor material 88 may be considered as a second doped semiconductor material adjacent to the panel 98 within the memory regions 12a and 12b. The conductive doped semiconductor material 88 is adjacent to and electrically coupled to the channel material pillar 24. In contrast, the doped semiconductor material 40 is not adjacent to the conductive pillar 32, but rather there is at least one insulating material (e.g., a second material 36) between the doped semiconductor material 40 and the conductive pillar 32, such that the conductive pillar is not electrically coupled to the doped semiconductor material 40.

[0114] The doped semiconductor material 40 has the above reference Figure 5 The generally H-shaped structure 48 is described. However, the panel material 96 divides the strip portion 46 into pairs of segments 47a and 47b located on opposite sides of the panel 98. Figure 12C-1 Showing something similar to Figure 12C The configuration, but based on Figure 12A-1 The configuration of the assembly (i.e., the assembly in which panel 98 does not penetrate the doped semiconductor material 40). Figure 12C-1 Panel 98 penetrates the conductive doped semiconductor material 88 of memory regions 12a and 12b, but does not penetrate the doped semiconductor material 40 of the intermediate region 14. Therefore, the strip region 46 of the generally H-shaped structure 48 is located below panel 98 (as schematically illustrated by showing panel 98 in a dashed view relative to the intermediate region 14) and is not divided by the panel.

[0115] Figure 12C and 12C-1 The illustrated panel 98 may be one of a plurality of panels extending across regions 12a, 12b, and 14 and spacing the first memory block region and the second memory block region apart from each other. Therefore, the illustrated memory block regions 104 and 106 may represent regions that can be accessed by... Figure 12C and 12C-1 The diagram illustrates a large number of memory block regions formed at the processing stage. The panels may be laterally spaced from each other, and each panel may extend along a portion of the doped semiconductor material 40. Therefore, the illustrated strip portion 46 of the H-shaped structure 48 may be one of a plurality of strip portions extending across the intermediate region 14. In such embodiments, the strip portion 46, together with the first portion 42 and the second portion 44 of the H-shaped structure 48, may form a trapezoidal configuration, wherein the H-shaped structure 48 is the rung of the trapezoidal configuration, and the first portion 42 and the second portion 44 are the handrails of the trapezoidal configuration. In some embodiments, the illustrated H-shaped structure 48 may be considered as a representative segment of an example trapezoidal configuration.

[0116] The assemblies and structures discussed above can be used within integrated circuits (the term "integrated circuit" refers to electronic circuits supported by a semiconductor substrate) and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be any of the following wide range of systems: for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting systems, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, and so on.

[0117] Unless otherwise specified, the various materials, substances, compositions, etc. described herein can be formed by any suitable method now known or to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0118] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The term “dielectric” in some cases and the term “insulating” (or “electrically insulating”) in others may be used within this disclosure to provide linguistic variation to simplify the premises of the following claims, rather than to indicate any significant chemical or electrical differences.

[0119] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. The use of one term in some instances and another in others may be to provide linguistic variation within this disclosure to simplify the presuppositions in the appended claims.

[0120] The specific orientations of the various embodiments in the figures are for illustrative purposes only, and in some applications, embodiments may be rotated relative to the shown orientation. The descriptions provided herein and the following claims relate to any structure having the described relationships between various features, regardless of whether the structure is in a specific orientation of the figures or rotated relative to such an orientation.

[0121] Unless otherwise specified, the cross-sectional views in the accompanying drawings show only the features within the plane of the cross-section and do not show the material behind the plane of the cross-section in order to simplify the drawings.

[0122] When a structure is referred to as "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may be an intervening structure. Conversely, when a structure is referred to as "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there is no intervening structure. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless otherwise explicitly stated), but instead indicate upright alignment.

[0123] A structure (e.g., a layer, material, etc.) may be referred to as “vertically extending” to indicate that the structure generally extends upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend generally orthogonally relative to the upper surface of the substrate.

[0124] Some embodiments include an integrated assembly having a memory region and another region adjacent to the memory region. Channel material pillars are arranged within the memory region, and pillars are arranged within the other region. Source structures are coupled to a lower region of the channel material pillars. At least some of the pillars are conductive pillars and have a lower region coupled to a logic circuit system. A panel extends across the memory region and the other region, and separates a first memory block region from a second memory block. A first doped semiconductor material is adjacent to the panel within the other region. A second doped semiconductor material is adjacent to the panel within the memory region. The first doped semiconductor material is not electrically coupled to the conductive pillars. The second doped semiconductor material is electrically coupled to the channel material pillars.

[0125] Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region located between the first and second memory regions. The intermediate region has a first edge adjacent to the first memory region and a second edge adjacent to the second memory region. A first channel material pillar is disposed within the first memory region. A second channel material pillar is disposed within the second memory region. Conductive pillars are disposed within the intermediate region. A panel extends across the first memory region, the intermediate region, and the second memory region. The panel is laterally positioned between the first and second memory block regions. A doped semiconductor material is located within the intermediate region and configured in a generally H-shaped structure having a first foot region along the first edge, a second foot region along the second edge, and a strip region adjacent to the panel.

[0126] Some embodiments include a method of forming an integrated assembly. A configuration is formed comprising a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first and second memory regions. The configuration includes a first stack extending across the first memory region, the second memory region, and the intermediate region. The first stack includes alternating semiconductor-containing regions and intermediate regions. At least three of the semiconductor-containing regions are present, wherein one of the semiconductor-containing regions is a central semiconductor-containing region and is vertically located between the other two semiconductor-containing regions. The configuration also includes a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein the second stack is located above the first stack. The second stack includes alternating first and second levels, wherein the first level includes a sacrificial material and the second level includes an insulating material. The intermediate region has a first edge adjacent to the first memory region and a second edge adjacent to the second memory region. The central semiconductor-containing region has relatively doped portions and relatively undoped portions. The relatively undoped portions are located within the memory region and the intermediate region. The relatively doped portion is located only within the intermediate region and is configured as a generally H-shaped structure having a first foot region along the first edge, a second foot region along the second edge, and a strip region extending from the first foot region to the second foot region. A second stack is formed extending through the first and second memory regions and at least partially into the first stack within the first and second memory regions. The pillar comprises cell material and channel material. A pillar is formed extending through the second stack within the intermediate region and into the first stack within the intermediate region. A slit opening is formed through the second stack and reaching the central semiconductor-containing region of the first stack. The slit opening extends across the first memory region, the intermediate region, and the second memory region, and is located above and along the strip region. The central semiconductor-containing region is removed from the first and second memory regions by one or more etchants flowing into the slit opening. The relatively doped portion of the central semiconductor-containing region is resistant to the one or more etchants. The removal of the central semiconductor-containing region forms a conduit in the first stack within the first and second memory regions. The conduit extends through the unit material and reaches the channel material of the pillar. A doped semiconductor material is formed within the extended conduit. A dopant diffuses outward from the doped semiconductor material into the channel material. The outwardly diffused dopant extends upward to at least one of the first layers. At least some of the sacrificial materials in the first layers are replaced with conductive material.

[0127] As per the regulations, the subject matter disclosed herein has been described in more or less specific language regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the apparatus disclosed herein includes exemplary embodiments. Therefore, the claims have the full scope as stated in the writings and should be properly interpreted in accordance with the principle of equivalence.

Claims

1. An integrated assembly comprising: The memory area and another area adjacent to the memory area; Channel material pillars arranged in the memory region, and pillars arranged in the other region; A source structure coupled to the lower region of the channel material pillar; At least some of the pillars are conductive pillars and have a lower region coupled to the logic circuit system; A panel that extends across the memory region and the other region and separates a first memory block region from a second memory block region, wherein the first memory block region and the second memory block region are located within the memory region; A first doped semiconductor material, which is adjacent to the panel in the other region and is resistant to one or more etchants; A second doped semiconductor material is located adjacent to the panel within the memory region; The first doped semiconductor material is not electrically coupled to the conductive pillar; and The second doped semiconductor material is electrically coupled to the channel material.

2. The integrated assembly of claim 1, wherein the other region has a boundary edge adjacent to the memory region; wherein the boundary edge extends along a first direction and the panel extends along a second direction intersecting the first direction; and wherein the first doped semiconductor material is configured to include a first portion extending along the boundary edge and along the first direction, and a second portion extending along the second direction.

3. The integrated assembly of claim 2, wherein the second portion comprises a pair of segments located on opposite sides of the panel.

4. The integrated assembly of claim 2, wherein the second portion is located below the panel.

5. The integrated assembly of claim 2, wherein the second direction is substantially orthogonal to the first direction.

6. The integrated assembly of claim 2, wherein the memory region is a first memory region; wherein the boundary edge is a first boundary edge and extends along a first side of the other region; wherein the second memory region extends along a second side of the other region, wherein the second side is opposite to the first side; wherein the second boundary edge of the other region extends along the second side; and wherein the first doped semiconductor material is configured to include a third portion extending along the second boundary edge and along the first direction.

7. The integrated assembly of claim 1, wherein the first doped semiconductor material and the second doped semiconductor material comprise silicon.

8. The integrated assembly of claim 7, wherein the first doped semiconductor material comprises a dopant, the dopant comprising one or more of carbon, phosphorus, arsenic, boron, nitrogen, oxygen and gallium.

9. The integrated assembly of claim 8, wherein the dopant is at a concentration of 10 15 From atoms per cubic centimeter to 10 25 It exists at concentrations in the range of atoms per cubic centimeter.

10. The integrated assembly of claim 7, wherein the first doped semiconductor material comprises p-type doped silicon, and the second doped semiconductor material comprises n-type doped silicon.

11. The integrated assembly of claim 10, wherein the first doped semiconductor material comprises boron-doped silicon, and wherein the second doped semiconductor material comprises phosphorus-doped silicon.

12. The integrated assembly of claim 1, wherein the bit line is located above and electrically coupled to the channel material pillar; wherein the bit line is also coupled to the conductive pillar; and wherein the logic circuit system comprises a sense amplifier circuit system.

13. The integrated assembly of claim 1, comprising a vertically stacked conductive layer above the memory region and the other region; and wherein the channel material pillars and the pillars extend through the vertically stacked conductive layer.

14. The integrated assembly of claim 13, wherein the upper conductive layer of the vertically stacked conductive layers is a memory cell layer, and wherein the lower conductive layer of the vertically stacked conductive layers is a selection device layer.

15. The integrated assembly of claim 13, wherein the conductive layer comprises a metal.

16. The integrated assembly of claim 15, wherein the conductive layers are spaced apart from each other by intervening layers comprising insulating material.

17. An integrated assembly comprising: A first memory region, a second memory region offset from the first memory region, and an intermediate region located between the first memory region and the second memory region; the intermediate region has a first edge adjacent to the first memory region and a second edge adjacent to the second memory region; A first channel material column is arranged within the first memory region; A second channel material column is arranged within the second memory region; Conductive pillars are arranged within the intermediate region; A panel extending across the first memory region, the intermediate region, and the second memory region; the panel is laterally positioned between the first memory block region and the second memory block region, wherein the first memory block region and the second memory block region are within the first memory region and the second memory region; and A doped semiconductor material is located within the intermediate region and configured as a generally H-shaped structure having a first foot region along the first edge, a second foot region along the second edge, and a strip region adjacent to the panel. The doped semiconductor material is resistant to one or more etchants.

18. The integrated assembly of claim 17, wherein the strip region comprises a first segment on one side of the panel and a second segment on the opposite side of the panel.

19. The integrated assembly of claim 17, wherein the strip region is located below the panel.

20. The integrated assembly of claim 17, wherein the doped semiconductor material comprises silicon.

21. The integrated assembly of claim 20, wherein the doped semiconductor material comprises a dopant, the dopant comprising one or more of carbon, phosphorus, arsenic, boron, nitrogen, oxygen and gallium.

22. The integrated assembly of claim 21, wherein the dopant is at a concentration of 10 15 From atoms per cubic centimeter to 10 25 It exists at concentrations in the range of atoms per cubic centimeter.

23. The integrated assembly of claim 21, wherein the dopant is at a concentration of 10 18 From atoms per cubic centimeter to 10 22 It exists at concentrations in the range of atoms per cubic centimeter.

24. The integrated assembly of claim 17, wherein the doped semiconductor material comprises boron-doped silicon, wherein the boron is in a state from 10 18 From atoms per cubic centimeter to 10 22 It exists at concentrations in the range of atoms per cubic centimeter.

25. The integrated assembly of claim 17, wherein each of the conductive pillars has a lower region laterally surrounded by a ring comprising silicon dioxide.

26. The integrated assembly of claim 25, wherein the ring is an outer ring and laterally surrounds an inner ring comprising a semiconductor material.

27. The integrated assembly of claim 26, wherein the semiconductor material comprises silicon.

28. The integrated assembly according to claim 17, comprising: The source structure is electrically coupled to the lower region of the first channel material pillar; and A CMOS circuit system located below and electrically coupled to the conductive pillar.

29. The integrated assembly of claim 28, wherein the source structure comprises a vertically stacked layer of doped semiconductor material.

30. The integrated assembly of claim 29, comprising an insulating material interlayer between the vertically stacked layers of doped semiconductor material.

31. The integrated assembly of claim 17, wherein the component is operatively adjacent to the channel material pillar and also coupled to the conductive pillar, and wherein the conductive pillar is electrically coupled to a logic circuit system.

32. The integrated assembly of claim 31, wherein the component is a bit line, and wherein the logic circuitry includes a sense amplifier circuitry.

33. A method for forming an integrated assembly, comprising: A configuration is formed comprising a first memory region, a second memory region laterally offset from the first memory region, and an intermediate region laterally located between the first memory region and the second memory region; the configuration comprises a first stack extending across the first memory region, the second memory region, and the intermediate region; the first stack comprises alternating semiconductor-containing regions and intermediate regions; The configuration includes at least three of the semiconductor-containing regions, wherein one of the semiconductor-containing regions is a central semiconductor-containing region and is vertically positioned between the other two semiconductor-containing regions; the configuration further includes a second stack extending across the first memory region, the second memory region, and the intermediate region, wherein the second stack is positioned above the first stack; the second stack includes alternating first and second levels, wherein the first level includes a sacrificial material and the second level includes an insulating material; the intermediate region has a first edge adjacent to the first memory region and a second edge adjacent to the second memory region; the central semiconductor-containing region has a relatively doped portion and a relatively undoped portion; the relatively undoped portion is located within the memory region and the intermediate region; the relatively doped portion is located only within the intermediate region and is configured as a generally H-shaped structure having a first foot region along the first edge, a second foot region along the second edge, and a strip region extending from the first foot region to the second foot region; A pillar is formed that extends through the first memory region and the second memory region and at least partially enters the first stack of the first memory region and the second memory region, the pillar comprising cell material and channel material; Form pillars that extend through the second stack in the intermediate zone and into the first stack in the intermediate zone; A slit opening is formed that passes through the second stack and reaches the central semiconductor material region of the first stack; The slit opening extends across the first memory region, the intermediate region, and the second memory region, and is located above and along the strip region; The central semiconductor-containing region is removed from the first and second memory regions by one or more etchants flowing into the slit opening, wherein the relatively doped portion of the central semiconductor-containing region is resistant to the one or more etchants; the removal of the central semiconductor-containing region forms a conduit in the first stack within the first and second memory regions. The conduit extends through the unit material and reaches the channel material of the column; Doped semiconductor material is formed within the extended conduit; The dopant diffuses outward from the doped semiconductor material into the channel material, and the outwardly diffused dopant extends upward to at least one of the first layers; and At least some of the sacrificial materials in the first layer are replaced with conductive materials.

34. The method of claim 33, further comprising forming a panel within the slit opening and forming memory cells along the first layer within the first memory region and the second memory region, wherein the memory cells include regions of the channel material; wherein the memory cells are subdivided within the first memory block region and the second memory block region; and wherein the panel is located between the first memory block region and the second memory block region.

35. The method of claim 33, further comprising forming the source selection device to include at least one of the first layers.

36. The method of claim 33, wherein the central semiconductor material region comprises silicon, and wherein the relatively doped portion of the central semiconductor material region comprises a dopant, the dopant comprising one or more of carbon, phosphorus, arsenic, boron, nitrogen, oxygen and gallium.

37. The method of claim 36, wherein the dopant is used in a process from 10 18 From atoms per cubic centimeter to 10 22 It exists at concentrations in the range of atoms per cubic centimeter.

38. The method of claim 37, wherein the relatively undoped portion of the central semiconductor material region includes a concentration of less than or equal to 10. 16 Any dopant per atom per cubic centimeter.

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