Power supply switching circuit and power supply switching method

Abstract

A power switching circuit includes a first switching circuit, a second switching circuit, a control circuit and a driving circuit. The first switching circuit is configured to receive a first power voltage and coupled to an output terminal. The first switching circuit includes a first P-type transistor and a second P-type transistor coupled in series. The second switching circuit is configured to receive a second power voltage and coupled to the output terminal. The second switching circuit includes a third P-type transistor and a fourth P-type transistor coupled in series. The control circuit is configured to generate a control signal according to one of the first power voltage and the second power voltage, an output voltage of the output terminal and a power state signal. The driving circuit is configured to generate a first driving signal or a second driving signal according to the control signal to control the first switching circuit or the second switching circuit.

Description

TECHNICAL FIELD

[0001] Embodiments described in the present disclosure relate to a power switching technique, and in particular, to a power switching circuit and a power switching method. BACKGROUND

[0002] With the development of technology, the requirement of power saving or power consumption of electronic devices is getting higher and higher. Generally, a power switching circuit can be arranged between an electronic device and a power management chip to achieve the requirement of power saving or low power consumption. However, in some related technologies, the power switching circuit needs to additionally arrange a charge pump circuit and is prone to have a leakage problem. SUMMARY

[0003] Some embodiments of the present disclosure relate to a power switching circuit. The power switching circuit includes a first switching circuit, a second switching circuit, a control circuit, and a driving circuit. The first switching circuit is configured to receive a first power voltage and is coupled to an output terminal. The first switching circuit includes a first P-type transistor and a second P-type transistor coupled in series. The second switching circuit is configured to receive a second power voltage and is coupled to the output terminal. The second switching circuit includes a third P-type transistor and a fourth P-type transistor coupled in series. The control circuit is configured to generate a control signal according to one of the first power voltage and the second power voltage, an output voltage of the output terminal, and a power state signal. The driving circuit is configured to generate a first driving signal or a second driving signal according to the control signal to control the first switching circuit or the second switching circuit.

[0004] Some embodiments of the present disclosure relate to a power switching method. The power switching method includes: receiving, by a first switching circuit, a first power voltage, wherein the first switching circuit includes a first P-type transistor and a second P-type transistor coupled in series; receiving, by a second switching circuit, a second power voltage, wherein the second switching circuit includes a third P-type transistor and a fourth P-type transistor coupled in series; generating, by a control circuit, a control signal according to one of the first power voltage and the second power voltage, an output voltage of an output terminal, and a power state signal; and generating, by a driving circuit, a first driving signal or a second driving signal according to the control signal to control the first switching circuit or the second switching circuit.

[0005] In summary, the power switching circuit and the power switching method of the present disclosure do not need to additionally arrange a high-voltage driving circuit (for example, a charge pump circuit) or a high-voltage process (for example, a lateral double-diffusion metal-oxide semiconductor field effect transistor process), and can avoid the leakage paths that can be formed by various VCONN power supply devices under different use conditions. BRIEF DESCRIPTION OF DRAWINGS

[0006] In order to make the above and other purposes, features, advantages and embodiments of the present disclosure more obvious and easy to understand, the following describes the drawings:

[0007] Figure 1 These are schematic diagrams of electronic systems illustrated in accordance with some embodiments of the present disclosure;

[0008] Figure 2 These are circuit diagrams of power switching circuits illustrated according to some embodiments of the present disclosure; and

[0009] Figure 3 This is a flowchart illustrating a power switching method according to some embodiments of the present disclosure. Detailed Implementation

[0010] The term "coupled" as used in this article can also refer to "electrical coupling," and the term "connection" can also refer to "electrical connection." "Coupled" and "connection" can also refer to the cooperation or interaction of two or more components.

[0011] refer to Figure 1 . Figure 1 This is a schematic diagram of an electronic system S illustrated according to some embodiments of the present disclosure. Figure 1 For example, the electronic system S includes an electronic device D1, an audio adapter D2, and an audio playback device D3.

[0012] In some embodiments, the electronic device D1 may be a smartphone, laptop computer, tablet computer, or other electronic device that can provide audio data. The audio adapter D2 may be a dongle. The audio playback device D3 may be headphones, a speaker, or other playback device with audio playback functionality.

[0013] The above-described implementations of electronic device D1, audio adapter D2, and audio playback device D3 are for illustrative purposes only, and all implementations of electronic device D1, audio adapter D2, and audio playback device D3 are within the scope of this disclosure.

[0014] Audio adapter D2 can be coupled between electronic device D1 and audio playback device D3. Figure 1 For example, electronic device D1 includes connector P1. Audio adapter D2 includes connector T1 and connector P2. Audio playback device D3 includes connector T2. Connector T1 corresponds to connector P1. For example, connector P1 is a female connector conforming to the Universal Serial Bus (USB) Type-C standard, and connector T1 is a male connector conforming to the USB Type-C standard, and connector T1 can be inserted into connector P1. Connector T2 corresponds to connector P2. For example, connector P2 is a headphone jack, connector T2 is a headphone plug, and connector T2 can be inserted into connector P2.

[0015] The implementations of the connection portions T1-T2 and P1-P2 are merely for illustrative purposes, and various implementations of the connection portions T1-T2 and P1-P2 are within the scope of the present disclosure.

[0016] In operation, the electronic device D1 can couple the audio adapter D2 through the connection portion P1 and the connection portion T1 to provide the audio data AD and the power supply voltages VIN1-VIN2 to the audio adapter D2. For example, a battery BT in the electronic device D1 can provide a voltage, which is boosted by a boost circuit to generate the power supply voltage VIN1 or the power supply voltage VIN2, and the power supply voltage VIN1 or the power supply voltage VIN2 is transmitted to the audio adapter D2 through the connection portion P1 and the connection portion T1. In some embodiments, the power supply voltage VIN2 is less than or equal to the power supply voltage VIN1. For example, the power supply voltage VIN1 can be 5 volts, and the power supply voltage VIN2 can be 3.6-5 volts.

[0017] The values of the power supply voltages VIN1-VIN2 are merely for illustrative purposes, and various values of the power supply voltages VIN1-VIN2 are within the scope of the present disclosure.

[0018] In some embodiments, the audio adapter D2 includes a power supply switching circuit 200 and a functional circuit 300. The power supply switching circuit 200 can receive the power supply voltage VIN1 or the power supply voltage VIN2 and provide an output voltage (e.g., the output voltage VOUT in Figure 2 The functional circuit 300 can be, for example, a step-down conversion circuit, a voice codec, an analog-to-digital circuit, a digital-to-analog circuit, or other various circuits. In addition, the audio adapter D2 can provide a supply voltage VS to the audio playback device D3. In some embodiments, in addition to the supply voltage VS, the audio adapter D2 also generates an audio signal AS from the audio data AD from the electronic device D1 and outputs the audio signal AS to the audio playback device D3.

[0019] In some embodiments, the audio adapter D2 can also be integrated into the audio playback device D3 to form a single electronic device.

[0020] The implementations of the functional circuit 300 are merely for illustrative purposes, and various implementations of the functional circuit 300 are within the scope of the present disclosure.

[0021] Reference is made to Figure 2 . Figure 2 is a circuit diagram of the power supply switching circuit 200 according to some embodiments of the present disclosure. In Figure 2For example, the power switching circuit 200 includes a switching circuit 202, a switching circuit 204, a control circuit 206, a driving circuit 208, and a discharging circuit 210.

[0022] The switching circuit 202 can receive a power voltage VIN1. For example, the switching circuit 202 can receive the power voltage VIN1 from a power supply (not shown). Figure 2 For example, the switching circuit 202 includes P-type transistors M1-M2 coupled in series. The P-type transistor M1 includes a body diode BD1. The P-type transistor M2 includes a body diode BD2. A first end of the P-type transistor M1 is coupled to an input terminal IN1 to receive the power voltage VIN1. A first end of the P-type transistor M2 is coupled to an output terminal OUT. A second end of the P-type transistor M1, a second end of the P-type transistor M2, a cathode end of the body diode BD1, and a cathode end of the body diode BD2 are coupled to a node N1. The body diode BD1 and the body diode BD2 form a face-to-face structure. A voltage VNW at the node N1 is established in accordance with the power voltage VIN1.

[0023] Similarly, the switching circuit 204 can receive a power voltage VIN2. For example, the switching circuit 204 can receive the power voltage VIN2 from a power supply (not shown). Figure 2 For example, the switching circuit 204 includes a resistor Rg and P-type transistors M3-M4 coupled in series. The P-type transistor M3 includes a body diode BD3. The P-type transistor M4 includes a body diode BD4. A first end of the P-type transistor M3 is coupled to an input terminal IN2 to receive the power voltage VIN2. A first end of the P-type transistor M4 is coupled to the output terminal OUT. A second end of the P-type transistor M3, a second end of the P-type transistor M4, a cathode end of the body diode BD3, and a cathode end of the body diode BD4 are coupled to a node N2. The resistor Rg is coupled between the node N2 and a node N3. The body diode BD3 and the body diode BD4 also form a face-to-face structure.

[0024] The control circuit 206 can generate a control signal CT in accordance with one of the power voltage VIN1 and the power voltage VIN2, an output voltage VOUT, and a power status signal SHD. For example, the control circuit 206 can generate the control signal CT in accordance with the power voltage VIN1, the output voltage VOUT, and the power status signal SHD. Figure 2For example, the control circuit 206 includes a comparison circuit 2061, a logic circuit 2062, and switches S1-S2. A first terminal of the switch S1 can receive a power supply voltage VIN1, a second terminal of the switch S1 is coupled to a first input terminal (e.g., a negative input terminal) of the comparison circuit 2061, and a control terminal of the switch S1 can receive a power status signal SHD. A first terminal of the switch S2 can receive a power supply voltage VIN2, a second terminal of the switch S2 is coupled to a first input terminal (e.g., a negative input terminal) of the comparison circuit 2061, and a control terminal of the switch S2 can receive the power status signal SHD. In other words, the switches S1-S2 are controlled by the power status signal SHD. A second input terminal (e.g., a positive input terminal) of the comparison circuit 2061 can receive an output voltage VOUT. The comparison circuit 2061 can compare a signal at the first input terminal (the power supply voltage VIN1 or VIN2) with a signal at the second input terminal (the output voltage VOUT) to generate a comparison result CR. The logic circuit 2062 is coupled to an output terminal of the comparison circuit 2061 to receive the comparison result CR. The logic circuit 2062 can also receive the power status signal SHD to generate a control signal CT according to the comparison result CR and the power status signal SHD.

[0025] The drive circuit 208 can generate drive signals DS1-DS2 according to the control signal CT to control the switch circuit 202 or the switch circuit 204, respectively. For example, the drive circuit 208 can generate the drive signal DS1 according to the control signal CT to control the switch circuit 202, and the drive circuit 208 can generate the drive signal DS2 according to the control signal CT to control the switch circuit 204. Figure 2 For example, the drive circuit 208 includes a driver 2081 and a driver 2082.

[0026] The driver 2081 includes switches S3-S4 and a transistor M5. The driver 2081 is coupled between the control circuit 206 and the switch circuit 202. Specifically, the driver 2081 is coupled to the logic circuit 2062, a control terminal of the P-type transistor M1, and a control terminal of the P-type transistor M2. The driver 2081 can receive the control signal CT from the logic circuit 2062 and generate the drive signal DS1 according to the control signal CT to control the P-type transistor M1 and the P-type transistor M2.

[0027] The driver 2082 includes a switch S5. The driver 2082 is coupled between the control circuit 206 and the switch circuit 204. Specifically, the driver 2082 is coupled to the logic circuit 2062 and coupled to the resistance Rg, a control terminal of the P-type transistor M3, and a control terminal of the P-type transistor M4 at a node N3. The driver 2082 can receive the control signal CT from the logic circuit 2062 and generate the drive signal DS2 according to the control signal CT to control the P-type transistor M3 and the P-type transistor M4.

[0028] The discharge circuit 210 can discharge the output voltage VOUT. For example, the discharge circuit 210 can include a resistor Rdis and a switch S6. The resistor Rdis is coupled between the node N1 and the node N2. The switch S6 is coupled between the node N1 and a ground. The switch S6 can be controlled by a discharge signal SD. When the switch S6 is turned on, the output voltage VOUT can be discharged through the resistor Rdis and the switch S6. Figure 2For example, the discharging circuit 210 includes a resistor Rl and a switch S6. The resistor Rl and the switch S6 are coupled in series between the output terminal OUT and the ground terminal GND.

[0029] In operation, the electronic device Dl first provides the power supply voltage VINl to the power switching circuit 200 in the audio adapter D2. Based on the power supply voltage VINl at the input terminal INl, the voltage VNW is established. For example, the voltage VNW is equal to the difference between the power supply voltage VINl and the on voltage of the P-type transistor Ml. At this time, since the power supply voltage VINl is detected, the power status signal SHD has a first logic value (e.g., logic value 0). Based on the power status signal SHD having the first logic value, the switch SI is on and the switch S2 is off. The comparison circuit 2061 compares the power supply voltage VINl and the output voltage VOUT. Since the power supply voltage VINl is just supplied, the output voltage VOUT is less than the power supply voltage VINl and the difference between the output voltage VOUT and the power supply voltage VINl is large. The comparison result CR outputted by the comparison circuit 2061 (e.g., an operational amplifier) can reflect the difference between the output voltage VOUT and the power supply voltage VINl. The logic circuit 2062 outputs the control signal CT according to the comparison result CR and the power status signal SHD. The driver 2081 outputs the drive signal DS1 according to the control signal CT under the condition that the difference between the output voltage VOUT and the power supply voltage VINl is large (e.g., greater than a first threshold). For example, based on the control signal CT and the power status signal SHD, the switch S3 is off and the switch S4 is on. Since the switch S4 is on, the drive signal DS1 is generated at the control terminal of the transistor M5 to control the on degree of the P-type transistors Ml-M2 to be small (e.g., a first state), thereby avoiding the charging current being too large. In this way, the power supply voltage VINl can charge the output terminal OUT through the P-type transistors Ml-M2 with a small on degree and in a current-limiting manner.

[0030] After a period of time, the output voltage VOUT at the output terminal OUT is charged to a higher voltage level such that the difference between the output voltage VOUT and the supply voltage VIN1 is small. The driver 2081 outputs the drive signal DS1 according to the control signal CT obtained when the difference between the output voltage VOUT and the supply voltage VIN1 is small (e.g., equal to or less than the first threshold). For example, based on the control signal CT, the switch S3 is turned on. At this time, the driver 2081 can output the drive signal DS1 according to the potential of the ground terminal GND to control the on-state of the P-type transistors M1-M2 to be large (e.g., the second state) (the on-state of the second state is larger than the on-state of the first state). In this way, the supply voltage VIN1 can charge the output terminal OUT through the P-type transistors M1-M2 with a large on-state (non-current limiting state). Since the difference between the output voltage VOUT and the supply voltage VIN1 is small, the charging current for charging the output terminal OUT through the P-type transistors M1-M2 with a large on-state (non-current limiting state) is also not too large. In addition, when the on-state of the P-type transistors M1-M2 is large, the on-resistance (Ron) can be small.

[0031] The above is the relevant work of the first stage (slow start procedure) of the output voltage VOUT.

[0032] Next, the electronic device Dl provides the power supply voltage VIN2 to the power supply switching circuit 200 in the audio switching device D2. Since the power supply voltage VIN2 can be detected, the power supply status signal SHD has a second logic value (e.g., logic value 1). The switch S6 can be turned on according to the power supply status signal SHD having the second logic value, so that the output terminal OUT is discharged through the resistor Rl and the ground terminal GND of the switch S6. In addition, based on the power supply status signal SHD having the second logic value, the switch Sl is turned off and the switch S2 is turned on. The comparison circuit 2061 compares the power supply voltage VIN2 and the output voltage VOUT. Since the output terminal OUT was charged according to the voltage higher power supply voltage VINl previously and the output terminal OUT was just discharged, the difference between the output voltage VOUT and the power supply voltage VIN2 is large. The comparison result CR outputted by the comparison circuit 2061 (e.g., an operational amplifier) can reflect the difference between the output voltage VOUT and the power supply voltage VIN2. The logic circuit 2062 outputs the control signal CT according to the comparison result CR and the power supply status signal SHD. The driver 2082 outputs the drive signal DS2 according to the control signal CT in the case that the difference between the output voltage VOUT and the power supply voltage VIN2 is large (e.g., greater than a second threshold value). For example, based on the control signal CT, the switch S5 is turned off. At this time, the driver 2082 can generate the drive signal DS2 to directly turn off (e.g., the third state) the P-type transistors M3-M4, thereby avoiding the output voltage VOUT from causing a large current to flow back to the power supply voltage VIN2. In this stage, the output voltage VOUT is discharged through the switch S6 first, and until the output voltage VOUT is discharged to be close to the power supply voltage VIN2, the P-type transistors M3-M4 are turned on.

[0033] Specifically, when a period of time elapses, the output voltage VOUT of the output terminal OUT is discharged to be close to the power supply voltage VIN2. That is, the driver 2082 outputs the drive signal DS2 according to the control signal CT in the case that the difference between the output voltage VOUT and the power supply voltage VIN2 is small (e.g., equal to or less than a second threshold value). For example, based on the control signal CT, the switch S5 is turned on. At this time, the driver 2082 can output the drive signal DS2 according to the potential of the ground terminal GND to turn on (e.g., the fourth state) the P-type transistors M3-M4 (the turn-on degree of the fourth state is greater than that of the third state described above). The power supply voltage VIN2 can supply power to the output terminal OUT through the P-type transistors M3-M4 having a large turn-on degree (non-current limiting state). Since the difference between the output voltage VOUT and the power supply voltage VIN2 is small, even if the turn-on degree of the P-type transistors M3-M4 is controlled to be large, the (instantaneous) charging current can be prevented from being too large. In addition, when the turn-on degree of the P-type transistors M3-M4 is large, the on-resistance (Ron) can be small.

[0034] The above is the related operation of the second stage (turning into the power saving mode) of the output voltage VOUT. Since the power supply voltage VIN2 is less than the power supply voltage VIN1, in some embodiments, in order to achieve the power saving and the effect of reducing the power consumption, the last stage (the second stage) is powered by the power supply voltage VIN2.

[0035] Some power switching circuits in the related art use N-type transistors as the switching circuits. In these related arts, since the N-type transistors are turned on by high voltage, an additional high voltage driving circuit (for example, a charge pump circuit) needs to be set and a high voltage process needs to be used. The high voltage process is, for example, a lateral double-diffused metal-oxide-semiconductor (LDMOS) process. In addition, these related arts are prone to have a leakage problem. Furthermore, some related arts need to configure an additional enable signal and a circuit related to the enable signal.

[0036] Compared with the above related art, the power switching circuit 200 of the present disclosure uses P-type transistors as the switching circuits 202 and 204. Since the P-type transistors are turned on by low voltage, an additional high voltage driving circuit (for example, a charge pump circuit) or a high voltage process is not needed, and the leakage path that may be formed by the VCONN-powered device (VPD) complying with the Universal Serial Bus Type-C standard under different use conditions can be avoided. In addition, since the body diode BD1 and the body diode BD2 form a face-to-face structure and the conduction degree of the P-type transistors M1-M2 can be controlled by the driving signal DS1, the leakage between the output terminal OUT and the power supply voltage VIN1 can be avoided. Similarly, since the body diode BD3 and the body diode BD4 form a face-to-face structure and the conduction degree of the P-type transistors M3-M4 can be controlled by the driving signal DS2, the leakage between the output terminal OUT and the power supply voltage VIN2 can be avoided. Furthermore, the power switching circuit 200 of the present disclosure does not need to be controlled by an additional enable signal, so the power switching circuit 200 of the present disclosure does not need to set a circuit related to the enable signal, which can reduce the circuit area, the circuit power consumption, and the cost.

[0037] As mentioned earlier, to achieve power saving and reduced power consumption, the final stage (second stage) is powered by the power supply voltage VIN2. Depending on the application, the power supply voltage VIN1 may be in a normal power supply state (continuing to provide 5 volts), a floating state, or a grounded state in the final stage. However, since the body diodes BD1 and BD2 form a face-to-face structure and the conduction level of the P-type transistors M1-M2 can be controlled by the drive signal DS1, leakage current between the output terminal OUT and the power supply voltage VIN1 can be avoided regardless of the state of the power supply voltage VIN1 in the final stage, thus preventing abnormal circuit operation.

[0038] Furthermore, compared to the aforementioned related technologies, the power switching circuit 200 disclosed herein has lower static power consumption under steady-state conditions (e.g., less than 5 microamps), thus achieving power saving.

[0039] In some other embodiments, if the power supply voltage VIN2 is supplied to the power switching circuit 200 at an earlier time than the first stage described above, the voltage at node N3 can be quickly pulled up by the P-type transistor M3 and resistor Rg, causing the P-type transistors M3-M4 to turn off. The resistance value of resistor Rg can be designed according to the requirements of this response time (e.g., time constant). In some embodiments, resistor Rg can prevent excessive current consumption of driver 2082 to ground GND when P-type transistors M3-M4 are fully turned on. In addition, since body diodes BD3 and BD4 form a face-to-face structure and the conduction degree of P-type transistors M3-M4 can be controlled by drive signal DS2, leakage between the output terminal OUT and the power supply voltage VIN2 can be avoided. That is to say, the power switching circuit 200 of this disclosure is applicable not only to the example where the power supply voltage VIN1 is supplied first, but also to the example where the power supply voltage VIN2 is supplied first.

[0040] refer to Figure 3 . Figure 3 This is a flowchart illustrating a power switching method 3000 according to some embodiments of the present disclosure. The power switching method 3000 includes operations S320, S340, S360, and S380.

[0041] In some embodiments, the power switching method 3000 is applied to Figure 2 The power switching circuit 200 is used, but this disclosure is not limited thereto. For ease of understanding, the power switching method 3000 will be paired with... Figure 2 The power switching circuit 200 will be discussed.

[0042] In operation S320, the power supply voltage VIN1 is received by the switching circuit 202. Figure 2For example, the switch circuit 202 includes P-type transistors M1-M2 coupled in series, and body diode BD1 and body diode BD2 form a face-to-face structure.

[0043] In operation S340, the power supply voltage VIN2 is received by the switch circuit 204. In Figure 2 For example, the switch circuit 204 includes P-type transistors M3-M4 coupled in series, and body diode BD3 and body diode BD4 form a face-to-face structure.

[0044] In operation S360, the control signal CT is generated by the control circuit 206 according to one of the power supply voltages VIN1-VIN2, the output voltage VOUT of the output terminal OUT, and the power supply state signal SHD. In some embodiments, the power supply state signal SHD has a first logic value when the power supply voltage VIN1 is detected. The power supply state signal SHD has a second logic value when the power supply voltage VIN2 is detected. The comparison circuit 2061 of the control circuit 206 compares one of the power supply voltages VIN1-VIN2 and the output voltage VOUT according to the power supply state signal SHD to generate a comparison result CR. The logic circuit 2062 of the control circuit 206 generates the control signal CT according to the comparison result CR and the power supply state signal SHD.

[0045] In operation S380, the drive signal DS1 or the drive signal DS2 is generated by the drive circuit 208 according to the control signal CT to control the switch circuit 202 or the switch circuit 204. In some embodiments, the driver 2081 of the drive circuit 208 generates the drive signal DS1 according to the control signal CT to control the P-type transistors M1-M2. The driver 2082 of the drive circuit 208 generates the drive signal DS2 according to the control signal CT to control the P-type transistors M3-M4.

[0046] In summary, the power supply switching circuit and the power supply switching method of the present disclosure do not require an additional high-voltage drive circuit (e.g., a charge pump circuit) and can avoid leakage or do not require a high-voltage process (e.g., a lateral double-diffused metal oxide semiconductor field effect transistor process), and can avoid leakage paths that can be formed by various VCONN power supply devices under different use conditions.

[0047] Various functional means and blocks have been described herein. For those skilled in the art, the functional blocks can be implemented by circuitry (whether special or general purpose circuitry operating under control of computer software or otherwise), which generally comprises transistors or other similar circuit components that operate in a manner that is consistent with the functionality and operations described herein. Further, it is understood by those skilled in the art that the specific configuration and interconnection of the circuit components can be determined by a compiler, such as a Register Transfer Language (RTL) compiler. The RTL compiler operates on a script that is similar to assembly language code to compile the script into a form that is used to layout or otherwise create the final circuit.

[0048] Although the present disclosure has been disclosed in terms of embodiments thereof, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure. It is therefore intended that such changes and modifications be included within the scope of the protection granted to the present disclosure as set forth in the claims below.

[0049] SYMBOL DESCRIPTION

[0050] 200: power switching circuit

[0051] 202, 204: switching circuit

[0052] 206: control circuit

[0053] 2061: comparison circuit

[0054] 2062: logic circuit

[0055] 208: drive circuit

[0056] 2081, 2082: driver

[0057] 210: discharge circuit

[0058] 300: functional circuit

[0059] 3000: power switching method

[0060] S: electronic system

[0061] D1: electronic device

[0062] D2: audio switching device

[0063] D3: audio playback device

[0064] BT: battery

[0065] VIN1, VIN2: power supply voltage

[0066] P1, P2, T1, T2: connection portion

[0067] VS: supply voltage

[0068] AD: audio data

[0069] AS: audio signal

[0070] VOUT: output voltage

[0071] IN1, IN2: input terminal

[0072] OUT: output terminal

[0073] M1, M2, M3, M4, M5: transistor

[0074] BD1, BD2, BD3, BD4: body diode

[0075] N1, N2, N3: node

[0076] VNW: voltage

[0077] Rg, R1: resistance

[0078] S1, S2, S3, S4, S5, S6: switch

[0079] CR: comparison result

[0080] SHD: power state signal

[0081] CT: control signal

[0082] DS1, DS2: drive signal

[0083] GND: ground terminal

[0084] S320, S340, S360, S380: operation

Claims

1. A power switching circuit, comprising: a first switching circuit for receiving a first supply voltage and coupled to an output terminal, wherein the first switching circuit comprises a first P-type transistor and a second P-type transistor coupled in series, wherein a body diode of the first P-type transistor, a body diode of the second P-type transistor, one end of the first P-type transistor and one end of the second P-type transistor are coupled to a first node, and a voltage of the first node is established according to the first supply voltage; a second switching circuit for receiving a second supply voltage and coupled to the output terminal, wherein the second switching circuit comprises a third P-type transistor and a fourth P-type transistor coupled in series; a control circuit for generating a control signal according to one of the first supply voltage and the second supply voltage, an output voltage of the output terminal and a power state signal; a driving circuit for generating a first driving signal or a second driving signal according to the control signal to control the first switching circuit or the second switching circuit.

2. The power switching circuit of claim 1, wherein a body diode of the third P-type transistor, a body diode of the fourth P-type transistor, one end of the third P-type transistor and one end of the fourth P-type transistor are coupled to a second node.

3. The power switching circuit of claim 2, further comprising: a resistor coupled between the second node and a third node, wherein a control terminal of the third P-type transistor and a control terminal of the fourth P-type transistor are coupled to the third node.

4. The power switching circuit of claim 1, wherein the control circuit comprises: a comparison circuit for comparing the first supply voltage or the second supply voltage with the output voltage to generate a comparison result; and a logic circuit for generating the control signal according to the comparison result and the power state signal.

5. The power switching circuit of claim 4, wherein the driving circuit comprises: a first driver coupled between the control circuit and the first switching circuit, wherein when the power state signal has a first logic value and the comparison result indicates that a difference between the first supply voltage and the output voltage is greater than a first threshold, the first driver outputs the first driving signal according to the control signal to drive the first P-type transistor and the second P-type transistor to a first state, wherein when the power state signal has the first logic value and the comparison result indicates that the difference between the first supply voltage and the output voltage is equal to or less than the first threshold, the first driver outputs the first driving signal according to the control signal to drive the first P-type transistor and the second P-type transistor to a second state, wherein a conduction degree of the second state is greater than a conduction degree of the first state.

6. The power switching circuit of claim 5, further comprising: a discharging circuit, wherein when the power state signal has a second logic value, the output terminal is discharged to a ground terminal through the discharging circuit.

7. The power switching circuit of claim 6, wherein the driving circuit further comprises: ​ a second driver coupled between the control circuit and the second switching circuit, wherein when the power status signal has the second logic value and the comparison result indicates that the difference between the output voltage and the second power supply voltage is greater than a second threshold, the second driver outputs the second driving signal according to the control signal to drive the third P-type transistor and the fourth P-type transistor to a third state, wherein when the power status signal has the second logic value and the comparison result indicates that the difference between the output voltage and the second power supply voltage is equal to or less than the second threshold, the second driver outputs the second driving signal according to the control signal to drive the third P-type transistor and the fourth P-type transistor to a fourth state, wherein the fourth state has a greater on-state degree than the third state.

8. The power switching circuit of claim 6, wherein the power status signal is changed from the first logic value to the second logic value when the second power supply voltage is detected.

9. A power switching method, comprising: receiving a first power supply voltage by a first switching circuit, wherein the first switching circuit comprises a first P-type transistor and a second P-type transistor coupled in series, wherein a body diode of the first P-type transistor, a body diode of the second P-type transistor, one end of the first P-type transistor, and one end of the second P-type transistor are coupled to a first node, and a voltage of the first node is established according to the first power supply voltage; receiving a second power supply voltage by a second switching circuit, wherein the second switching circuit comprises a third P-type transistor and a fourth P-type transistor coupled in series; generating a control signal by a control circuit according to one of the first power supply voltage and the second power supply voltage, an output voltage of an output terminal, and a power status signal; and generating a first driving signal or a second driving signal by a driving circuit according to the control signal to control the first switching circuit or the second switching circuit.

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