A bleeder circuit and a DC-DC converter

Abstract

The application provides a bleeder circuit and a DC-DC converter. The DC-DC converter comprises an input unit, an output unit, an output feedback unit, an error amplification unit and a bleeder circuit. A bleeder passage in the bleeder circuit is connected in parallel with the output unit and used for bleeding the output unit. The application provides a bleeder circuit and a DC-DC converter. When the working mode of the circuit is converted from PWM to PFM, the bleeder circuit is used for bleeding, and the stable time of the output current can be shortened.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit, in particular to a bleeder circuit and a DC-DC converter. BACKGROUND

[0002] DC-DC (Direct Current to Direct Current) is widely used in various electronic products as a power module, providing stable working voltage for its subsequent circuit and high efficiency. In order to improve efficiency, various working mode DC-DC circuits have emerged. The most commonly used are pulse width modulation mode (PWM) and pulse frequency modulation mode (PFM). The efficiencies of these two modes are different for light load and heavy load. In order to improve efficiency, the two modes are usually combined to make the circuit have high output efficiency in both heavy load and light load states. Therefore, there is a DC-DC circuit that contains both PWM and PFM modes. Such a DC-DC has good output efficiency in both light load and heavy load.

[0003] However, in the current DC-DC converter, when the working mode of the circuit changes from PWM to PFM, the output current instantaneously decreases due to the change from heavy load to light load mode, which cannot effectively stabilize the overshoot phenomenon formed during the conversion process. Therefore, it is necessary to provide a more effective and reliable technical solution to shorten the stabilization time. SUMMARY

[0004] The present application provides a bleeder circuit and a DC-DC converter, which can shorten the stabilization time of the output current when the working mode of the circuit changes from PWM to PFM.

[0005] One aspect of the present application provides a bleeder circuit, comprising: a control circuit, configured to output a control signal according to a PWM enable signal and a PFM enable signal; a pulse timing circuit, an input end of the pulse timing circuit being connected to an output end of the control circuit, configured to receive the control signal and output a switching signal; and a bleeder path, an input end of the bleeder path being connected to an output end of the pulse timing circuit, the switching signal being used to control switching of the bleeder path.

[0006] In some embodiments of the present application, the control circuit outputs an effective control signal according to the PFM enable signal, the pulse timing circuit receives the effective control signal, outputs an effective switching signal, and starts a timing signal, and the bleeder path is turned on.

[0007] In some embodiments of the present application, the pulse timing circuit further outputs a feedback signal after the timing of the timing signal is completed, the control circuit outputs an invalid control signal according to the feedback signal, the pulse timing circuit receives the invalid control signal and outputs an invalid switch signal, and the bleeder path is closed.

[0008] In some embodiments of the present application, the control circuit outputs an invalid control signal according to a PWM enable signal, the pulse timing circuit receives the invalid control signal and outputs an invalid switch signal, and the bleeder path is not opened.

[0009] In some embodiments of the present application, the pulse timing circuit comprises a plurality of timing modules, each of which receives a control signal and outputs a feedback signal, and part of the timing modules are further configured to output a switch signal.

[0010] In some embodiments of the present application, the plurality of timing modules are D flip-flops.

[0011] In some embodiments of the present application, the plurality of timing modules comprise twenty-fifth to thirty-fourth timing modules, each of which receives a control signal and outputs a feedback signal, and the thirty-fourth timing module is further configured to output a switch signal.

[0012] In some embodiments of the present application, the control circuit comprises first to twenty-fourth modules, wherein the first to third modules and the ninth to fifteenth modules are feedback units configured to receive the feedback signal.

[0013] In some embodiments of the present application, the first to twenty-fourth modules comprise NAND gates, NOR gates, and inverters.

[0014] In some embodiments of the present application, the input ends of the first to second modules and the ninth to twelfth modules are connected to the output ends of the twenty-fifth to thirty-fourth timing modules.

[0015] In some embodiments of the present application, the bleeder path comprises a resistor and an NMOS transistor, and the switch signal controls the switch of the NMOS transistor.

[0016] Another aspect of the present application provides a DC-DC converter, comprising an input unit, an output unit, an output feedback unit, an error amplification unit, and a bleeder circuit as described above; the bleeder path in the bleeder circuit is connected in parallel with the output unit to bleed the output unit.

[0017] In some embodiments of the present application, the DC-DC converter further comprises a comparison unit, a modulation unit, and a feedback circuit; one input terminal of the comparison unit is connected to an output terminal of the feedback circuit, and the other input terminal is connected to an output terminal of the error amplifier unit; an input terminal of the modulation unit is connected to an output terminal of the comparison unit, and an output terminal of the modulation unit is connected to the input unit; and an input terminal of the feedback circuit is connected to an output terminal of the input unit.

[0018] In some embodiments of the present application, the modulation mode of the modulation unit comprises a PWM mode and a PFM mode.

[0019] In some embodiments of the present application, the modulation unit is further connected to a control circuit in the bleeder circuit.

[0020] In some embodiments of the present application, the modulation mode is a PWM mode, and the modulation unit outputs a PWM enable signal to the control circuit.

[0021] In some embodiments of the present application, the modulation mode is a PFM mode, and the modulation unit outputs a PFM enable signal to the control circuit.

[0022] The present application provides a bleeder circuit and a DC-DC converter, when the working mode of the circuit is converted from PWM to PFM, the bleeder circuit is used for bleeder, which can shorten the stable time of the output current. BRIEF DESCRIPTION OF DRAWINGS

[0023] The following drawings in detail describe the exemplary embodiments disclosed in the present application. The same reference signs in the several views of the drawings represent similar structures. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other ways of embodiments can also achieve the same intention of the invention in the present application. It should be understood that the drawings are not drawn to scale.

[0024] wherein:

[0025] Figure 1 Fig. 1 is a schematic diagram of a DC-DC converter;

[0026] Figure 2 Fig. 2 is a circuit diagram of a control circuit of a bleeder circuit according to an embodiment of the present application;

[0027] Figure 3 Fig. 3 is a circuit diagram of a pulse timing circuit of a bleeder circuit according to an embodiment of the present application;

[0028] Figure 4 Fig. 4 is a circuit diagram of a bleeder path of a bleeder circuit according to an embodiment of the present application;

[0029] Figure 5 This is a schematic diagram of a DC-DC converter according to an embodiment of this application. Detailed Implementation

[0030] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0031] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0032] Figure 1 This is a schematic diagram of a DC-DC converter.

[0033] refer to Figure 1 The diagram shown is a current-mode DC-DC converter circuit. A current-mode DC-DC converter is a dual-loop system. Current flows from input 100 through inductor L1, then through output feedback unit 110 to output 120, from output feedback unit 110 to error amplifier 130, and from error amplifier 130 to comparator 140. After passing through modulation unit 150, it returns to input 100, forming an outer loop. The current feedback module 160, comparator 140, modulation unit 150, and input 100 together form the inner loop.

[0034] One characteristic of current-mode DC-DC converters is their relatively fast speed. This is due to their dual-loop circuit structure, which allows the circuit to establish a stable connection more quickly. A traditional method to accelerate the establishment speed of a current-mode DC-DC converter is to adjust the loop bandwidth at the output of the error amplifier 130 by adjusting resistor R5, capacitor C4, and compensation capacitor C3, thus achieving a faster speed. Another method is to add capacitor C2 between the output terminal 120 and the output feedback unit 110. The function of capacitor C2 is to accelerate the DC-DC converter through the action of the feedforward zero.

[0035] With the increased speed of the DC-DC loop, the overshoot voltage is relatively small, only tens of millivolts, when the circuit's modulation unit switches from PWM mode to PFM mode. This significantly shortens the time required for the overshoot voltage to drop back down. However, despite the reduced overshoot voltage, the settling time is still very long when the load is only a few microamps. Alternatively, overvoltage protection can be used. When the overshoot voltage exceeds the rated output voltage, the circuit activates overvoltage protection to restore the output to normal. However, this method only works when the overshoot voltage is very large.

[0036] In some DC-DC converters, when the DC-DC output current changes from 50mA to the microamp level, and the set output is 4.2V, there may be an overshoot voltage of about 120mV. This is because the output current after the overshoot is at the microamp level, while the output capacitor is a large capacitor, ranging from tens to hundreds of microfarads. At this time, the discharge is very slow, and even after hundreds of microseconds, the change in output voltage is not obvious.

[0037] To address the aforementioned issues, this application provides a current-discharging circuit and a DC-DC converter. When the circuit's operating mode transitions from PWM to PFM, the current-discharging circuit discharges current, thereby shortening the stabilization time of the output current.

[0038] Embodiments of this application provide a leakage circuit, referencing Figures 2 to 4 It includes: a control circuit 210, used to output a control signal according to the PWM enable signal and the PFM enable signal; a pulse timing circuit 220, the input terminal of which is connected to the output terminal of the control circuit, used to receive the control signal and output a switch signal; and a leakage path 230, the input terminal of which is connected to the output terminal of the pulse timing circuit, the switch signal being used to control the switching of the leakage path.

[0039] The control circuit 210 can generate a control signal for the pulse timing circuit 220 based on the enable signals of the two input modes, so that the pulse timing circuit 220 generates a high-level signal that is maintained for a certain period of time (the specific time can be set according to actual needs, such as 512μs). This high-level signal is used to control the switching state of the leakage circuit 230.

[0040] Figure 2 This is a circuit diagram of the control circuit of the leakage circuit described in the embodiments of this application; Figure 3 This is a circuit diagram of the pulse timing circuit of the leakage circuit described in the embodiments of this application; Figure 4This is a circuit diagram of the leakage path of the leakage circuit described in the embodiments of this application. Since the leakage circuit described in this application has many components, it is not convenient to draw it in one diagram. For convenience, the leakage circuit is divided into three parts for description: a control circuit, a pulse timing circuit, and the leakage path. The connection relationship between these three parts will also be explained.

[0041] refer to Figure 2 As shown, the control circuit 210 outputs a control signal CTL based on the PWM enable signal PWM_EN and the PFM enable signal PFM_EN. The PWM enable signal and the PFM enable signal can originate from the DC-DC converter, and the control circuit 210 outputs the corresponding control signal according to the operating mode of the DC-DC converter. Specifically, when the PWM enable signal is valid (output high level), the control signal output is invalid (output low level), i.e., an invalid control signal; when the PFM enable signal is valid (output high level), the control signal output is valid (output high level), i.e., a valid control signal.

[0042] In some embodiments of this application, the control circuit 210 includes a first module 1 to a twenty-fourth module 24, wherein the first module 1 to the third module 3 and the ninth module 9 to the fifteenth module 15 are feedback units that receive the feedback signal; the sixteenth module 16 to the twenty-fourth module 24 are PFM enable signal receiving units that receive the PFM enable signal; the fourth module 4 and the fifth module 5 are PWM enable signal receiving units that receive the PWM enable signal; the sixth module 6 and the seventh module 7 are latch circuits; and the eighth module 8 is an output unit that outputs the control signal.

[0043] In some embodiments of this application, when the DC-DC converter operates in PWM mode (i.e., when the output is under heavy load), the control circuit 210 receives the PWM enable signal, the control circuit 210 outputs an invalid control signal according to the PWM enable signal, the pulse timing circuit 220 receives the invalid control signal and outputs an invalid switching signal, and the leakage path 230 is not opened.

[0044] Specifically, such as Figure 2As shown, one input terminal of the fourth module 4 is used to receive the PWM enable signal PWM_EN. The PWM enable signal is a pulse signal; that is, when a "1" signal is input to the fourth module 4, the fourth module 4 outputs a "0" signal. This "0" signal is inverted by the fifth module 5 and arrives at the latch circuit composed of the sixth module 6 and the seventh module 7. The output of the latch circuit is inverted by the eighth module 8 and outputs a control signal to the pulse timing circuit 220. The pulse timing circuit 220 does not output a switching signal, and the leakage path 230 is not opened. The latch circuit is a storage unit circuit that is sensitive to pulse levels; it can change its state under the action of a specific input pulse level.

[0045] The fourth module 4 can be a NOR gate. The fifth module 5 can be an inverter. The sixth module 6 and the seventh module 7 can be NOR gates. The eighth module 8 can be an inverter. An inverter can reverse the phase of an input signal by 180 degrees and is typically composed of multiple transistors and resistors. A NOR gate is a logic gate in digital logic that implements logical OR and NOT. If all inputs are low (0), the output is high (1); if at least one input is high (1), the output is low (0).

[0046] In some embodiments of this application, when the operating mode of the DC-DC converter is switched from PWM mode to PFM mode (that is, when the output is lightly loaded), the control circuit 210 receives the PFM enable signal PFM_EN. The control circuit 210 outputs a valid control signal according to the PFM enable signal. The pulse timing circuit 220 receives the valid control signal, outputs a valid switch signal SWITCH, and starts the timing signal (the specific timing time can be set according to actual needs, such as 512μs). The leakage path 230 is opened.

[0047] Specifically, such as Figure 2As shown, one input terminal of the sixteenth module 16 and one input terminal of the twenty-third module 23 are used to receive the PFM enable signal PFM_EN. Then, a narrow pulse signal is generated by the twenty-fourth module 24. This narrow pulse signal is another input to the latch circuit composed of the sixth module 6 and the seventh module 7. The output of the latch circuit, after being inverted by the eighth module 8, outputs a control signal CTL to the pulse timing circuit 220. The pulse timing circuit 220 outputs a switch signal SWITCH and starts the timing signal (e.g., timing 512μs). The highest bit output of the pulse timing circuit 220 then opens the leakage path 230. The PFM enable signal, after being input to the sixteenth module 16, can also pass through the seventeenth to twenty-second modules 22, generating a delay before entering the twenty-third module 23. In other embodiments, the sixteenth to twenty-second modules 16 may be omitted, or the number of these modules may be changed. The more modules there are, the higher the delay; the specific choice can be made according to needs.

[0048] Among them, the sixteenth module 16 to the twenty-second module 22 can be inverters or other devices used to achieve a delay effect, such as non-inverting buffers, NAND gates, NOR gates, and flip-flops, all of which can be used as delay units. However, inverters have a simple structure and are sufficient for most applications. The twenty-third module 23 can be a NAND gate. The twenty-fourth module 24 can be an inverter. A NAND gate is a basic logic circuit in digital circuits. If all inputs are high (1), the output is low (0); if at least one input is low (0), the output is high (1).

[0049] In some embodiments of this application, after the timing signal finishes timing (i.e., after the preset leakage time is reached), the pulse timing circuit 220 also outputs a feedback signal FEEDBACK, the control circuit 210 outputs a control signal according to the feedback signal, the pulse timing circuit 220 receives the control signal and outputs a switch signal, and the leakage path 230 is closed.

[0050] Specifically, refer to Figure 2As shown, the feedback unit, composed of modules 1 to 3 and modules 9 to 15, receives the 10-bit output of the pulse timing circuit 220 as its input, which is used to receive the feedback signal FEEDBACK. The function of this feedback unit is to output a signal when the timing is complete and the leakage ends, telling the pulse timing circuit 220 to stop working. This signal, along with the PWM enable signal, becomes the input of module 4. Module 4 is a NOR gate. When the timing circuit completes the timing, it inputs a "1" signal to its input terminal, at which point module 4 outputs a "0". This signal is inverted by module 5 and goes to the latch circuit composed of modules 6 and 7. The output of the latch circuit is inverted by module 8 and outputs a control signal to the pulse timing circuit 220. The pulse timing circuit 220 then outputs a switching signal to disconnect the leakage path 230. Specifically, the input terminals of modules 9 through 12 are connected to the feedback output terminal of the pulse timing circuit 220 (the specific connection method is described in detail below); the output terminals of modules 11 and 12 are connected to the input terminal of module 14, and the output terminal of module 14 is connected to the input terminal of module 15; the output terminals of modules 9 and 10 are connected to the input terminal of module 13, and the output terminal of module 13 is connected to the input terminal of module 15; the output terminal of module 15 is connected to the input terminal of module 3; the input terminal of module 2 is connected to the feedback output terminal of the pulse timing circuit 220 and the output terminal of module 1; the output terminal of module 2 is connected to the input terminal of module 3; the input terminal of module 1 is connected to the feedback output terminal of the pulse timing circuit 220; and the output terminal of module 3 is connected to the output terminal of module 4.

[0051] Wherein, the first module 1 can be an inverter; the second module 2 and the ninth to twelfth modules 12 can be NAND gates; the thirteenth module 13 and the fourteenth module 14 can be NOR gates; the fifteenth module 15 can be a NAND gate; and the third module 3 can be a NOR gate.

[0052] In some embodiments of this application, it should be noted that the appendix... Figure 2 The various modules or devices in the control circuit 210 shown are merely illustrative examples, and some simple, conventional wiring is not shown, such as the power supply line and ground line of each module or device.

[0053] refer to Figure 3The input terminal of the pulse timing circuit 220 is connected to the output terminal of the control circuit 210 (the output terminal of the eighth module 8), and is used to receive the control signal and output a switching signal. When the eighth module 8 outputs an invalid control signal, the pulse timing circuit 220 outputs an invalid switching signal, and the leakage path is closed; when the eighth module 8 outputs a valid control signal, the pulse timing circuit outputs a valid switching signal, opens the leakage path, and simultaneously starts the timing signal. The timing time is the opening time of the leakage path, which is the preset leakage time.

[0054] In some embodiments of this application, the pulse timing circuit 220 includes several timing modules for timing the switching signal output by the pulse timing circuit (or timing the leakage time). Each timing module can receive control signals and output feedback signals. Some timing modules are also used to output switching signals.

[0055] In some embodiments of this application, the timing modules are D flip-flops. A D flip-flop is an information storage device with memory function and two stable states. It is the most basic logic unit for constructing various sequential circuits and an important unit circuit in digital logic circuits.

[0056] In some embodiments of this application, the number of the plurality of timing modules is equal to the number of input terminals of the feedback unit in the control circuit. The number of the plurality of timing modules can also be set according to the required timing time (i.e., the required leakage time). The more timing modules there are, the longer the timing time can be.

[0057] In some embodiments of this application, the plurality of timing modules includes a 25th timing module 25 to a 34th timing module 34. Each timing module can receive a control signal (each timing module receives the control signal output by the 8th module 8) and output a feedback signal. The 34th timing module 34 is also used to output a switch signal. Each timing module may include at least three ports: a ground port, a power port, and a control signal input port. Figure 3 For the sake of brevity, only one port of each module is shown to illustrate the connection relationship between modules, omitting the ground port, power port, and some control signal input ports.

[0058] In some embodiments of this application, the feedback signals output by the 25th timing module 25 to the 34th timing module 34 are respectively labeled as FEEDBACK25 to FEEDBACK34.

[0059] In some embodiments of this application, the input terminals of the first module 1 to the second module 2 and the ninth module 9 to the twelfth module 12 are connected to the output terminals of the twenty-fifth timing module 25 to the thirty-fourth timing module 34. For example, the output terminals of the twenty-fifth timing module 25 and the twenty-sixth timing module 26 are respectively connected to the two input terminals of the twelfth module 12; the output terminals of the twenty-seventh timing module 27 and the twenty-eighth timing module 28 are respectively connected to the two input terminals of the eleventh module 11; the output terminals of the twenty-ninth timing module 29 and the thirtieth timing module 30 are respectively connected to the two input terminals of the tenth module 10; the output terminals of the thirty-first timing module 31 and the thirty-second timing module 32 are respectively connected to the two input terminals of the ninth module 9; the output terminal of the thirty-third timing module 33 is connected to one input terminal of the second module 2; and the output terminal of the thirty-fourth timing module 34 is also connected to the input terminal of the first module 1.

[0060] refer to Figure 4 The input terminal of the leakage path 230 is connected to the output terminal of the pulse timing circuit 220 (the output terminal of the thirty-fourth module 34), and the switch signal SWITCH is used to control the switching of the leakage path 230.

[0061] In some embodiments of this application, the leakage path 230 includes a resistor R7 and an NMOS transistor, and the switching signal controls the switching of the NMOS transistor.

[0062] The leakage circuit described in this application embodiment can switch the leakage circuit on and off according to the PWM enable signal and the PFM enable signal.

[0063] Embodiments of this application also provide a DC-DC converter, see reference. Figure 5 It includes: an input unit 300, an output unit 320, an output feedback unit 310, an error amplification unit 330, and a current leakage circuit as described above; the current leakage path 230 in the current leakage circuit is connected in parallel with the output unit 320 to leakage current from the output unit 320.

[0064] Figure 5 This is a schematic diagram of a DC-DC converter according to an embodiment of this application.

[0065] In some embodiments of this application, the DC-DC converter further includes: a comparison unit 340, a modulation unit 350, and a feedback circuit 360; one input terminal of the comparison unit 340 is connected to the output terminal of the feedback circuit 360, and the second input terminal is connected to the output terminal of the error amplification unit 330; the input terminal of the modulation unit 350 is connected to the output terminal of the comparison unit 340, and the output terminal of the modulation unit 350 is connected to the input unit 300; the input terminal of the feedback circuit 360 is connected to the output terminal of the input unit 300.

[0066] The current flows from the input unit 300 through inductor L1, then through the output feedback unit 310 to the output unit 320, from the output feedback unit 310 to the error amplification unit 330, and from the error amplification unit 330 to the comparator unit 340. It then passes through the modulation unit 350 back to the input unit 300, forming an outer loop. The feedback circuit 360, together with the comparator unit 340, the modulation unit 350, and the input unit 300, form the inner loop.

[0067] In some embodiments of this application, the modulation mode of the modulation unit 350 includes PWM mode and PFM mode. The modulation unit 350 can switch between PWM mode and PFM mode.

[0068] In some embodiments of this application, the modulation unit 350 is also connected to the control circuit 210 in the bleed circuit.

[0069] In some embodiments of this application, the modulation unit 350 is in PWM mode, and the modulation unit outputs a PWM enable signal to the control circuit.

[0070] In some embodiments of this application, the modulation unit is in PFM mode, and the modulation unit outputs a PFM enable signal to the control circuit.

[0071] When the modulation unit 350 of the DC-DC converter is in PWM mode, the output voltage always stabilizes quickly after an overshoot, regardless of how small the output current change. This is because in PWM mode, after an output overshoot, there is always a reverse path, allowing the overshoot charge to be released through this reverse path. However, a reverse path is not allowed in PFM mode. Therefore, if a signal is given to the bleeder circuit when the circuit enters PFM mode, and this signal establishes a bleeder path, the overshoot energy can be released more quickly.

[0072] Taking an overshoot voltage of 120mV as an example, when the output capacitor is 5uF, the total charge that needs to be discharged due to the overshoot is:

[0073] Q = V * C = 120 mV * 5 uF; (1)

[0074] If the current under light load is 10uA, then the time required for discharge is:

[0075] t=Q / I=120mV*5uF / 10uA=60ms; (2)

[0076] As can be seen from formulas (1) and (2), under light load conditions, it takes a long time to discharge the charge from the overshoot voltage. Taking a 5uF capacitor as an example, even if the overshoot voltage is only 50mV, the discharge time is still 25ms. If the capacitor is 100uF or larger, this time will be even longer.

[0077] In circuit engineering, the PWM enable signal and the PFM enable signal can be used to identify which mode the circuit is currently operating in. The PFM enable signal, in particular, remains active when the output is under light load until it becomes heavy load again. When the output enters a light load state and an overshoot occurs, the PWM enable signal turns to 0, and the PWM signal ceases to function. Simultaneously, the PFM enable signal goes high, activating PFM mode. If the rising edge of the PFM enable signal is used to create a brief bleed path to ground, the discharge time of the output overshoot will be significantly shortened.

[0078] From formula (2), it can be seen that when the output current reaches the milliampere level, the stabilization time will be greatly shortened. In some DC-DC circuits, the output below 3mA is considered a light load mode. However, the output current is affected by many factors. In order to ensure that the circuit does not mistakenly enter PWM mode in PFM mode, the maximum leakage current is defined as about 1.5mA. This is an approximate value, the purpose of which is to ensure that the working modes do not interfere with each other. Taking 1.5mA as an example, formula (2) becomes:

[0079] t=Q / I=120mV*5uF / 1.5mA=400μs; (3)

[0080] This section implements a circuit that provides a 512μs discharge time with a discharge current of 1.5mA. Considering that the current may decrease, it is necessary to leave sufficient margin in the discharge time. When the discharge current increases, because the circuit is still in light-load mode, it will not introduce a large overshoot during the transition between PWM mode and PFM mode.

[0081] In conventional DC-DC converters, when the circuit's operating mode transitions from PWM to PFM, the output current decreases instantaneously due to the shift to a light-load mode. This fails to effectively stabilize the overshoot phenomenon that occurs during the transition, often requiring a certain settling time. However, in the DC-DC converter described in this embodiment, a bleed circuit, including a control circuit 210, a pulse timing circuit 220, and a bleed path 230, is connected in parallel at the output.

[0082] When the DC-DC converter is in PWM mode, the control circuit 210 receives the PWM enable signal and outputs a control signal to keep the pulse timing circuit 220 off and the leakage path 230 closed. When the DC-DC converter switches from PWM mode to PFM mode, the control circuit 210 receives the PFM enable signal and outputs a control signal to start the pulse timing circuit 220 and open the leakage path 230 to discharge current to the output unit 320, shortening the output current stabilization time. After the discharge is completed (i.e., after the timing is completed), the pulse timing circuit 220 outputs a feedback signal to the control circuit 210. After receiving the feedback signal, the control circuit 210 outputs a control signal to stop the pulse timing circuit 220 from working and close the leakage path 230 to stop the discharge.

[0083] In some embodiments, when the output current changes from a heavy load of 50mA to a light load, the output of the switching power supply with the added bleeder circuit stabilizes completely after 414μs. The bleeder circuit effectively accelerates the stabilization time of the switching power supply output when changing from a heavy load to a light load.

[0084] During the transition between heavy and light loads in a DC-DC converter, PWM and PFM signals are used to discharge current at the output, and a pulse timing circuit controls the discharge time, ensuring rapid overshoot and stabilization of the output. Compared to accelerating the loop speed, this more effectively solves the problem of excessively long output stabilization time during heavy-load to light-load transitions. Compared to overcurrent protection circuits, the overshoot magnitude can be disregarded, and discharge can be uniformly applied throughout the heavy-load to light-load transition process. This effectively solves the problem of excessively long overshoot stabilization time during heavy-load to light-load transitions.

[0085] The current bleedering circuit and DC-DC converter described in this application can shorten the stabilization time of the output current by bleeding current through the current bleedering circuit when the circuit's operating mode changes from PWM to PFM.

[0086] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0087] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0088] It should also be understood that the terms “comprising,” “including,” “including,” or “comprise”, when used in this application, indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or groups thereof.

[0089] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0090] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, the areas shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the areas of the device, nor to limit the scope of the exemplary embodiments.

Claims

1. A current-bleeding circuit, characterized in that, include: The control circuit is used to output control signals based on the PWM enable signal and the PFM enable signal; A pulse timing circuit, the input terminal of which is connected to the output terminal of the control circuit, is used to receive the control signal and output a switching signal; A leakage circuit is provided, the input terminal of which is connected to the output terminal of the pulse timing circuit, and the switching signal is used to control the switching of the leakage circuit. The control circuit outputs a valid control signal based on the PFM enable signal. The pulse timing circuit receives the valid control signal, outputs a valid switch signal, and starts the timing signal. The leakage path is then opened. The control circuit outputs an invalid control signal based on the PWM enable signal, the pulse timing circuit receives the invalid control signal and outputs an invalid switching signal, and the leakage path is not opened.

2. The bleeder circuit as described in claim 1, characterized in that, After the timing signal finishes timing, the pulse timing circuit also outputs a feedback signal. The control circuit outputs an invalid control signal based on the feedback signal. The pulse timing circuit receives the invalid control signal and outputs an invalid switch signal, thus closing the leakage path.

3. The bleeder circuit as described in claim 1, characterized in that, The pulse timing circuit includes several timing modules. Each timing module can receive control signals and output feedback signals. Some timing modules are also used to output switching signals.

4. The bleeder circuit as described in claim 3, characterized in that, The aforementioned timing modules are D triggers.

5. The bleeder circuit as described in claim 3, characterized in that, The aforementioned timing modules include timing modules 25 to 34. Each timing module can receive control signals and output feedback signals. The 34th timing module is also used to output switch signals.

6. The bleeder circuit as described in claim 5, characterized in that, The control circuit includes modules one through twenty-four, wherein modules one through three and modules nine through fifteen are feedback units that receive the feedback signals.

7. The bleeder circuit as described in claim 6, characterized in that, The first to the twenty-fourth modules include NAND gates, NOR gates, and inverters.

8. The bleeder circuit as described in claim 6, characterized in that, The input terminals of the first to second modules and the ninth to twelfth modules are connected to the output terminals of the twenty-fifth to thirty-fourth timing modules.

9. The bleeder circuit as described in claim 1, characterized in that, The leakage path includes a resistor and an NMOS transistor, and the switching signal controls the switching of the NMOS transistor.

10. A DC-DC converter, characterized in that, include: The input unit, the output unit, the output feedback unit, the error amplification unit, and the leakage circuit as described in any one of claims 1 to 9; The bleed-out circuit is connected in parallel with the output unit to bleed out current from the output unit.

11. The DC-DC converter as claimed in claim 10, characterized in that, Also includes: Comparison unit, modulation unit, feedback circuit; One input terminal of the comparison unit is connected to the output terminal of the feedback circuit, and the second input terminal is connected to the output terminal of the error amplification unit. The input terminal of the modulation unit is connected to the output terminal of the comparison unit, and the output terminal of the modulation unit is connected to the input unit; The input terminal of the feedback circuit is connected to the output terminal of the input unit.

12. The DC-DC converter as claimed in claim 11, characterized in that, The modulation modes of the modulation unit include PWM mode and PFM mode.

13. The DC-DC converter as claimed in claim 12, characterized in that, The modulation unit is also connected to the control circuit in the bleed circuit.

14. The DC-DC converter as claimed in claim 13, characterized in that, The modulation mode is PWM mode, and the modulation unit outputs a PWM enable signal to the control circuit.

15. The DC-DC converter as claimed in claim 13, characterized in that, The modulation mode is PFM mode, and the modulation unit outputs a PFM enable signal to the control circuit.

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