A control method for a CLLC converter and a controller therefor

Abstract

The present disclosure relates to a control method for a CLLC converter and a controller therefor. The control method may include detecting an output current on the secondary side of the CLLC converter. The control method may compare a fluctuation parameter of the detected output current with respect to a reference value in its previous steady state with a first threshold. In the case where the fluctuation parameter exceeds the first threshold, the switching frequency of the CLLC converter may be adjusted based on a maximum voltage related parameter of a second capacitor of the CLLC converter such that the maximum voltage related parameter of the second capacitor is within a dead zone in a transition state before the next steady state, the dead zone causing the CLLC converter to operate in a P mode or an O mode. Thus, it is possible to restore to a stable state with good dynamic performance (including but not limited to shorter response time, less overshoot, less electromagnetic interference, etc.) in the case of a load change.

Description

Technical Field

[0001] The present disclosure relates to a control method for an electrical device and a controller therefor. Specifically, the present disclosure relates to a control method for a power converter and a controller therefor. Background Art

[0002] Due to its excellent soft-switching characteristics, the CLLC converter is considered a promising topology for bidirectional power transfer. As Figure 1 shown, the CLLC converter may include a primary side 101, a secondary side 102, and a transformer 100 that couples the primary side 101 and the secondary side 102 to each other. The transformer 100 may include a magnetic inductor L m , and the ratio of the number of turns of the coil on the primary side 101 to the number of turns of the coil on the secondary side 102 may be n:1. The primary side 101 may include an input capacitor C in connected in parallel between the two poles of the input (indicated by "+" and "-" on the left), a first switch branch, and a second switch branch. Among them, the first switch branch includes a first switch S1 and a second switch S2 connected in series, and the second switch branch includes a third switch S3 and a fourth switch S4 connected in series. The secondary side 102 may include an output capacitor C out connected in parallel between the two poles of the output (indicated by "+" and "-" on the right), a third switch branch, and a fourth switch branch. The third switch branch may include a fifth switch S5 and a sixth switch S6 connected in series, and the fourth switch branch may include a seventh switch S7 and an eighth switch S8 connected in series. The two ends of the primary side 101 of the transformer 100 are connected to the access point A between the first switch S1 and the second switch S2 of the first switch branch and the access point B between the third switch S3 and the fourth switch S4 of the second switch branch via a first inductor L r1 and a first capacitor C r1 respectively, so as to be applied with a voltage u AB . The two ends of the secondary side 102 of the transformer 100 are connected to the access point C between the fifth switch S5 and the sixth switch S6 of the third switch branch and the access point D between the seventh switch S7 and the eighth switch S8 of the fourth switch branch via a second inductor L r2 and a second capacitor C r2 respectively, so as to be applied with a voltage u CD . In some embodiments, each of the switches S1-S8 may be a silicon-based metal oxide semiconductor field effect transistor (MOSFET), or a gallium nitride transistor, etc., which will not be elaborated here. For the convenience of description hereinafter, use i p to represent the primary side current, use i s to represent the secondary side current, and use i oDenote the output current as i Lm Denote the current flowing through the magnetic inductor L m as i c Denote the charging and discharging current for the output capacitor C out as U in Denote the input voltage as U out Denote the output voltage as f s Denote the switching frequency as f r Denote the resonant frequency. Sometimes, the transformer 100 (including the magnetic inductor L m ) together with the first inductor L r1 , the first capacitor C r1 , the second inductor L r2 and the second capacitor C r2 are collectively referred to as the resonant tank

[0003] Although some control methods for CLLC converters have been proposed, however, most control methods are for voltage regulation. Conventional PI methods are usually used for constant current control and are effective for constant loads and slowly changing loads; while there are dynamic performance problems in the case of significantly especially rapidly changing loads, the conversion process is long and the overshoot is long Summary of the Invention

[0004] The present disclosure is provided to solve the above problems existing in the prior art

[0005] There is a need for a control method for a CLLC converter and a controller therefor, which can restore to a stable state (such as but not limited to a stable output current) with good dynamic performance (including but not limited to shorter response time, less overshoot, less electromagnetic interference, etc.) under load change conditions

[0006] According to a first aspect of the present disclosure, there is provided a control method for a CLLC converter

[0007] The CLLC converter includes a primary side, a secondary side, and a transformer that couples the primary side and the secondary side to each other. The primary side includes an input capacitor connected in parallel between two poles of an input, a first switch branch, and a second switch branch. The secondary side includes an output capacitor connected in parallel between two poles of an output, a third switch branch, and a fourth switch branch. The first switch branch includes a first switch and a second switch connected in series, and the second switch branch includes a third switch and a fourth switch connected in series. Two ends of the primary side of the transformer are respectively connected to an access point between the first switch and the second switch of the first switch branch and an access point between the third switch and the fourth switch of the second switch branch via a first inductor and a first capacitor. The third switch branch includes a fifth switch and a sixth switch connected in series, and the fourth switch branch includes a seventh switch and an eighth switch connected in series. Two ends of the secondary side of the transformer are respectively connected to an access point between the fifth switch and the sixth switch of the third switch branch and an access point between the seventh switch and the eighth switch of the fourth switch branch via a second inductor and a second capacitor.

[0008] The control method may include detecting an output current of the secondary side of the CLLC converter. The control method may compare a fluctuation parameter of the detected output current with respect to a reference value in its previous steady state with a first threshold. In a case where the fluctuation parameter exceeds the first threshold, the switching frequency of the CLLC converter may be adjusted based on a maximum voltage related parameter of the second capacitor of the CLLC converter, so that the maximum voltage related parameter of the second capacitor is within a dead zone in a transition state before the next steady state, and the dead zone enables the CLLC converter to operate in a P mode or an O mode.

[0009] According to a second aspect of the present disclosure, a controller for a CLLC converter is provided. The controller may be configured to implement the control method of the CLLC converter according to various embodiments of the present disclosure.

[0010] By using the control method of the CLLC converter according to various embodiments of the present disclosure and the controller therefor, it can be restored to a steady state (such as but not limited to a stable output current) with good dynamic performance (including but not limited to shorter response time, less overshoot, less electromagnetic interference, etc.) under load variation conditions. Description of the Drawings

[0011] In the accompanying drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same reference numerals with alphabetical suffixes or different alphabetical suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments by way of example and not limitation, and are used in conjunction with the description and the claims to explain the disclosed embodiments. Such embodiments are illustrative and are not intended to be exhaustive or exclusive embodiments of the apparatus or method.

[0012] Figure 1 Shows a circuit diagram of a CLLC converter according to the prior art;

[0013] Figure 2 Shows a schematic diagram of a control method of a CLLC converter according to an embodiment of the present disclosure;

[0014] Figure 3 Shows a schematic circuit diagram of the output side of a CLLC converter according to an embodiment of the present disclosure;

[0015] FIG. 4(a) shows the waveform of the secondary side current in the CLLC converter;

[0016] FIG. 4(b) shows the waveform of the current after the secondary side current rectification process in the CLLC converter;

[0017] FIG. 5(a) shows a conversion curve graph of the output voltage of the CLLC converter in the case of increasing load according to an embodiment of the present disclosure;

[0018] FIG. 5(b) shows a conversion curve graph of the output current of the CLLC converter in the case of increasing load according to an embodiment of the present disclosure;

[0019] FIG. 5(c) shows a conversion curve graph of the output voltage of the CLLC converter in the case of decreasing load according to an embodiment of the present disclosure;

[0020] FIG. 5(d) shows a conversion curve graph of the output current of the CLLC converter in the case of decreasing load according to an embodiment of the present disclosure;

[0021] FIG. 6(a) shows a schematic diagram of the equivalent circuit of the CLLC converter in the P mode according to an embodiment of the present disclosure;

[0022] FIG. 6(b) shows a schematic diagram of the equivalent circuit of the CLLC converter in the O mode according to an embodiment of the present disclosure;

[0023] FIG. 6(c) shows a schematic diagram of the equivalent circuit of the CLLC converter in the N mode according to an embodiment of the present disclosure;

[0024] FIG. 6(d) shows a schematic diagram of the unified equivalent circuit of the CLLC converter in P, N, and O modes according to an embodiment of the present disclosure;

[0025] Figures 7(a) - 7(c) FIG. 7 shows a trajectory diagram during the entire process in the case of load reduction according to an embodiment of the present disclosure. FIG. 7(a) shows the previous steady-state trajectory before load reduction, FIG. 7(b) shows the transformation trajectory when the switching frequency changes from the switching frequency in the previous steady state to the switching frequency in the subsequent steady state during load reduction, and FIG. 7(c) shows the subsequent steady-state trajectory after load reduction;

[0026] Figures 8(a) - 8(c) FIG. 8 shows a trajectory diagram during the entire process in the case of load increase according to an embodiment of the present disclosure. FIG. 8(a) shows the previous steady-state trajectory before load increase, FIG. 8(b) shows the transformation trajectory when the switching frequency changes from the switching frequency in the previous steady state to the switching frequency in the subsequent steady state during load increase, and FIG. 8(c) shows the subsequent steady-state trajectory after load increase;

[0027] FIG. 9(a) shows a schematic diagram of the flow of the control method of the CLLC converter in the case of load increase according to an embodiment of the present disclosure;

[0028] FIG. 9(b) shows a schematic diagram of the flow of the control method of the CLLC converter in the case of load reduction according to an embodiment of the present disclosure;

[0029] FIG. 10(a) shows a schematic diagram of the response waveform obtained by executing the control method according to an embodiment of the present disclosure on a laboratory-level prototype under load increase conditions;

[0030] FIG. 10(b) shows a schematic diagram of the response waveform obtained by executing the existing PI control method on a laboratory-level prototype under load increase conditions;

[0031] FIG. 11(a) shows a schematic diagram of the response waveform obtained by executing the control method according to an embodiment of the present disclosure on a laboratory-level prototype under load reduction conditions; and

[0032] FIG. 11(b) shows a schematic diagram of the response waveform obtained by executing the existing PI control method on a laboratory-level prototype under load reduction conditions. Detailed implementation manners

[0033] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure will be described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and specific examples, but this is not a limitation on the present disclosure. The terms "first", "second", and "third" used in the present disclosure are only intended to distinguish the corresponding features, and do not represent the need for such an order, nor necessarily represent only the singular form.

[0034] Figure 2 A schematic diagram showing a control method of a CLLC converter according to an embodiment of the present disclosure. As Figure 2 shown, the output current i of the secondary side 102 of the CLLC converter can be detected o , and the output current i o together with the maximum voltage u across the second capacitor C r2 can be provided to the controller 201 as feedback variables, so that the controller 201 can determine the adjustment time and adjustment method of the switching frequency f cr2,max accordingly. Specifically, in the case of load changes, such as but not limited to slow gradual changes or transients, the controller 201 can determine the fluctuation parameter of the detected output current i s relative to its reference value in the previous steady state, such as but not limited to the current amplitude difference, the current amplitude change rate per unit time, etc., and compare the fluctuation parameter with a first threshold. When the fluctuation parameter exceeds the first threshold, the controller 201 can adjust the switching frequency f of the CLLC converter based on the maximum voltage related parameter of the second capacitor C o of the CLLC converter, so that the maximum voltage related parameter of the second capacitor C r2 is within the dead zone in the transition state before the next steady state, and the dead zone enables the CLLC converter to operate in the P mode or the O mode. In the present disclosure, the term "maximum voltage related parameter of the second capacitor C s " can represent various parameters related to the maximum voltage u of the second capacitor C r2 , such as but not limited to the maximum voltage u of the second capacitor C r2 itself, parameters obtained by performing operations (such as but not limited to division, subtraction, etc.) based on the maximum voltage u of the second capacitor C r2 and considering other parameters such as but not limited to the output voltage U cr2,max , the output current i r2 , etc., as long as the "maximum voltage related parameter of the second capacitor C cr2,max " is related to the second capacitor C r2 and considering other parameters such as but not limited to the output voltage U cr2,max and considering other parameters such as but not limited to the output voltage U out , the output current i o , etc. (such as but not limited to division, subtraction, etc.) obtained by performing operations, etc., as long as the "maximum voltage related parameter of the second capacitor C r2 " is related to the second capacitor Cr2 The maximum voltage u cr2,max is related to and directly or indirectly reflects the maximum voltage u r2 of the second capacitor C cr2，max The time-domain information (especially real-time information) thereof will not be elaborated here.

[0035] By using the maximum voltage u r2 across the second capacitor C cr2，max as feedback, it is possible to reflect the charging and discharging current i out of the output capacitor C c The real-time information of the charging and discharging current i c can determine the charging and discharging process of the output capacitor C out (which is usually a stable value), and further determine the dynamic performance of the CLLC converter during load changes. Thus, the controller 201 can control the charging and discharging current i c well, can rapidly increase or decrease the charging and discharging current i c and know in a timely manner when the charging and discharging current i c reaches its limit, so as to obtain good dynamic performance of the CLLC converter, especially good dynamic performance of the CLLC converter in the transition state between the previous steady state and the next steady state under load change conditions.

[0036] Regarding the maximum voltage u r2 across the second capacitor C cr2，max for the charging and discharging current i out of the output capacitor C c The real-time feedback effect can be verified through circuit analysis of the CLLC converter. By making the maximum voltage related parameters of the second capacitor C r2 fall within the dead zone in the transition state, and the dead zone enables the CLLC converter to operate in the P mode or the O mode, it is possible to avoid its operation in the N mode, and accordingly, avoid too small a charging and discharging current i c , avoid the temporary operation of each switch S1 - S4 on the primary side 101 under hard-switching conditions, and further avoid higher voltage spikes and more electromagnetic interference, which is also verified through analysis of the state trajectory model of the CLLC converter.

[0037] The controller 201 may be configured to execute a control method of a CLLC converter according to various embodiments of the present disclosure. The controller 201 may include a processor (not shown) and a memory (not shown), and computer-executable instructions may be stored on the memory, and when executed by the processor, may execute the control method according to various embodiments of the present disclosure. The processor may be a processing device including more than one general-purpose processing device, such as a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), etc. More specifically, the processor may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor running other instruction sets, or a processor running a combination of instruction sets. The processor may also be more than one dedicated processing device, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a system-on-chip (SoC), etc. The processor may be communicatively coupled to the memory and configured to execute the computer-executable instructions stored thereon to execute a control method such as that described in various embodiments of the present disclosure.

[0038] The memory may be a non-transitory computer-readable medium, such as a read-only memory (ROM), a random access memory (RAM), a phase change random access memory (PRAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), an electrically erasable programmable read-only memory (EEPROM), other types of random access memory (RAM), a flash drive or other forms of flash memory, a cache, a register, a static memory, a compact disc read-only memory (CD-ROM), a digital versatile disc (DVD) or other optical memory, a cassette tape or other magnetic storage device, or any other possible non-transitory medium used to store information or instructions accessible by a computer device, etc.

[0039] In some embodiments, the controller 201, together with the included processor and memory, may be implemented as a distributed control system, such as a control system in the cloud.

[0040] Figure 3 A circuit schematic diagram of the output side of a CLLC converter according to an embodiment of the present disclosure is shown. As Figure 3 shown, the charge and discharge current i c can be calculated according to formula (1):

[0041] i c = mean(i s,rec ) - i o Formula (1)

[0042] wherein, i sRepresents the secondary - side current of the resonant cavity, whose waveform is shown in Fig. 4(a) for example, \(i\) s,rec Represents \(i\) s 's rectified current, whose waveform is shown in Fig. 4(b) for example, \(mean(i\) s,rec ) represents the average value of \(i\) s,rec . Under steady state, \(mean(i\) s,rec ) is equal to the output current \(i\) o , and the output voltage \(U\) out remains stable.

[0043] Taking constant - current control as an example, the conversion process of the CLLC converter is described. In constant - current control, the controller 201 of the CLLC converter will attempt to maintain the output current \(i\) o at the target value \(i\) o,set . Since the output current \(i\) o can be regarded as a constant, the larger the load resistance \(R\) L (as shown in Figure 3 ), the greater the output power.

[0044] As shown in Fig. 5(a) and Fig. 5(b), the output voltage in the previous steady state is \(U\) out,0 . As the load resistance \(R\) L increases, the output current \(i\) o will decrease. By reducing the switching frequency \(f\) s , the average value of the rectified current of \(i\) s , \(mean(i\) s，rec ), can be increased, thereby charging the output capacitor \(C\) out , causing the output voltage \(U\) out to increase accordingly (for example, increase and stabilize to \(U\) out,1 ). Correspondingly, the output current \(i\) o increases to recover and stabilize to the target value \(i\) o,set , thus transitioning to the next steady state.

[0045] As shown in Fig. 5(c) and Fig. 5(d), the output voltage in the previous steady state is \(U\) out,0 . As the load resistance \(R\) L decreases, the output current \(i\) o will increase. By increasing the switching frequency \(f\) s , the average value of the rectified current of \(i\) s , \(mean(i\) s，rec ), can be decreased, thereby discharging the output capacitor \(C\) out , causing the output voltage \(U\) out to decrease accordingly (for example, decrease and stabilize to \(U\) out,1 ). Correspondingly, the output current \(i\) o decreases to recover and stabilize to the target value \(i\)o,set , thus switching to the next steady state.

[0046] It can be seen that the charging and discharging process of the output capacitor C out determines the dynamic performance during load changes (especially during load transients). Given that the capacitance of the output capacitor C out is a stable value, the charging and discharging current i c determines the dynamic performance of the CLLC converter during load changes.

[0047] The maximum voltage u r2 across the second capacitor C cr2，max and the average value mean(i s ) of the rectified current of the secondary - side current i s,rec ) of the resonant cavity have the following relationship:

[0048]

[0049] where, T s represents the switching period, which is the reciprocal of the switching frequency f s .

[0050] According to formula (2), the maximum voltage u r2 across the second capacitor C cr2,max is closely related to the average value mean(i s ) of the rectified current of the secondary - side current i s，rec ) of the resonant cavity. Refer to formula (1) and co - reference Figures 5(a) - 5(d) , the average value mean(i s ) of the rectified current of the secondary - side current i s,rec ) of the resonant cavity is then closely related to the conversion process in the resonant cavity and can reflect the real - time information of the charging and discharging current i c . Further, the maximum voltage u r2 across the second capacitor C cr2,max can reflect when the charging and discharging current i c reaches its limit. Specifically, if u cr2,max is zero, then i c is minimum; if u cr2，max reaches the limit, then i c reaches its limit accordingly. Through the above process analysis, it can be verified that by using the feedback of the maximum voltage u r2 across the second capacitor C cr2，max , the charging and discharging current i out of the output capacitor C c can be well controlled, thus providing a basis for obtaining good dynamic performance of the CLLC converter under load changes.

[0051] The operation process of the CLLC converter can be divided into P mode, O mode, and N mode. For simplicity, the turns ratio n of transformer 100 is set to 1. The equivalent circuits of the CLLC converter in P mode, O mode, and N mode under such a simplified setting can be respectively referred to Fig. 6(a), Fig. 6(b), and Fig. 6(c). Note that the turns ratio of 1 is only an example. In the case where the turns ratio is not equal to 1, the second capacitor C r2 and the second inductor L r2 can be folded to the primary side 101 according to the turns ratio, and each current and voltage on the secondary side 102 (such as the current i s on the secondary side, the output voltage U out , the voltage u r2 across the two ends of the second capacitor C cr2 , etc.) are also folded to the primary side 101 accordingly to obtain the equivalent circuits in the corresponding modes. The method of folding the relevant circuit parameters from the secondary side to the primary side according to the turns ratio is known and can be implemented by those skilled in the art, and will not be elaborated here.

[0052] For simplicity of description, in the following text, the turns ratio is set to 1 as an example. However, it should be noted that the following analysis can be directly applied to various CLLC converters with a turns ratio n not equal to 1 as long as the corresponding circuit parameters are folded from the secondary side to the primary side according to the actual turns ratio n, and will not be elaborated here.

[0053] As shown in Fig. 6(a), Fig. 6(b), and Fig. 6(c), the CLLC resonator is a fourth-order circuit, making the operation processes in P and N modes fourth-order oscillations rather than simple LC oscillations, and the state trajectory analysis cannot be applied. The inventor constructed a unified equivalent circuit for the operation processes of the CLLC converter in P, N, and O modes. Among them, i p +i s and u cr1 +u cr2 can be used as state variables, thereby simplifying the operation processes in P mode and N mode to LC oscillations. As shown in Fig. 6(d), U dc can represent the equivalent voltage, L can represent the equivalent inductor, and C can represent the equivalent capacitor.

[0054] Specifically, as shown in Fig. 6(d), the unified LC oscillation circuit includes the equivalent voltage U dc , and the equivalent inductor L and equivalent capacitor C connected in series between its two ends. The equivalent current flowing through the equivalent inductor L is the current i p on the primary side of the CLLC converter plus (folded to the primary side) the current i s on the secondary side., the equivalent voltage across the equivalent capacitor C is the voltage u across the first capacitor and the second capacitor (transformed to the primary side). cr1 and u cr2 sum. Table 1 lists the parameter values of the equivalent voltage U dc , equivalent inductance L, and equivalent capacitor C of this equivalent circuit in the P mode, 0 mode, and N mode.

[0055] Table 1 Parameter values of the equivalent voltage U dc , equivalent inductance L, and equivalent capacitor C of the equivalent circuit in the P mode, O mode, and N mode

[0056] <![CDATA[U dc (Positive half cycle)]]> <![CDATA[U dc (negative half cycle)]]> L C P mode <![CDATA[U in -U out > <![CDATA[-U in +U out > <![CDATA[L r1 or L r2 > <![CDATA[C r1 or C r2 > N mode <![CDATA[U in +U out > <![CDATA[-U in -U out > <![CDATA[L r1 or L r2 > <![CDATA[C r1 or C r2 > O mode <![CDATA[U in +u cr2，max > <![CDATA[-U in -u cr2，max > <![CDATA[L r1 +L m > <![CDATA[C r1 >

[0057] As shown in Table 1, by setting the equivalent voltage U dc , equivalent inductor L, and equivalent capacitor C as follows, the resonant circuits in the P mode, O mode, and N mode can be respectively simulated.

[0058] For the P mode, the equivalent voltage U dc in the positive half - cycle can be set to the difference between the input voltage U in across the input capacitor C of the CLLC converter in and the output voltage U out transformed to the primary side. The equivalent voltage U dc in the negative half - cycle can be set to the difference between the output voltage U out transformed to the primary side of the CLLC converter and the input voltage U in across the input capacitor C in . The equivalent inductor L can be set to the first inductor L r1 or the second inductor L r2 transformed to the primary side. The equivalent capacitor C can be correspondingly set to the first capacitor C r1 or the second capacitor C r2 transformed to the primary side.

[0059] For the N mode, the equivalent voltage U dc in the positive half - cycle can be set to the sum of the input voltage U in across the input capacitor C of the CLLC converter in and the output voltage U out transformed to the primary side. The equivalent voltage U dc in the negative half - cycle can be set to the difference between the input voltage U in across the input capacitor C of the CLLC converter in and the output voltage U outThe reverse voltage of the sum, set the equivalent inductor L to the first inductor L r1 or the second inductor L (referred to the primary side) r2 , set the equivalent capacitor C accordingly to the first capacitor C r1 or the second capacitor C (referred to the primary side) r2 .

[0060] For the O mode, the equivalent voltage U in the positive half cycle dc can be set to the input voltage across the input capacitor C of the CLLC converter in C in and the maximum voltage u of the second capacitor C (referred to the primary side) r2 . Set the equivalent voltage U in the negative half cycle cr2，max to the reverse voltage of the sum of the input voltage across the input capacitor C of the CLLC converter dc C in and the maximum voltage u of the second capacitor C (referred to the primary side) in . Set the inductance value of the equivalent inductor L to the sum of the inductance value of the first inductor L r2 and the equivalent inductance value L of the transformer cr2，max . Set the equivalent capacitor C to the first capacitor C r1 . During the O mode, the voltage value of the second capacitor C m is the maximum value of u r1 , that is, u r2 cr2 cr2，max .

[0061] By simplifying the operation process of the CLLC converter in three modes to an LC oscillation circuit through the above settings, state trajectory analysis can be performed on it. Taking load transient as an example, the change of the state trajectory under load change is described below.

[0062] In the case of load increase, assume that before the load transient, the switching frequency f s = f s1 < f r (resonant frequency). Then, the CLLC converter will operate in the P mode (shown by the thick line) and the O mode (shown by the thin line). Fig. 7(a) shows the steady-state trajectory when the switching frequency is f s1 (which is shown as a dotted line in Fig. 7(c) as the trajectory of the previous steady state). In the steady state before the load increase, U out = U out,0 , u cr2,max = u cr2,max,0 and i c ​​= 0. Once an increase in load is detected, the controller 201 will reduce the switching frequency, and the transient process in the resonant cavity will start. Assume the switching frequency f s is reduced from f s1 to f s2 (f s2 < f s1 ). Fig. 7(b) shows the transient trajectory when the switching frequency f s changes from f s1 to f s2 .

[0063] According to the trajectory ABCDE, it can be seen that if the switching frequency f s decreases, the radius of the trajectory in the P mode will be longer during the O mode, and then more energy will be transferred to the secondary side 102 during the P mode. This process will repeat, and the state trajectory will expand. During the process of trajectory expansion, more energy will be transferred to the secondary side 102. The output capacitor C out is charged and the output voltage U out will increase. As can be known from Table 1, this process will reduce the radius of the next P mode trajectory. When the two processes reach equilibrium, the CLLC converter will enter a new stable state as shown in Fig. 7(c), where U out = U out，1 , u cr2，max = u cr2，max，1 and i c = 0.

[0064] In the case of load reduction, it is similar. As Figures 8(a) - 8(c) shown, the switching frequency f s is increased from f s2 to f s1 , and the trajectory will contract and finally reach equilibrium.

[0065] The expansion or contraction of the state trajectory has limitations. The limitation of contraction is that the trajectory contracts to zero, and the limitation of expansion is that the trajectory expands to the P mode and N mode. Through the study of the expansion of the state trajectory, it is confirmed that in the case of expansion to the N mode, the charge and discharge current i c will be smaller, and each switch S1 to S4 on the primary side 101 may temporarily operate under hard switching conditions, resulting in higher voltage spikes and more electromagnetic interference. In some embodiments, according to the circuit parameters and operating conditions parameters of the CLLC converter, for the second capacitor C r2The maximum voltage-related parameters are preset to operate in the dead zone of the P mode or the O mode, such as but not limited to presetting the dead zone boundary, dead zone margin, etc. For example, in the P mode or the O mode, a CLLC converter with predetermined circuit parameters and operating condition parameters can be simulated to predetermine the dead zone boundary. In this way, the controller 201 can well control the second capacitor C r2 The maximum voltage-related parameters are such that it is in the dead zone during the transition state before the next steady state, for example, basically stable within a certain fluctuation range in the dead zone, so as to ensure that the CLLC converter basically operates in the P mode or the O mode during the transition state before the next steady state. This can avoid the possible temporary operation of each switch S1 to S4 on the primary side 101 under hard switching conditions, higher voltage spikes, more electromagnetic interference, as well as related long transition times, poor overshoot, and other poor dynamic performances.

[0066] Multiple defined maximum voltage-related parameters of the second capacitor C can be adopted. r2 For example, the maximum voltage u r2 of the second capacitor C cr2，max can be used as the maximum voltage-related parameter of the second capacitor C r2 For another example, the ratio of the maximum voltage u r2 of the second capacitor C cr2，max to the output voltage U out of the secondary side 102 of the CLLC converter can be used as the maximum voltage-related parameter of the second capacitor C r2 In some embodiments, when the load increases, the ratio of the maximum voltage u r2 of the second capacitor C cr2,max to the output voltage U out of the secondary side 102 of the CLLC converter can be used as the maximum voltage-related parameter of the second capacitor C r2 In some embodiments, when the load increases, the ratio of the maximum voltage u r2 of the second capacitor C cr2,max to the output voltage U out of the secondary side 102 of the CLLC converter together with the maximum voltage u cr2,max can be used as the maximum voltage-related parameter of the second capacitor C r2 In some embodiments, when the load decreases, the maximum voltage u r2 of the second capacitor C cr2,max can be used as the maximum voltage-related parameter of the second capacitor C r2

[0067] By Figures 7(a) - 8(c)Analyzing the trajectory under the shown load variation, it can be confirmed that: when the load increases, if the maximum voltage u of the second capacitor C r2 and the ratio of the output voltage U of the CLLC converter satisfy the conditions defined by formula (3), the CLLC converter will operate in the P mode and / or the O mode; when the load decreases, if the maximum voltage u of the second capacitor C cr2,max and the output voltage U of the CLLC converter out satisfy the conditions defined by formula (4), the CLLC converter will operate in the P mode and / or the O mode. r2 and the maximum voltage u cr2,max satisfy the conditions defined by formula (4), the CLLC converter will operate in the P mode and / or the O mode.

[0068]

[0069] u cr2,max <Δ formula (4)

[0070] The following takes the constant current control method as an example for illustration, but it should be noted that the control method is not limited to this. By adapting the control methods according to the various embodiments of the present disclosure, they can be applied to various specific actual requirements such as constant current, predetermined current waveforms, predetermined voltage waveforms, etc., and ensure good dynamic performance.

[0071] Figure 9(a) shows a schematic diagram of the flow of the control method of the CLLC converter under increasing load according to an embodiment of the present disclosure. In the application scenario with a constant current requirement, before the load changes, existing methods including PI can be used to maintain a stable output current i o . When the load increases, the output current i o will decrease. The decrease value of the output current i o relative to its reference value i o,set in the previous steady state can be used as the fluctuation parameter. As shown in Figure 9(a), when this fluctuation parameter exceeds the first threshold i o,threshold , u cr2，max can be used as the feedback variable. Based on the maximum voltage related parameters of the second capacitor of the CLLC converter, such as the ratio u cr2,max / U out of the maximum voltage of the second capacitor to the output voltage of the secondary side of the CLLC converter, the switching frequency f s of the CLLC converter can be adjusted in stages.

[0072] Specifically, the transition state can be executed in approximately three stages, namely stage 1, stage 2, and stage 3.

[0073] In stage 1, when the output current i o relative to its reference value i o,setThe decrease value exceeds the first threshold i o,threshold In this case, by setting the switching frequency f s in each control period (as shown by the interval between adjacent vertical dotted lines in FIG. 9(a)) to decrease by a first frequency adjustment value Δf I such that the ratio u cr2,max / U out increases to its dead zone boundary λ. As defined by formula (3), above the dead zone boundary λ, the ratio u cr2,max / U out is considered to be in the dead zone. In this case, the CLLC converter is in the P mode or the O mode, and not in the N mode. In some embodiments, a suitable first frequency adjustment value Δf I can be employed such that the ratio u cr2,max / U out quickly reaches the dead zone boundary while avoiding the CLLC converter being in the N mode during the transition. In some embodiments, the first frequency adjustment value Δf I can be 1 kHz - 5 kHz.

[0074] In stage 2, the switching frequency f s can be adjusted as needed to maintain the ratio u cr2,max / U out maintained near the dead zone boundary within the dead zone, for example, within a certain margin above the dead zone boundary. Specifically, for example, when the ratio u cr2，max / U out is to be less than its dead zone boundary λ, the switching frequency f s in each control period can be decreased by a second frequency adjustment value Δf II . In some embodiments, if the ratio u cr2,max / U out is greater than its dead zone boundary λ, no action may be taken, or the second frequency adjustment value Δf II can also be further decreased. The process of stage 2 can continue until the output current i o on the secondary side of the CLLC converter resumes its reference value i o,set at the previous steady state. The second frequency adjustment value Δf II can be smaller than the first frequency adjustment value Δf I so as to more stably maintain the ratio u cr2,max / U out near the dead zone boundary in stage 2 while avoiding excessive oscillations in charging and discharging. In some embodiments, the second frequency adjustment value Δf II can be a few hundred hertz.

[0075] In stage 3, by setting the switching frequency f sIncrease the third frequency adjustment value Δf in each control cycle III , such that the maximum voltage u cr2,max of the second capacitor is reduced to the reference value u cr2,max,ref of its next steady state. In some embodiments, this reduction process may start when the output current i o returns to the reference value i o,set at its previous steady state. Among them, the third frequency adjustment value Δf III may be less than the second frequency adjustment value Δf II , so as to enable the CLLC converter to smoothly enter the next steady state and prevent overshoot.

[0076] Specifically, the reference value u cr2,max of the next steady state of the maximum voltage u cr2,max,ref of the second capacitor can be calculated by formula (5):

[0077]

[0078] In some embodiments, the first frequency adjustment value Δf I may be 4 to 10 times the second frequency adjustment value Δf II , and the second frequency adjustment value Δf II may be 4 to 10 times the third frequency adjustment value Δf III . In this way, a good dynamic performance curve of the CLLC converter can be obtained, that is, quickly switch to the dead zone boundary, stabilize near the dead zone boundary with a slight fluctuation at a lower control load, and smoothly switch to the next steady state, effectively preventing overshoot, electromagnetic interference and excessive oscillation of charge and discharge.

[0079] After switching to the next steady state, various control methods including PI can be used to continue to maintain a stable output current i o .

[0080] The control method process in the case of load reduction is similar to that in the case of load increase. In some embodiments, in the case of load reduction, the increased value of the output current i o relative to its reference value i o,set at its previous steady state can be used as the fluctuation parameter, and the maximum voltage u cr2,max of the second capacitor can be used alone as the parameter related to the maximum voltage of the second capacitor.

[0081] As shown in FIG. 9(b), a load reduction will cause an increase in the output current i o relative to its reference value i o,set at its previous steady state. When this increased value exceeds the first threshold i o,thresholdIn the case of, it can be divided into three stages, and based on the maximum voltage related parameters of the second capacitor, such as the maximum voltage u of the second capacitor cr2,max , to adjust the switching frequency f of the CLLC converter s . Before and after these three stages, the CLLC converter is in different steady states, namely the previous steady state and the subsequent steady state. Various control methods including PI can be used to maintain a stable output current i o .

[0082] In stage 1, when the increase value of the output current i o relative to its reference value in the previous steady state exceeds the first threshold i o,threshold , the switching frequency f s can be increased by a fourth frequency adjustment value Δf IV in each control cycle, so that the maximum voltage u cr2,max of the second capacitor is reduced to its dead zone boundary Δ. This dead zone boundary Δ is defined by formula (4) and can usually be a small value close to zero.

[0083] In stage 2, when the maximum voltage u cr2,max of the second capacitor is greater than its dead zone boundary Δ, the switching frequency f s can be increased by a fifth frequency adjustment value Δf V in each control cycle. As shown in FIG. 9(b), the maximum voltage u cr2,max is less than its dead zone boundary Δ, that is, it is in the dead zone. When the maximum voltage u cr2,max is less than the dead zone boundary Δ, no action can be taken, or the fifth frequency adjustment value Δf V can be further reduced. In this way, the maximum voltage u cr2，max can be basically stabilized near the dead zone boundary Δ in the dead zone. This process continues until the output current i o on the secondary side of the CLLC converter resumes its reference value i o,set in the previous steady state. In some embodiments, the fifth frequency adjustment value Δf V is less than the fourth frequency adjustment value Δf IV .

[0084] In stage 3, the switching frequency f s can be decreased by a sixth frequency adjustment value Δf VI in each control cycle, so that the maximum voltage u cr2，max of the second capacitor is increased to its reference value u cr2，max，ref of the next steady state, which can be defined by formula (5) for example. In some embodiments, the sixth frequency adjustment value Δf VI can be less than the fifth frequency adjustment value Δf V。

[0085] In some embodiments, similar to the numerical relationship between the first frequency adjustment value Δf I , the second frequency adjustment value Δf II and the third frequency adjustment value Δf III , the fourth frequency adjustment value Δf IV can be 4 to 10 times the fifth frequency adjustment value Δf V , and the fifth frequency adjustment value Δf V can be 4 to 10 times the sixth frequency adjustment value Δf VI . In this way, a good dynamic performance curve of the CLLC converter can be obtained, that is, quickly transition to the dead zone boundary, stably stay within the dead zone with a low control load, slightly fluctuate near the dead zone boundary, and smoothly transition to the next steady state, effectively preventing overshoot, electromagnetic interference, and excessive oscillation of charge and discharge.

[0086] To verify the control method of the CLLC converter according to the embodiments of the present disclosure, a laboratory-level prototype of the CLLC converter was established, and the parameters of the prototype are shown in Table 2.

[0087] Table 2 Parameters of the laboratory-level prototype

[0088]

[0089] The target value i of the output current o,set is 2 A. A rapid load transition process can be achieved by changing the value of the load resistance. Under the condition of load increase, setting the load resistance to increase from 160 ohms to 220 ohms, the output current i o can first maintain the moment within the range of (±3% + 1)i o,set as the end of the conversion process. FIG. 10(a) shows a schematic diagram of the response waveform obtained by performing the control method according to the embodiments of the present disclosure on the above laboratory-level prototype under the condition of load increase, while FIG. 10(b) shows a schematic diagram of the response waveform obtained by performing the existing PI control method on the laboratory-level prototype under the condition of load increase. Note that FIG. 10(a), FIG. 10(b), and FIGS. 11(a) and 11(b) below are all the interface displays of the oscilloscope.

[0090] As shown in FIGS. 10(a) and 10(b), at the moment of load increase, i o changes from 2 A to 1.4 A, which is a 30% current drop. For the dead zone-based control method according to the various embodiments of the present disclosure, it only takes 5.6 milliseconds to restore i o to i o,set and no overshoot is detected. For the PI method, it takes 12.8 milliseconds to restore i o to io,set And an overshoot of 8% is detected (i.e., the maximum value of i o is 2.16 A). In addition, during the transient process, significant electromagnetic interference is found on the waveform of i o , and the time when i o first reaches the range of (±3% + 1)i o,set is 35.7% longer than that of the proposed dead - zone - based method (7.6 ms vs. 5.6 ms) because the converter operates in the N - mode, the switches are in the hard - switching state, and the charging and discharging current i c is smaller.

[0091] As shown in FIGS. 11(a) and 11(b), under the condition of load reduction, the load resistance decreases from 220 ohms to 160 ohms. Correspondingly, the output current i o changes from 2 A to 2.75 A, an increase of 37.5%. The response time of the dead - zone - based control method according to various embodiments of the present disclosure is 5.3 ms, and no overshoot is detected; while the response time of the PI method is 12.4 ms, and the overshoot is 8%.

[0092] Table 3 lists the comparison of the dynamic performance between the control method according to various embodiments of the present disclosure and the PI method.

[0093] Table 3 Comparison of the dynamic performance between the control method according to various embodiments of the present disclosure and the PI method

[0094]

[0095] From the above comparison, it can be confirmed that the control method according to various embodiments of the present disclosure can well control the transient process in the resonant cavity. As a result, compared with the traditional PI method, the dynamic performance of the proposed method under fast load transients (>30% load change) has been significantly improved. The experimental results show that the response time is greatly shortened (less than 50% of the PI method), and no overshoot is detected.

[0096] In addition, although exemplary embodiments have been described herein, their scope includes any and all embodiments based on the present disclosure having equivalent elements, modifications, omissions, combinations (e.g., schemes that cross various embodiments), adaptations, or alterations. The elements in the claims will be broadly interpreted based on the language used in the claims and are not limited to the examples described in this specification or during the implementation of this application, and the examples will be interpreted as non - exclusive. Therefore, this specification and the examples are intended to be considered only as examples, and the true scope and spirit are indicated by the following claims and the full scope of their equivalents.

[0097] The order of the various steps in this disclosure is merely exemplary and not restrictive. Without affecting the implementation of this disclosure (without disrupting the logical relationship between the required steps), the order of execution of the steps can be adjusted, and the various embodiments obtained after the adjustment still fall within the scope of this disclosure.

[0098] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more of their aspects) can be used in combination with each other. For example, those of ordinary skill in the art can use other embodiments when reading the above description. Additionally, in the above detailed description, the various features can be grouped together to simplify this disclosure. This should not be construed as an intention that any feature of the disclosure that is not claimed is necessary for any claim. On the contrary, the subject matter of the present invention can be less than all the features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description as examples or embodiments, where each claim stands on its own as a separate embodiment, and these embodiments can be combined with each other in various combinations or permutations. The scope of the present invention should be determined with reference to the appended claims and the full scope of equivalents to which those claims are entitled.

Claims

1. A control method for a CLLC converter, the CLLC converter comprising a primary side, a secondary side, and a transformer that couples the primary side and the secondary side to each other. The primary side includes an input capacitor connected in parallel between two poles of an input, a first switch branch, and a second switch branch. The secondary side includes an output capacitor connected in parallel between two poles of an output, a third switch branch, and a fourth switch branch. The first switch branch includes a first switch and a second switch connected in series. The second switch branch includes a third switch and a fourth switch connected in series. Two ends of the primary side of the transformer are respectively connected to an access point between the first switch and the second switch of the first switch branch and an access point between the third switch and the fourth switch of the second switch branch via a first inductor and a first capacitor. The third switch branch includes a fifth switch and a sixth switch connected in series. The fourth switch branch includes a seventh switch and an eighth switch connected in series. Two ends of the secondary side of the transformer are respectively connected to an access point between the fifth switch and the sixth switch of the third switch branch and an access point between the seventh switch and the eighth switch of the fourth switch branch via a second inductor and a second capacitor, characterized in that, The control method includes: Detecting the output current on the secondary side of the CLLC converter; Comparing the fluctuation parameter of the detected output current with respect to its reference value in the previous steady state with a first threshold. When the fluctuation parameter exceeds the first threshold, adjusting the switching frequency of the CLLC converter based on the maximum voltage related parameter of the second capacitor of the CLLC converter, so that the maximum voltage related parameter of the second capacitor is within the dead zone during the transition state before the next steady state, and the dead zone enables the CLLC converter to operate in the P mode or the O mode; When the load increases, using the decrease value of the output current with respect to its reference value in the previous steady state as the fluctuation parameter, and using the ratio of the maximum voltage of the second capacitor to the output voltage on the secondary side of the CLLC converter as the maximum voltage related parameter of the second capacitor; When the fluctuation parameter of the output current with respect to its reference value in the previous steady state exceeds the first threshold, adjusting the switching frequency of the CLLC converter based on the maximum voltage related parameter of the second capacitor of the CLLC converter includes: In the first stage of the transition state, when the decrease value of the output current with respect to its reference value in the previous steady state exceeds the first threshold, by reducing the switching frequency by a first frequency adjustment value in each control period, the ratio of the maximum voltage of the second capacitor to the output voltage on the secondary side of the CLLC converter is increased to its dead zone boundary; In the second stage of the transition state, when the ratio of the maximum voltage of the second capacitor to the output voltage on the secondary side of the CLLC converter is less than its dead zone boundary, reducing the switching frequency by a second frequency adjustment value in each control period. The second stage of the transition state lasts until the output current on the secondary side of the CLLC converter recovers its reference value in the previous steady state, and the second frequency adjustment value is less than the first frequency adjustment value; and In the third stage of the transition state, by increasing the switching frequency by a third frequency adjustment value in each control period, the maximum voltage of the second capacitor is reduced to its reference value in the next steady state, and the third frequency adjustment value is less than the second frequency adjustment value; Wherein, the dead zone boundary corresponding to the ratio of the maximum voltage of the second capacitor to the output voltage on the secondary side of the CLLC converter is the dead zone boundary λ. When the ratio of the maximum voltage of the second capacitor to the output voltage on the secondary side of the CLLC converter is greater than the dead zone boundary λ, the ratio of the maximum voltage of the second capacitor to the output voltage on the secondary side of the CLLC converter is within the dead zone; The control method further includes: modeling the CLLC converter as a unified LC oscillation circuit when the second capacitor and the second inductor are reduced to the primary side according to the turns ratio, and the unified LC oscillation circuit includes an equivalent voltage U dc and an equivalent inductor L and an equivalent capacitor C connected in series between its two ends. The equivalent current flowing through the equivalent inductor L is the current on the primary side of the CLLC converter plus the current on the secondary side reduced to the primary side. The equivalent voltage across the equivalent capacitor C is the sum of the voltages across the first capacitor and the second capacitor reduced to the primary side. By setting the equivalent voltage U dc , the equivalent inductor L and the equivalent capacitor C as follows, to respectively simulate the resonant circuits in the P mode and the O mode: For the P mode, the equivalent voltage U in the positive half cycle dc is set to the difference between the input voltage across the input capacitor of the CLLC converter and the output voltage referred to the primary side. The equivalent voltage U in the negative half cycle dc is set to the difference between the output voltage referred to the primary side of the CLLC converter and the input voltage across the input capacitor. The equivalent inductor L is set to the first inductor or the second inductor referred to the primary side, and the equivalent capacitor C is correspondingly set to the first capacitor or the second capacitor referred to the primary side; For the O mode, the equivalent voltage U in the positive half cycle dc is set to the sum of the input voltage across the input capacitor of the CLLC converter and the maximum voltage of the second capacitor referred to the primary side. The equivalent voltage U in the negative half cycle dc is set to the reverse voltage of the sum of the input voltage across the input capacitor of the CLLC converter and the maximum voltage of the second capacitor referred to the primary side. The inductance value of the equivalent inductor L is set to the sum of the inductance value of the first inductor and the equivalent inductance value of the transformer. The equivalent capacitor C is set to the first capacitor.

2. The control method according to claim 1, wherein The first frequency adjustment value is 4 to 10 times the second frequency adjustment value, and the second frequency adjustment value is 4 to 10 times the third frequency adjustment value.

3. The control method according to claim 1, wherein When the load is reduced, the increased value of the output current relative to its reference value in the previous steady state is used as the fluctuation parameter, and the maximum voltage of the second capacitor is used as the parameter related to the maximum voltage of the second capacitor.

4. The control method according to claim 3, characterized in that When the fluctuation parameter of the output current relative to its reference value in the previous steady state exceeds the first threshold, adjusting the switching frequency of the CLLC converter based on the parameter related to the maximum voltage of the second capacitor of the CLLC converter includes: In the first stage of the transition state, when the increased value of the output current relative to its reference value in the previous steady state exceeds the first threshold, by increasing the fourth frequency adjustment value in each control period of the switching frequency, the maximum voltage of the second capacitor is reduced to its dead zone boundary; In the second stage of the transition state, when the maximum voltage of the second capacitor is greater than its dead zone boundary, increase the fifth frequency adjustment value in each control period of the switching frequency. The second stage of the transition state continues until the output current on the secondary side of the CLLC converter resumes its reference value in the previous steady state. The fifth frequency adjustment value is less than the fourth frequency adjustment value; and In the third stage of the transition state, by reducing the sixth frequency adjustment value in each control period of the switching frequency, the maximum voltage of the second capacitor is increased to its reference value in the next steady state. The sixth frequency adjustment value is less than the fifth frequency adjustment value; Wherein, the dead zone boundary corresponding to the maximum voltage of the second capacitor is the dead zone boundary Δ. When the maximum voltage of the second capacitor is less than the dead zone boundary Δ, the maximum voltage of the second capacitor is within the dead zone.

5. The control method according to claim 4, characterized in that The fourth frequency adjustment value is 4 to 10 times the fifth frequency adjustment value, and the fifth frequency adjustment value is 4 to 10 times the sixth frequency adjustment value.

6. The control method according to claim 1 or 4, characterized in that The reference value of the next steady state of the maximum voltage of the second capacitor is calculated by formula (5): where, u cr2,max,ref represents the reference value of the next steady state of the maximum voltage of the second capacitor, i o,set represents the reference value of the output current on the secondary side of the CLLC converter in steady state, C r2 represents the capacitance value of the second capacitor, T s represents the switching period of the CLLC converter.

7. The control method according to claim 1 or 4, characterized in that The dead zone is preset according to the circuit parameters and operating condition parameters of the CLLC converter.

8. The control method according to any one of claims 1, 3, and 4, characterized in that The maximum voltage of the second capacitor is the voltage value of the second capacitor in the O mode.

9. The control method according to claim 1, characterized in that Also, by setting the equivalent voltage U dc , the equivalent inductor L, and the equivalent capacitor C as follows, the resonant circuit in the N mode is simulated: Set the equivalent voltage U in the positive half - cycle dc as the sum of the input voltage across the input capacitor of the CLLC converter and the output voltage referred to the primary side. Set the equivalent voltage U in the negative half - cycle dc as the reverse voltage of the sum of the input voltage across the input capacitor of the CLLC converter and the output voltage referred to the primary side. Set the equivalent inductor L as the first inductor or the second inductor referred to the primary side, and set the equivalent capacitor C as the first capacitor or the second capacitor referred to the primary side accordingly.

10. A controller for a CLLC converter, characterized in that, The controller is configured to execute the control method of the CLLC converter according to any one of claims 1-9.

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