Display substrate and display device

Abstract

A display substrate and a display device, the display substrate comprising a display area (91) and a peripheral area, the peripheral area comprising a circuit area (92), the display area comprising: a plurality of sub-pixels (1), a plurality of data lines (11) extending along a first direction (991), and a plurality of gate lines (12) extending along a second direction (992); the circuit area (92) comprising a plurality of driving unit groups, the circuit area (92) comprising a first sub-area (921) and a second sub-area (922) opposite on both sides of the display area (91) along the first direction (991), the first sub-area (921) comprising a plurality of multiplexing unit groups, and the second sub-area (922) comprising a plurality of test unit groups, the driving unit (4) being configured to provide a driving signal to the gate line (12), the multiplexing unit (2) being configured to provide a data signal to the data line (11), and the test unit (3) being configured to provide a test signal to the data line (11); in the first sub-area (921), the driving unit groups and the multiplexing unit groups are arranged alternately; and in the second sub-area (922), the driving unit groups and the test unit groups are arranged alternately.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diode (OLED) display technology has been widely used in televisions, smartphones, wearable display devices, virtual reality (VR) displays, automotive displays and other fields due to its advantages such as being thin, flexible, shock resistant and fast response.

[0003] With the development of technology, a large screen-to-body ratio (i.e., the proportion of the actual display area in the total display area) has become one of the aesthetic characteristics pursued by display devices. In particular, for wearable display devices (such as smartwatches), based on considerations such as portability and viewing angle, ultra-narrow bezels or even full-screen displays have become an important development trend.

[0004] In some related technologies, circuits used to drive subpixels can be placed directly outside the display area of ​​the display substrate. Obviously, the area where the driving circuits are located cannot be directly displayed, hence the term "bezel" for the display device. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This disclosure provides a display substrate, including a display area and a peripheral area. The peripheral area includes a circuit area. The display area includes: a plurality of sub-pixels, a plurality of data lines extending along a first direction, and a plurality of gate lines extending along a second direction intersecting the first direction. Each data line connects to a plurality of sub-pixels, and each gate line connects to a plurality of sub-pixels.

[0007] The circuit region includes a first sub-region and a second sub-region opposite to each other on both sides of the display region along the first direction. The circuit region includes multiple driving unit groups. The first sub-region includes multiple multiplexing unit groups. The second sub-region includes multiple test unit groups. Each multiplexing unit group includes at least one multiplexing unit. Each test unit group includes at least one test unit. Each driving unit group includes at least one driving unit. The driving unit is configured to provide a driving signal to the gate line. The multiplexing unit is configured to provide a data signal to the data line. The test unit is configured to provide a test signal to the data line.

[0008] In the first sub-region, the drive unit group and the multiplexing unit group are alternately arranged; in the second sub-region, the drive unit group and the test unit group are alternately arranged.

[0009] In an exemplary embodiment, the circuit region further includes a connection sub-region located between the first sub-region and the second sub-region, the connection sub-region being configured to electrically connect the first sub-region and the second sub-region;

[0010] The circuit area also includes a signal line protection unit, which is located on the side of the connection sub-area away from the display area and is electrically connected to the signal line of the circuit area.

[0011] In an exemplary embodiment, the signal line protection unit includes at least one polysilicon resistor, and the circuit area further includes multiple signal lines, each of the at least one polysilicon resistor being connected between at least two of the signal lines.

[0012] In an exemplary embodiment, the signal lines include test signal lines connected to the test unit and drive signal lines connected to the drive unit. The drive signal lines include high-level lines and low-level lines. The test signal lines include test control lines and test data lines. At least one of the polysilicon resistors is connected to the test control lines and the high-level lines.

[0013] In an exemplary embodiment, the signal line includes a multiplexed signal line connected to the multiplexing unit and a test signal line connected to the test unit. The test signal line includes a test control line and a test data line. The multiplexed signal line includes a multiplexing control line and a multiplexing data line. At least one of the polysilicon resistors is connected to the test control line and the multiplexing control line.

[0014] In an exemplary embodiment, the signal line protection unit includes at least one electrostatic discharge unit, and the signal line includes a multiplexed signal line connected to the multiplexing unit, a test signal line connected to the test unit, and a drive signal line connected to the drive unit. Each of the at least one electrostatic discharge unit is connected to one signal line.

[0015] In an exemplary embodiment, the drive signal line includes a high-level line and a low-level line, the test signal line includes a test control line and a test data line, the multiplexed signal line includes a multiplexed control line and a multiplexed data line, at least one of the electrostatic discharge units is connected to the test control line, or at least one of the electrostatic discharge units is connected to the test data line, or at least one of the electrostatic discharge units is connected to the multiplexed control line.

[0016] In an exemplary embodiment, within the first sub-region, the number C of multiplexing units included in the multiplexing unit group between two adjacent drive unit groups and the size D of the gap between two adjacent drive unit groups satisfy the following relationship:

[0017] D = a*C + (C+1)*d1;

[0018] Where, a is the dimension of each multiplexing unit along the arrangement direction of the multiplexing units, d1 is the gap size between adjacent multiplexing units; and / or,

[0019] In the second sub-region, the number E of test units in the test unit group between two adjacent drive unit groups and the size F of the gap between two adjacent drive unit groups satisfy the following relationship:

[0020] F = b*E + (E+1)*d2;

[0021] Where b is the dimension of each test unit along the arrangement direction of the test units, and d2 is the gap size between adjacent test units.

[0022] In an exemplary embodiment, d1 is 1 micrometer to 5 micrometers, and d2 is 1 micrometer to 5 micrometers.

[0023] In an exemplary embodiment, the first sub-region includes a first arc region, and the second sub-region includes a second arc region;

[0024] In the first sub-area, the driving unit group and the multiplexing unit group are alternately arranged, specifically: in the first arc area, the driving unit group and the multiplexing unit group are alternately arranged along the edge of the first arc area near the display area;

[0025] In the second sub-area, the driving unit group and the test unit group are alternately arranged, specifically: in the second arc area, the driving unit group and the test unit group are alternately arranged along the edge of the second arc area near the display area.

[0026] In an exemplary embodiment, within the first arc region, the line trajectory connecting the center points of the coverage areas of the plurality of driving unit groups is the first arc trajectory, and the line trajectory connecting the center points of the coverage areas of the plurality of multiplexing unit groups is the second arc trajectory. The center points corresponding to the first arc trajectory and the second arc trajectory approximately coincide with the center point corresponding to the edge of the first arc region near the display area; and / or

[0027] In the second arc area, the line trajectory connecting the center points of the coverage areas of the multiple drive unit groups is the third arc trajectory, and the line trajectory connecting the center points of the coverage areas of the multiple test unit groups is the fourth arc trajectory. The center of the circle corresponding to the third arc trajectory and the center of the circle corresponding to the fourth arc trajectory roughly coincide with the center of the circle corresponding to the edge of the second arc area near the display area.

[0028] In an exemplary embodiment, the first arc region is semi-circular, and the second arc region is semi-circular.

[0029] In an exemplary embodiment, the first sub-region includes a first U-shaped ring region, the second sub-region includes a second U-shaped ring region, the first U-shaped ring region includes two segments of the first arc region and at least one segment of a second rectangular region, and the second U-shaped ring region includes two segments of the second arc region and at least one segment of a third rectangular region;

[0030] In the second rectangular region, a plurality of the multiplexing units are disposed along a side of the second rectangular region close to the display region;

[0031] In the third rectangular region, a plurality of the test units are disposed along a side of the third rectangular region close to the display region.

[0032] In an exemplary embodiment, the circuit region further includes a plurality of segments of a first rectangular region, and the first rectangular region is disposed between the first arc region and the second arc region;

[0033] In the first rectangular region, a plurality of the driving units are disposed along a side of the first rectangular region close to the display region.

[0034] In an exemplary embodiment, in the first sub-region, the multiplexing unit group includes a first multiplexing unit group and a second multiplexing unit group. The first multiplexing unit group includes M multiplexing units, the second multiplexing unit group includes N multiplexing units, where N and M are integers greater than 1, and M < N. The second multiplexing unit group is located in the middle of the first sub-region, and the first multiplexing unit group is located at both ends of the first sub-region away from the middle of the first sub-region;

[0035] and / or,

[0036] In the second sub-region, the test unit group includes a first test unit group and a second test unit group. The first test unit group includes K test units, the second test unit group includes L test units, where L and K are integers greater than 1, and K < L. The second test unit group is located in the middle of the second sub-region, and the first test unit group is located at both ends of the second sub-region away from the middle of the second sub-region.

[0037] In an exemplary embodiment, the peripheral region further includes a connection region on a side of the first sub-region away from the display region. The connection region includes a plurality of connectors, and at least some of the connectors are connected to signal lines. The signal lines include: a multiplexing signal line connected to the multiplexing unit, a test signal line connected to the test unit, and a driving signal line connected to the driving unit.

[0038] In an exemplary embodiment, the peripheral area further includes a fan-out area disposed between the connector area and the first sub-area, the fan-out area including a plurality of the multiplexed signal lines.

[0039] In an exemplary embodiment, the multiplexed signal line includes multiple multiplexed control lines and multiple multiplexed data lines;

[0040] At least one of the multiplexing units includes a plurality of multiplexing transistors; the gate of each multiplexing transistor is connected to a multiplexing control line, the first terminal is connected to a data line, and the second terminal is connected to a multiplexing data line;

[0041] The second terminals of all multiplexing transistors in the same multiplexing unit are connected to the same multiplexing data line, and the second terminals of multiplexing transistors in different multiplexing units are connected to different multiplexing data lines.

[0042] In an exemplary embodiment, the test signal line includes a test control line and a test data line; at least one test unit includes a plurality of test transistors; the gate of each test transistor is connected to a test control line, the first electrode is connected to a data line, and the second electrode is connected to a test data line; each test data line is connected to a plurality of test units.

[0043] This disclosure also provides a display device, including: a display substrate as described in any of the preceding embodiments.

[0044] Other aspects will become clear after reading and understanding the accompanying drawings and embodiments of this disclosure. Attached Figure Description

[0045] The accompanying drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0046] Figure 1 This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure;

[0047] Figure 2 A schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure (some leads are not shown);

[0048] Figure 3 A circuit diagram of a pixel circuit in a display substrate provided in an embodiment of this disclosure;

[0049] Figure 4 This is a schematic diagram of another display substrate provided in an embodiment of the present disclosure;

[0050] Figure 5 A schematic diagram of another display substrate provided in an embodiment of this disclosure (some leads are not shown);

[0051] Figure 6 A circuit diagram of a multiplexing unit in a display substrate provided for an embodiment of this disclosure;

[0052] Figure 7 A circuit diagram of a test unit in a display substrate provided in an embodiment of this disclosure;

[0053] Figure 8 A circuit diagram of another test unit in a display substrate provided in an embodiment of this disclosure;

[0054] Figure 9 A circuit diagram of a gate shift register in a display substrate provided for embodiments of this disclosure;

[0055] Figure 10 A driving timing diagram of a gate shift register in a display substrate provided in an embodiment of this disclosure;

[0056] Figure 11 A circuit diagram of a control pole shift register in a display substrate provided for embodiments of this disclosure;

[0057] Figure 12 A driving timing diagram of a control pole shift register in a display substrate provided in an embodiment of this disclosure;

[0058] Figure 13 This is a partial structural diagram of a connection sub-region in a display substrate provided in an embodiment of the present disclosure;

[0059] Figure 14 This disclosure provides a schematic diagram of the distribution density of different units in a display substrate;

[0060] Figure 15 This disclosure provides a schematic diagram of the distribution density of different units in another display substrate;

[0061] Figure 16 A circuit diagram of an electrostatic discharge unit in a display substrate provided in an embodiment of this disclosure;

[0062] Figure 17 A partial structural schematic diagram of a compensation capacitor unit in a display substrate provided in an embodiment of this disclosure;

[0063] In the accompanying drawings of the embodiments of this disclosure, the meanings of the reference numerals are as follows:

[0064] 1. Subpixel; 11. Data line; 12. Gate line; 13. Control line; 19. Anode signal line;

[0065] 2. Multiplexing unit; 21. Multiplexing transistor;

[0066] 3. Test unit; 31. Test transistor; 311. First test transistor; 312. Second test transistor; 313. Third test transistor; 314. Fourth test transistor; 315. Fifth test transistor;

[0067] 4. Driving unit; 41. Gate driving unit; 42. Control electrode driving unit;

[0068] 5. Compensation capacitor unit; 51. Compensation capacitor;

[0069] 6. Connector; 62. Multiplexed signal line; 621. Multiplexed control line; 622. Multiplexed data line; 63. Test signal line; 631. Test control line; 6311. First test control line; 6312. Second test control line; 6313. Third test control line; 632. Test data line; 6321. First test data line; 6322. Second test data line; 6323. Third test data line;

[0070] 64. Drive signal line; 641. High-level line; 642. Low-level line;

[0071] 71. Polysilicon resistor; 711. First polysilicon resistor; 712. Second polysilicon resistor; 72. Electrostatic discharge unit; 721. First discharge transistor; 722. Second discharge transistor;

[0072] 91. Display area; 92. Circuit area; 921. First sub-area; 922. Second sub-area; 923. Connection sub-area; 93. Fan-out area; 94. Connector area; 95. Capacitor area; 991. First direction; 992. Second direction;

[0073] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; Cst, storage capacitor; Reset, first reset terminal; Reset', second reset terminal; Vinit, initialization terminal; Gate, gate line terminal; Data, data line terminal; EM, control electrode line terminal; VDD, anode signal terminal; VSS, cathode signal terminal;

[0074] K1, First gate transistor; K2, Second gate transistor; K3, Third gate transistor; K4, Fourth gate transistor; K5, Fifth gate transistor; K6, Sixth gate transistor; K7, Seventh gate transistor; K8, Eighth gate transistor; C1, First gate capacitor; C2, Second gate capacitor; N1, First gate node; N2, Second gate node; N3, Third gate node;

[0075] M1, First gate transistor; M2, Second gate transistor; M3, Third gate transistor; M4, Fourth gate transistor; M5, Fifth gate transistor; M6, Sixth gate transistor; M7, Seventh gate transistor; M8, Eighth gate transistor; M9, Ninth gate transistor; M10, Tenth gate transistor; C1', First gate capacitor; C2', Second gate capacitor; C3', Third gate capacitor; N1', First gate node; N2', Second gate node; N3', Third gate node; N4', Fourth gate node. Detailed Implementation

[0076] To enable those skilled in the art to better understand the technical solutions of the embodiments of this disclosure, the display substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0077] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms and should not be construed as limited to the embodiments set forth in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of this disclosure.

[0078] Embodiments of this disclosure can be described with reference to plan views and / or cross-sectional views, taking into account the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0079] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0080] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0081] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0082] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0083] In the embodiments of this disclosure, the size of each component, the thickness of a layer, or the area shown in the accompanying drawings is sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0084] In this embodiment of the disclosure, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of constituent elements, rather than to limit the quantity.

[0085] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of this specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as needed.

[0086] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure based on the specific circumstances.

[0087] In this embodiment of the disclosure, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0088] In the embodiments disclosed herein, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0089] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0090] In this embodiment of the disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than -10° and less than 10°, and therefore also includes a state in which the angle is greater than -5° and less than 5°. In addition, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than 80° and less than 100°, and therefore also includes a state in which the angle is greater than 85° and less than 95°.

[0091] In this embodiment of the disclosure, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0092] In this embodiment of the disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0093] Firstly, referring to Figures 1 to 2 , Figures 4 to 5 This disclosure provides a display substrate.

[0094] The display substrate of this disclosure is a substrate used in a display device, such as an array substrate having a thin-film transistor (TFT) array.

[0095] The display substrate of this embodiment includes a display area 91 and a peripheral area surrounding the display area 91. The peripheral area includes a capacitor area 95, a circuit area 92, a fan-out area 93, and a connector area 94.

[0096] The display area 91 includes: a plurality of sub-pixels 1; a plurality of data lines 11 extending along a first direction 991, each data line 11 connecting to a plurality of sub-pixels 1; and a plurality of gate lines 12 extending along a second direction 992 intersecting the first direction 991, each gate line 12 connecting to a plurality of sub-pixels 1.

[0097] The circuit area 92 surrounds the display area 91. The circuit area 92 includes a first sub-area 921 and a second sub-area 922 located opposite each other on both sides of the display area 91 along a first direction 991. The first sub-area 921 includes a plurality of multiplexing unit groups, which are configured to provide data signals to a plurality of data lines 11. Each multiplexing unit group includes at least one multiplexing unit 2. The second sub-area 922 includes a plurality of test unit groups, which are configured to provide test signals to a plurality of data lines 11. Each test unit group includes at least one test unit 3. The circuit area 92 also includes a plurality of drive unit groups, which include at least one drive unit 4. In the first sub-area 921, the drive unit groups and the multiplexing unit groups are alternately arranged circumferentially. In the second sub-area 922, the drive unit groups and the test unit groups are alternately arranged circumferentially.

[0098] The capacitor area 95 is located between the second sub-area 922 and the display area 91. The capacitor area 95 includes multiple compensation capacitor units 5, and each compensation capacitor unit 5 is connected to a data line 11.

[0099] The connector area 94 is located on the side of the first sub-area 921 away from the display area 91. The connector area 94 includes a plurality of connectors 6, at least some of which are connected to signal lines. The signal lines include a multiplexed signal line 62 connected to the multiplexing unit 2, a test signal line 63 connected to the test unit 3, and a drive signal line 64 connected to the drive unit 4.

[0100] Fan-out area 93 is located between connector area 94 and first sub-area 921. Fan-out area 93 includes multiple multiplexed signal lines 62.

[0101] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The display substrate of this embodiment is divided into multiple regions, with the display area 91 (or AA region) located in the middle for display, and the sub-pixel 1 (or sub-pixel) for display located in the display area 91.

[0102] Here, subpixel 1 refers to the smallest structure that can be used to independently display the required content, that is, the smallest "point" that can be independently controlled in the display device.

[0103] The specific form of sub-pixel 1 can vary, as long as it can be displayed independently.

[0104] For example, sub-pixel 1 may include a pixel circuit that can emit light of the desired brightness under the control of corresponding gate lines 12, data lines 11, etc. For instance, the pixel circuit may be a 7T1C structure (i.e., including 7 transistors and 1 capacitor), see reference... Figure 3 The pixel circuit of the above 7T1C may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor Cst, an organic light-emitting diode (OLED), a first reset terminal Reset, a second reset terminal Reset', an initialization terminal Vinit, a gate terminal Gate, a data terminal Data, a control terminal EM, an anode signal terminal VDD, and a cathode signal terminal VSS, etc.; wherein, each transistor can be a P-type transistor (such as PMOS). The data terminal Data can be connected to data line 11, the gate terminal Gate can be connected to gate line 12, the control terminal EM can be connected to control line 13, the first reset terminal Reset and the second reset terminal Reset' can be simultaneously connected to the gate line of the previous row, the second reset terminal Reset' can also be connected to the gate line of the current row, and the other terminals can also be connected to the corresponding signal sources.

[0105] In other words, in each sub-pixel 1 of the display substrate in this embodiment, an organic light-emitting diode (OLED) can be used as the light-emitting device. Specifically, it is an organic light-emitting diode display substrate, which is also an array substrate with a thin-film transistor (TFT) array.

[0106] Different sub-pixels 1 can have different colors, thus achieving color display through the mixing of light from different sub-pixels 1. To achieve color display, multiple sub-pixels 1 of different colors arranged together can form a "pixel (or pixel unit)," meaning the light emitted by these sub-pixels 1 mixes together to form a visual "dot." For example, three sub-pixels 1 of red, green, and blue colors can form a single pixel. Alternatively, there may not be a defined pixel (or pixel unit), but color display can be achieved through the "sharing" of adjacent sub-pixels 1.

[0107] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5The display area 91 is further provided with a data line 11 extending along a first direction 991 and a gate line 12 extending along a second direction 992. The first direction 991 intersects with the second direction 992 (i.e., they are not parallel to each other). Thus, each intersection of the data line 11 and the gate line 12 can define a sub-pixel 1. Through the joint control of the gate line 12 and the data line 11, the sub-pixel 1 at the intersection of the two can be displayed.

[0108] In some embodiments, the first direction 991 is perpendicular to the second direction 992, that is, the first direction 991 may be a column direction ( Figure 1 , Figure 2 , Figure 4 , Figure 5 The middle direction is vertical), and the second direction 992 can be the row direction perpendicular to the column direction ( Figure 1 , Figure 2 , Figure 4 , Figure 5 (The middle part is horizontal).

[0109] It should be understood that the first direction 991 and the second direction 992 are actually just two relative directions corresponding to the data line 11 and the gate line 12. They are not necessarily column directions or row directions, and have no necessary relationship with the shape, position, or placement of the display substrate (or display device).

[0110] In some embodiments, the sub-pixels 1 in the display area 91 can be arranged in an array, that is, the sub-pixels 1 can be arranged in multiple rows and columns, wherein each row of sub-pixels 1 is connected to a gate line 12, and each column of sub-pixels 1 is connected to a data line 11.

[0111] It should be understood that sub-pixels 1 are not necessarily arranged in an array, and each data line 11 and gate line 12 are not necessarily connected to sub-pixels 1 in the same column or row.

[0112] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The area outside the display area 91 is the circuit area 92 surrounding it, so the display area 91 is ring-shaped as a whole. Since the peripheral area does not display, it corresponds to the "bezel" of the display device.

[0113] The peripheral area includes the circuit area 92 surrounding the display area 91; therefore, the circuit area 92 is also ring-shaped. It includes a first sub-area 921 and a second sub-area 922 arranged opposite each other on both sides of the display area 91 along the first direction 991, such as... Figure 1 , Figure 2 The "lower half" and "upper half" of the region. The first sub-region 921 includes multiple multiplexing units 2 (MUX), each multiplexing unit 2 starting from one side (…). Figure 1 , Figure 2 , Figure 4 , Figure 5 The lower section (center) connects to the data line 11, which provides a data signal (data voltage) to the data line 11 during display; while the second sub-area 922 includes multiple test units 3 (CTs), each test unit 3 connected from the other side (…). Figure 1 , Figure 2 , Figure 4 , Figure 5 The middle (top) connects to the data line 11, which is used to provide test signals to the data line 11 during the testing phase to detect whether there are defects in the display substrate.

[0114] In addition, the circuit area 92 is provided with multiple drive units 4 to provide other drive signals.

[0115] In some embodiments, at least a portion of the driving units 4 are configured to provide driving signals to the gate lines 12, that is, at least a portion of the driving units 4 are connected to the gate lines 12 and are used to provide signals to the gate lines 12 to control the operation of the sub-pixels 1 connected to the corresponding gate lines 12.

[0116] As can be seen, the multiplexing units 2 constitute multiple "multiplexing unit groups," each multiplexing unit group including one multiplexing unit 2, or multiple multiplexing units 2 arranged consecutively; the test units 3 constitute multiple "test unit groups," each test unit group including one test unit 3, or multiple test units 3 arranged consecutively; the drive units 4 constitute multiple "drive unit groups," each drive unit group including one drive unit 4, or multiple drive units 4 arranged consecutively. Therefore, different units are provided in the circuit area 92, and these units are "mixed."

[0117] Specifically, refer to Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 14 , Figure 15 In the first sub-region 921, the drive unit group and the multiplexing unit group are alternately arranged along the "circumferential direction".

[0118] "Circumferential direction" refers to the direction of rotation around the center of a planar figure, or the direction of rotation around the edge of the figure, either clockwise or counterclockwise.

[0119] That is, in this embodiment of the present disclosure, when traversing the substantially circular circuit region 92 in a clockwise or counterclockwise manner, in the first sub-region 921, the driving unit group and the multiplexing unit group appear alternately, i.e., one driving unit group - one multiplexing unit group - one driving unit group - one multiplexing unit group... and so on. Of course, each "group" includes one or more consecutive corresponding units, so the driving unit 4 and the multiplexing unit 2 in the first sub-region 921 are "mixed (but each type of unit may be arranged in multiple consecutive rows)", rather than being concentrated in different positions in the first sub-region 921 respectively.

[0120] Specifically, Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 14 , Figure 15 In the second sub-region 922, the drive unit group and the test unit group are alternately arranged along the circumferential direction.

[0121] That is, when traversing the essentially circular circuit region 92 in a clockwise or counterclockwise manner, in the second sub-region 922, drive unit groups and test unit groups appear alternately, i.e., one drive unit group - one test unit group - one drive unit group - one test unit group... and so on. Of course, each "group" includes one or more consecutive corresponding units, so the drive unit 4 and test unit 3 in the second sub-region 922 are "mixed (but each type of unit may have multiple consecutive units arranged together)," rather than being concentrated in different positions in the first sub-region 921.

[0122] In one exemplary embodiment, in the first sub-region 921, the number C of multiplexing units 2 included in the multiplexing unit group between two adjacent drive unit groups and the size of the gap D between the two adjacent drive unit groups satisfy the following relationship:

[0123] D = a*C + (C+1)*d1;

[0124] Where a is the dimension of each multiplexing unit 2 along the arrangement direction of the multiplexing unit 2, and d1 is the gap size between adjacent multiplexing units 2.

[0125] In one exemplary embodiment, in the second sub-region 922, the number E of test units 3 included in the test unit group between two adjacent drive unit groups and the size of the gap F between two adjacent drive unit groups satisfy the following relationship:

[0126] F = b*E + (E+1)*d2;

[0127] Where b is the dimension of each test unit 3 along the arrangement direction of the test units 3, and d2 is the gap size between adjacent test units 3.

[0128] In one exemplary embodiment, the gap between two adjacent units (such as multiplexing unit 2, test unit 3, and drive unit 4) is 1 micrometer to 5 micrometers. For example, the gap between two adjacent drive units 4 (or two adjacent multiplexing units 2 or two adjacent test units 3) can be 1.5 micrometers, the gap between adjacent drive units 4 and multiplexing units 2 can be 1.5 micrometers, the gap between adjacent drive units 4 and test units 3 can be 1.5 micrometers, etc.

[0129] The “gap” mentioned above refers to the shortest straight-line distance between devices belonging to two adjacent units.

[0130] Obviously, each circuit in circuit area 92 also requires certain signals to work. Therefore, the peripheral area also includes connector area 94 for introducing these signals. Connector area 94 includes multiple connectors 6, and connectors 6 are connected to signal lines. The signal lines may include multiplexed signal lines 62, test signal lines 63, drive signal lines 64, etc., which supply power to multiplexing unit 2, test unit 3, and drive unit 4 respectively. Of course, each type of signal line is connected to the corresponding unit and connector 6.

[0131] Among them, connector 6 (Pad or Pin) refers to the structure in the display substrate that can acquire other signals and introduce the signals into the signal line.

[0132] Specifically, connector 6 can be used to bond with a flexible printed circuit board (FPC) or driver chip to obtain signals from the FPC or driver chip.

[0133] Alternatively, connector 6 can also be used to contact the test probe of the test device to obtain a signal from the test probe.

[0134] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The connector area 94 is located on the side of the circuit area 92 away from the display area 91 (i.e., the outer side). A fan-out area 93 is also provided between the connector area 94 and the first sub-area 921. The fan-out area 93 includes multiple multiplexed signal lines 62. That is, after the multiplexed signal lines 62 are led out from the connector area 94, they pass through the fan-out area 93 and are connected to the corresponding multiplexing unit 2.

[0135] Generally speaking, the number of multiplexed signal lines 62 is much greater than the total number of test signal lines 63 and drive signal lines 64. Therefore, by setting the fan-out area 93 between the connector area 94 and the first sub-area 921 of the multiplexing unit 2, the large number of multiplexed signal lines 62 can be connected to the multiplexing unit 2 "nearby". Although the drive signal lines 64 and test signal lines 63 need to extend a long distance to connect to the drive unit 4 and test unit 3, the total length of their leads will not be too large because the number of drive signal lines 64 and test signal lines 63 is small. Thus, the above design can reduce the total length of the leads and the layout area occupied, reduce the bezel of the display device, and increase the screen-to-body ratio.

[0136] Of course, in addition to the multiplexed signal line 62, a portion of the drive signal line 64 and the test signal line 63 may also be located in the fan-out area 93.

[0137] Reference Figure 1 , Figure 2 Because the second sub-region 922 is located on the side ( Figure 1 , Figure 2 There is no fan-out area 93 on the upper side of the display area 91, so there is still space on this side to set other structures. Therefore, a capacitor area 95 can be set between the second sub-area 922 and the display area 91. The capacitor area 95 is provided with multiple compensation capacitor units 5 connected to the data lines 11 to compensate for the capacitance difference of different data lines 11. Its function will be described in detail later.

[0138] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 In the display substrate of this embodiment, the various units (multiplexing unit 2, test unit 3, and drive unit 4) are mixed and arranged, so that each unit can provide signals to the corresponding data line 11, gate line 12, etc. nearby; at the same time, the various structures are relatively evenly distributed, making full use of the space at each position of the display substrate, reducing the bezel of the display device, and improving the screen occupancy ratio.

[0139] In some embodiments, the first sub-region 921 includes a first arc region, and the second sub-region 922 includes a second arc region. The first arc region 921 is closer to the center of the display area 91 than the second arc region is closer to the center of the display area 91.

[0140] Reference Figure 1 , Figure 2 , Figure 14 The first sub-region 921 and the second sub-region 922 may include an "arc-shaped (ring-shaped)" portion.

[0141] For example, the main surface of the display substrate may be substantially circular, and the display area 91 may also be substantially circular, so that the circuit area 92 is substantially annular surrounding the circular display area 91, and the first sub-area 921 and the second sub-area 922 are respectively "half annular" ( Figure 1 , Figure 2 The middle part consists of an "upper semicircle" and a "lower semicircle", and the openings of the two parts are opposite each other.

[0142] Moreover, the edge of the first arc area (first sub-area 921) near the display area 91 is closer to the center of the display area 91 than the edge of the second arc area (second sub-area 922) near the display area 91; or, in other words, the inner side of the first arc area is "smaller" than the inner side of the second arc area, because the inner side of the second sub-area 922 is also provided with a capacitor area 95.

[0143] In some embodiments, the centers of the first arc region (first sub-region 921) and the second arc region (second sub-region 922) are the same, and the radius of the first arc region near the edge of the display area 91 is 210 to 420 μm smaller than the radius of the second arc region near the edge of the display area 91.

[0144] For example, the first and second arc regions can be concentric, and the difference between their inner diameters can be 210–420 μm (the inner diameter of the first arc region is smaller), and further can be 250–350 μm.

[0145] The main surface of the display substrate can be one side surface of its substrate, that is, the surface of the substrate of the display substrate in this embodiment can be circular.

[0146] The substrate is the foundation for supporting other structures on the display substrate. It is a sheet-like structure made of materials such as glass, silicon (such as single crystal silicon), and polymer materials (such as polyimide). It can be rigid or flexible, and its thickness can be on the order of millimeters.

[0147] In this embodiment of the disclosure, "A is essentially B" means that, on the overall scale of A, it conforms to feature B, but from a scale significantly smaller than A as a whole, A may not perfectly conform to feature B. For example, "A is essentially circular" means that A can be a perfect circle or ellipse, or that the overall shape of A is circular or elliptical, but some of its detailed structures are not strictly circular: for example, the boundary of A may have a small portion of straight lines, broken lines, etc.; for example, the boundary of A may have some convex or concave parts; for example, the boundary of A may have a small portion of arcs that are approximately arcs but not strictly arcs; for example, the boundary of A at different locations may be arcs with different diameters, etc.

[0148] Reference Figure 1 , Figure 2When the circuit area 92 is "circular", most of its positions correspond to data lines 11 and gate lines 12 at the same time (that is, there are corresponding sub-pixels 1 in both the row and column directions). Therefore, in this case, the multiplexing unit 2, test unit 3 and drive unit 4 in the circuit area 92 are mixed together, which is most conducive to each unit being connected to the corresponding data lines 11, gate lines 12, etc. nearby.

[0149] Of course, the above shapes are not a limitation on the specific form of the display substrate and its various regions; the display substrate and its various regions may also be in other shapes.

[0150] For example, in some other embodiments, the first sub-region 921 includes a first U-shaped ring region, and the second sub-region 922 includes a second U-shaped ring region.

[0151] Reference Figure 4 , Figure 5 , Figure 15 As another embodiment of this disclosure, the main surface of the display substrate may also be substantially an arc-shaped rectangle, and the display area 91 may also be substantially an arc-shaped rectangle, so that the circuit area 92 is substantially an arc-shaped rectangular ring surrounding the circular display area 91.

[0152] Therefore, the first sub-region 921 and the second sub-region 922 are respectively "U-shaped rings" ( Figure 4 , Figure 5 The two U-shaped rings are the "upper U-shaped ring" and the "lower U-shaped ring", and their openings are opposite each other. Of course, the bottom of the U-shaped ring is a straight line, not an arc.

[0153] Among them, "arc-angled rectangle" refers to a shape that is similar to a rectangle, with four straight sides, but the difference from a rectangle is that its four corners are not right angles, but rather "arc-angled" with a relatively uniform transition. It can also be called "rounded corners". That is, "arc-angled rectangle" can also be called "rounded rectangle".

[0154] Correspondingly, circuit area 92 is an "arc-cornered rectangular ring," that is, an annular region sandwiched between two "arc-cornered rectangles" of different sizes, so it can also be regarded as a "hollow arc-cornered rectangle." Of course, furthermore, circuit area 92 can also be a "rounded rectangular ring" (i.e., a "hollow rounded rectangle").

[0155] In some embodiments, the width of the first U-shaped ring region (i.e., the distance between the two straight sections of the U-shape) is approximately equal to the width of the second U-shaped ring region, and the height of the first U-shaped ring region (i.e., the distance from the bottom of the U-shape to its opening) is approximately equal to the height of the second U-shaped ring region.

[0156] Reference Figure 4 , Figure 5 The dimensions of the first U-shaped ring region and the second U-shaped ring region can be basically the same, so the two can be basically "symmetrical from top to bottom".

[0157] In some embodiments, the inner edge of the first U-shaped ring area (i.e., the outer edge of the display area 91) includes two first arc-shaped boundaries, and the inner edge of the second U-shaped ring area (i.e., the outer edge of the display area 91) includes two second arc-shaped boundaries. The inner edge of the circuit area (i.e., the outer edge of the display area 91) further includes: two first straight-line boundaries extending along the first direction 991 (each first straight-line boundary spans the first sub-area 921 and the second sub-area 922), a second straight-line boundary extending along the second direction 992 (belonging to the first sub-area 921), and a third straight-line boundary (belonging to the second sub-area 922).

[0158] Of course, it should be understood that the outer edges of the first sub-region 921 and the second sub-region 922 (i.e. the outer edge of the circuit region 92) should have a shape that is basically similar to their inner edges.

[0159] Furthermore, at any point on the inner edge of the circuit region 92, the distance from the outer edge along the normal direction can be the same, that is, the "width" of each position in the circuit region 92 can be the same.

[0160] In some embodiments, in the first sub-region 921 and the second sub-region 922, a plurality of driving units 4 are arranged along a first straight boundary; in the first sub-region 921, a plurality of multiplexing units 2 are arranged along a second straight boundary; and in the second sub-region 922, a plurality of testing units 3 are arranged along a third straight boundary.

[0161] In some embodiments, in the first sub-region 921, the driving unit 4 and the multiplexing unit 2 are alternately arranged along the first arc-shaped boundary; in the second sub-region 922, the driving unit 4 and the testing unit 3 are alternately arranged along the second arc-shaped boundary.

[0162] That is, refer to Figure 4 , Figure 5 When the first sub-region 921 and the second sub-region 922 are in the form of the above "arc-angled rectangular ring", different units can be mixed only at the "arc-angle of the rectangular ring", while only one type of unit is used at the "straight edge of the rectangular ring".

[0163] In some embodiments, in the first sub-region 921, the line trajectory connecting the center points of the coverage areas of the multiple drive unit groups is a first arc trajectory, and the line trajectory connecting the center points of the coverage areas of the multiple multiplexing unit groups is a second arc trajectory. The center of the circle corresponding to the first arc trajectory, the center of the circle corresponding to the second arc trajectory, and the center of the circle corresponding to the first arc boundary roughly coincide.

[0164] In this embodiment, the centers of the first circular arc trajectory, the second circular arc trajectory, and the center of the first arc-shaped boundary are substantially coincident, which means that the centers of the first circular arc trajectory, the second circular arc trajectory, and the center of the first arc-shaped boundary can be completely coincident, or the distance between each center is less than 10 micrometers.

[0165] In some embodiments, in the second sub-region 922, the trajectory of the connection lines of the center points of the coverage areas of multiple driving unit groups is the third circular arc trajectory, and the trajectory of the connection lines of the center points of the coverage areas of multiple test unit groups is the fourth circular arc trajectory. The centers of the third circular arc trajectory and the fourth circular arc trajectory are substantially coincident with the center of the second arc-shaped boundary.

[0166] In this embodiment, the centers of the third circular arc trajectory, the fourth circular arc trajectory, and the center of the second arc-shaped boundary are substantially coincident, which means that the centers of the third circular arc trajectory, the fourth circular arc trajectory, and the center of the second arc-shaped boundary can be completely coincident, or the distance between each center is less than 10 micrometers.

[0167] That is, referring to Figure 4 、 Figure 5 , in each sub-region, each type of unit at the corresponding arc-shaped boundary is arranged along a circular trajectory, and the circles corresponding to the circular trajectories of the two types of units at the same arc-shaped boundary, and the corresponding circle of the arc-shaped boundary itself, are concentric or substantially concentric.

[0168] In some embodiments, in the first sub-region 921, the multiplexing unit group includes a first multiplexing unit group and a second multiplexing unit group. The first multiplexing unit group includes M multiplexing units 2, and the second multiplexing unit group includes N multiplexing units 2. N and M are integers greater than 1, and M < N. The second multiplexing unit group is located in the middle of the first sub-region 921, and the first multiplexing unit group is located at both ends of the first sub-region 921 far from the middle of the first sub-region 921;

[0169] And / or,

[0170] In the second sub-region 922, the test unit group includes a first test unit group and a second test unit group. The first test unit group includes K test units 3, and the second test unit group includes L test units. L and K are integers greater than 1, and K < L. The second test unit group is located in the middle of the second sub-region 922, and the first test unit group is located at both ends of the second sub-region 922 far from the middle of the second sub-region 922.

[0171] At least one second multiplexing unit group is provided in the middle of the first sub-region 921 (i.e., at the top of the semicircular ring), and each second multiplexing unit group includes N multiplexing units 2; while at both ends of the first sub-region 921 (i.e., at both ends of the semicircular ring or the open side), at least one first multiplexing unit group is provided, and each first multiplexing unit group includes M multiplexing units 2, where M is less than N.

[0172] That is, the middle of the first sub-region 921 has a larger number of multiplexing units 2 included in the multiplexing unit group (second multiplexing unit group), while the two ends of the first sub-region 921 have a smaller number of multiplexing units 2 included in the multiplexing unit group (first multiplexing unit group). Therefore, overall, the middle of the first sub-region 921 has a larger number of multiplexing units 2 and a smaller number of driving units 4, while the two ends of the first sub-region 921 have a smaller number of multiplexing units 2 and a larger number of driving units 4.

[0173] In some embodiments, N can be 7, 6, or 5; while in other embodiments, M can be 1, 2, or 3.

[0174] In some embodiments, there may be other multiplexing unit groups between the first multiplexing unit group and the second multiplexing unit group, and the number of multiplexing units in these multiplexing unit groups may be greater than M and less than N.

[0175] At least one second test unit group is provided in the middle of the second sub-region 922 (i.e., at the top of the semicircular ring), and each second test unit group includes L test units 3; while at both ends of the second sub-region 922 (i.e., at both ends of the semicircular ring or the open side), at least one first test unit group is provided, and each first test unit group includes K test units 3, where K is less than L.

[0176] That is, the test unit group (second test unit group) in the middle of the second sub-region 922 includes a larger number of test units 3, while the test unit groups (first test unit groups) at both ends of the first sub-region 921 include a smaller number of test units 3. Therefore, overall, the middle of the second sub-region 922 has a larger number of test units 3 and a smaller number of drive units 4, while the ends of the second sub-region 922 have a smaller number of test units 3 and a larger number of drive units 4.

[0177] In some embodiments, L can be 7, 6, or 5; while in other embodiments, K can be 1, 2, or 3.

[0178] In some embodiments, there may be other test unit groups between the first test unit group and the second test unit group, and the number of test units in these test unit groups may be greater than K and less than L.

[0179] In some embodiments, in the first sub-region 921, in the direction from both ends of the first sub-region 921 to the middle of the first sub-region 921, the distribution density of the driving unit 4 gradually decreases, and the distribution density of the multiplexing unit 2 gradually increases.

[0180] In the second sub-region 922, the distribution density of the driving unit 4 gradually decreases and the distribution density of the test unit 3 gradually increases in the direction from both ends of the second sub-region 922 to the middle of the second sub-region 922.

[0181] In each sub-region of circuit region 92, the distribution density of driving unit 4 gradually decreases in the direction from both ends of the sub-region (i.e., the position adjacent to another sub-region) to the middle of the sub-region (i.e., the position furthest from another sub-region). Meanwhile, the distribution density of test unit 3 gradually increases.

[0182] The increase in the distribution density of unit A along a certain direction does not mean that the number of unit A at each alternating location along that direction increases sequentially. Rather, it means that the number of unit A along that direction gradually increases in terms of the overall distribution over a relatively large area.

[0183] The decrease in the distribution density of unit A along a certain direction does not mean that the number of unit A at each alternating location along that direction decreases sequentially. Rather, it means that the number of unit A along that direction gradually decreases in terms of the overall distribution over a relatively large area.

[0184] For example, when the first sub-region 921 and the second sub-region 922 respectively include the first arc region and the second arc region, refer to Figure 1 , Figure 2 In the two semi-circular sub-regions above, the closer to the apex of the semi-circular ring ( Figure 1 , Figure 2 At the top and bottom sides, the number of rows of sub-pixel 1 corresponding to the same arc length (or the corresponding number of gate lines 12) is less (i.e., the number of corresponding gate lines 12 is less), while the number of columns of sub-pixel 1 corresponding to the same arc length (or the corresponding number of corresponding data lines 11 is more); conversely, at the ends or opening sides of the two semicircles (the middle of the longitudinal direction in each figure), the number of columns of sub-pixel 1 corresponding to the same arc length (or the corresponding number of corresponding data lines 11) is less (i.e., the number of corresponding sub-pixel 11 is less), while the number of rows of sub-pixel 1 corresponding to the same arc length (or the corresponding number of gate lines 12 is more).

[0185] Therefore, refer to Figure 1 , Figure 2If each unit is to be connected to the corresponding row and column as close as possible, then the closer to the top of the semicircular ring, the more multiplexing units 2 or test units 3 should be, and the fewer drive units 4 should be; conversely, the closer to the opening of the semicircular ring, the fewer multiplexing units 2 or test units 3 should be, and the more drive units 4 should be. That is, the "distribution density" of each drive unit 4 conforms to the above rules.

[0186] Of course, the specific distribution location and quantity in each unit circuit area 92 should be determined according to the specific distribution location and quantity of gate lines 12, data lines 11, etc. in the display area 91, so as to make each unit as close as possible to its own connecting leads.

[0187] For example, when the first sub-region 921 and the second sub-region 922 are respectively the first U-shaped ring region and the second U-shaped ring region mentioned above, refer to Figure 4 , Figure 5 The distribution density of multiplexing unit 2, test unit 3, and drive unit 4 also conforms to the above pattern.

[0188] That is, in the two U-shaped ring regions mentioned above, the closer to the top of the U-shaped ring region ( Figure 4 , Figure 5 At the top and bottom ends of the middle section, the fewer rows of sub-pixel 1 corresponding to the same side length range (i.e., the fewer gate lines 12), the more columns of sub-pixel 1 (i.e., the more data lines 11); conversely, the closer to the two ends of the two U-shaped ring regions ( Figure 4 , Figure 5 At the middle of the longitudinal direction, the fewer columns of sub-pixel 1 corresponding to the same side length range (i.e., the fewer data lines 11), the more rows of sub-pixel 1 (i.e., the more gate lines 12).

[0189] Therefore, refer to Figure 4 , Figure 5 If each unit is to be connected to the corresponding row and column as close as possible, then the number of multiplexing units 2 or test units 3 should be more and the number of drive units 4 should be less as they are closer to the top of the U-shaped ring area; conversely, the number of multiplexing units 2 or test units 3 should be less and the number of drive units 4 should be more as they are closer to the two ends of the U-shaped ring area. That is, the "distribution density" of each drive unit 4 conforms to the above rules.

[0190] Among them, Figure 1 , Figure 2 ,According to Figure 4 , Figure 5 In order to clearly represent other structures, the number of each element is relatively small. Therefore, for more detailed information on the distribution density of each element, please refer to [reference needed]. Figure 14 and Figure 15 As shown.

[0191] In some embodiments, the circuit area 92 is divided into a first half-area and a second half-area that are opposite each other on both sides of the display area 91 along the second direction 992;

[0192] The driving unit 4 includes multiple gate driving units 41;

[0193] The first half-region includes a plurality of gate driving units 41, which are configured to provide gate driving signals to a plurality of gate lines 12.

[0194] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The circuit area 92 can also be divided into two "half-areas" opposite each other on both sides of the display area 91 along the second direction 992, and each "half-area" is also basically a semi-circular ring (e.g. Figure 1 , Figure 2 (left and right semicircular rings) or U-shaped (e.g.) Figure 4 , Figure 5 (The left and right half of the U-shaped ring).

[0195] Since the gate line 12 extends along the second direction 992, all gate lines 12 correspond to the first half-region ( Figure 1 , Figure 2 The left semicircle in the middle, or Figure 4 , Figure 5 The left half of the U-shaped ring in the first half region), therefore, the driving unit 4 in the first half region may include a gate driving unit 41 that provides gate driving signals to multiple gate lines 12 (furthermore, all driving units 4 in the first half region 921 may be gate driving units 41), so that the gate driving unit 41 can be connected to the corresponding gate line 12 nearby.

[0196] Specifically, each gate drive unit 41 can be a gate shift register (GOA), and multiple gate shift registers can be cascaded so that multiple gate shift registers can provide drive signals to multiple gate lines 12 respectively.

[0197] The specific form of a gate shift register varies. For example, the circuit structure and driving timing of a gate shift register can be found in [reference needed]. Figure 9 and Figure 10 Specifically, the low level of each of the following signals can be equal to the low level signal VGL, and the high level of each signal can be equal to the high level signal VGH.

[0198] At input stage t1, the first gate clock signal CK is at a low level, the second gate clock signal CB is at a high level, and the input signal STV is at a low level. Since the first gate clock signal CK is at a low level, the second gate transistor K2 is turned on, and the input signal STV is transmitted to the third gate node N3 via the second gate transistor K2. Since the second gate transistor K2 has a threshold loss, the level of the third gate node N3 is STV - Vth2, that is, VGL - Vth2, where Vth2 represents the threshold level of the second gate transistor K2. Since the gate of the sixth gate transistor K6 receives the low-level signal VGL, the sixth gate transistor K6 is in an on state. Thus, the level VGL - Vth2 is transmitted to the first gate node N1 via the sixth gate transistor K6. For example, the threshold level of the sixth gate transistor K6 is denoted as Vth6. Similarly, since the sixth gate transistor K6 has a threshold loss, the level of the first gate node N1 is VGL - VthN1, where VthN1 is the smaller one of Vth2 and Vth6. The level of the first gate node N1 can control the eighth gate transistor K8 to be turned on, and the second gate clock signal CB is taken as the gate output signal GOUT via the eighth gate transistor K8. That is, at input stage t1, the gate output signal GOUT is the second gate clock signal CB at a high level, that is, equal to VGH.

[0199] At input stage t1, since the first gate clock signal CK is at a low level, the first gate transistor K1 is turned on, and the low-level signal VGL is transmitted to the second gate node N2 via the first gate transistor K1. Since the level of the third gate node N3 is VGL - Vth2, the seventh gate transistor K7 is turned on, and the low-level first gate clock signal CK is transmitted to the second gate node N2 via the seventh gate transistor K7. For example, the threshold level of the seventh gate transistor K7 is denoted as Vth7, and the threshold level of the first gate transistor K1 is denoted as Vth1. When Vth1 < Vth7 + Vth2, the level of the second gate node N2 is VGL - Vth7 - Vth2; when Vth1 > Vth7 + Vth2, the level of the second gate node N2 is VGL - Vth1. At this time, both the third gate transistor K3 and the fourth gate transistor K4 are turned on. Since the second gate clock signal CB is at a high level, the fifth gate transistor K5 is cut off.

[0200] In output phase t2, the first gate clock signal CK is high, the second gate clock signal CB is low, and the input signal SKT is high. The eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8. In input phase t1, the level of one end of the second gate capacitor C2 connected to the first gate node N1 is VGL-VthN1, and the level of the other end is high. In output phase t2, the level of one end of the second gate capacitor C2 connected to the output terminal GOUT becomes VGL. Due to the bootstrap effect of the second gate capacitor C2, the level of one end of the second gate capacitor C2 connected to the first gate node N1 becomes 2VGL-VthN1-VGH, that is, the level of the first gate node N1 becomes 2VGL-VthN1-VGH. At this time, the sixth gate transistor K6 is turned off, and the eighth gate transistor K8 can be turned on more effectively. The gate output signal GOUT is the low-level signal VGL.

[0201] During output phase t2, the first gate clock signal CK is high, thus turning off both the second gate transistor K2 and the first gate transistor K1. The level of the third gate node N3 remains VGL-VthN1, and the seventh gate transistor K7 is turned on. The high-level first gate clock signal CK is transmitted to the second gate node N2 via the seventh gate transistor K7, meaning the level of the second gate node N2 is VGH. Consequently, both the third gate transistor K3 and the fourth gate transistor K4 are turned off. Since the second gate clock signal CB is low, the fifth gate transistor K5 is turned on.

[0202] During the buffer phase t3, both the first gate clock signal CK and the second gate clock signal CB are high, and the input signal SKT is high. The eighth gate transistor K8 is turned on, and the second gate clock signal CB is used as the gate output signal GOUT via the eighth gate transistor K8. At this time, the gate output signal GOUT is the high-level second gate clock signal CB, i.e., VGH. Due to the bootstrap effect of the second gate capacitor C2, the level of the first gate node N1 becomes VGL-VthN1.

[0203] During the buffer phase t3, the first gate clock signal CK is high, thus turning off both the second gate transistor K2 and the first gate transistor K1. The level of the first gate node N1 becomes VGL-VthN1. At this time, the sixth gate transistor K6 is turned on, and the level of the third gate node N3 is also VGL-VthN1. The seventh gate transistor K7 is turned on, and the high-level first gate clock signal CK is transmitted to the second gate node N2 via the seventh gate transistor K7, meaning the level of the second gate node N2 is VGH. Consequently, both the third gate transistor K3 and the fourth gate transistor K4 are turned off. Since the second gate clock signal CB is high, the fifth gate transistor K5 is turned off.

[0204] In the first sub-stage t41 of the stable phase t4, the first gate clock signal CK is low, the second gate clock signal CB is high, and the input signal SKT is high. Since the first gate clock signal CK is low, the second gate transistor K2 is turned on, and the input signal SKT is transmitted to the third gate node N3 via the second gate transistor K2. Because the second gate transistor K2 transmits a high level without threshold loss, the level of the third gate node N3 is VGH, and the seventh gate transistor K7 is turned off. Since the sixth gate transistor K6 is on, the level of the first gate node N1 is the same as that of the third gate node N3, that is, the level of the first gate node N1 is VGH, and the eighth gate transistor K8 is turned off. Since the first gate clock signal CK is low, the first gate transistor K1 is turned on, the level of the second gate node N2 is VGL-Vth1, and both the third gate transistor K3 and the fourth gate transistor K4 are turned on. The high-level signal VGH is transmitted via the third gate transistor K3 as the gate output signal GOUT, i.e., the gate output signal is the high-level signal VGH.

[0205] In the second sub-stage t42 of the stable phase t4, the first gate clock signal is high, the second gate clock signal is low, and the input signal SKT is high. The levels of the first gate node N1 and the third gate node N3 are VGH, and the eighth gate transistor K8 and the seventh gate transistor K7 are both off. The first gate clock signal CK is high, thus the second gate transistor K2 and the first gate transistor K1 are both off. Due to the holding effect of the first gate capacitor C1, the level of the second gate node N2 is still VGL-Vth1, and the third gate transistor K3 and the fourth gate transistor K4 are both on. The high-level signal VGH is used as the gate output signal GOUT through the third gate transistor K3, that is, the gate output signal is the high-level signal VGH.

[0206] In the second sub-stage t42, since the second gate clock signal CB is low, the fifth gate transistor K5 is turned on, so the high-level signal VGH is transmitted to the third gate node N3 and the first gate node N1 via the fourth gate transistor K4 and the fifth gate transistor K5, so that the level of the first gate node N1 and the level of the third gate node N3 are kept high.

[0207] In the third sub-stage t43 of the stable phase t4, both the first gate clock signal CK and the second gate clock signal CB are high, and the input signal SKT is high. The levels of the first gate node N1 and the third gate node N3 are VGH, and the eighth gate transistor K8 and the seventh gate transistor K7 are off. The first gate clock signal CK is high, thus the second gate transistor K2 and the first gate transistor K1 are both off, the level of the second gate node N2 remains VGL-Vth1, and the third gate transistor K3 and the fourth gate transistor K4 are both on. The high-level signal VGH is used as the gate output signal GOUT via the third gate transistor K3, meaning the gate output signal is the high-level signal VGH.

[0208] In some embodiments, the display area 91 further includes a plurality of control pole lines 13 extending along the second direction 992, each control pole line 13 being connected to a plurality of sub-pixels 1;

[0209] Drive unit 4 is a control pole drive unit 42;

[0210] The second half-region includes multiple control pole drive units 42, which are configured to provide control pole drive signals to multiple control pole lines 13.

[0211] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 The display area 91 may also be provided with control lines 13 that extend along the second direction 992. Each control line 13 may also be connected to one or two rows of sub-pixels 1, specifically to the control line terminal EM of the above 7T1C pixel circuit.

[0212] Since control pole line 13 also extends along the second direction 992, all control pole lines 13 correspond to the second half-region ( Figure 1 , Figure 2 The right semicircle in the middle, or Figure 4 , Figure 5 The right half of the U-shaped ring in the second half of the region), therefore, the drive unit 4 in the second half of the region may include a control pole drive unit 42 that provides control pole drive signals to multiple control pole lines 13 (furthermore, all drive units 4 in the second half of the region 922 may be control pole drive units 42), so that the control pole drive unit 42 can be connected to the corresponding control pole line 13 nearby.

[0213] Therefore, referring to Figure 1 , Figure 2 , Figure 4 , Figure 5In the circuit area 92 of the display substrate in this embodiment, the test unit 3 and the gate driving unit 41 are mixed in the upper left area, the test unit 3 and the control electrode driving unit 42 are mixed in the upper right area, the multiplexing unit 2 and the gate driving unit 41 are mixed in the lower left area, and the multiplexing unit 2 and the control electrode driving unit 42 are mixed in the lower right area.

[0214] Among them, reference Figure 1 , Figure 2 Since the radial direction is different at different positions of the annulus, the units arranged in it can also "rotate" depending on their arrangement position, and generally their output ends are always ensured to face the center of the circle.

[0215] Additionally, refer to Figure 4 , Figure 5 Each unit at the corresponding "arc boundary" can also "rotate" depending on its arrangement position, and its output end is generally always ensured to face the center of the circle.

[0216] Of course, it should be understood that Figure 1 , Figure 2 , Figure 4 , Figure 5 The use of "rectangles" to represent each unit and sub-pixel 1 is only illustrative. In reality, each unit and sub-pixel 1 is composed of multiple devices, and the area they occupy is not necessarily rectangular.

[0217] Of course, it should be understood that for an actual display substrate, each unit corresponds to only a very small part of the annulus. Therefore, in the following figures, many structures in the local area of ​​each unit will be approximated as straight lines.

[0218] Of course, it should be understood that, due to area limitations, the shapes, sizes, size ratios, numbers, number ratios, and positions of various structures such as sub-pixel 1 leads (e.g., signal lines), connectors, units, and regions in many of the accompanying drawings of the embodiments of this disclosure are merely exemplary and not intended to limit the embodiments of this disclosure. For example, the actual number of test signal lines 63, drive signal lines 64, etc., should be greater than... Figure 1 , Figure 2 , Figure 4 , Figure 5 More is shown in the image.

[0219] Of course, the specific form of the driving unit 4 described above is not a limitation on the embodiments of this disclosure.

[0220] For example, the driving units 4 in both halves can also be gate driving units 41, and provide gate driving signals for different gate lines 12 respectively, or provide gate driving signals for each gate line 12 from both sides simultaneously (i.e., dual-side driving).

[0221] Specifically, each control pole drive unit 42 can be a control pole shift register (EM GOA), and multiple control pole shift registers can be cascaded so that multiple control pole shift registers can provide drive signals to multiple control pole lines 12 respectively.

[0222] The specific forms of control-polar shift registers vary. For example, the circuit structure and driving timing of a control-polar shift register can be found in [reference needed]. Figure 11 and Figure 12 Specifically, the low level of each of the following signals can be equal to the low level signal VGL, and the high level of each signal can be equal to the high level signal VGH.

[0223] In the first stage P1, the first control gate clock signal CK' is low, so the first control gate transistor M1 and the third control gate transistor M3 are turned on. The turned-on first control gate transistor M1 transmits the high-level start signal ESTV to the first control gate node N1', thus making the level of the first control gate node N1' high. Therefore, the second control gate transistor M2, the eighth control gate transistor M8, and the tenth control gate transistor M10 are turned off. Meanwhile, the turned-on third control gate transistor M3 transmits the low-level signal VGL to the second control gate node N2', thus making the level of the second control gate node N2' low. Therefore, the fifth control gate transistor M5 and the sixth control gate transistor M6 are turned on. Since the second control gate clock signal CB' is high, the seventh control gate transistor M7 is turned off. Furthermore, due to the storage effect of the third control gate capacitor C3', the level of the fourth control gate node N4 can remain high, thus turning off the ninth control gate transistor M9. In the first stage P1, since both the ninth control transistor M9 and the tenth control transistor M10 are turned off, the control output signal EMOUT remains at the previous low level.

[0224] In the second stage P2, the second control gate clock signal CB' is low, so the fourth control gate transistor M4 and the seventh control gate transistor M7 are turned on. Since the first control gate clock signal CK' is high, the first control gate transistor M1 and the third control gate transistor M3 are turned off. Due to the storage effect of the first control gate capacitor C1', the second control gate node N2' can continue to maintain the low level of the previous stage, so the fifth control gate transistor M5 and the sixth control gate transistor M6 are turned on. The high-level signal VGH is transmitted to the first control gate node N1' through the turned-on fifth control gate transistor M5 and fourth control gate transistor M4, thus causing the level of the first control gate node N1' to continue to maintain the high level of the previous stage, so the second control gate transistor M2, the eighth control gate transistor M8, and the tenth control gate transistor M10 are turned off. In addition, the low-level second control gate clock signal CB' is transmitted to the fourth control gate node N4' through the conducting sixth control gate transistor M6 and seventh control gate transistor M7, thereby making the level of the fourth control gate node N4' low. Therefore, the ninth control gate transistor M9 is turned on, and the turned-on ninth control gate transistor M9 outputs the high-level signal VGH, so the control gate output signal EMOUT is high.

[0225] In the third stage P3, the first control gate clock signal CK' is low, so the first control gate transistor M1 and the third control gate transistor M3 are turned on. The second control gate clock signal CB' is high, so the fourth control gate transistor M4 and the seventh control gate transistor M7 are turned off. Due to the storage effect of the third control gate capacitor C3', the level of the fourth control gate node N4' can remain low from the previous stage, thus keeping the ninth control gate transistor M9 on. The on-state ninth control gate transistor M9 outputs a high-level signal VGH, so the control gate output signal EMOUT remains high.

[0226] In the fourth stage P4, the first control gate clock signal CK' is high, so the first control gate transistor M1 and the third control gate transistor M3 are turned off. The second control gate clock signal CB' is low, so the fourth control gate transistor M4 and the seventh control gate transistor M7 are turned on. Due to the storage effect of the second control gate capacitor C2', the level of the first control gate node N1' remains high from the previous stage, thereby turning off the second control gate transistor M2, the eighth control gate transistor M8, and the tenth control gate transistor M10. Due to the storage effect of the first control gate capacitor C1', the second control gate node N2 continues to remain low from the previous stage, thereby turning on the fifth control gate transistor M5 and the sixth control gate transistor M6. In addition, the low-level second control gate clock signal CB' is transmitted to the fourth control gate node N4' through the conducting sixth control gate transistor M6 and seventh control gate transistor M7, thereby making the level of the fourth control gate node N4' low. Therefore, the ninth control gate transistor M9 is turned on, and the turned-on ninth control gate transistor M9 outputs the high-level signal VGH. So the control gate output signal EMOUT is still high.

[0227] In stage P5, the first control gate clock signal CK' is low, so the first control gate transistor M1 and the third control gate transistor M3 are turned on. The second control gate clock signal CB' is high, so the fourth control gate transistor M4 and the seventh control gate transistor M7 are turned off. The turned-on first control gate transistor M1 transmits the low-level start signal ESTV to the first control gate node N1', thus making the level of the first control gate node N1' low, so the second control gate transistor M2, the eighth control gate transistor M8, and the tenth control gate transistor M10 are turned on. The turned-on second control gate transistor M2 transmits the low-level first control gate clock signal CK' to the second control gate node N2', which can further pull down the level of the second control gate node N2', so the second control gate node N2' continues to maintain the low level of the previous stage, thus turning on the fifth control gate transistor M5 and the sixth control gate transistor M6. Furthermore, the conducting eighth gate transistor M8 transmits a high-level signal VGH to the fourth gate node N4', causing the level of the fourth gate node N4 to become high, thus turning off the ninth gate transistor M9. The conducting tenth gate transistor M10 outputs a low-level signal VGL, so the gate output signal EMOUT becomes low.

[0228] In some embodiments, the multiplexed signal line 62 includes multiple multiplexed control lines 621 and multiple multiplexed data lines 621;

[0229] At least one multiplexing unit 2 includes a plurality of multiplexing transistors 21; the gate of each multiplexing transistor 21 is connected to a multiplexing control line 621, the first terminal is connected to a data line 11, and the second terminal is connected to a multiplexing data line 621;

[0230] The second terminals of all multiplexing transistors 21 in the same multiplexing unit 2 are connected to the same multiplexing data line 621, and the second terminals of multiplexing transistors 21 in different multiplexing units 2 are connected to different multiplexing data lines 621.

[0231] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 6 The multiplexing signal line 62 includes a multiplexing control line 621 and a multiplexing data line 622, and each multiplexing unit 2 includes multiple ( Figure 6 (Taking 6 as an example) Multiplexing transistors 21, the gate of each multiplexing transistor 21 is connected to the multiplexing control line 621, the first terminal is connected to the data line 11, and the second terminal is connected to the multiplexing data line 621; moreover, the same multiplexing unit 2 is connected to the same multiplexing data line 621, and different multiplexing units 2 are connected to different multiplexing data lines 621.

[0232] Thus, referring to Figure 6 When displaying, conduction signals (signals that enable transistors to conduct) can be sequentially input into multiple multiplexed control lines 621, while shutdown signals (signals that enable transistors to turn off) can be input into other multiplexed control lines 621. This allows one multiplexed data line 621 to be sequentially connected to multiple different data lines 11 through multiple multiplexed transistors 21 in a multiplexing unit 2. Thus, the required data signals are provided to multiple data lines 11 through one multiplexed data line 621, which realizes the control of multiple data lines 11 through one signal source (such as connector 6) (i.e., realizing "one-to-many", such as one-to-6). This makes the number of signal sources providing signals to data lines 11 much smaller than the number of data lines 11, simplifying the product structure, for example, reducing the number of driver chips required.

[0233] From the perspective of simplifying the structure, the number of multiplexing control lines 621 can be equal to the number of multiplexing transistors 21 in each multiplexing unit 2 (e.g., 6 in each case). That is, each multiplexing transistor 21 in each multiplexing unit 2 can be connected to a different multiplexing control line 621, and each multiplexing control line 621 is connected to one multiplexing transistor 21 in each multiplexing unit 2.

[0234] Since the multiplexing control line 621 needs to connect multiple multiplexing units 2, the multiplexing control line 621 may have a portion extending circumferentially along the fan-out area 93, and different positions of this portion are connected to different multiplexing units 2; while each multiplexing data line 621 only connects to one multiplexing unit 2, so each multiplexing data line 621 can be directly connected from the fan-out area 93 to the corresponding multiplexing unit 2.

[0235] Obviously, based on the above structure, the further away from the connecting sub-region 923 in the circumferential direction in the fan-out area 93, the fewer the number of multiplexed data lines 621, and thus the smaller the size of the fan-out area 93 can be.

[0236] In some embodiments, the test signal line 63 includes a test control line 631 and a test data line 632;

[0237] At least one test unit 3 includes a plurality of test transistors 31; the gate of each test transistor 31 is connected to a test control line 631, the first terminal is connected to a data line 11, and the second terminal is connected to a test data line 632.

[0238] Each test data line 632 is connected to multiple test units 3.

[0239] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 7 , Figure 8 The test signal line 63 includes a test control line 631 and a test data line 632. Correspondingly, each test unit 3 may include multiple test transistors 31. The gate of the test transistor 31 is connected to the test control line 631, the first terminal is connected to the data line 11, and the second terminal is connected to the test data line 632. Therefore, by passing a conduction signal to the test control line 631, the signal in the test signal line 63 can pass through the test transistors 31 in different test units and enter multiple corresponding data lines 11 to realize the detection of the display device.

[0240] Since each test data line 632 is connected to multiple test units 3, the number of test data lines 632 is much smaller than the number of multiplexed data lines 621. Therefore, although the test unit 3 is located far from the connector area 94, it can be controlled by only a few test signal lines 63 extending to the test unit 3, so these few test signal lines 63 will not occupy a large layout area.

[0241] The correspondence between test data line 632, test control line 631 and test unit 3 can be varied.

[0242] For example, refer to Figure 7The number of test data lines 632 can be equal to the number of test transistors 31 in each test unit 3 (e.g., 3 in each case), while there is only one test control line 631. That is, each test data line 632 is connected to the second terminal of one test transistor 31 in each test unit 3, and the first terminals of different test transistors 31 are connected to different data lines 11. The gates of all test transistors 31 in all test units 3 are connected to the test control line 631.

[0243] In this case, refer to Figure 7 Each data line 11 can connect to sub-pixels 1 of the same color (in the figure, R represents red sub-pixel 1, G represents green sub-pixel 1, and B represents blue sub-pixel 1). Furthermore, the sub-pixels 1 connected to the data line 11 corresponding to each test data line 632 are of the same color. Therefore, by continuously supplying the same test signal to the test data line 632, sub-pixels 1 of the same color can display the same brightness (such as displaying a white screen or other monochrome screen), which makes it easier to locate defective sub-pixels 1.

[0244] For example, each data line 11 connects to a different sub-pixel 1, as shown in the reference. Figure 8 In every 4 columns of sub-pixel 1, two columns of sub-pixel 1 are green, and in each of the remaining two columns of sub-pixel 1, red and blue sub-pixel 1 are arranged alternately, and in these two columns of sub-pixel 1, any two sub-pixel 1 in the same row are blue and red respectively.

[0245] Furthermore, refer to Figure 8 There are 3 test data lines 632 and 3 test control lines 631. Each test unit 3 may include 5 test transistors 31, which are used to control 4 data lines 11 (corresponding to the above 4 columns of sub-pixels 1). In each test unit 3, the first electrode of the first test transistor 311 and the third test transistor 313 is connected to a column of red and blue mixed sub-pixels 1, the first electrode of the second test transistor 312 and the fourth test transistor 314 is connected to another column of red and blue mixed sub-pixels 1, the second electrode of the first test transistor 311 and the second test transistor 312 is connected to the first test data line 6321, the second electrode of the third test transistor 313 and the fourth test transistor 314 is connected to the second test data line 6322, the gate of the first test transistor 311 and the fourth test transistor 314 is connected to the first test control line 6311, and the gate of the second test transistor 312 and the third test transistor 313 is connected to the second test control line 6312; while the fifth test transistor 315 has its gate connected to the third test control line 6313, its first electrode connected to two columns of green sub-pixels 1, and its second electrode connected to the third test data line 6323.

[0246] As can be seen from the above settings, by alternately providing conduction signals to the first test control line 6311 and the second test control line 6312, the first test data line 6321 and the second test data line 6322 can control the blue and green sub-pixels 1 respectively, while the third test control line 6313 and the third test data line 6323 control all green sub-pixels 1, so as to achieve the same brightness for sub-pixels 1 of the same color.

[0247] In some embodiments, the test signal line 63 is located on the side of the circuit area 92 away from the display area 91; the drive signal line 64 is located on the side of the circuit area 92 away from the display area 91.

[0248] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 13 To facilitate connection with the corresponding unit, both the test signal line 63 and the drive signal line 64 can be set along the side of the circuit area 92 away from the display area 91 (outer side). Of course, since the fan-out area 93 is also located outside the circuit area 92, a portion of the test signal line 63 and the drive signal line 64 are also located in the fan-out area 93.

[0249] The specific number of test signal lines 63 and drive signal lines 64 can be set according to the different forms of their corresponding units.

[0250] For example, when test unit 3 is the reference Figure 7 In the form of a test signal line 63, the test signal line 63 may include three test data lines 632 and one test control line 631, that is, a total of four test signal lines 63 arranged around the circuit area 92.

[0251] For example, when the gate driving unit 41 is a reference Figure 9 When in the form of [symbol], the corresponding drive signal line 64 can be 4 lines, which are used to transmit the first gate clock signal CK, the second gate clock signal CB, the high-level signal VGH, and the low-level signal VGL, respectively.

[0252] For example, when the control pole drive unit 42 is used as a reference Figure 11 In the form of [the signal], the corresponding drive signal line 64 can be 4 lines, which are used to transmit the first control electrode clock signal CK', the second control electrode clock signal CB', the high-level signal VGH, and the low-level signal VGL, respectively.

[0253] Since the first gate clock signal CK, the second gate clock signal CB, the first control gate clock signal CK', and the second control gate clock signal CB' are all different, they can correspond to four different drive signal lines 64. Because the high-level signals VGH and VGL in the gate drive unit 41 and the control gate drive unit 42 can be the same, all high-level signals VGH can be transmitted through one drive signal line 64 (such as high-level line 641), and all low-level signals VGL can be transmitted through one drive signal line 64 (such as low-level line 642). Of course, the high-level line 641 and the low-level line 642 should be distributed both outside the first and second halves of the circuit area 92.

[0254] For example, refer to Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 13 The test signal line 63 can be located on the side of the drive signal line 64 away from the display area 91 (outer side).

[0255] In some embodiments, the end of the first sub-region 921 closest to the second sub-region 922 is closer to the display area 91 than the end of the second sub-region 922 closest to the first sub-region 921.

[0256] Reference Figure 1 , Figure 2 , Figure 13 Since the first sub-region 921 also has a capacitor area 95 inside, and the second sub-region 922 has a display area 91 inside, the first sub-region 921 can be "more inward" than the second sub-region 922. Therefore, at the adjacent ends of the two sub-regions, the first sub-region 921 is also "more inward" than the second sub-region 922. For example, the radius of the first semicircular ring can be smaller than the radius of the second semicircular ring.

[0257] Of course, when the first sub-region 921 and the second sub-region 922 do not include the above-mentioned "arc area" and are other shapes, they may not have a "radius", but their ends can still conform to the above positional relationship, that is, the first sub-region 921 can still be "smaller" than the second sub-region 922.

[0258] In some embodiments, the circuit region 92 further includes a connection sub-region 923 located between the first sub-region 921 and the second sub-region 922, the connection sub-region being configured to electrically connect the first sub-region 921 and the second sub-region 922.

[0259] In some embodiments, the connecting sub-region 923 is connected between the end of the first sub-region 921 closest to the second sub-region 922 and the end of the second sub-region 922 closest to the first sub-region 921.

[0260] Reference Figure 13 The end of the first sub-region 921 is "more inward" than the end of the second sub-region 922, so the ends of the two are "misaligned" and may need to be connected by an obliquely set connecting sub-region 923.

[0261] It should be understood that the connection sub-region 923 also belongs to the circuit region 92, and may also be equipped with a drive unit 4 (but since it is not the first sub-region 921 and the second sub-region 922, it does not have a multiplexing unit 2 and a test power supply). However, from the perspective of structural regularity, the structure in the connection sub-region 923 should be as simple as possible, for example, with only necessary leads (such as leads for cascading between different drive units 4).

[0262] At the same time, in order to maintain the regularity of the structure, the test signal lines 63 and drive signal lines 64 located outside the circuit area 92 can also be bent at the corresponding connection sub-area 923 to ensure that the distance between each test signal line 63, drive signal line 64 and the circuit area 92 remains basically unchanged.

[0263] In some embodiments, the circuit area further includes a signal line protection unit located on the side of the connection sub-area 923 away from the display area 91 and electrically connected to the signal line of the circuit area 92. The signal line protection unit is configured to protect the signal line of the circuit area 92.

[0264] In some embodiments of this disclosure, the signal line protection unit includes:

[0265] At least one polysilicon resistor 71, each of the at least one polysilicon resistor 71 being connected between two signal lines; the polysilicon resistor 71 is located on the side of the first sub-region 921 closest to the end of the second sub-region 922 away from the display area 91, or on the side of the connection sub-region 923 away from the display area 91.

[0266] The polysilicon resistor 71, also known as a "poly resistor," is a high-resistance resistor made of polysilicon (p-Si) material. When connected between different signal lines, the polysilicon resistor 71 allows the signal from the other signal line to enter the line after a delay when one signal line is not receiving a signal, preventing signal fluctuations caused by floating. Simultaneously, when both signal lines are receiving signals, the high resistance of the polysilicon resistor 71 prevents short circuits, ensuring that the signals do not interfere with each other.

[0267] In order to achieve the largest possible resistance in the smallest possible layout area, the polysilicon resistor 71 can be a structure in which a linear polysilicon material is bent in a small area.

[0268] As before, the end of the first sub-region 921 is "more inward" than the end of the second sub-region 922. Therefore, the end of the first sub-region 921 and the outer side of the connecting sub-region 923 will have a certain amount of space "empty" relative to each other. Figure 1 , Figure 2 , Figure 13 This allows the polysilicon resistor 71 to be positioned precisely at this location. For example, along both sides of the second direction 992 ( Figure 1 , Figure 2 Polysilicon resistors 71 can be provided at the ends of the first sub-region 921 (on both the left and right sides) and on the outer side of the connecting sub-region 923.

[0269] In some embodiments, the test signal line 63 is located on the side of the circuit area 92 away from the display area 91;

[0270] The drive signal line 64 is located on the side of the circuit area 92 away from the display area 91;

[0271] The polysilicon resistor 71 is located on the side of the test signal line 63 and drive signal line 64 away from the display area 91.

[0272] Reference Figure 1 , Figure 2 , Figure 13 When the test signal line 63 and the drive signal line 64 are also located outside the circuit area 92, the polysilicon resistor 71 can be placed outside these signal lines to avoid the polysilicon resistor 71 affecting the connection between these signal lines and the corresponding units in the circuit area 92.

[0273] In some embodiments, the drive signal line 64 includes a high-level line 641 and a low-level line 642, the test signal line 63 includes a test control line 631 and a test data line 632, the multiplexed signal line 62 includes a multiplexed control line 621 and a multiplexed data line 622, and at least one polysilicon resistor 71 is connected to the test control line 631 and the high-level line 641, and at least one polysilicon resistor 71 is connected to the test control line 631 and the multiplexed control line 621.

[0274] In some embodiments of this disclosure, the signal line protection unit further includes:

[0275] At least one electrostatic discharge unit 72; each electrostatic discharge unit 72 is connected to a signal line and configured to discharge static electricity in the signal line to which it is connected; the electrostatic discharge unit 72 is located on the side of the first sub-region 921 closest to the end of the second sub-region 922 away from the display area 91, or on the side of the connecting sub-region 923 away from the display area 91.

[0276] To prevent damage caused by electrostatic discharge due to the accumulation of static electricity in the signal line, an electrostatic discharge unit 72 (ESD) can be provided to release the static electricity accumulated in the signal line and protect the signal line.

[0277] As before, the end of the first sub-region 921 is "more inward" than the end of the second sub-region 922. Therefore, the end of the first sub-region 921 and the outer side of the connecting sub-region 923 will have a certain amount of space "empty" relative to each other. Figure 1 , Figure 2 , Figure 13 This allows the electrostatic discharge unit 72 to be positioned precisely at this location. For example, along both sides of the second direction 992 ( Figure 1 , Figure 2 Electrostatic discharge units 72 can be provided at the ends of the first sub-region 921 (on both the left and right sides) and on the outer side of the connecting sub-region 923.

[0278] The positions occupied by the polysilicon resistor 71 and the electrostatic discharge unit 72 should not exceed the position difference between the end of the first sub-region 921 and the end of the second sub-region 922. For example, their dimensions can be 100 to 150 μm.

[0279] Of course, even when the size of the first sub-region 921 is not smaller than the size of the second sub-region 922 (for example, when the sub-region includes a U-shaped ring region), refer to Figure 4 The polysilicon resistor 71 and the electrostatic discharge unit 72 can also be located on the outside of the boundary between the first sub-region 921 and the second sub-region 922.

[0280] It should be understood that, in the various circuit diagrams of the embodiments of this disclosure (such as...), Figure 7 , Figure 16 The polysilicon resistors 71 shown in the diagram (such as the first polysilicon resistor 711 and the second polysilicon resistor 712) only represent the electrical connection structure of the polysilicon resistors 71, and do not represent the physical positional relationship between the polysilicon resistors 71 and other units.

[0281] In some embodiments, the test signal line 63 is located on the side of the circuit area 92 away from the display area 91;

[0282] The drive signal line 64 is located on the side of the circuit area 92 away from the display area 91;

[0283] The electrostatic discharge unit 72 is located on the side of the test signal line 63 and drive signal line 64 away from the display area 91.

[0284] Reference Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 13 When the test signal line 63 and the drive signal line 64 are located outside the circuit area 92, the electrostatic discharge unit 72 can also be located outside these signal lines to avoid the electrostatic discharge unit 72 affecting the connection between these signal lines and the corresponding units in the circuit area 92.

[0285] In some embodiments, the multiplexed signal line 62 includes multiple multiplexed control lines 621 and multiple multiplexed data lines 621; the signal line connected to each electrostatic discharge unit 72 is either a test signal line 63 or a multiplexed control line 621.

[0286] Reference Figure 13 There may be multiple electrostatic discharge units 72, which are respectively connected to the above test signal lines 63 (e.g., 4 test signal lines 63) and multiplexing control lines 621 (e.g., 6 multiplexing control lines 621) and protect them.

[0287] In some embodiments, the drive signal line 64 includes a high-level line 641 and a low-level line 642, wherein the high-level line 641 is configured to connect to a high-level signal source and the low-level line 642 is configured to connect to a low-level signal source.

[0288] Each electrostatic discharge unit 72 includes a first discharge transistor 721 and a second discharge transistor 722: the gate and first terminal of the first discharge transistor 721 are connected to a high-level line 641, and the second terminal is connected to the signal line (test signal line 63 or multiplexed control line 621) corresponding to the electrostatic discharge unit 72; the gate and first terminal of the second discharge transistor 722 are connected to the signal line corresponding to the electrostatic discharge unit 72, and the second terminal is connected to a low-level line 642.

[0289] Reference Figure 13 , Figure 16 As one embodiment of this disclosure, the electrostatic discharge unit 72 may include two discharge transistors, wherein one terminal of each discharge transistor is connected to its own gate, thereby forming an equivalent diode connection; the signal line to be protected is connected between the two "diodes", and the other two ends of the two "diodes" are respectively connected to the high-level line 641 (transmitting the high-level signal VGH) and the low-level line 642 (transmitting the low-level signal VGL). Thus, when a momentary high voltage (e.g., 100V) occurs in the signal line due to the accumulation of positive charge, the "diode" of the first discharge transistor 721 conducts, releasing the positive charge in the signal line; and when a momentary low voltage (e.g., -100V) occurs in the signal line due to the accumulation of negative charge, the "diode" of the second discharge transistor 722 conducts, releasing the negative charge in the signal line.

[0290] In some embodiments, the polysilicon resistor 71 includes a first polysilicon resistor 711, and each first polysilicon resistor 711 is connected to two signal lines, namely a high-level line 641 and a test control line 631.

[0291] Reference Figure 7 , Figure 13At least a portion of the polysilicon resistors 71 (the first polysilicon resistor 711) can be connected between the high-level line 641 (transmitting the high-level signal VGH) and the test control line 631 (transmitting the control signal of the test unit 3). During testing (such as ET testing), the test control line 631 receives a conduction signal or a cutoff signal as needed, and the first polysilicon resistor 711 is protected from the influence of the high-level signal VGH. During normal display, no further testing is required, so the test control line 631 can be supplied with a fixed cutoff signal, and the first polysilicon resistor 711 ensures the stability of its level.

[0292] In some embodiments, the polysilicon resistor 71 includes a second polysilicon resistor 712, and the two signal lines connected to each second polysilicon resistor 712 are respectively the high-level line 641 and the signal line corresponding to the electrostatic discharge unit 72.

[0293] Reference Figure 13 , Figure 16 At least a portion of the polysilicon resistor 71 (second polysilicon resistor 712) may be connected between the high-level line 641 (transmitting high-level signal VGH) and the signal line corresponding to the electrostatic discharge unit 72 (test signal line 63 or multiplexed control line 621) to prevent excessively high levels from occurring.

[0294] Of course, it should be understood that since different electrostatic discharge units 72 correspond to different signal lines, different electrostatic discharge units 72 should also be connected to different second polysilicon resistors 712, that is, the number of second polysilicon resistors 712 can be the same as the number of electrostatic discharge units 72. However, Figure 13 In order to clearly show the connection relationship, only a portion of the second polysilicon resistor 712 is shown.

[0295] In some embodiments, at least some of the different data lines 11 connect to different numbers of sub-pixels 1;

[0296] Except for the data line 11 which has the most connected sub-pixels, each of the other data lines 11 is connected to a compensation capacitor unit 5.

[0297] Reference Figure 1 , Figure 2 In some cases, the number of sub-pixels 1 connected by different data lines 11 is different. For example, when the display area 91 is basically circular and each data line 11 connects to a column of sub-pixels 1, the number of sub-pixels 1 connected by different data lines 11 is also different because the number of sub-pixels 1 in different columns is different.

[0298] Obviously, each sub-pixel 1 has a certain capacitance (pixel capacitance), and this capacitance is equivalent to the "load" of the data line 11 connected to it. Therefore, the number of sub-pixels 1 connected to the data line 11 is different, which is equivalent to the different loads of the data line 11. This will result in the same signal being applied to the data line 11, but the actual signal received by the sub-pixels 1 connected to different data lines 11 will be different, affecting the display.

[0299] Therefore, except for the data line 11 with the most connected sub-pixels (i.e., the data line 11 with the largest load), all other data lines 11 can be connected to the compensation capacitor unit 5. The compensation capacitor unit 5 is used to "add (or compensate)" a certain load to the data lines 11 so that the total load (total capacitance) of all data lines 11 is as close as possible and the display effect is uniform.

[0300] In some embodiments, each compensation capacitor unit 5 includes one or more compensation capacitors 51;

[0301] Except for the data line 11 with the most connected sub-pixels, the number n of compensation capacitors 51 of the compensation capacitor unit 5 connected to the other data lines 11 satisfies:

[0302] n = Nmax - N;

[0303] Wherein, Nmax is the number of sub-pixels 1 connected to the data line 11 with the most connected sub-pixels 1, and N is the number of sub-pixels 1 connected to the data line 11 connected to the compensation capacitor unit 5.

[0304] Reference Figure 17 Each compensation capacitor unit 5 may include multiple compensation capacitors 51, and the number of compensation capacitors 51 is equal to the difference between the number of sub-pixels 1 connected to the data line 11 corresponding to the compensation capacitor unit 5 (N) and the number of sub-pixels 1 connected to the data line 11 with the largest number of sub-pixels 1 (Nmax). In this way, as long as the capacitance value of a single compensation capacitor 51 is basically equal to the capacitance value of a single sub-pixel 1, the total capacitance (total load) connected to all data lines 11 after compensation can be basically the same.

[0305] Generally, multiple actual sub-pixels 1 can be prepared first, and the actual capacitance value of a single sub-pixel 1 can be detected. Then, the actual size of the compensation capacitor 51 can be set based on the actual capacitance value. Specifically, to reduce errors, the total capacitance value of multiple (e.g., 10) sub-pixels 1 can be detected and then divided by the number of sub-pixels 1 (e.g., 10) to obtain the capacitance value of a single sub-pixel 1 (usually around 20-30 fF).

[0306] In some embodiments, the data line 11 is connected to the first pole of all the compensation capacitors 51 of the compensation capacitor unit 5 to which it is connected;

[0307] The second terminal of the compensation capacitor 51 is connected to the same constant-level signal line.

[0308] Reference Figure 17 Specifically, data line 11 can be connected to one terminal of each compensation capacitor 51 in the corresponding compensation capacitor unit 5, while the other terminal of all compensation capacitors 51 only needs to be connected to a fixed-level signal line to obtain the same fixed level. For example, the other terminal of all compensation capacitors 51 can be connected to the anode signal line 19 that supplies power to the anode signal terminal VDD of the pixel circuit.

[0309] In some embodiments, the plurality of sub-pixels 1 connected by each data line 11 are arranged in a column along a first direction 991;

[0310] The compensation capacitor unit 5, which is connected to each data line 11, is disposed along the first direction 991 between a column of sub-pixels 1 and the second sub-region 922 connected to the data line 11.

[0311] Reference Figure 17 When sub-pixels 1 are arranged in multiple columns and each data line 11 connects to one column of sub-pixels 1, the shorter the column, the fewer sub-pixels 1 there are. Therefore, the number of compensation capacitors 51 in the corresponding compensation capacitor unit 5 is more, and the area required for the compensation capacitor unit 5 is also larger. Therefore, from the perspective of making full use of space, the compensation capacitor unit 5 can be placed between the sub-pixels 1 in its corresponding column and the second sub-region 922.

[0312] Of course, the connection relationship, specific form, and setting position of the compensation capacitor unit 5 described above are not intended to limit the scope of protection of the embodiments disclosed herein.

[0313] In a second aspect, embodiments of this disclosure provide a display device, which includes:

[0314] Any of the above-mentioned display substrates.

[0315] The above display substrate can be combined with other components (such as a cover plate, flexible circuit board, driver chip, power supply component, etc.) to form a display device with display function.

[0316] In some embodiments, the display device is a wearable display device.

[0317] Specifically, the above display devices are particularly suitable as wearable display devices that can be worn on the human body, such as smartwatches worn on a person's wrist.

[0318] Of course, wearable display devices may also include devices such as watch straps that are worn on the human body.

[0319] Of course, the above display devices are not limited to wearable display devices; they can also be any product or component with display function, such as electronic paper, mobile phones, tablets, televisions, monitors, laptops, digital photo frames, and navigators.

[0320] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A display substrate, comprising a display area and a peripheral area, the peripheral area including a circuit area, the display area including: Multiple sub-pixels, multiple data lines extending in a first direction, and multiple gate lines extending in a second direction intersecting the first direction. Each of the data lines connects multiple of the sub-pixels, and each of the gate lines connects multiple of the sub-pixels; The circuit region includes a first sub-region and a second sub-region opposite to each other on both sides of the display region along the first direction. The circuit region includes multiple driving unit groups. The first sub-region includes multiple multiplexing unit groups, the second sub-region includes multiple testing unit groups. The multiplexing unit group includes at least one multiplexing unit, the testing unit group includes at least one testing unit, the driving unit group includes at least one driving unit. The driving unit is configured to provide a driving signal to the gate line, the multiplexing unit is configured to provide a data signal to the data line, and the testing unit is configured to provide a testing signal to the data line; In the first sub-region, the driving unit groups and the multiplexing unit groups are alternately arranged; in the second sub-region, the driving unit groups and the testing unit groups are alternately arranged; In the first sub-region, the multiplexing unit group includes a first multiplexing unit group and a second multiplexing unit group. The first multiplexing unit group includes M multiplexing units, the second multiplexing unit group includes N multiplexing units. N and M are integers greater than 1, and M < N. The second multiplexing unit group is located in the middle of the first sub-region, and the first multiplexing unit group is located at both ends of the first sub-region away from the middle of the first sub-region; and / or, in the second sub-region, the testing unit group includes a first testing unit group and a second testing unit group. The first testing unit group includes K testing units, the second testing unit group includes L testing units. L and K are integers greater than 1, and K < L. The second testing unit group is located in the middle of the second sub-region, and the first testing unit group is located at both ends of the second sub-region away from the middle of the second sub-region; The circuit region includes multiple signal lines. The multiple signal lines include testing signal lines connected to the testing units and driving signal lines connected to the driving units. The testing signal lines are located on one side of the driving signal lines away from the display region; In the first sub-region, the number C of multiplexing units included in the multiplexing unit group between two adjacent driving unit groups and the size D of the gap between two adjacent driving unit groups satisfy the following relationship: D = a*C+(C + 1)*d1; Where, a is the size of each multiplexing unit along the arrangement direction of the multiplexing units, and d1 is the size of the gap between adjacent multiplexing units; and / or, In the second sub-region, the number E of testing units included in the testing unit group between two adjacent driving unit groups and the size F of the gap between two adjacent driving unit groups satisfy the following relationship: F = b*E+(E + 1)*d2; Where, b is the size of each testing unit along the arrangement direction of the testing units, and d2 is the size of the gap between adjacent testing units.

2. The display substrate according to claim 1, wherein, The circuit area further includes a connection sub-region located between the first sub-region and the second sub-region, the connection sub-region being configured to electrically connect the first sub-region and the second sub-region; The circuit area also includes a signal line protection unit, which is located on the side of the connection sub-area away from the display area and is electrically connected to the signal line of the circuit area.

3. The display substrate according to claim 2, wherein, The signal line protection unit includes at least one polysilicon resistor, each of which is connected between at least two of the signal lines.

4. The display substrate according to claim 3, wherein, The drive signal line includes a high-level line and a low-level line, and the test signal line includes a test control line and a test data line. At least one of the polysilicon resistors is connected to the test control line and the high-level line.

5. The display substrate according to claim 3, wherein, The signal line also includes a multiplexed signal line connected to the multiplexing unit. The test signal line includes a test control line and a test data line. The multiplexed signal line includes a multiplexed control line and a multiplexed data line. At least one of the polysilicon resistors is connected to the test control line and the multiplexed control line.

6. The display substrate according to claim 2, wherein, The signal line protection unit includes at least one electrostatic discharge unit, and the signal line also includes a multiplexed signal line connected to the multiplexing unit. Each of the at least one electrostatic discharge unit is connected to a signal line.

7. The display substrate according to claim 6, wherein, The drive signal line includes a high-level line and a low-level line, the test signal line includes a test control line and a test data line, the multiplexed signal line includes a multiplexed control line and a multiplexed data line, at least one of the electrostatic discharge units is connected to the test control line, or at least one of the electrostatic discharge units is connected to the test data line, or at least one of the electrostatic discharge units is connected to the multiplexed control line.

8. The display substrate according to claim 1, wherein, d1 ranges from 1 micrometer to 5 micrometers, and d2 ranges from 1 micrometer to 5 micrometers.

9. The display substrate according to any one of claims 1 to 8, wherein, The first sub-region includes a first circular arc region, and the second sub-region includes a second circular arc region; In the first sub-area, the driving unit group and the multiplexing unit group are alternately arranged, specifically: in the first arc area, the driving unit group and the multiplexing unit group are alternately arranged along the side of the first arc area close to the display area; In the second sub-area, the driving unit group and the test unit group are alternately arranged, specifically: in the second arc area, the driving unit group and the test unit group are alternately arranged along the side of the second arc area closer to the display area.

10. The display substrate according to claim 9, wherein, In the first arc region, the line trajectory connecting the center points of the coverage areas of the plurality of driving unit groups is the first arc trajectory, and the line trajectory connecting the center points of the coverage areas of the plurality of multiplexing unit groups is the second arc trajectory. The center of the circle corresponding to the first arc trajectory and the center of the circle corresponding to the second arc trajectory coincide with the center of the circle corresponding to the edge of the first arc region near the display area; and / or In the second arc area, the line trajectory connecting the center points of the coverage areas of the multiple drive unit groups is the third arc trajectory, and the line trajectory connecting the center points of the coverage areas of the multiple test unit groups is the fourth arc trajectory. The center of the circle corresponding to the third arc trajectory and the center of the circle corresponding to the fourth arc trajectory coincide with the center of the circle corresponding to the edge of the second arc area near the display area.

11. The display substrate according to claim 9, wherein, The first arc area is a semicircle, and the second arc area is a semicircle.

12. The display substrate according to claim 9, wherein, The first sub-region includes a first U-shaped ring region, the second sub-region includes a second U-shaped ring region, the first U-shaped ring region includes two segments of the first circular arc region and at least one segment of the second rectangular region, and the second U-shaped ring region includes two segments of the second circular arc region and at least one segment of the third rectangular region; In the second rectangular area, a plurality of the multiplexing units are arranged along the side of the second rectangular area closer to the display area; In the third rectangular area, a plurality of the test units are arranged along the side of the third rectangular area closest to the display area.

13. The display substrate according to claim 12, wherein, The circuit area also includes multiple first rectangular areas, which are disposed between the first arc area and the second arc area; In the first rectangular area, a plurality of driving units are arranged along the side of the first rectangular area closer to the display area.

14. The display substrate according to claim 1, wherein, The peripheral area also includes a connector area located on the side of the first sub-area away from the display area. The connector area includes multiple connectors, and at least some of the connectors are connected to signal lines. The signal lines also include multiplexed signal lines connected to the multiplexing unit.

15. The display substrate according to claim 14, wherein, The peripheral area also includes a fan-out area disposed between the connector area and the first sub-area, the fan-out area including multiple multiplexed signal lines.

16. The display substrate according to any one of claims 14 to 15, wherein, The multiplexed signal lines include multiple multiplexed control lines and multiple multiplexed data lines; At least one of the multiplexing units includes a plurality of multiplexing transistors; the gate of each multiplexing transistor is connected to a multiplexing control line, the first terminal is connected to a data line, and the second terminal is connected to a multiplexing data line; The second terminals of all multiplexing transistors in the same multiplexing unit are connected to the same multiplexing data line, and the second terminals of multiplexing transistors in different multiplexing units are connected to different multiplexing data lines.

17. The display substrate according to any one of claims 14 to 15, wherein, The test signal lines include test control lines and test data lines; At least one of the test units includes a plurality of test transistors; the gate of each test transistor is connected to a test control line, the first electrode is connected to a data line, and the second electrode is connected to a test data line; Each of the test data lines is connected to one of the test units.

18. A display device, comprising: The display substrate as described in any one of claims 1 to 17.

Images