Cryogenic refrigeration for cryogenic equipment

Abstract

An active cooling structure (200, 200a) is provided, comprising a non-superconductor layer (220), a superconductor layer (210), and an array (240) of superconductor-insulator-normal metal (NIS) tunnel junctions. The non-superconductor layer may include a plurality of non-superconductor traces (222). The superconductor layer may include a plurality of superconductor traces (212). The array of superconductor-insulator-normal metal (NIS) tunnel junctions may be located between the plurality of non-superconductor traces and the plurality of superconductor traces.

Description

Technical Field

[0001] A cooling apparatus and method of manufacture for cryogenic electronic devices, and more particularly for active cooling of cryogenic and ultra-cold superconductor devices, is disclosed. Background Art

[0002] Molecules and subatomic particles obey the laws of quantum mechanics, a branch of physics that explores how the physical world works at a fundamental level. At this level, particles behave in strange ways, taking on more than one state at a time and interacting with other particles at great distances. Quantum computing exploits these quantum phenomena to process information.

[0003] Many quantum devices suitable for quantum computing require low or extremely low temperatures to function. If the temperature rises above these levels, errors will be introduced into the quantum computing process. However, traditional vapor compression coolers are bulky, expensive, and not completely reliable for maintaining device arrays at these temperatures. Summary of the Invention

[0004] According to one or more embodiments, an active cooling structure includes a non-superconductor layer, a superconductor layer, and an array of superconductor-insulator-normal metal (NIS) tunnel junctions. The non-superconductor layer may include a plurality of non-superconductor traces. The superconductor layer may include a plurality of superconductor traces. The array of superconductor-insulator-normal metal (NIS) tunnel junctions may be located between the plurality of non-superconductor traces and the plurality of superconductor traces.

[0005] According to one or more embodiments, a quantum processor includes a first substrate, a plurality of qubits formed on the first substrate, and an active cooling structure in thermal communication with the qubits. The active cooling structure may include a non-superconductor layer, a superconductor layer, and an insulator layer between the non-superconductor layer and the superconductor layer.

[0006] The quantum processor may further include, for example, at least one or more of the following features:

[0007] The active cooling structure may include a mesh of superconductor-insulator-normal metal (NIS) tunnel structures between a non-conductive layer and a superconductor layer. The non-superconductor layer may include a plurality of non-superconductor traces extending in a first direction; and the superconductor layer may include a plurality of superconductor traces extending in a second direction. The plurality of superconductor traces and the plurality of non-superconductor traces may intersect at a plurality of locations in the XY plane.

[0008] The non-superconductor layer may include silver, the insulator layer may be selected from the group consisting of silicon dioxide and hafnium dioxide, and the superconductor layer may be selected from the group consisting of aluminum and niobium.

[0009] According to one or more embodiments, a method for cooling a quantum processor to an extremely low temperature includes applying a voltage to an active cooling structure in thermal communication with the quantum processor. The active cooling structure may include a non-superconductor layer, a superconductor layer, and an insulator layer between the non-superconductor layer and the superconductor layer.

[0010] According to one or more embodiments, a method for fabricating an active cooling structure is provided, the method comprising forming an array of superconductor-insulator-normal metal (NIS) tunnel structures between a non-superconductor layer and a superconductor layer. The non-superconductor layer may include a plurality of non-superconductor traces extending in a first direction. The superconductor layer may include a plurality of superconductor traces extending in a second direction.

[0011] The method for manufacturing an active cooling structure may further include, for example, at least one or more of the following features:

[0012] The manufacturing method may include forming a first plurality of pads electrically connecting the plurality of superconductor traces in parallel and forming a second plurality of pads electrically connecting the non-superconductor traces in parallel.

[0013] The manufacturing method may include: applying a photoresist layer to a substrate; exposing the photoresist layer in a pattern to produce exposed photoresist and unexposed photoresist; removing the exposed photoresist layer; applying a metal layer to the unexposed photoresist and the substrate; and removing the unexposed photoresist.

[0014] The manufacturing method may include forming an insulator layer on the non-superconductor layer.

[0015] The manufacturing method may include: applying a stripping photoresist layer to the insulator layer; exposing the stripping photoresist layer in a pattern to produce exposed stripping photoresist and unexposed stripping photoresist; removing the exposed stripping photoresist layer; applying the superconductor layer to the unexposed stripping photoresist layer and the insulator layer; and removing the unexposed stripping photoresist.

[0016] According to one or more embodiments, a method for fabricating a quantum processor is provided, the method comprising forming a plurality of qubits on a first substrate and forming an active cooling structure in thermal communication with the qubits. The active cooling structure may comprise a non-superconducting metal layer, an insulator layer formed on top of the non-superconducting layer, and a superconductor layer formed on top of the insulator layer.

[0017] The method for manufacturing the quantum processor may further include, for example, at least one or more of the following features:

[0018] The manufacturing method may include: applying a photoresist layer to a substrate; exposing the photoresist layer in a pattern to produce exposed photoresist and unexposed photoresist; removing the exposed photoresist layer; coating the metal layer on the unexposed photoresist and the substrate, and removing the unexposed photoresist.

[0019] The manufacturing method may include forming an insulator layer on the non-superconductor layer.

[0020] The manufacturing method may include: applying a stripping photoresist layer to the insulator layer; exposing the stripping photoresist layer in a pattern to produce exposed stripping photoresist and unexposed stripping photoresist; removing the exposed stripping photoresist layer; applying the superconductor layer to the unexposed stripping photoresist layer and the insulator layer; and removing the unexposed stripping photoresist.

[0021] According to one or more embodiments, a semiconductor manufacturing system for manufacturing a thermalized structure is provided. The semiconductor manufacturing system may include a computer-readable storage medium having encoded thereon an instruction set for a manufacturing facility, the instruction set causing a manufacturing method to be performed when operated by a processor. The manufacturing method may include forming an array of superconductor-insulator-normal metal (NIS) tunnel structures between a non-conductive layer and a superconductor layer. The non-superconductor layer may include a plurality of non-superconductor traces extending in a first direction, and the superconductor layer may include a plurality of superconductor traces extending in a second direction.

[0022] The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings included in this application are incorporated into and form a part of the specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The accompanying drawings illustrate only certain embodiments and do not limit the present disclosure.

[0024] Figure 1A block diagram depicting a network of data processing systems consistent with some embodiments;

[0025] Figure 2A illustrates a top view of an example active planar cooling structure consistent with some embodiments;

[0026] Figure 2B Shown is a section taken along line BB Figure 2A An exemplary cooling structure of

[0027] Figure 2C Another example active planar cooling structure according to some embodiments is shown;

[0028] Figure 3A An example actively cooled quantum processor consistent with some embodiments is presented;

[0029] Figure 3B Another exemplary actively cooled quantum processor consistent with some embodiments is presented;

[0030] Figure 4 Another exemplary actively cooled quantum processor consistent with some embodiments is presented;

[0031] Figure 5 Another exemplary actively cooled quantum processor consistent with some embodiments is presented;

[0032] Figure 6A Another exemplary actively cooled quantum processor consistent with some embodiments is presented;

[0033] Figure 6B Another exemplary actively cooled quantum processor consistent with some embodiments is presented;

[0034] Figures 7A-7D are device cross sections depicting a device at various stages of an example process for fabricating an active planar quantum cooling structure, consistent with some embodiments.

[0035] Figure 8 Depicted is an example computer-implemented process for fabricating an active planar quantum cooling structure consistent with some embodiments.

[0036] Although the present invention is susceptible to various modifications and alternative forms, details thereof have been shown by way of example in the drawings and will be described in detail. However, it should be understood that the present invention is not limited to the specific embodiments described. On the contrary, the present invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention. DETAILED DESCRIPTION

[0037] As used herein, the "cryogenic" range refers to the cryogenic temperature range beginning at or about 77 Kelvin (K). "Extremely low temperatures" begin at or about 10 Kelvin and extend down to at least 1 milliKelvin (0.001 K), and in some cases as low as possible using available technology, currently about 0.000001 K.

[0038] A "low temperature device" (LTD) is a device that operates in the low or extreme low temperature range. Most LTDs that operate at low or extreme temperatures rely on materials that exhibit superconductor properties at those temperatures.

[0039] Overview

[0040] Aspects of the present disclosure relate to a cooling apparatus and manufacturing method for cryogenic electronic devices, and more particularly to active cooling for cryogenic and ultra-cold superconductor devices. While the present disclosure is not necessarily limited to such applications, various aspects of the present disclosure may be understood through a discussion of various examples using the described context.

[0041] LTD devices, including superconductors, generate heat during operation. However, heat removal in this cryogenic temperature range presents unique challenges.

[0042] Some embodiments package an active solid-state cooling device in the cooling chamber of the dilution refrigerator, close to or in contact with the LTD device, to help keep the LTD device at low or very low temperatures. Some embodiments may also allow for the reduction of some of the other cooling structures and may improve overall reliability.

[0043] Quantum computing

[0044] Most computers used today are called classical computers. Classical computers use conventional processors, semiconductor memories, and magnetic or solid-state storage devices made using semiconductor materials and technologies, the so-called von Neumann architecture. Specifically, the processors of traditional computers are binary processors, that is, they operate on binary data represented by 1 and 0. In contrast, quantum processors (q processors) use the unique properties of entangled quantum bit devices (herein compactly referred to as "qubits" or multiple "qubits") to perform computing tasks. In the specific field where quantum mechanics operates, material particles can exist in multiple states - such as "on" state, "off" state, and simultaneous "on" and "off" states. Where binary computing using semiconductor processors is limited to using only on and off states (equivalent to 1 and 0 in binary coding), quantum processors use these quantum material states to output signals that can be used for data calculations.

[0045] Classical computers encode information in bits. Each bit can take on a value of either 1 or 0. These 1s and 0s act as on / off switches that ultimately drive the computer's function. Quantum computers, on the other hand, are based on qubits, which operate according to two key principles of quantum physics: superposition and entanglement. Superposition means that each qubit can represent both 1 and 0 at the same time. Entanglement means that qubits in a superposition can be related to each other in a nonclassical way; that is, the state of one qubit (whether it is 1 or 0 or both) can depend on the state of another qubit, and more information can be ascertained when the two qubits are entangled than when they are processed separately.

[0046] Using these two principles, qubits operate as more complex information processors, enabling quantum computers to operate in ways that allow them to solve difficult problems that are intractable using conventional computers.

[0047] Superconductor qubits, in turn, typically use one or more layers of different materials to achieve device characteristics and functionality. The material layers can be superconducting, conducting, semiconducting, insulating, resistive, inductive, capacitive, or have any number of other properties. Different material layers may have to be formed using different methods, depending on the nature of the material, its shape, size, or arrangement, other materials adjacent to it, and many other considerations.

[0048] Most quantum devices suitable for use as qubits in quantum computing require low or extremely low temperatures in order to function.

[0049] Data processing environment

[0050] Figure 1 A block diagram of a network of data processing environments in which the illustrative embodiments may be implemented is shown. Data processing environment 100 is a computer network in which the illustrative embodiments may be implemented. Data processing environment 100 includes network 102. Network 102 is a medium for providing communication links between different devices and computers connected together within data processing environment 100. Network 102 may include connections such as wired or wireless communication links or fiber optic cables.

[0051] Data processing environment 100 includes a plurality of clients 110 , 112 , 114 , 132 and a plurality of servers 104 , 106 exchangeably coupled to storage unit 108 via network 102 . Figure 1Clients 110, 112, 114, servers 104, 106, and storage device unit 108 depicted in FIG are devices described in merely exemplary roles of certain data processing systems connected to network 102 and are not intended to exclude other configurations or roles of these data processing systems. Any component in data processing environment 100, such as server 104 or 106 or client 110, 112, 114, or 132, may contain data and may have software applications and / or software tools 105 executing thereon.

[0052] Device 132 and client 114 are examples of client devices. For example, device 132 may take the form of a smartphone, a tablet computer, a laptop computer, a wearable computing device, an appliance, or any other suitable device. In some embodiments, the device described as Figure 1 A software application and / or tool 105 executed in another data processing system in the device 132 may be configured for execution in a similar manner. In some embodiments, Figure 1 Data or information stored or generated in another data processing system in may be configured to be stored or generated in device 132 in a similar manner.

[0053] The lithography application 105a can be used to implement or partially implement some of the embodiments described herein. In those embodiments, the lithography application 105a is a software component of a system for fabricating active planar cooling structures, Josephson junctions, qubits, and / or other superconductor structures used in quantum computing devices. The lithography application 105a provides instructions to such a fabrication system that cause the assembly of some of the novel low-temperature methods and systems contemplated in some of the embodiments described herein.

[0054] Cooling structure

[0055] Figure 2A A top view of an example active planar cooling structure 200 is shown, in accordance with some embodiments. Figure 2B Shown is a section taken along line B Figure 2A An exemplary cooling structure 200 is provided. Figure 2A and Figure 2B, a cooling structure 200 includes a superconductor layer 210 and a normal metal (i.e., non-superconductor) layer 220 separated by an insulator layer 230. In some embodiments, the superconductor layer 210 is formed as a plurality of substantially parallel superconductor traces 212 (only some of which are labeled for clarity) extending in a first direction (e.g., the Y direction as depicted). The superconductor traces 202 can be electrically connected to common pads 214a and 214b. The normal metal layer 210 is similarly formed as a plurality of substantially parallel normal metal traces 222 (only some of which are labeled for clarity) extending in a second linear direction orthogonal to the first direction (e.g., the X direction as depicted). The normal metal traces 222 are electrically connected to common pads 224a and 224b. In some embodiments, the superconductor layer 220 is first formed on top of (i.e., adjacent to) the substrate 260, and the normal metal layer 210 is subsequently formed on top of (i.e., adjacent to) the insulator layer 230. In other embodiments, conventional metal layer 210 is formed first on top of (ie, adjacent to) substrate 260 , followed by formation of superconductor layer 220 on top of (ie, adjacent to) insulator layer 230 .

[0056] An array of superconductor-insulator-normal metal (NIS) tunnel structures 240 (only some are labeled for clarity) is formed in a grid pattern (in the XY plane) at the intersections of the superconductor traces 212 and the normal metal traces 222. The example cooling structure 200 also includes a plurality of electrical contacts 250 (only some are labeled for clarity) and can be produced on the surface of the substrate 260.

[0057] In some embodiments, when a small potential (bias voltage V) is applied between superconductor layer 210 and normal metal layer 220, relatively high energy ("hot") electrons can pass through the dielectric between the two layers. In contrast, relatively low energy ("cold") electrons cannot pass through the dielectric. Overall, this has the effect of transferring thermal energy away from a heat source (such as a quantum device or interface electronics).

[0058] In some embodiments, the normal metal layer may be compatible with substrate 260 and subsequently formed with the remainder of structure 200 (see FIG. 7- Figure 8 ) and / or any material that is compatible with any manufacturing process required for the cooled device (see Figures 3-6). In some embodiments and for some applications, it may also be desirable that the normal metal layer not act as a superconductor at the selected low and / or extreme low operating temperature, but still be a good normal conductor to reduce the heat added to the system through resistance, and that the normal metal layer be non-magnetic to avoid interference with the qubits. Suitable normal metals include, but are not limited to, silver, gold, copper, platinum, and palladium.

[0059] In some embodiments, the superconductor layer 210 can be any substance that exhibits superconductor properties at a selected low and / or very low operating temperature, and is compatible with other selected materials and any manufacturing process used. Suitable superconductor materials for some embodiments and some applications include, but are not limited to, aluminum, niobium, tantalum, titanium, tantalum nitride, titanium nitride, vanadium, lead, tin, and gallium. The insulator layer 230 can be any substance that acts as a dielectric between the superconductor metal layer 210 and the normal layer 220 at a low and / or very low operating temperature, and is compatible with other selected materials and manufacturing processes. For some embodiments and some applications, suitable such substances include silicon dioxide (SiO2), hafnium dioxide (HfO2) and aluminum oxide (Al2O3). Different nitrides may also be suitable for some embodiments and some applications, such as silicon nitride, hafnium nitride, aluminum nitride and zirconium nitride.

[0060] Figure 2C Another example active planar cooling structure 200c is shown in accordance with some embodiments. Figure 2C The active flat cooling structure 200c in FIG. 1 further includes a superconductor layer 210 and a normal metal (ie, non-superconductor) layer 220 separated by an insulator layer 230. However, Figure 2C The superconductor layer 210 and the normal metal layer 220 in the embodiment include a single plane 272, 282 of superconductor material or normal metal, respectively. Figures 2A to 2B As in the embodiment of FIG, the NIS tunnel structure 240 is formed where the two planes 272, 282 overlap. The active planar cooling structure embodiment 200c is desirable for active cooling in space-constrained locations, such as Figure 3B Active planar cooling structure 303 in.

[0061] Figure 3A and Figure 3B An example actively cooled quantum processor 300 is shown, consistent with some embodiments. Figure 3A The quantum processor 300a in FIG. 3 includes four active planar cooling structures 302 that are elongated and arranged around the periphery of a cooled device, such as a quantum processor 310. The quantum circuit 310 in turn includes a plurality of quantum devices, such as qubits 315 (only some of which are labeled for clarity). Figure 3B The quantum processor 300B in FIG. 3 includes five active planar cooling structures 302 and 303. Figure 3A Four of the active planar cooling structures 302 are elongated and arranged around the periphery of the device being cooled, such as quantum processor 310. The fifth active planar cooling structure 303 is placed within the periphery of the cooled device, such as between two groups of qubits 315.

[0062] exist Figure 3A and Figure 3B In both, active planar cooling structures 302 are formed directly on the same surface (e.g., the top surface) of substrate 360, next to and / or between qubits 315 that make up quantum circuit 310. These arrangements may be desirable because active planar cooling structures 302 can be formed simultaneously using the same fabrication process as quantum circuit 310. This arrangement may also be desirable because these active planar cooling structures 302 are physically located near these quantum devices.

[0063] Figure 4 Another exemplary actively cooled quantum processor 400 consistent with some embodiments of the present invention is shown. Quantum processor 400 includes a generally square-shaped active planar cooling structure 402 formed on one surface (e.g., bottom) of substrate 460. On the opposite surface (e.g., top), a plurality of quantum devices 415 (only some of which are labeled for clarity) have been formed, which can be combined to form a quantum circuit 410.

[0064] Figure 5 Another example actively cooled quantum processor 500 is shown. In this example, an active planar cooling structure 502 is formed on one substrate 560a, and quantum devices 515 (only one is labeled for clarity) that make up quantum circuit 510 are formed on a second substrate 560b. The two substrates 560a and 560b are then bonded back-to-back, mechanically clamped, or otherwise joined together. These quantum processor embodiments 400 and 500 may be desirable because they may offer a wider range of options in materials and manufacturing processes.

[0065] Figure 6A Another exemplary actively cooled quantum processor 600a is shown, consistent with some embodiments of the present invention. Figure 6A The quantum processor 600 in FIG. 1 includes two active planar cooling structures, one 602 a formed on one surface (e.g., bottom) of a first substrate 660 a and one 602 b formed on one surface (e.g., top) of a second substrate 660 b. The two substrates 660 a and 660 b in this embodiment can be bonded, clamped, or otherwise joined together such that the two substrates 660 a and 660 b sandwich the quantum devices 615 (only one labeled for clarity) that comprise the quantum circuit 610. Figure 6BAnother exemplary actively cooled quantum processor 600b is shown, consistent with some embodiments of the present invention. In this embodiment of quantum processor 600b, a top active planar cooling structure 602b is on the surface of substrate 660b closest to (i.e., facing) the quantum devices 615 (only one is labeled for clarity) that make up quantum circuit 610.

[0066] Figure 6B Also included are a plurality of spacers 680 that prevent physical contact with the quantum device 615 when the two substrates 660a and 660b are bonded, clamped, or otherwise bonded together. These spacers 680 may optionally include a plurality of channels (not shown) to allow a coolant (e.g., liquid hydrogen or helium) to enter and pass through a passage 690 between the quantum circuit 610 and the top active planar cooling structure 602b. Figure 6A and 6B The embodiments in are desirable because they can also protect the quantum device 615 and the quantum circuit 610.

[0067] Manufacturing method

[0068] Figures 7A-7D is a device cross section depicting the device at various stages of an example process for fabricating an active planar quantum cooling structure according to some embodiments. Figure 7A As shown, a photoresist layer 770 is first deposited on a substrate 760, and then a mask and a light source (not shown) are used to expose a photoresist pattern of a first layer 710 (e.g., a conventional metal layer) to the photoresist layer 770. After the exposed / developed photoresist is washed away, the material for the first layer of the structure (e.g., the selected conventional metal) can be applied. The remaining unexposed / undeveloped photoresist layer 770 can then be dissolved by a solvent suitable for the selected material and substrate. Figure 7B The resulting structure is shown.

[0069] Next, an insulating layer 730 (e.g., SiO2 or HfO2) is deposited over the remaining (i.e., patterned) layer 710 of the structure (e.g., the normal metal layer). Suitable methods include, but are not limited to, atomic layer deposition (ALD), chemical vapor deposition (CVD), and physical vapor deposition (PVD). Figure 7C The resulting structure is shown in FIG. A pattern can be applied to lift off the photoresist layer 780 for forming the next layer 720 of the structure (e.g., a superconductor layer). A mask and light source (not shown) can then be used to expose a reverse pattern on the photoresist layer 780, and the material for the second layer (e.g., the selected superconductor) can be deposited. The resulting structure is shown in FIG. Figure 7D. Next, the exposed / developed photoresist layer 780 is washed away along with any material on its surface to form a second layer of the desired shape (e.g., a superconductor). Finally, electrical contacts (not shown) suitable for the array of ordinary metals and / or superconductors are produced and packaged in a suitable orientation for installation into a cryogenic cooling structure.

[0070] Figure 8 An example computer-implemented process 800 for fabricating an active planar quantum cooling structure consistent with some embodiments is depicted. In some embodiments, process 800 may be performed in Figure 1 . At block 802, the lithography application 105a creates a pattern for a first layer 710 (e.g., a normal metal layer) of a planar active cooling structure to be deposited on a substrate 760. Next, at block 804, the lithography application 105a causes a photoresist layer to be deposited on the substrate 760 and exposed to a first pattern to expose the photoresist layer. At block 806, the lithography application 105a causes the exposed / developed photoresist to be washed away and an appropriate material (e.g., the selected normal metal) to be applied to the resulting structure. Then, at block 807, the lithography application 105a causes the unexposed / undeveloped photoresist and any adjacent normal metal to be removed, thereby forming a patterned layer 710.

[0071] At block 808, the photolithography application 105a deposits an insulating layer 730 onto the patterned layer 710. At block 810, the photolithography application 105a creates a pattern for a second (e.g., superconductor) layer 720. The photolithography application 105a then directs the application of a patterned stripping photoresist layer 780 to the current structure (at block 812), followed by exposing the patterned stripping photoresist layer 780 using a mask and light (at block 814). The photolithography application 105a then deposits a second layer 720 (e.g., a superconductor layer) onto the current structure at block 816. The photolithography application 105a then directs the exposed / developed photoresist layer 780, along with any superconductor on its surface, to be washed away, thereby forming the patterned layer 720. Finally, at block 820, the photolithography application 105a attaches electrical contacts to the current structure. The photolithography application 105a then ends.

[0072] Overview

[0073] Although the present invention has been described in detail with reference to some examples of the present invention, the present invention may also be embodied in other specific forms without departing from its basic spirit or attributes. For example, some embodiments can be distributed as an instruction set for a manufacturing facility ("fab") encoded onto a computer-readable storage medium (e.g., a release interface tape or "RIT," "tape output," "GDS2," etc.). The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device such as a punch card, or a protruding structure in a groove with instructions recorded thereon, and any suitable combination thereof. Computer-readable storage media as used herein should not be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses passing through fiber optic cables), or electrical signals transmitted through wires.

[0074] The computer-readable instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network), or downloaded to an external computer or external storage device. The network can include copper transmission cables, optical transmission fibers, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in a computer-readable storage medium within the corresponding computing / processing device.

[0075] Embodiments of the present invention may also be delivered as part of a service engagement with a client company, non-profit organization, government entity, internal organizational structure, etc. Aspects of these embodiments may also include analyzing specifications from the client entity, creating recommendations in response to the analysis, generating designs for circuits that implement some or all of the recommendations, delivering manufacturing instructions for the designs, and testing the resulting circuits.

[0076] Various embodiments of the present invention are described herein with reference to the accompanying drawings. Without departing from the scope of the present invention, alternative embodiments may be designed. Although different connections and positional relationships (e.g., above, below, adjacent, etc.) between elements are described in the following description and the accompanying drawings, it will be appreciated by those skilled in the art that many of the positional relationships described herein are orientation-independent when the described functions are maintained (even if the orientation is changed). Unless otherwise specified, these connections and / or positional relationships may be direct or indirect, and the present invention is restrictive in this respect and in the schematic diagram. Therefore, the connection of an entity may refer to a direct or indirect connection, and the positional relationship between entities may be a direct or indirect positional relationship. As an example of an indirect positional relationship, it is mentioned in this specification that forming layer "A" on layer "B" includes the situation where one or more intermediate layers (e.g., layer "C") are between layer "A" and layer "B", as long as the intermediate layer does not substantially change the relevant features and functions of layer "A" and layer "B".

[0077] The following definitions and abbreviations will be used to interpret the claims and description. As used herein, the terms "comprises," "comprising," "including," "having," "containing," or "having" or any other variations thereof are intended to cover a non-exclusive inclusion. For example, a composition, mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.

[0078] Additionally, the term "illustrative" is used herein to mean "serving as an example, instance, or illustration." Any embodiment or design described herein as "illustrative" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms "at least one" and "one or more" should be understood to include any integer greater than or equal to one, i.e., one, two, three, four, etc. The term "plurality" should be understood to include any integer greater than or equal to two, i.e., two, three, four, five, etc. The term "connected" may include both indirect and direct "connections."

[0079] References in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is considered within the knowledge of those skilled in the art to affect such feature, structure, or characteristic in conjunction with other embodiments (whether or not explicitly described).

[0080] The terms "about," "substantially," "approximately," and variations thereof are intended to include the degree of error associated with measurement of a particular quantity based on the equipment available at the time the application is filed. For example, "about" may include a range of ±8%, or 5%, or 2% of a given value.

[0081] The description of various embodiments of the present invention has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements that are superior to those found in the market, or to enable those of ordinary skill in the art to understand the embodiments described herein. Therefore, it is intended that the embodiments described herein be considered in all respects to be illustrative and not restrictive, and that the scope of the invention be determined with reference to the appended claims.

Claims

1. An active cooling structure comprising: a non-superconductor layer comprising a plurality of non-superconductor traces; a superconductor layer comprising a plurality of superconductor traces orthogonal to the plurality of non-superconductor traces; as well as A grid of superconductor-insulator-normal metal (NIS) tunnel junctions between the plurality of non-superconductor traces and the plurality of superconductor traces. 2 . The active cooling structure of claim 1 , further comprising a first plurality of common pads connecting the plurality of superconductor traces in parallel. 3 . The active cooling structure of claim 2 , further comprising a second plurality of common pads connecting the plurality of non-superconductor traces in parallel.

4. The actively cooled structure of claim 1 further comprising an insulator layer between the non-superconductor layer and the superconductor layer.

5. The active cooling structure according to claim 4, wherein: The non-superconductor layer comprises silver; The insulator layer comprises silicon dioxide; and The superconductor layer includes aluminum.

6. The active cooling structure according to claim 4, wherein: The non-superconductor layer comprises silver; The insulator layer comprises silicon dioxide; and The superconductor layer includes niobium.

7. The active cooling structure according to claim 4, wherein: The non-superconductor layer comprises silver; The insulator layer includes hafnium dioxide; and The superconductor layer includes aluminum.

8. The active cooling structure according to claim 4, wherein: The non-superconductor layer comprises silver; The insulator layer includes hafnium dioxide; and The superconductor layer includes niobium.

9. A quantum processor comprising: a first substrate; a plurality of qubits, the plurality of qubits being formed on the first substrate; as well as an actively cooled structure in thermal communication with the qubits, the actively cooled structure comprising: a non-superconductor layer comprising a plurality of non-superconductor traces; a superconductor layer comprising a plurality of superconductor traces orthogonal to the plurality of non-superconductor traces; and A grid of superconductor-insulator-normal metal (NIS) tunnel junctions between the plurality of non-superconductor traces and the plurality of superconductor traces.

10. The quantum processor according to claim 9: wherein the first substrate comprises a first surface and a second surface; and wherein the plurality of qubits are formed on the first surface and the active cooling structure is formed on the second surface.

11. A quantum processor according to claim 9 or 10, wherein the active cooling structure is adjacent to the plurality of qubits.

12. A quantum processor according to claim 9 or 10, wherein the active cooling structure is between the plurality of qubits.

13. The quantum processor of claim 9, further comprising a second substrate, wherein the plurality of qubits are formed on the first substrate and the active cooling structure is formed on the second substrate.

14. The quantum processor of claim 13, wherein: The first substrate includes a first surface and a second surface; The second substrate includes a third surface and a fourth surface; and The plurality of qubits are formed on a first surface of the first substrate and the active cooling structure is formed on a third surface of the second substrate.

15. The quantum processor of claim 14, wherein the second surface is in contact with the fourth surface.

16. The quantum processor according to any one of claims 13 to 15, further comprising a fluid channel between the first substrate and the second substrate.

17. The quantum processor of claim 9, wherein: The non-superconductor layer consists essentially of a plane of non-superconductor material; and The superconductor layer essentially consists of a plane of superconductor material.

18. A method for cooling a quantum processor to an extremely low temperature, comprising: applying a voltage to an active cooling structure in thermal communication with the quantum processor, the active cooling structure comprising: a non-superconductor layer comprising a plurality of non-superconductor traces; a superconductor layer comprising a plurality of superconductor traces orthogonal to the plurality of non-superconductor traces; and A grid of superconductor-insulator-normal metal (NIS) tunnel junctions between the plurality of non-superconductor traces and the plurality of superconductor traces.

19. A method for manufacturing an actively cooled structure, comprising: A lattice of superconductor-insulator-normal metal (NIS) tunnel junctions is formed between the non-superconductor layer and the superconductor layer, wherein The non-superconductor layer includes a plurality of non-superconductor traces extending along a first direction; and The superconductor layer includes a plurality of superconductor traces extending in a second direction orthogonal to the first direction.

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