Reconfigurable transistor device

Abstract

A reconfigurable transistor device includes a substrate, a plurality of first transistor fingers disposed in a first region above the substrate, and a phase change switch (PCS) including a phase change material (PCM) block disposed in a second region above the substrate for selectively coupling a first group of the plurality of first transistor fingers to a bus, wherein the PCM block is electrically insulating in an amorphous state and electrically conductive in a crystalline state. The PCS further includes a thermal element disposed proximate to the PCM block, wherein the first thermal element can maintain the PCM block within a first temperature range until the PCM block transitions to the amorphous state and maintain the PCM block within a second temperature range until the first PCM block transitions to the crystalline state.

Description

[0001] Related Patent Applications

[0002] This application claims the benefit of provisional patent application No. 62 / 935,662, filed November 15, 2019, the disclosure of which is incorporated by reference in its entirety into this disclosure. TECHNICAL FIELD

[0003] The present invention relates to transistors, and more particularly to radio frequency transistor structures. BACKGROUND

[0004] Silicon-based digital and analog integrated circuits simulate variable total gate width of transistor device periphery by selectively turning on and off parallel transistors comprising the transistor device. However, the off transistors' parasitic capacitance, inductance, and resistance affect the on transistors' performance. As frequency and output power increase, the performance of radio frequency (RF) field effect transistor (FET) devices, such as RF amplifiers, decrease at an increasing rate. Accordingly, isolation switches on each end of the FETs, including RF amplifiers, are employed to improve performance. However, because the isolation switches are moderately valued, performance is only relatively slightly improved. Moreover, the isolation switches are typically at least an order of magnitude larger than the active devices of the amplifier periphery. Thus, a new transistor structure is needed that provides compactness and relatively high isolation between on and off transistors within the transistor device to minimize the effects of parasitics (decreasing performance of the transistor device). SUMMARY

[0005] A reconfigurable transistor device is disclosed, comprising a substrate, a plurality of transistor fingers disposed in a first region above the substrate, and a phase change switch (PCS) comprising a first phase change material (PCM) block disposed in a second region above the substrate for selectively coupling a first group of the plurality of first transistor fingers to a first bus, wherein the first PCM block is electrically insulating in an amorphous state and electrically conductive in a crystalline state. A thermal element is disposed proximate to the first PCM block, wherein the thermal element is operable to maintain the PCM block within a first temperature range until the first PCM block transitions to the amorphous state when a current within a first current range flows through the first thermal element, and is operable to maintain the first PCM block within a second temperature range until the first PCM block transitions to the crystalline state when a current within a second current range flows through the first thermal element.

[0006] The scope of the invention will be pointed out in the following detailed description with reference to the attached drawings, wherein: BRIEF DESCRIPTION OF DRAWINGS

[0007] The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate certain aspects of the present application and together with the description, explain the principles of the application.

[0008] Figure 1 Cross-sectional view of a first embodiment of a phase change switch (PCS) based on a phase change material (PCM) according to the present application.

[0009] Figure 2 Cross-sectional view of a second embodiment of a PCS based on a PCM according to the present application.

[0010] Figure 3 Layout view of an exemplary embodiment of a reconfigurable transistor device constructed in accordance with the present application.

[0011] Figure 4 Plot of the minimum noise figure NFmin versus frequency for a reconfigurable transistor device comprising four parallel transistors each comprising an isolation Figure 3 PCS switch for a reconfigurable transistor device or the like as shown.

[0012] Figure 5 Smith chart showing the optimal gamma for a reconfigurable transistor device comprising four parallel transistors each comprising an isolation Figure 3 PCS switch for a reconfigurable transistor device or the like as shown.

[0013] Figure 6 Plot of the maximum gain versus frequency for a reconfigurable transistor device comprising four parallel transistors each comprising an isolation Figure 3 PCS switch for a reconfigurable transistor device or the like as shown. DETAILED DESCRIPTION

[0014] The examples described below represent essential information to enable one skilled in the art to practice the examples and illustrate the best mode of practicing the examples. Upon reading the following description, one skilled in the art will understand how to make and use the concepts within the present application and will recognize the applicability of these concepts to other applications. It will be understood by those skilled in the art that these concepts and applications not specifically mentioned herein are within the scope of the present application and the appended claims.

[0015] It is to be understood that the terms "first", "second", and the like, used herein do not connote any hierarchy or order. Such terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. In the present disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0016] It will be understood that when an element (such as a layer, region, or substrate) is referred to as being "on" or "extended to" another element, it can be directly on the other element or indirectly on the other element with intervening elements present. In contrast, when an element is referred to as being "directly on" or "directly extending to" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "above" or "on top of" another element, it can be directly above or on top of the other element, or there can be intervening elements present. In contrast, when an element is referred to as being "directly above" or "directly on top of" another element, there are no intervening elements present. In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there can be intervening elements present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0017] Relative terms such as "below" or "above," "upper" or "lower," "horizontal" or "vertical," and the like can be used herein for ease of description to describe one element's or portion's relationship to another element(s) or portion(s) as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of an apparatus in addition to the orientation depicted in the figures.

[0018] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. Herein, the use of "a", "an" and "the" includes singular and plural referents, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] Figure 11 is a cross-sectional view of a first exemplary embodiment of a phase-changing switch (PCS) 10 according to the present invention, which is made of a phase-changing material (PCM) 12 (such as a chalcogenide phase-changing material, including but not limited to vanadium dioxide (VO2), germanium telluride (GeTe), and germanium antimony telluride (GST)). PCS 10 includes a substrate 14 made of a semiconductor material such as silicon or silicon carbide. A first semiconductor contact 16 and a second semiconductor contact 18 are laterally separated and disposed above substrate 14. In this exemplary embodiment, the first semiconductor contact 16 and the second semiconductor contact 18 are both gallium nitride (GaN) high electron mobility transistor (HEMT) source contacts. However, the first semiconductor contact 16 and the second semiconductor contact 18 can be other types of semiconductor contacts, such as a gate contact and a drain contact. In addition, the first semiconductor contact 16 and the second semiconductor contact 18 can be made of other semiconductor materials such as gallium arsenide.

[0021] A thermal insulation layer 20 is disposed above substrate 14 between first semiconductor contact 16 and second semiconductor contact 18. The thermal conductivity of thermal insulation layer 20 is between 0.1 W / m-Kelvin and 0.4 W / m-Kelvin. Thermal insulation layer 20 may be made of silicon dioxide and include an air cavity for additional insulation. A thermal element 22 is disposed above substrate 14 and thermal insulation layer 20. Thermal element 22 may be made of a thermoelectric semiconductor material or an ohmic material used in resistors. Such materials include, but are not limited to, metals and carbon compounds.

[0022] A first dielectric layer 24 is disposed over the thermal insulation layer 20 and the thermal element 22. The thermal conductivity of the first dielectric layer 24 is typically at least 30 W / m-Kelvin. In the exemplary embodiment, the first dielectric layer 24 is made of silicon nitride.

[0023] The PCM block 12 is disposed above the thermal element 22. In this exemplary embodiment, the PCM block 12 is disposed above the thermal element 22, with a distance of tens to hundreds of nanometers between the PCM block 12 and the thermal element 22. In some embodiments, the PCM block 12 may be directly located on the thermal element 22.

[0024] A first metal layer segment 26 is disposed above substrate 14 and electrically contacts the first semiconductor contact 16 and the leftmost portion of PCM block 12. A second metal layer segment 28 is disposed above substrate 14 and electrically contacts the second semiconductor contact 18 and the rightmost portion of PCM block 12, separated by a gap above PCM block 12. In the exemplary embodiment, the gap is between 1 micron and 7 microns. In some embodiments, the gap is between 1 micron and 4 microns. In other embodiments, the gap is between 4 microns and 7 microns.

[0025] A second dielectric layer 30 is disposed in the gap above the PCM block 12. A first external electrical contact 32 is disposed above the first metal layer segment 26 and is in electrical conduction with the first metal layer segment 26 and the first semiconductor contact 16. A second external electrical contact 34 is disposed above the second metal layer segment 28 and is in electrical conduction with the second metal layer segment 28 and the second semiconductor contact 18. The second dielectric layer 30 (disposed in the gap above the PCM block 12) electrically isolates the first external electrical contact 32 from the second external electrical contact 34.

[0026] When the PCS 10 is working, in order to keep the PCS 10 in the off state, the current is driven through the thermal element 22 to make the temperature of the PCM block 12 rise from the crystallization temperature T c Rising to the melting temperature T m , which lasts for about 100 nanoseconds. In this case, the melting temperature T m The PCM block 12 is converted from a crystalline state to an amorphous state. Conversely, to keep the PCS 10 in the on state, a current is driven through the thermal element 22 to maintain the temperature of the PCM block 12 at the crystallization temperature T c , which lasts for about 1 microsecond. In this case, the crystallization temperature T c The PCM block 12 will be transformed from an amorphous state to a crystalline state. c and melting temperature T m Depends on the PCM type. In certain embodiments, the crystallization temperature T c The range is 100℃-300℃, the melting temperature T m The range is 500℃-800℃.

[0027] Figure 2 FIG2 is a cross-sectional view of a second embodiment of a phase changing switch (PCS) 10 based on a phase changing material (PCM) 12 according to the present invention. In this exemplary embodiment, the first PCM block 12 is sandwiched between a first thermal element 22 and a substrate 14, and a thermal insulation layer 20 is disposed above the thermal element 22. The operation of the second embodiment of the PCS 10 is substantially the same as that of FIG2. Figure 1 The operation of the first embodiment of the PCS 10 shown is the same.

[0028] Figure 3FIG3 is a layout diagram of an exemplary embodiment of a reconfigurable transistor device 36 constructed according to the present invention. The reconfigurable transistor device 36 includes a substrate 38 and a plurality of first transistor fingers 40 (disposed in a first region 42 above the substrate 38). A first phase-changing switch (PCS) 44 includes a first phase-changing material (PCM) block 46 (disposed in a second region 48 above the substrate 38) for selectively coupling the first plurality of first transistor fingers 40 to a first bus 50. The first PCM block 46 is electrically insulating in an amorphous state and conductive in a crystalline state. In this exemplary embodiment, the first bus 50 is a gate bus, and the first plurality of first transistor fingers 40 include gate fingers G1, G2, G3, and G4. The first thermal element 52 is disposed adjacent to the first PCM block 46. When a current within a first current range flows through the first thermal element 52, the first thermal element 52 maintains the first PCM block 46 within the first temperature range until the first PCM block 46 transitions to an amorphous state. When a current within a second current range flows through the first thermal element 52, the first PCM block 46 maintains the first PCM block 46 within the second temperature range until the first PCM block 46 transitions to a crystalline state. In an exemplary embodiment, the first current range is 200 mA to 500 mA, and the second current range is 700 mA to 1000 mA. However, it should be understood that the first and second current ranges depend on the actual size and resistivity of the first thermal element 52, the thickness of the thin-film resistor layer, and other factors. Therefore, other current intensities within the first and second current ranges can produce the first and second temperature ranges, respectively.

[0029] The first thermal element 52 can be coupled to one or more output terminals 54 of a controller 56, wherein when the controller 56 generates a first output voltage range at the one or more output terminals 54 for a first duration, a current within a first current range flows through the first thermal element 52 for the first duration, and when the controller 56 generates a second output voltage range at the one or more output terminals 54 for a second duration, a current within a second current range flows through the first thermal element 52 for the second duration. The first PCS 44 can be configured to Figure 1 The structure of the first embodiment of PCS10 shown or Figure 2 The structure of the second embodiment of PCS10 is shown.

[0030] The reconfigurable transistor device 36 further includes a second PCS 58 including a second PCM block 60 (disposed in a third region 62 above the substrate 38) for selectively coupling the plurality of first transistor fingers second set 40 to a second bus 64, wherein the second PCM block 60 is electrically insulating in an amorphous state and electrically conductive in a crystalline state. In the present exemplary embodiment, the second bus 64 is a source bus and the plurality of first transistor fingers second set 40 includes source fingers S1, S2, and S3.

[0031] A second thermal element 66 is disposed proximate the second PCM block 60, wherein the second thermal element 66 can maintain the second PCM block 60 in a first temperature range until the second PCM block 60 transitions to an amorphous state when a current in a first current range flows through the second thermal element 66, and can maintain the second PCM block 60 in a second temperature range until the second PCM block 60 transitions to a crystalline state when a current in a second current range flows through the second thermal element 66.

[0032] The second thermal element 66 can be coupled to one or more outputs 54 of the controller 56, wherein a current in the first current range flows through the second thermal element 66 for a first duration when the controller 56 generates a first output voltage range at the one or more outputs 54 for the first duration, and a current in the second current range flows through the second thermal element 66 for a second duration when the controller 56 generates a second output voltage range at the one or more outputs 54 for the second duration. The second PCS 58 can employ Figure 1 the structure of the first embodiment of the PCS 10 shown in Figure 2 the structure of the second embodiment of the PCS 10 shown in.

[0033] The reconfigurable transistor device 36 further includes a third PCS 68 including a third PCM block 70 (disposed in a fourth region 72 above the substrate 38) for selectively coupling the plurality of first transistor fingers third set 40 to a third bus 74, wherein the third PCM block 70 is electrically insulating in an amorphous state and electrically conductive in a crystalline state. In the present exemplary embodiment, the third bus is a drain bus and the plurality of first transistor fingers third set 40 includes drain fingers D1 and D2.

[0034] A third thermal element 76 is disposed proximate the third PCM block 70, wherein the third thermal element 76 can maintain the third PCM block 70 in a first temperature range for a first duration when a current in a first current range flows through the third thermal element 76, and can maintain the third PCM block 70 in a second temperature range for a second duration when a current in a second current range flows through the third thermal element 76.

[0035] The third thermal element 76 can be coupled with one or more outputs 54 of the controller 56, wherein when the controller 56 generates a first range of output voltages at the one or more outputs 54 for a first duration of time, a current within a first range of currents flows through the third thermal element 76 for the first duration of time, and when the controller 56 generates a second range of output voltages at the one or more outputs 54 for a second duration of time, a current within a second range of currents flows through the third thermal element 76 for the second duration of time. The third PCS 68 can be implemented as Figure 1 the structure of the first embodiment of the PCS 10 shown in FIG. 1 or Figure 2 the structure of the second embodiment of the PCS 10 shown in FIG. 2. The third thermal element forms a complete circuit with the ground terminal 77 of the controller 56, which can be coupled with the substrate 38, through the GND1 ground.

[0036] The reconfigurable transistor device 36 also includes a plurality of second transistor fingers 78 (disposed in a fifth region 80 above the substrate 38), wherein a first set of the plurality of second transistor fingers 78 is coupled with the first bus 50, a second set of the plurality of second transistor fingers 78 is coupled with the second bus 64, and a third set of the plurality of second transistor fingers 78 is coupled with the third bus 74. In the present exemplary embodiment, the first set of the plurality of second transistor fingers 78 includes gate fingers G5, G6, G7, and G8, and the second set of the plurality of second transistor fingers 78 includes source fingers S4, S5, and S6. The source finger S6 can be grounded by a GND2 second ground. The third set of the plurality of second transistor fingers 78 includes drain fingers D3 and D4.

[0037] The source finger S3 and the source finger S4 are adjacent source fingers of the plurality of first transistor fingers 40 and the plurality of second transistor fingers 78. The second PCS 58 crosses the source finger S3 and the source finger S4. In some embodiments, the source finger S3 and the source finger S4 are separated by the second PCS 58 by 40-50 microns. In other embodiments, the source finger S3 and the source finger S4 are separated by 30-40 microns. In other embodiments, the source finger S3 and the source finger S4 are separated by 20-30 microns. In other embodiments, the source finger S3 and the source finger S4 are separated by 1-20 microns.

[0038] In some embodiments, the plurality of first transistor fingers 40 and the plurality of second transistor fingers 78 are fabricated using gallium nitride technology. In some embodiments, the switching figure of merit of the reconfigurable transistor device 36 is in the range of 10 terahertz to 35 terahertz. In some embodiments, the on-state resistance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 0.1 Ω to 1.0 Ω. In other embodiments, the on-state resistance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 0.1 Ω to 0.5 Ω. In other embodiments, the on-state resistance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 0.5 Ω to 1.0 Ω. In some embodiments, the off-state resistance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 1000 Ω to 1000000 Ω. In other embodiments, the off-state resistance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 1000Ω to 500,000Ω. In other embodiments, the off-state resistance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 500,000Ω to 1,000,000Ω. In certain embodiments, the off-state capacitance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 0.5 picofarad to 0.001 picofarad. In other embodiments, the off-state capacitance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 0.5 picofarad to 0.1 picofarad. In other embodiments, the off-state capacitance of the first PCS 44, the second PCS 58, and the third PCS 68 is in the range of 0.1 picofarad to 0.001 picofarad.

[0039] Figure 4 The minimum noise figure NFmin of the reconfigurable transistor device is plotted against frequency (2 GHz-12 GHz). The reconfigurable transistor device includes four parallel transistors, each of which includes a Figure 3 The PCS switch of the reconfigurable transistor device 36 is shown. The minimum noise figure only moderately degrades when switching between a total gate width of 800 microns and 200 microns.

[0040] Figure 5 The Smith chart of the optimal γ of the reconfigurable transistor device is shown. The reconfigurable transistor device includes four parallel transistors, each of which includes a Figure 3 The PCS switch of the reconfigurable transistor device 36 is shown. Compared to non-switching isolation transistors (which only change the effective gate width by turning the transistor bias on or off), the optimal gamma shift provided by the PCS switch provides a relatively significant improvement in typical isolation technology for reconfigurable transistor devices.

[0041] Figure 6 A plot of maximum gain MaxGain versus frequency range (2-12 GHz) for a reconfigurable transistor device comprising four parallel transistors, each transistor comprising a gate isolation Figure 3 PCS switch of the reconfigurable transistor device shown. The maximum gain only modestly decreases when switching between total gate widths of 800 microns - 200 microns.

[0042] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present application. All such improvements and modifications are within the scope of the concepts described herein and the following claims.

Claims

1. A reconfigurable transistor device, comprising: ·Substrate; a plurality of first transistor fingers made of gallium nitride, disposed in a first region above the substrate; as well as The first phase-changing switch (PCS) includes: a first phase change material (PCM) block disposed in a second region above the substrate for selectively coupling a first group of the plurality of first transistor fingers to a first bus, wherein the first PCM block is electrically insulating in an amorphous state and electrically conductive in a crystalline state; and a first thermal element disposed proximate to the first PCM block, wherein the first thermal element is configured to maintain the first PCM block within a first temperature range until the first PCM block transitions to an amorphous state when a current within a first current range flows through the first thermal element, and to maintain the first PCM block within a second temperature range until the first PCM block transitions to a crystalline state when a current within a second current range flows through the first thermal element.

2. The reconfigurable transistor device according to claim 1, wherein: The first thermal element is configured to be coupled to one or more output terminals of a controller, wherein when the controller generates a first output voltage range at the one or more output terminals within a first duration, a current within a first current range flows through the first thermal element within the first duration, and when the controller generates a second output voltage range at the one or more output terminals within a second duration, a current within a second current range flows through the first thermal element within the second duration.

3. The reconfigurable transistor device according to claim 1, wherein: The first current range is 200 mA-500 mA, and the second current range is 700 mA-1000 mA.

4. The reconfigurable transistor device according to claim 1, wherein: The first PCM block is vanadium dioxide (VO2).

5. The reconfigurable transistor device according to claim 1, wherein: The first PCM block is germanium telluride (GeTe).

6. The reconfigurable transistor device according to claim 1, wherein: The on-state resistance of the first PCS is in the range of 0.1Ω-1.0Ω.

7. The reconfigurable transistor device according to claim 1, wherein: The off-state resistance of the first PCS is in the range of 1000Ω-1000000Ω.

8. The reconfigurable transistor device according to claim 1, wherein: The off-state capacitance of the first PCS is in the range of 0.5 pico-farad to 0.001 pico-farad.

9. The reconfigurable transistor device according to claim 1, wherein: The switching figure of merit of the reconfigurable transistor device ranges from 10 terahertz to 35 terahertz.

10. The reconfigurable transistor device according to claim 1, wherein: The first temperature range is 500°C-800°C.

11. The reconfigurable transistor device according to claim 10, wherein: The second temperature range is 100°C-300°C.

12. The reconfigurable transistor device according to claim 1, wherein: The substrate includes silicon carbide.

13. The reconfigurable transistor device according to claim 2, further comprising: · Second PCS, including: a second PCM block disposed in a third region above the substrate for selectively coupling a second group of the plurality of first transistor fingers to a second bus, wherein the second PCM block is electrically insulating in an amorphous state and electrically conductive in a crystalline state; and a second thermal element disposed proximate the second PCM block, wherein the second thermal element is configured to maintain the second PCM block within a first temperature range until the second PCM block transitions to an amorphous state when a current within a first current range flows through the second thermal element, and to maintain the second PCM block within a second temperature range until the second PCM block transitions to a crystalline state when a current within a second current range flows through the second thermal element.

14. The reconfigurable transistor device according to claim 13, wherein: The second thermal element is configured to be coupled to the one or more output terminals of the controller, wherein when the controller generates a first output voltage range at the one or more output terminals within a first duration, a current within a first current range flows through the second thermal element within the first duration, and when the controller generates a second output voltage range at the one or more output terminals within a second duration, a current within a second current range flows through the second thermal element within the second duration.

15. The reconfigurable transistor device according to claim 14, further comprising: · Third PCS, including: a third PCM block disposed in a fourth region above the substrate, for selectively coupling a third group of the plurality of first transistor fingers to a third bus, wherein the third PCM block is electrically insulating in an amorphous state and electrically conductive in a crystalline state; and a third thermal element disposed proximate the third PCM block, wherein the third thermal element is configured to maintain the third PCM block within a first temperature range for a first duration when a current within a first current range flows through the third thermal element, and to maintain the third PCM block within a second temperature range for a second duration when a current within a second current range flows through the third thermal element.

16. The reconfigurable transistor device according to claim 15, wherein: The third thermal element is configured to be coupled to the one or more output terminals of the controller, wherein when the controller generates a first output voltage range at the one or more output terminals within a first duration, a current within a first current range flows through the third thermal element within the first duration, and when the controller generates a second output voltage range at the one or more output terminals within a second duration, a current within a second current range flows through the third thermal element within the second duration.

17. The reconfigurable transistor device according to claim 16, further comprising a plurality of second transistor fingers disposed in a fifth region above the substrate, wherein A first group of the second plurality of transistor fingers is coupled to a first bus, a second group of the second plurality of transistor fingers is coupled to a second bus, and a third group of the second plurality of transistor fingers is coupled to a third bus.

18. The reconfigurable transistor device according to claim 17, wherein: The first group of the first plurality of transistor fingers and the first group of the second plurality of transistor fingers are gate fingers, and the first bus is a gate bus.

19. The reconfigurable transistor device according to claim 18, wherein: The second group of the plurality of first transistor fingers and the second group of the plurality of second transistor fingers are source fingers, and the second bus is a source bus.

20. The reconfigurable transistor device according to claim 19, wherein: Adjacent source fingers of the plurality of first transistor fingers and the plurality of second transistor fingers are separated by a second PCS and are 40 microns to 50 microns apart.

21. The reconfigurable transistor device according to claim 19, wherein: Adjacent source fingers of the plurality of first transistor fingers and the plurality of second transistor fingers are separated by a second PCS and are 30 microns to 40 microns apart.

22. The reconfigurable transistor device according to claim 19, wherein: Adjacent source fingers of the plurality of first transistor fingers and the plurality of second transistor fingers are separated by a second PCS and are 20 micrometers to 30 micrometers apart.

23. The reconfigurable transistor device according to claim 19, wherein: Adjacent source fingers of the plurality of first transistor fingers and the plurality of second transistor fingers are separated by a second PCS and are 1 micron to 20 microns apart.

24. The reconfigurable transistor device according to claim 19, wherein: A third group of the plurality of first transistor fingers and a third group of the plurality of second transistor fingers are drain fingers, and the third bus is a drain bus.

25. The reconfigurable transistor device according to claim 1, wherein: The first thermal element is sandwiched between the first PCM block and the substrate. 26 . The reconfigurable transistor device of claim 25 , further comprising a thermal insulation layer disposed between the first thermal element and the substrate.

27. The reconfigurable transistor device according to claim 26, wherein: The thermal conductivity of the thermal insulation layer is between 0.1 W / m-Kelvin and 0.4 W / m-Kelvin.

28. The reconfigurable transistor device according to claim 1, wherein: The first PCM block is sandwiched between the first thermal element and the substrate. 29 . The reconfigurable transistor device of claim 1 , further comprising a thermal insulation layer disposed above the first thermal element.

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