A UAV-borne radar signal processor and processing system

Abstract

The present invention relates to a radar signal processor and processing system for unmanned aerial vehicles. The signal processor is designed based on a Zynq chip. The Zynq chip includes a programmable logic and a processor system. The programmable logic is used to perform digital down-conversion, pulse compression, moving target detection, and constant false alarm detection on digital signals in sequence to obtain detection data. The processor system is connected to the programmable logic and is used to control the front-end intermediate frequency to transmit different radar waveforms for different targets in different working modes, and at the same time, perform differential processing on different detection data according to the control signal to obtain target information, so as to realize the search and tracking of moving targets. The signal processor is designed based on a Zynq chip. The programmable logic and processor system in the Zynq chip perform signal processing on radar echoes to obtain target information, and can realize the search and tracking of moving targets. It has the advantages of small size, low power consumption, high integration, strong reliability, low cost, etc., and can adapt to different scenarios.

Description

Technical Field

[0001] The present invention belongs to the technical field of radar signal processing, and in particular relates to an unmanned aerial vehicle-borne radar signal processor and a processing system. Background Art

[0002] Radar has the characteristics of all-day, all-weather, and long-range, and is widely used in the field of military detection. With the increasing complexity of radar signal processing algorithms, higher requirements are placed on the power consumption, integration, speed, etc. of radar signal processing systems.

[0003] Traditional radar signal processing systems mostly use DSP+FPGA architecture, which has the following defects: First, DSP and FPGA are multiple chips in themselves, and integrating them on the signal processing board will cause a large volume; second, under this architecture, the signal processor consumes relatively high power when working; third, because multiple chips are cascaded, it involves information interaction among multiple chips, and reliability may be easily affected. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a drone-mounted radar signal processor and processing system. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] An embodiment of the present invention provides a radar signal processor for an unmanned aerial vehicle, wherein the signal processor includes a target chip, and the target chip includes a programmable logic and a processor system, wherein:

[0006] The programmable logic is used to perform digital down-conversion, pulse compression, moving target detection, and constant false alarm detection on the digital signal in sequence to obtain detection data;

[0007] The processor system is connected to the programmable logic and is used to control the front-end intermediate frequency to transmit different radar waveforms for different targets under different working modes, and at the same time, perform differential processing on different detection data according to the control signal to obtain target information, thereby realizing the search and tracking of moving targets.

[0008] In one embodiment of the present invention, the target chip includes a Zynq chip.

[0009] In one embodiment of the present invention, the programmable logic includes a digital down-conversion module, a pulse compression module, a moving target detection module and a constant false alarm detection module, wherein:

[0010] The digital down-conversion module is used to sequentially mix, filter and extract the digital signal to obtain digital down-conversion data;

[0011] The pulse compression module is used to perform pulse compression on the digital down-converted data in a frequency domain manner to obtain pulse compression data;

[0012] The moving target detection module is used to perform moving target detection on the pulse compression data to obtain moving target detection data;

[0013] The constant false alarm detection module is used to perform one-dimensional sliding window processing on the moving target detection data by adopting a unit constant false alarm detection method to obtain the detection data.

[0014] In one embodiment of the present invention, a memory is further included, which is connected to the target chip and is used to store and output the pulse compression data of each frame, the moving target detection data of each frame, the detection data and the target information.

[0015] In one embodiment of the present invention, the processor system includes a first ARM core and a second ARM core, wherein:

[0016] The first ARM core is connected to the programmable logic, and is used to exchange information with the external module according to the control signal, and at the same time set the radar transmission waveform parameters of the front-end intermediate frequency, analyze the working mode of the signal processor, and send the radar transmission waveform parameters to the programmable logic, and send the analysis result of the working mode to the second ARM core;

[0017] The second ARM core is connected to the first ARM core and is used to receive the analysis result. When the analysis result is a search mode, the detection data is subjected to target aggregation, distance calculation, speed calculation, azimuth and pitch angle calculation to search for the target. When the analysis result is a tracking mode, the detection data is subjected to target aggregation, distance calculation, speed calculation, azimuth and pitch angle calculation, and at the same time, the position where the target appears in the next frame is calculated based on the current position of the target, and the data gate is clamped to the corresponding position to track the target.

[0018] In one embodiment of the present invention, an analog-to-digital conversion module is also included, wherein:

[0019] The analog-to-digital conversion module is connected to the programmable logic, and is used for receiving an analog signal and converting the analog signal into the digital signal.

[0020] In one embodiment of the present invention, the analog-to-digital conversion module includes an AD9694 chip.

[0021] Another embodiment of the present invention provides a drone-borne radar signal processing system, including a host computer display control and a signal processor, wherein:

[0022] The host computer display control is connected to the signal processor, and is used to send control information to the signal processor, and receive and display target information sent by the signal processor;

[0023] The signal processor adopts the drone-mounted radar signal processor as described in the above embodiment.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The drone-borne radar signal processor of the present invention is designed based on a target chip. The radar echo is processed by the programmable logic and processor system in the target chip to obtain relevant information of the target, so as to realize the search and tracking of moving targets. In addition, the front-end intermediate frequency is controlled to emit different radar waveforms for different targets in different working modes, so as to better realize the search and tracking of moving targets. The drone-borne radar signal processor has the advantages of small size, low power consumption, high integration, strong reliability, low cost, etc., and can adapt to different scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the structure of a drone-mounted radar signal processor provided by an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of a flow chart of a unit constant false alarm detection provided by an embodiment of the present invention;

[0028] Figure 3 A flowchart of a first ARM core control program provided by an embodiment of the present invention;

[0029] Figure 4 A flowchart of a second ARM core processing program provided by an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of the structure of a drone-mounted radar signal processing system provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0032] Embodiment 1

[0033] See also Figure 1 , Figure 1A schematic diagram of the structure of a drone-mounted radar signal processor provided by an embodiment of the present invention. The drone-mounted radar signal processor includes a target chip, an analog-to-digital conversion module and a memory, and the target chip includes a programmable logic (PL) and a processor system (PS). The programmable logic is used to perform digital down-conversion, pulse compression, moving target detection, and constant false alarm detection on the digital signal in sequence to obtain detection data; the processor system is connected to the programmable logic, and is used to control the front-end intermediate frequency to transmit different radar waveforms for different targets in different working modes, and at the same time, perform differential processing on different detection data to obtain target information, so as to realize the search and tracking of the target. The memory is connected to the target chip, and is used to store and output the pulse compression data of each frame, the moving target detection data and the detection data of each frame in the programmable logic, and store and output the target information obtained by the processor system. The analog-to-digital conversion module is connected to the programmable logic, and is used to receive analog signals and convert the analog signals into digital signals.

[0034] In a specific embodiment, the target chip includes a Zynq chip, which is composed of a programmable logic and a processor system. The Zynq chip integrates FPGA and ARM cores into a single chip, and has the characteristics of low power consumption, small size, high integration, and high reliability. The PL end of Zynq is the FPGA resource, and the PS end is mainly composed of two ARM cores. For some radar signal processing algorithms with high parallelism, they can be placed on the PL end for processing, while the PS has advantages in process control and the implementation of complex algorithms. The PL and PS of the Zynq chip can perform high-bandwidth, low-latency data transmission through a high-speed AXI interface, that is, the FPGA and ARM can exchange information through AXI, which has the characteristics of high bandwidth, low latency, and high reliability.

[0035] The drone-borne radar signal processor of this embodiment is designed based on the Zynq chip. Under the control of the ARM core, the radar signal processor has higher flexibility. It can control the front end to emit different radar waveforms for different targets in multiple working modes and perform differential processing on different data, thereby achieving more accurate search and more stable tracking of targets. It has the advantages of small size, low power consumption, high integration, strong reliability, low cost, etc.

[0036] In a specific embodiment, the signal processor and the front-end intermediate frequency exchange information through the RS422 serial port, the communication rate between the signal processor and the front-end intermediate frequency is 5Mbps, and the communication period is the same as the pulse repetition period.

[0037] In a specific embodiment, the analog-to-digital conversion module can use an AD9694 chip, which together with the Zynq chip forms a signal processor. The AD9694 has four channels and 14-bit accuracy, and can convert the input sum, difference and three intermediate frequency analog signals into digital signals, and send them to the PL end for subsequent processing through the JESD204B protocol.

[0038] Specifically, the AD chip automatically starts to collect analog signals from the front-end intermediate frequency after power-on and configuration is completed, converts the three-way sum and difference analog signals of the front-end intermediate frequency input into digital signals, and sends the digital signals to the PL end through the high-speed serial interface; when the working mode is set to search or tracking and the gate is set, the PL end will perform signal processing on the data in the post-AD gate.

[0039] In a specific embodiment, the memory includes but is not limited to DDR. In this embodiment, the DDR is externally mounted on the PL end, and the pulse pressure data of multiple pulses can be stored. After a certain number of pulses are accumulated, the data can be used for moving target detection.

[0040] In a specific embodiment, the programmable logic includes a digital down-conversion module, a pulse compression module, a moving target detection module and a constant false alarm detection module. It can be understood that the four steps of digital down-conversion, pulse compression, moving target detection and constant false alarm detection are signal processing algorithms implemented in the programmable logic (PL) of the Zynq chip.

[0041] The digital down-conversion module is used to mix, filter and extract the digital signal in sequence to obtain digital down-conversion data.

[0042] Specifically, digital down-conversion includes three parts: mixing, filtering, and decimation. Mixing is to convert the intermediate frequency signal input from the front end to zero frequency, and then filter out the high-frequency component through a low-pass filter. Since the adoption rate of AD is relatively high and the amount of data is relatively large, the data is decimated 5 times after filtering, which greatly reduces the amount of data to be processed and reduces the pressure on subsequent signal processing.

[0043] The pulse compression module is used to perform pulse compression on the digital down-converted data in the frequency domain to obtain pulse compression data.

[0044] Specifically, the time domain method is to perform time domain convolution on the down-converted data input and the matched filter; the frequency domain method is to first convert the input signal and the matched filter to the frequency domain, perform complex multiplication, and then perform inverse Fourier transform and transform to the time domain. The radar signal processor of this embodiment adopts a pulse compression method in the frequency domain, performs Fourier transform on the matched filter, stores the generated coefficients in the RAM of the PL end, performs Fourier transform on the input down-converted data, and then performs complex multiplication with the data read out from the RAM, and finally performs inverse Fourier transform to complete pulse compression.

[0045] The moving target detection module is used to perform moving target detection (MTD) on the pulse compression data to obtain moving target detection data.

[0046] Specifically, this embodiment accumulates 64 pulses, and 64 pulses form a frame. Four storage addresses are opened in the memory DDR and named A, B, C, and D respectively. The data after the 64 pulses are compressed is stored in the address A of the DDR. After the data of the first frame is stored, it is read out after transposition, and the 64-point MTD is performed. Then, the MTD data is written into the address B of the DDR again. After all the data of a frame are MTDed and stored in the DDR, it is read out from the DDR after transposition again, and the unit constant false alarm detection is performed.

[0047] Furthermore, two storage areas are opened in DDR to perform ping-pong operation on the data. After the nth frame of data is stored, the data of the nth frame is transposed and read out for processing. At this time, the data of the n+1th frame is also continuously input, so another address is opened in DDR to store the data of the n+1th frame. Before the data of the n+1th frame is stored, the data of the nth frame will be processed. When the data of the n+2th frame arrives, it will be stored in the address where the data of the nth frame was previously stored. It can be understood that after the data of the n+1th frame is stored, it will be transposed and read out from DDR for processing. At the same time, the data of the n+2th frame arrives and is stored in the address of the data of the nth frame. This cycle is repeated to perform ping-pong operation on the data, which better improves the real-time and parallel performance of signal processing. For example, while processing the data of the first frame, the data of the 64 pulses compressed in the second frame are also continuously arriving. When processing the data of the first frame, the pulse compressed data of the second frame will be stored in address C. After all the data of the second frame are written into DDR, the data will be transposed and read out for subsequent MTD, and then the MTD data will be stored in address D. After completion, the data will be transposed and read out for constant false alarm detection. At this time, when processing the data of the second frame, the data of the third frame has also arrived, and it will be stored in the address of the first frame, overwriting the data of the first frame, and so on. It can be seen that the prerequisite for this operation is to be able to complete the MTD and constant false alarm detection of one frame of data within one frame of data, that is, 64 pulses, that is, the MTD and constant false alarm detection of the nth frame of data must be completed before the data of the 64 pulses of the n+1th frame are completely written into DDR.

[0048] The constant false alarm detection module is used to perform one-dimensional sliding window processing on moving target detection data by adopting a unit constant false alarm detection method to obtain detection data.

[0049] Specifically, the CFAR detection algorithm uses a unit CFAR detection method, which has the advantage of being simple and easy to implement, and can easily implement parallel CFAR detection on the PL side. Figure 2 , Figure 2 A schematic diagram of a flow chart of a unit constant false alarm detection provided by an embodiment of the present invention. The unit constant false alarm detection of this embodiment adopts a one-dimensional sliding window processing, based on Figure 2 , the steps are as follows: the first step is to calculate the threshold coefficient value T according to the clutter distribution corresponding to the environmental background to be detected and the false alarm probability of the indicator; the second step is to take the modulus value of the data of the sum path and only detect the sum path data; the third step is to take two protection units before and after the unit D to be detected; the fourth step is to take 16 reference units in front of the front protection unit and behind the rear protection unit, namely x1~xn and y1~yn, and respectively calculate the mean values ​​X and Y of the front and rear reference units; the fifth step is to add the mean values ​​X and Y of the reference units to get Z, multiply it by the threshold coefficient T and compare it with the unit D to be detected. If the value is greater than the unit to be detected, unit, it is not the target scattering point; if the value is less than or equal to the unit to be detected, it indicates that the unit to be detected is the scattering point of the target, and its distance point number, Doppler channel number, and amplitude size are stored in RAM, and the amplitude values ​​of the two difference data corresponding to the same distance point number and Doppler channel number are also stored in RAM; in the sixth step, take the next unit to be detected, repeat the second to fourth steps until all the data are detected by the sliding window; in the seventh step, when all the data are detected, the amplitude values ​​of the sum, difference and difference three-way data, the corresponding distance point number and Doppler channel number are transmitted to the processor system through the Zynq's on-chip AXI bus.

[0050] In a specific embodiment, the processor system includes a first ARM core and a second ARM core. The first ARM core is connected to the programmable logic, and is used to exchange information with the external module according to the control signal, and at the same time set the radar transmission waveform parameters of the front-end intermediate frequency, analyze the working mode of the signal processor, and send the radar transmission waveform parameters to the programmable logic, and send the analysis result of the working mode to the second ARM core. The second ARM core is connected to the first ARM core, and is used to receive the analysis result. When the analysis result is the search mode, the detection data is subjected to target condensation, distance calculation, speed calculation, azimuth and pitch angle calculation to search for the target. When the analysis result is the tracking mode, the detection data is subjected to target condensation, distance calculation, speed calculation, azimuth and pitch angle calculation, and at the same time, the position where the target will appear in the next frame is calculated according to the current position of the target, and the data wave gate is clamped to the corresponding position to track the target. The radar transmission waveform parameters obtained by the first ARM core are directly forwarded to the front-end intermediate frequency through the programmable logic.

[0051] It can be understood that the processor system (PS) is mainly composed of two ARM cores, core 0 (i.e., the first ARM) and core 1 (i.e., the second ARM core). Core 0 is mainly responsible for external information exchange, switching different working states according to the commands received from the upper computer display control, setting the radar transmission waveform parameters of the front-end intermediate frequency, parsing the working mode of the signal processor, and sending the radar transmission waveform parameters to the programmable logic, and sending the parsing results of the signal processor working mode to core 1; wherein the working mode includes but is not limited to standby, self-test, search, tracking, etc. Core 1 receives the parsing results of the working mode from core 0, and performs different data processing according to different working modes, mainly further processing the data detected by the PL end and calculating the distance, speed, angle and other information of the target. In the tracking stage, core 1 is also responsible for setting the wave gate and setting the front-end intermediate frequency radar transmission waveform parameters to track the target more accurately.

[0052] See also Figure 3 , Figure 3 A flowchart of a first ARM core control program provided by an embodiment of the present invention. Figure 3 According to the flowchart, the programmable logic will generate an information update interrupt with a cycle consistent with the frame cycle, which notifies core 0 to initiate direct memory access (DMA) transmission. Core 0 sends the control parameters of the front-end intermediate frequency, the target information parameters after signal processing, etc. from the processor system to the programmable logic, and the programmable logic then forwards them outward according to the timing; within a communication cycle, after the programmable logic completes the reception of the control information of the host computer display and control, an upper computer display and control system interrupt will be generated, which notifies core 0 to initiate DMA transmission and transmits the control information of the host computer from the programmable logic to the DDR of the processor system. Core 0 analyzes the working mode based on this information and performs corresponding subsequent operations according to the working mode; each time the programmable logic completes the constant false alarm detection of the signal data, a PL-end data detection completion interrupt will be generated, which will inform core 0 to initiate DMA transmission and transmit the detected data from the programmable logic to the DDR of the processor system for further processing; after the programmable logic completes the reception of the front-end intermediate frequency information, a front-end intermediate frequency information transmission interrupt will be generated, which notifies core 0 to receive the information from the front-end intermediate frequency for standby use.

[0053] If it is a control command from the host computer, core 0 will determine what the specific command is. If the control command is standby mode, the parameters of the signal processor and the front-end intermediate frequency are initialized, and the radar transmission of the front-end intermediate frequency is set to 0, so that it is in a closed state. At this time, core 0 will not start core 1 for the next step of signal processing. If the control command is self-test mode, core 0 starts core 1 and further processes the detected data transmitted by PL to see whether the result is consistent with the expected result. If it meets the expected result, it will determine whether the self-test status transmitted by the intermediate frequency is normal. If the signal processor and the front-end intermediate frequency are normal, the reported information will be set to self-test success. If there is a problem with one of them, it will be set to self-test abnormal. If the control command is search mode, the wave gate of the PL end card is calculated according to the upper and lower limits of the search distance, and the front-end transmission is set to 1 to start the transmission; at the same time, wake up core 1 to let it perform further signal processing on the detection results transmitted by PL. If the control command is tracking mode, similarly, the wave gate position is calculated according to the tracking range, and the front-end radar is in the transmitting state. The difference from searching is that in the tracking phase, only the distance range adjustment gate set for the first time is valid. The gate position in the subsequent tracking phase is calculated by the target distance after signal processing. In this way, after detecting the target in the tracking mode, the processor system can adjust the gate through its own signal processing results and predict the target's position, adjust the azimuth and pitch angles of the front-end servo system, and realize automatic tracking of the target.

[0054] See also Figure 4 , Figure 4 A flowchart of a second ARM core processing program provided by an embodiment of the present invention. Figure 4The flowchart of core 1, core 1 is mainly used to further process the data of the threshold point after detection, and it mainly works in three modes. The first is in the self-check mode, the detection results sent by PL are subjected to target condensation, and the distance of the target is calculated according to the distance points and gate information of the condensed target, the speed of the target is calculated according to the number of Doppler channels, and the pitch angle and azimuth are calculated according to the corresponding sum data and two-way difference data; and the obtained distance, speed, azimuth, and pitch angle information are compared with the expected results to determine whether the signal processor self-checks normally. The second is in the search mode, and the detection results sent by the PL end are also subjected to target condensation. If there is no target, the target information is set to the initial state. If there is a target, the Doppler dimension and distance dimension target condensation are started, and the distance, speed, azimuth and pitch angle of the target are calculated according to the results of target condensation, and transmitted to the host computer. Core 1 can process three targets at the same time. The third type is in tracking mode. The detection results are subjected to target condensation in the Doppler dimension and the distance dimension. Only one target is selected for tracking during the tracking stage. Therefore, after the target condensation, only the target with the largest amplitude is selected, and its speed, distance, azimuth and pitch angle are calculated and transmitted to the upper computer display and control system. At the same time, the position of the target in the next frame is predicted based on the distance, speed and speed of the flight platform, and the position of the wave gate is set to shrink the distance of the wave gate, which is conducive to more stable and accurate tracking of the target. These set parameters will be transmitted to the PL end through DMA when the information update interrupt with a period consistent with the frame period arrives, and the wave gate and the front-end intermediate frequency of the signal processing are controlled, thereby realizing automatic tracking of the target.

[0055] This implementation can achieve automatic tracking of moving targets through information analysis of the target, and automatically adjust the emitted radar waveform according to different distances of the target, so as to better achieve stable tracking of the target.

[0056] Furthermore, high-bandwidth, low-latency data transmission is performed between the programmable logic (PL) and the processor system (PS) through a high-speed AXI interface for information exchange, which has the characteristics of high bandwidth, low latency and high reliability.

[0057] Furthermore, the signal processor of this embodiment is an unmanned aircraft radar system. The aircraft equipped with the radar system will have a speed. When processing the signal, the speed of the platform needs to be compensated. Therefore, this processor needs to obtain the flight speed of the aircraft and compensate for it during signal processing in order to accurately process the signal. When tracking, the flight speed itself will also affect the prediction of the wave gate. Knowing the flight speed of the aircraft can obtain a more accurate wave gate position. After the flight speed is known, according to the phase term formula, where v is the radial phase velocity of the radar platform relative to the target position, Tr is the pulse repetition period, M is the pulse sequence, and λ is the wavelength, the corresponding coefficient is calculated at the PS end and sent to the PL end to be multiplied by the corresponding pulse after pulse compression to complete the speed compensation. After speed compensation, the speed of the target relative to the stationary ground can be obtained.

[0058] The working process of the radar signal processor of this embodiment is as follows: the processor receives three-way sum and difference radar echo analog signals from the front-end intermediate frequency, and the two-way difference data are respectively the pitch difference data and the azimuth difference data. The pitch angle and azimuth angle errors of the target can be measured by using a single pulse angle measurement. The AD9694 chip converts the intermediate frequency analog signal into a digital signal and transmits the digital signal to the PL end through the high-speed interface JESD204B protocol. The sampling frequency of the ADC is 400MHz with 14-bit accuracy. After receiving the digital signal, the PL end performs digital down-conversion, pulse compression, and MTD processing on the three signals, and then performs unit constant false alarm detection on the sum signal, saves the distance position, number of Doppler channels, and amplitude of the threshold point, and finds the amplitude of the two difference data corresponding to the distance position and number of Doppler channels, and transmits this information to the processor system through the AXI bus protocol. After receiving these data, the processor system will process these data accordingly according to the working mode set by the host computer control. At the same time, the processor system will also set the working parameters of the front-end intermediate frequency according to the working mode set by the host computer to adapt to the emission of more suitable radar waveforms in different scenarios.

[0059] The radar signal processor of this embodiment can automatically set the radar waveform emitted by the front-end intermediate frequency by setting the distance range of the correlation search. The detection distance is between 150 meters and 12,000 meters, and it has good flexibility. At the same time, the radar signal processor can obtain relevant information such as the distance, speed, azimuth, and pitch angle of the target through the processing of the three-way signal of the sum and difference through the correlation signal processing algorithm, and the measured distance error is less than 7m, the speed error is less than 1m / s, and the angle error is less than 0.3 degrees in the linear area, and the measurement accuracy is relatively high.

[0060] The drone-borne radar signal processor of this embodiment is designed based on a target chip. The radar echo is processed by the programmable logic and processor system in the target chip to obtain target information, which can realize the search and tracking of moving targets. In addition, the front-end intermediate frequency can be controlled to emit different radar waveforms for different targets in different working modes, so as to better realize the search and tracking of targets. It has the advantages of small size, low power consumption, high integration, high reliability, low cost, etc., and can adapt to different scenarios, such as realizing the search and automatic tracking of targets such as vehicles moving on the ground.

[0061] Embodiment 2

[0062] Based on Example 1, see Figure 5 , Figure 5 A schematic diagram of the structure of a drone-mounted radar signal processing system provided by an embodiment of the present invention. The drone-mounted radar signal processing system includes: a host computer display control and a signal processor. The host computer display control is connected to the signal processor, and is used to send control information to the signal processor, and receive and display target information sent by the signal processor. The signal processor adopts the drone-mounted radar signal processor of embodiment 1.

[0063] In a specific embodiment, the function of the upper computer display control is mainly to control the radar signal processor, display the signal processing results in real time, and display the working status of the signal processor in real time. The control information it sends to the signal processor includes standby, self-test, search, and tracking. When the control information is in standby mode, the radar signal processing system is in standby mode and does not work. When the control information is in self-test mode, the signal processor will perform signal processing on the data burned in its own RAM. If the processing result is normal, it indicates that the hardware and algorithm of the signal processor are normal; the front-end intermediate frequency sends its own working status, self-test status and other information to the signal processor through the serial port. After determining that the signal processor is working normally, the self-test status sent to the signal processor by the front-end intermediate frequency is judged. If the signal processor and the front-end intermediate frequency are both self-tested normally, the signal processor reports the self-test to the upper computer. If one of the two parts is abnormal, the self-test abnormal state is sent. The upper computer can set the working mode of the signal processing system according to actual needs. After the self-test is normal, it indicates that the front-end intermediate frequency and the signal processor can work normally. At this time, the upper computer display and control sets the working mode to search mode, and sets the upper and lower limits of the search. After the signal processor receives the search command, it will calculate the position of the capo gate according to the upper and lower limits of the search, that is, determine which section of the front-end intermediate frequency input signal is within the search range, and perform signal processing on this part of the data.

[0064] Specifically, the host computer display and control communicate with the signal processor through the RS422 serial port. The communication rate between the signal processor and the host computer is 230.4kbps, and the communication cycle is 20ms.

[0065] The unmanned aerial vehicle radar signal processing system of this embodiment controls the working mode of the radar system through the upper computer display and control. Only the upper computer display and control are needed to control the entire radar signal processing system, and the operation is simple.

[0066] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A drone-mounted radar signal processor, characterized in that: The signal processor includes a target chip, and the target chip includes a programmable logic and a processor system, wherein: The programmable logic is used to perform digital down-conversion, pulse compression, moving target detection, and constant false alarm detection on the digital signal in sequence to obtain detection data; The processor system is connected to the programmable logic, and is used to control the front-end intermediate frequency to transmit different radar waveforms for different targets in different working modes, and at the same time, perform differential processing on different detection data according to the control signal to obtain target information, so as to realize the search and tracking of moving targets; The processor system includes a first ARM core and a second ARM core, wherein the first ARM core is connected to the programmable logic and is used to update an interrupt with an information update having a period consistent with a frame period generated by the programmable logic, and send control parameters of the front-end intermediate frequency and target information parameters after signal processing from the processor system to the programmable logic; transmit control information of the host computer from the programmable logic to the processor system according to an interrupt of the upper computer display and control system generated by the programmable logic, set a working state according to the control information, calculate the start and length parameters of the wave gate under the search and tracking commands, and adjust the waveform parameters of the front-end intermediate frequency radar according to the set search or tracking distance range; transmit the detection result of the target from the programmable logic to the processor system according to the programmable logic end data detection completion interrupt generated by the programmable logic, and send a start signal to the second ARM core in the search, tracking and self-test states, and initialize each control parameter in the standby state; transmit the information sent by the intermediate frequency to the processor system according to the front-end intermediate frequency information transmission interrupt generated by the programmable logic; The second ARM core is connected to the first ARM core, and is used to, in the self-test mode, perform target aggregation in the distance dimension and Doppler dimension on the detection results sent by the programmable logic, calculate the distance and speed of the target according to the distance unit and Doppler coordinates of the aggregated target, find the two difference data of the same distance unit and Doppler channel to calculate the pitch angle and azimuth, and when it is judged that the self-test result of the signal processor is the same as the expected result, judge whether the self-test of the front-end intermediate frequency is normal, and when the self-test of the front-end intermediate frequency is normal, set the self-test state to normal; in the search mode, perform target aggregation in the distance dimension and Doppler dimension on the detection results sent by the programmable logic The target is condensed, and the distance and speed of the target are calculated according to the distance unit and Doppler coordinates of the condensed target. The obtained distance, speed, azimuth and pitch angle of the target are saved and wait for the arrival of the first ARM core interrupt to be sent to the host computer for display; in the tracking mode, the detection results sent by the programmable logic are condensed into targets in the distance dimension and Doppler dimension, and the distance and speed of the target are calculated according to the distance unit and Doppler coordinates of the condensed target. The obtained distance, speed, azimuth and pitch angle of the target are saved and wait for the arrival of the first ARM core interrupt to be sent to the host computer for display, and the wave gate of the next frame is predicted according to the distance of the target, and the radar waveform emitted by the front-end intermediate frequency is set.

2. The UAV-mounted radar signal processor according to claim 1, characterized in that: The target chip includes a Zynq chip.

3. The UAV-mounted radar signal processor according to claim 1, characterized in that: The programmable logic includes a digital down-conversion module, a pulse compression module, a moving target detection module and a constant false alarm detection module, wherein: The digital down-conversion module is used to sequentially mix, filter and extract the digital signal to obtain digital down-conversion data; The pulse compression module is used to perform pulse compression on the digital down-converted data in a frequency domain manner to obtain pulse compression data; The moving target detection module is used to perform moving target detection on the pulse compression data to obtain moving target detection data; The constant false alarm detection module is used to perform one-dimensional sliding window processing on the moving target detection data by adopting a unit constant false alarm detection method to obtain the detection data.

4. The UAV-mounted radar signal processor according to claim 3, characterized in that: It also includes a memory, which is connected to the target chip and is used to store and output the pulse compression data of each frame, the moving target detection data of each frame, the detection data and the target information.

5. The UAV-mounted radar signal processor according to claim 1, characterized in that: It also includes an analog-to-digital conversion module, wherein: The analog-to-digital conversion module is connected to the programmable logic and is used to receive an analog signal and convert the analog signal into the digital signal.

6. The UAV-mounted radar signal processor according to claim 5, characterized in that: The analog-to-digital conversion module includes an AD9694 chip.

7. An unmanned aerial vehicle radar signal processing system, characterized in that: It includes host computer display control and signal processor, among which, The host computer display control is connected to the signal processor, and is used to send control information to the signal processor, and receive and display target information sent by the signal processor; The signal processor adopts the unmanned aerial vehicle radar signal processor as claimed in any one of claims 1 to 6.

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