Memristor-based integrated computing unit, array circuit, and control method

Abstract

The present invention provides a memristor-based storage and computing integrated computing unit, an array circuit, and a control method. The drain of a first MOS tube of the computing unit is connected to a first voltage input signal, and the source of a second MOS tube is connected to a second voltage input signal; the gate of the first MOS tube and the gate of the second MOS tube are commonly connected to a control voltage signal; the source of the first MOS tube is connected to one end of the first memristor, and the drain of the second MOS tube is connected to one end of the second memristor; the other end of the first memristor and the other end of the second memristor are commonly connected to the gate of a fourth MOS tube; the drain of the fourth MOS tube is connected to the source of the third MOS tube, the source of the fourth MOS tube is connected to the drain of a fifth MOS tube, the source of the fifth MOS tube is grounded, and the drain of the third MOS tube serves as a current output end, thereby improving the accuracy of the circuit output current and realizing a neural network pruning function in hardware.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a memristor-based storage and computing integrated computing unit, an array circuit, and a control method. Background Art

[0002] The von Neumann architecture is a classic computer structure. Its operating principle is that when calculations are required, data is first stored in storage units. Instructions then move the data from the storage units to the logic units. After the calculations are completed in the logic units, the results are stored in the storage units. However, as the amount of data in deep learning tasks increases, the traditional von Neumann architecture requires frequent memory reads and writes. The overhead of frequent memory access by the processor creates a memory wall. Integrated storage and computing is a solution designed to address this memory wall problem. The basic idea behind integrated storage and computing is to combine computation and storage, thereby reducing the frequency with which the processor accesses memory.

[0003] Integrated memory and computation circuits can be used for multiplication and addition operations in neural networks. Neural networks contain a large number of redundant neurons and weights, with only 5-10% of the weights involved in the main calculations and influencing the final results. Therefore, research on neural network pruning is particularly important. Pruning can not only filter out and delete unimportant neurons and weights from large networks, thereby compressing the network, but also preserve network performance as much as possible.

[0004] Therefore, how to implement the pruning function in hardware is still an urgent problem to be solved in the field of integrated circuit design. Summary of the Invention

[0005] The present invention provides a memristor-based integrated storage and computation computing unit, an array circuit, and a control method, to solve the problem in the prior art that neural network pruning cannot be implemented in hardware.

[0006] The present invention provides a memristor-based storage and computing integrated computing unit, the computing unit being used to perform convolution operations in a neural network, the computing unit comprising a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first memristor, and a second memristor;

[0007] The drain / source of the first MOS transistor is connected to a first voltage input signal, and the source / drain of the second MOS transistor is connected to a second voltage input signal; the gate of the first MOS transistor and the gate of the second MOS transistor are commonly connected to a control voltage signal; the source / drain of the first MOS transistor is connected to one end of the first memristor, and the drain / source of the second MOS transistor is connected to one end of the second memristor; the other end of the first memristor and the other end of the second memristor are commonly connected to the gate of the fourth MOS transistor; the drain of the fourth MOS transistor is connected to the source of the third MOS transistor, and the source of the fourth MOS transistor is connected to the drain / source of the fifth MOS transistor; the gate of the fifth MOS transistor is connected to a first bias voltage, and the source / drain of the fifth MOS transistor is grounded; the gate of the third MOS transistor is connected to a second bias voltage, and the drain of the third MOS transistor serves as a current output end.

[0008] The present invention further provides an array circuit, comprising: a plurality of memristor-based integrated storage and computation units as described above, arranged in an array;

[0009] The first bias voltage of each computing unit is the same, the second bias voltage of each computing unit is the same, the first voltage input signal of each computing unit in the same row is the same, the second voltage input signal of each computing unit in the same row is the same, and the current output ends of each computing unit in the same column are connected together.

[0010] According to an array circuit provided by the present invention, the control voltage signals of the computing units in the same column are the same.

[0011] The present invention further provides a control method based on the above array circuit, comprising:

[0012] determining a control voltage signal for each computing unit in the array circuit;

[0013] Based on the control voltage signal of each computing unit, the on-off of the first MOS transistor and the second MOS transistor of each computing unit is controlled to control the working state of each computing unit.

[0014] According to a control method provided by the present invention, the current at the current output end of any calculation unit is:

[0015] I out =V in ×W×IO

[0016] Among them, V in is the input value of any of the calculation units, W is the weight of any of the calculation units, and IO is the preset current;

[0017] The input value is determined based on a first voltage input signal and a second voltage input signal of any one of the computing units, and the weight is determined based on resistance values ​​of a first memristor and a second memristor of any one of the computing units.

[0018] According to a control method provided by the present invention, determining the control voltage signal of each computing unit in the array circuit includes:

[0019] Based on the bits corresponding to the weights of the calculation units, the control voltage signals of the calculation units are determined.

[0020] According to a control method provided by the present invention, the input value of any calculation unit is determined based on the following steps:

[0021] If the working state of any of the computing units is working, the first voltage input signal of any of the computing units is at a high level, and the second voltage input signal of any of the computing units is at a low level, then the input value of any of the computing units is the first input value;

[0022] Otherwise, the input value of any one of the calculation units is the second input value.

[0023] According to a control method provided by the present invention, the weight of any calculation unit is determined based on the following steps:

[0024] If the resistance value of the first memristor of any of the computing units is a low resistance value, and the resistance value of the second memristor of any of the computing units is a high resistance value, then the weight of any of the computing units is the first weight;

[0025] Otherwise, the weight of any one of the calculation units is the second weight.

[0026] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements any of the control methods described above when executing the program.

[0027] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which implements any of the control methods described above when executed by a processor.

[0028] The present invention provides a memristor-based integrated storage and computation computing unit, array circuit, and control method. The computing unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first memristor, and a second memristor. The computing unit can be used to perform convolution operations in a neural network and implement an integrated storage and computation function. The memristor resistance is divided to drive the gate of the fourth MOS transistor, and a cascode structure is combined to output current, thereby improving the accuracy of the circuit output current. Furthermore, by controlling the connection of a voltage signal to the gates of the first and second MOS transistors, a pruning function of the neural network can be implemented. This reduces the hardware overhead required for the calculation, reduces the number of operations, and improves the calculation speed of the neural network. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 This is a schematic diagram of the circuit structure of a memristor-based storage and computing integrated computing unit provided by the present invention;

[0031] Figure 2 This is one of the structural diagrams of the array circuit provided by the present invention;

[0032] Figure 3 This is the second structural diagram of the array circuit provided by the present invention;

[0033] Figure 4 This is one of the example diagrams of the connection method of the control voltage signal provided by the present invention;

[0034] Figure 5 This is the second example diagram of the connection method of the control voltage signal provided by the present invention;

[0035] Figure 6 This is the third example diagram of the connection method of the control voltage signal provided by the present invention;

[0036] Figure 7 It is a flow chart of the control method provided by the present invention;

[0037] Figure 8 It is a structural schematic diagram of the electronic device provided by the present invention;

[0038] Reference numerals:

[0039] M1: first MOS tube; M2: second MOS tube; M3: third MOS tube;

[0040] M4: fourth MOS transistor; M5: fifth MOS transistor; RRAM1: first memristor;

[0041] RRAM2: second memristor; VL1: first voltage input signal;

[0042] VLB1: second voltage input signal; Vopen1: control voltage signal;

[0043] VBIAS: first bias voltage; VCAS: second bias voltage;

[0044] IOUT11: current output terminal. DETAILED DESCRIPTION

[0045] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0046] The current mainstream storage and computing integrated circuits are mainly based on memristors. Memristors are a type of resistive nonlinear resistor whose resistance can be changed by controlling signals, making "1" represent high resistance and "0" represent low resistance. By utilizing its non-volatile properties, its resistance can be regarded as a way of data storage.

[0047] To this end, the present invention provides a memristor-based integrated storage and computation unit, which is used to perform convolution operations in a neural network. Figure 1 Schematic diagram of the circuit structure of the computing unit based on memristor storage and computing provided by the present invention, as shown in FIG. Figure 1 As shown, the computing unit includes a first MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a first memristor RRAM1, and a second memristor RRAM2;

[0048] Among them, the drain / source of the first MOS transistor M1 is connected to the first voltage input signal VL1, and the source / drain of the second MOS transistor M2 is connected to the second voltage input signal VLB1; the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are commonly connected to the control voltage signal Vopen1; the source / drain of the first MOS transistor M1 is connected to one end of the first memristor RRAM1, and the drain / source of the second MOS transistor M2 is connected to one end of the second memristor RRAM2; the other end of the first memristor RRAM1 One end of the second memristor RRAM2 and the other end of the second memristor RRAM2 are commonly connected to the gate of the fourth MOS transistor M4; the drain of the fourth MOS transistor M4 is connected to the source of the third MOS transistor M3, and the source of the fourth MOS transistor M4 is connected to the drain / source of the fifth MOS transistor M5; the gate of the fifth MOS transistor M5 is connected to the first bias voltage VBIAS, and the source / drain of the fifth MOS transistor M5 is grounded; the gate of the third MOS transistor M3 is connected to the second bias voltage VCAS, and the drain of the third MOS transistor M3 serves as the current output end IOUT11.

[0049] Specifically, the memory-computing integrated computing unit based on memristor includes three input voltage terminals, namely, a control voltage signal Vopen1, a first voltage input signal VL1, and a second voltage input signal VLB1, and a current output terminal IOUT11; the computing unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5, a first memristor RRAM1, and a second memristor RRAM2; the resistance values ​​of the first memristor RRAM1 and the second memristor RRAM2 are R1 and R2, respectively, and the corresponding conductances are G1 and G2, respectively, and the resistance types may include low-low resistance (LLRS), low resistance (LRS), high resistance (HRS), and high-high resistance (HHRS).

[0050] The drain of the first MOS transistor M1 is connected to the first voltage input signal VL1, and the source of the second MOS transistor M2 is connected to the second voltage input signal VLB1; the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are commonly connected to the control voltage signal Vopen1; the source of the first MOS transistor M1 is connected to one end of the first memristor RRAM1, and the drain of the second MOS transistor M2 is connected to one end of the second memristor RRAM2; the other end of the first memristor RRAM1 and the other end of the second memristor RRAM2 are commonly connected to the gate of the fourth MOS transistor M4; the drain of the fourth MOS transistor M4 is connected to the source of the third MOS transistor M3, and the source of the fourth MOS transistor M4 is connected to the drain of the fifth MOS transistor M5; the gate of the fifth MOS transistor M5 is connected to the first bias voltage VBIAS, the source of the fifth MOS transistor M5 is connected to the negative electrode of the power supply, and the negative electrode of the power supply is grounded; the gate of the third MOS transistor M3 is connected to the second bias voltage VCAS, and the drain of the third MOS transistor M3 serves as the current output terminal IOUT11;

[0051] In addition, according to the characteristics of the MOS transistors, the source and drain of the first MOS transistor M1, the second MOS transistor M2, and the fifth MOS transistor M5 are interchangeable without affecting the function of the device, that is, the source of the first MOS transistor M1 is connected to the first voltage input signal VL1, the drain of the first MOS transistor M1 is connected to one end of the first memristor RRAM1, the drain of the second MOS transistor M2 is connected to the second voltage input signal VLB1, the source of the second MOS transistor M2 is connected to one end of the second memristor RRAM2, the source of the fourth MOS transistor M4 is connected to the source of the fifth MOS transistor M5, and the drain of the fifth MOS transistor M5 is connected to the negative electrode of the power supply. Optionally, the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, and the fifth MOS transistor M5 are NMOS (N-Metal-Oxide-Semiconductor) transistors.

[0052] It can be understood that when VL1 is equal to VLB1, no current flows between VL1 and VLB1. When VL1 is greater than VLB1, current flows through RRAM1 and RRAM2, resulting in a voltage divider between RRAM1 and RRAM2. The other end of RRAM1 and the other end of RRAM2 are connected at node VP. The voltage at node VP is used to drive and control the conduction and cutoff of the fourth MOS transistor M4M4. Different values ​​of VL1, VLB1, R1, and R2 will cause the voltage value of node VP to change. To make M4 conductive, the following conditions must be met:

[0053] (VL1-VLB1)×(R2 / (R1+R2))>Vth4

[0054] Wherein, Vth4 is the threshold voltage of M4.

[0055] To ensure the normal operation of the circuit of this embodiment, appropriate VL1 and VLB1 should be selected; the minimum difference between VL1 and VLB1 is determined by the following formula:

[0056] (VL1-VLB1)>Vth4 / (R2 / (R1+R2))

[0057] For example, if the threshold voltage of M4 is 0.5V, R1 is 10K (LRS), and R2 is 100K (HRS), then the minimum difference between VL1 and VLB1 should be 0.55V to ensure the accuracy of the circuit in this embodiment.

[0058] It should be noted that, unlike the prior art method of directly outputting current from a node of the memristor, which has poor driving capability and cannot work properly, and because the high and low resistance margins of the memristor are low, it is difficult to control a precise resistance value, resulting in unstable current values. In the embodiment of the present invention, the gate of the fourth MOS tube M4 is driven by the memristor resistance voltage division to output current. First, the driving capability of the output node can be improved, and second, the error caused by the direct output of the current generated by the voltage passing through the memristor can be effectively prevented. On this basis, combined with the cascode current mirror formed by M3 and M5, the current output terminal IOUT11 can output a stable current of 10 A. It can be understood that when M4 is turned on, IOUT11 generates a current output of 10 A; when M4 is turned off, IOUT11 outputs a current of 0 A.

[0059] In addition, the control voltage signal Vopen1 of the computing unit is connected to the gates of M1 and M2. When the voltage value of Vopen1 is greater than the threshold voltage Vth1 of M1 and the threshold voltage Vth2 of M2, M1 and M2 are turned on, so that the computing unit is turned on and operates normally. When the voltage value of Vopen1 is less than Vth1 and Vth2, M1 and M2 are turned off, and the computing unit does not operate. This computing unit is used to perform convolution operations in the neural network, so that the corresponding computing unit can be pruned by controlling the voltage value of the voltage signal Vopen1, realizing the pruning function of the neural network. Furthermore, the specifications of M1 and M2 can be the same, and Vth1 and Vth2 can be the same.

[0060] The computing unit provided in an embodiment of the present invention includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first memristor, and a second memristor, and can be used to perform convolution operations in a neural network and realize a storage-computation integrated function. By using the memristor resistance voltage division to drive the gate of the fourth MOS transistor, and combining it with a cascode structure to output current, the accuracy of the circuit output current can be improved. In addition, by controlling the connection of the voltage signal to the gates of the first MOS transistor and the second MOS transistor, a pruning function of the neural network can be realized. While reducing the hardware overhead required for the calculation, the number of operations is reduced, and the calculation speed of the neural network is improved.

[0061] Based on the above embodiments, the present invention provides an array circuit. Figure 2 This is one of the structural diagrams of the array circuit provided by the present invention, such as Figure 2 As shown, the array circuit includes: a plurality of memristor-based integrated computing units as described in the above embodiment arranged in an array;

[0062] The first bias voltage of each computing unit is the same, the second bias voltage of each computing unit is the same, the first voltage input signal of each computing unit in the same row is the same, the second voltage input signal of each computing unit in the same row is the same, and the current output ends of each computing unit in the same column are connected together.

[0063] Specifically, the array circuit is composed of a plurality of memristor-based storage and computational integrated computing units arranged in an array as described in the above embodiments, with a total of K rows and N columns, where K and N are positive integers, thereby supporting convolution operations of larger-scale neural networks.

[0064] The first bias voltages of the K×N computing units can be the same, the second bias voltages of the K×N computing units can be the same, the first voltage input signals of the computing units in the same row can be the same, and the second voltage input signals of the computing units in the same row can be the same. The current output terminals of the computing units in the same column can be connected together, and the total current output by the computing units in each column can be accumulated.

[0065] It should be noted that, since it is necessary to control whether each computing unit is working through the control voltage signal of each computing unit to realize the pruning function of the neural network, the connection method of the control voltage signal of each computing unit in the embodiment of the present invention can be specifically set according to actual requirements such as control accuracy and control quantity. For example, each computing unit can be connected to an independent control voltage signal, every two computing units can be connected to a control voltage signal, every K computing units can be connected to a control voltage signal, every K×2 computing units can be connected to a control voltage signal, every K×3 computing units can be connected to a control voltage signal, or every K×N computing units can be connected to a control voltage signal, etc. The embodiment of the present invention does not make specific limitations on this.

[0066] The array circuit provided in an embodiment of the present invention, through a computing unit including a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first memristor, and a second memristor, can be used to perform convolution operations in a neural network and realize a storage-computation integrated function. By driving the gate of the fourth MOS transistor through voltage division by the memristor resistance value, and combining it with a cascode structure to output current, the accuracy of the circuit output current can be improved. In addition, by controlling the voltage signal connected to the gates of the first MOS transistor and the second MOS transistor, a pruning function of the neural network can be realized. While reducing the hardware overhead required for calculation, the number of operations is reduced and the calculation speed of the neural network is improved. On this basis, by including multiple computing units arranged in an array, convolution operations of larger-scale neural networks can be supported.

[0067] Based on any of the above embodiments, the control voltage signals of the computing units in the same column are the same.

[0068] Specifically, Figure 3 This is the second structural diagram of the array circuit provided by the present invention, such as Figure 3 As shown, the voltages on the nodes WL1, WL2, ..., WLK are VL1, VL2, ..., VLK, respectively, which serve as the first voltage input signals of the computing units in the 1st to Kth rows; the voltages on the nodes WLB1, WLB2, ..., WLBK are VLB1, VLB2, ..., VLBK, respectively, which serve as the second voltage input signals of the computing units in the 1st to Kth rows; the voltages on the nodes Wopen1, Wopen2, ..., WopenK are Vopen1, Vopen2, ..., VopenN, respectively, which serve as the control voltage signals of the computing units in the 1st to Nth columns; VBIAS serves as the first bias voltage of the K×N computing units, that is, the gate voltage input of M5; VCAS serves as the second bias voltage of the K×N computing units, that is, the gate voltage input of M3.

[0069] On this basis, by controlling the control voltage signals Vopen1, Vopen2, ..., VopenN of the computing units in columns 1-N, a given computing unit is pruned, thereby realizing the hardware pruning function. For example, by setting the control voltage signal of the computing unit in column 3 to 0, the first MOS transistor and the second MOS transistor of each computing unit in the column will be turned off, making each computing unit in the column inoperative.

[0070] in addition, Figure 4-Figure 6 Other connection modes of the control voltage signals of the calculation units provided by the present invention are schematically shown, such as Figure 4 As shown, the connection mode of the control voltage signal of each calculation unit can be that each calculation unit is connected to an independent control voltage signal, such as Figure 5 As shown, the connection mode of the control voltage signals of each computing unit can also be that every two computing units are connected to one control voltage signal, such as Figure 6 As shown, the control voltage signals of the calculation units may also be connected in a manner that one control voltage signal is connected to every K / 2 calculation units.

[0071] Based on any of the above embodiments, the present invention provides a control method based on the array circuit as described in the above embodiments. Figure 7 It is a flow chart of the control method provided by the present invention, such as Figure 7 As shown, the method includes:

[0072] Step 710, determining the control voltage signal of each computing unit in the array circuit;

[0073] Step 720 : Based on the control voltage signal of each computing unit, the on-off of the first MOS transistor and the second MOS transistor of each computing unit is controlled to control the working state of each computing unit.

[0074] Specifically, the array circuit is composed of K×N memristor-based integrated computing units as described in the above embodiments. First, the control voltage signal of each computing unit in the array circuit can be determined. Then, based on the control voltage signal of each computing unit, the on / off of the first MOS transistor and the second MOS transistor of each computing unit can be controlled to control the working state of each computing unit. The working state here refers to whether the computing unit is working or not working:

[0075] When the voltage value of the control voltage signal of any calculation unit is greater than the threshold voltage of the first MOS transistor and the threshold voltage of the second MOS transistor of the calculation unit, the first MOS transistor and the second MOS transistor of the calculation unit are turned on, so that the calculation unit is turned on and works normally; when the voltage value of the control voltage signal of the calculation unit is less than the threshold voltage of the first MOS transistor and the threshold voltage of the second MOS transistor of the calculation unit, the first MOS transistor and the second MOS transistor of the calculation unit are turned off, and the calculation unit does not work.

[0076] The method provided in an embodiment of the present invention, by applying an array circuit, can support convolution operations of a larger-scale neural network. Based on the control voltage signal of each computing unit in the array circuit, the on-off state of the first MOS transistor and the second MOS transistor of each computing unit is controlled to control the working state of each computing unit. This allows pruning of a given computing unit by controlling the voltage signal, thereby reducing the hardware overhead required for the calculation, lowering the number of operations, and improving the computing speed of the neural network.

[0077] Based on any of the above embodiments, the current at the current output terminal of any calculation unit is:

[0078] I out =V in ×W×IO

[0079] Among them, V in is the input value of the calculation unit, W is the weight of the calculation unit, and IO is the preset current;

[0080] The input value is determined based on a first voltage input signal and a second voltage input signal of the computing unit, and the weight is determined based on resistance values ​​of a first memristor and a second memristor of the computing unit.

[0081] Specifically, in order to implement the analog multiplication operation of the weight and input in the neural network, the input voltage is converted into a current output. The current at the current output terminal of any calculation unit in the embodiment of the present invention is:

[0082] I out =V in ×W×IO

[0083] Among them, V in is the input value of the calculation unit, W is the weight of the calculation unit, and IO is the preset current.

[0084] Here, the input value of the calculation unit can be determined according to the first voltage input signal and the second voltage input signal of the calculation unit. For example, when the first voltage input signal VL1 of the calculation unit is equal to the second voltage input signal VLB1 of the calculation unit, no current flows between VL1 and VLB1, and the input value V in is 0. The weight of the computing unit can be determined based on the resistance values ​​of the first memristor and the second memristor of the computing unit, namely R1 and R2. It can be understood that the current at the current output terminal is a multiple of IO, where IO is the current of the cascode current mirror at the output terminal, and the multiple is determined by VL1, VLB1, R1, and R2 at the input terminal.

[0085] The method provided in an embodiment of the present invention can realize analog multiplication operations of weights and inputs in a neural network through computing units. On this basis, an array circuit including multiple computing units is applied to support larger-scale current multiplication and addition operations. A given computing unit can be pruned by controlling a voltage signal, thereby improving the computing speed of the neural network by reducing the number of multiplication and addition operations.

[0086] Based on any of the above embodiments, step 710 includes:

[0087] Based on the bit corresponding to the weight of each calculation unit, the control voltage signal of each calculation unit is determined.

[0088] Specifically, the weights of the N computational units in each row form the N-bit weight for the row as a whole. Each computational unit weight corresponds to one bit. It is understood that weights in higher-order bits have a greater impact on the multiplication-addition result, while weights in lower-order bits have a smaller impact. For an array circuit consisting of K×N computational units, K N-bit weights W1, W2, …, WK are obtained.

[0089] Considering that neural network pruning will filter out unimportant neurons and weights from a large network and then delete them from the network while retaining the performance of the network as much as possible, in an embodiment of the present invention, under the condition of acceptable accuracy, the computing units corresponding to a custom number of low-order bits can be turned off by pruning, thereby reducing the number of multiplications and additions to reduce the occupation of computing resources without affecting the accuracy too much.

[0090] A specific pruning method can be to determine the control voltage signal of each computing unit based on the height of the bit corresponding to the weight of each computing unit and the number of computing units that need to be shut down. For example, if the bit order is that the weight of the computing unit in the front column corresponds to the high bit, and the weight of the computing unit in the back column corresponds to the low bit, and the number of computing units that need to be shut down is M×K, then the control voltage signals of all computing units in the last M columns can be set to 0 so that all computing units in the last M columns do not work, that is, the number of bits in the M columns is subtracted. At this time, it can be concluded that the number of multiplications reduced is M×K times.

[0091] The method provided in the embodiment of the present invention closes the calculation units corresponding to a custom number of low-order bits by pruning, which greatly reduces the hardware overhead required for calculation and also enables the weight calculation accuracy to be custom adjusted, corresponding to the number of multiplications required for calculation.

[0092] Based on any of the above embodiments, the input value of any calculation unit is determined based on the following steps:

[0093] If the working state of the calculation unit is working, the first voltage input signal of the calculation unit is at a high level, and the second voltage input signal of the calculation unit is at a low level, then the input value of the calculation unit is the first input value;

[0094] Otherwise, the input value of the calculation unit is the second input value.

[0095] Specifically, the voltage combination of the first voltage input signal VL1 and the second voltage input signal VLB1 of any calculation unit corresponds to the input value Vin of the calculation unit; wherein, the voltage input range of the first voltage input signal VL1 and the second voltage input signal VLB1 is from low level to high level; different combinations of the first voltage input signal VL1 and the second voltage input signal VLB1 within the voltage input range will not cause circuit function errors.

[0096] If the working state of the calculation unit is in operation, when the first voltage input signal VL1 is at a high level and the second voltage input signal VLB1 is at a low level, the input value Vin is the first input value, and at this time, it can be ensured that current flows between VL1 and VLB1; when the first voltage input signal VL1 is at a high level and the second voltage input signal VLB1 is at a high level, the input value Vin is the second input value; when the first voltage input signal VL1 is at a low level and the second voltage input signal VLB1 is at a high level, the input value Vin is the second input value; when the first voltage input signal VL1 is at a low level and the second voltage input signal VLB1 is at a low level, the input value Vin is the second input value;

[0097] If the working state of the calculation unit is off, then no matter the first voltage input signal VL1 and the second voltage input signal VLB1 are at a low level or a high level, the input value Vin is the second input value. Optionally, the first input value is 1 and the second input value is 0.

[0098] Based on any of the above embodiments, the weight of any computing unit is determined based on the following steps:

[0099] If the resistance value of the first memristor of the computing unit is a low resistance value, and the resistance value of the second memristor of the computing unit is a high resistance value, then the weight of the computing unit is the first weight;

[0100] Otherwise, the weight of the calculation unit is the second weight.

[0101] Specifically, the voltage division between the first memristor and the second memristor of any computing unit corresponds to the weight W of the computing unit, so that the non-volatile nature of the memristor can be used to store the weight. When the resistance of the first memristor is low and the resistance of the second memristor is high, the weight W of the computing unit is the first weight, which can ensure that the gate voltage of the fourth MOS tube is large. When the resistance of the first memristor is low and the resistance of the second memristor is low, the weight W of the computing unit is the second weight. When the resistance of the first memristor is high and the resistance of the second memristor is low, the weight W of the computing unit is the second weight. When the resistance of the first memristor is high and the resistance of the second memristor is low, the weight W of the computing unit is the third weight. When the resistance of the first memristor is high and the resistance of the second memristor is high, the weight W of the computing unit is the third weight. Optionally, the first weight is 1 and the second weight is 0.

[0102] Furthermore, Table 1 is a truth table of the current output terminal of the calculation unit. As shown in Table 1, the control voltage signal Vopen1 and the output product Vin×W corresponding to the input value Vin and the weight W can determine the current output terminal IOUT11; when Vopen1 is 0, that is, the working state of the calculation unit is not working, IOUT11 is 0A; when Vopen1 is 1, that is, the working state of the calculation unit is working, only when VL1 is VDD, VLB1 is 0, R1 is LRS, and R2 is HRS, the output product Vin×W is 1, and the output IOUT11 is 10 A. In other cases, IOUT11 is 0A.

[0103] Table 1

[0104]

[0105]

[0106] It should be noted that when the resistance value of the first memristor is low-low-resistance, it can be processed as if the resistance value is low-resistance; when the resistance value of the first memristor is high-high-resistance, it can be processed as if the resistance value is high-resistance; similarly, when the resistance value of the second memristor is low-low-resistance, it can be processed as if the resistance value is low-resistance; when the resistance value of the second memristor is high-high-resistance, it can be processed as if the resistance value is high-resistance.

[0107] Based on any of the above embodiments, Figure 3 As shown, taking the first column as an example, the current output terminals IOUT11, IOUT21, ..., IOUTK1 of K computing units are connected together at the node BL1, and the multiplication and addition current I1 is obtained at the node BL1. I1 can be expressed as:

[0108] I1=(Vin1×W1+Vin2×W2+…+VinK×WK)×IO

[0109] Similarly, the values ​​of the multiplication and addition currents I2, I3, ..., IN of the remaining N-1 columns can be obtained.

[0110] After the multiplication and addition currents of each column are obtained, analog-to-digital conversion and other processing can be performed on the multiplication and addition currents to finally obtain the output result of the convolution operation of the neural network.

[0111] The control device provided by the present invention is described below. The control device described below and the control method described above can be referenced to each other.

[0112] Based on any of the above embodiments, the present invention provides a control device based on the array circuit as described in the above embodiments, comprising:

[0113] a determination unit, configured to determine a control voltage signal of each calculation unit in the array circuit;

[0114] The control unit is used to control the on-off of the first MOS transistor and the second MOS transistor of each computing unit based on the control voltage signal of each computing unit, so as to control the working state of each computing unit.

[0115] Based on any of the above embodiments, the current at the current output terminal of any calculation unit is:

[0116] I out =V in ×W×IO

[0117] Among them, V in is the input value of the calculation unit, W is the weight of the calculation unit, and IO is the preset current;

[0118] The input value is determined based on a first voltage input signal and a second voltage input signal of the computing unit, and the weight is determined based on resistance values ​​of a first memristor and a second memristor of the computing unit.

[0119] Based on any of the foregoing embodiments, the determining unit is configured to:

[0120] Based on the bit corresponding to the weight of each calculation unit, the control voltage signal of each calculation unit is determined.

[0121] Based on any of the above embodiments, the input value of the calculation unit is determined based on the following steps:

[0122] If the working state of the calculation unit is working, the first voltage input signal of the calculation unit is at a high level, and the second voltage input signal of the calculation unit is at a low level, then the input value of the calculation unit is the first input value;

[0123] Otherwise, the input value of the calculation unit is the second input value.

[0124] Based on any of the above embodiments, the weight of the calculation unit is determined based on the following steps:

[0125] If the resistance value of the first memristor of the computing unit is a low resistance value, and the resistance value of the second memristor of the computing unit is a high resistance value, then the weight of the computing unit is the first weight;

[0126] Otherwise, the weight of the calculation unit is the second weight.

[0127] The device provided by the embodiment of the present invention, by applying an array circuit, can support convolution operations of a larger-scale neural network. Based on the control voltage signal of each computing unit in the array circuit, the first MOS transistor and the second MOS transistor of each computing unit are controlled to be on and off, thereby controlling the working state of each computing unit. This allows pruning of a given computing unit by controlling the voltage signal, thereby reducing the hardware overhead required for the calculation, lowering the number of operations, and improving the computing speed of the neural network.

[0128] Figure 8 An example of a physical structure diagram of an electronic device is shown below. Figure 8 As shown, the electronic device may include: a processor 810, a communications interface 820, a memory 830, and a communications bus 840, wherein the processor 810, the communications interface 820, and the memory 830 communicate with each other via the communications bus 840. The processor 810 may call logic instructions in the memory 830 to execute a control method, which includes: determining a control voltage signal for each computing unit in the array circuit; and controlling the on / off of a first MOS transistor and a second MOS transistor of each computing unit based on the control voltage signal of each computing unit to control the operating state of each computing unit.

[0129] In addition, the logic instructions in the above-mentioned memory 830 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0130] On the other hand, the present invention also provides a computer program product, which includes a computer program. The computer program can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the control method provided by the above-mentioned methods. The method includes: determining the control voltage signal of each computing unit in the array circuit; based on the control voltage signal of each computing unit, controlling the on and off of the first MOS transistor and the second MOS transistor of each computing unit to control the working state of each computing unit.

[0131] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the control method provided by the above-mentioned methods, the method comprising: determining the control voltage signal of each computing unit in the array circuit; based on the control voltage signal of each computing unit, controlling the on and off of the first MOS transistor and the second MOS transistor of each computing unit to control the working state of each computing unit.

[0132] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0133] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0134] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A memristor-based integrated computing unit, characterized in that: The computing unit is used to perform convolution operations in a neural network, and the computing unit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a first memristor, and a second memristor; The drain / source of the first MOS transistor is connected to a first voltage input signal, and the source / drain of the second MOS transistor is connected to a second voltage input signal; the gate of the first MOS transistor and the gate of the second MOS transistor are commonly connected to a control voltage signal; the source / drain of the first MOS transistor is connected to one end of the first memristor, and the drain / source of the second MOS transistor is connected to one end of the second memristor; the other end of the first memristor and the other end of the second memristor are commonly connected to the gate of the fourth MOS transistor; the drain of the fourth MOS transistor is connected to the source of the third MOS transistor, and the source of the fourth MOS transistor is connected to the drain / source of the fifth MOS transistor; the gate of the fifth MOS transistor is connected to a first bias voltage, and the source / drain of the fifth MOS transistor is grounded; the gate of the third MOS transistor is connected to a second bias voltage, and the drain of the third MOS transistor serves as a current output end.

2. An array circuit, characterized in that: include: A plurality of memristor-based integrated computing units as claimed in claim 1 arranged in an array; The first bias voltage of each computing unit is the same, the second bias voltage of each computing unit is the same, the first voltage input signal of each computing unit in the same row is the same, the second voltage input signal of each computing unit in the same row is the same, and the current output ends of each computing unit in the same column are connected together.

3. The array circuit according to claim 2, wherein: The control voltage signals of the computing units in the same column are the same.

4. A control method based on the array circuit according to claim 2 or 3, characterized in that: include: determining a control voltage signal for each computing unit in the array circuit; Based on the control voltage signal of each computing unit, the on-off of the first MOS transistor and the second MOS transistor of each computing unit is controlled to control the working state of each computing unit.

5. The control method according to claim 4, characterized in that: The current at the current output terminal of any calculation unit is: I out =V in ×W×IO Among them, V in is the input value of any of the calculation units, W is the weight of any of the calculation units, and IO is the preset current; The input value is determined based on a first voltage input signal and a second voltage input signal of any one of the computing units, and the weight is determined based on resistance values ​​of a first memristor and a second memristor of any one of the computing units.

6. The control method according to claim 5, characterized in that: The determining of the control voltage signal of each computing unit in the array circuit includes: Based on the bits corresponding to the weights of the calculation units, the control voltage signals of the calculation units are determined.

7. The control method according to claim 5, characterized in that: The input value of any of the calculation units is determined based on the following steps: If the working state of any of the computing units is working, the first voltage input signal of any of the computing units is at a high level, and the second voltage input signal of any of the computing units is at a low level, then the input value of any of the computing units is the first input value; Otherwise, the input value of any one of the calculation units is the second input value.

8. The control method according to claim 5, characterized in that: The weight of any of the computing units is determined based on the following steps: If the resistance value of the first memristor of any of the computing units is a low resistance value, and the resistance value of the second memristor of any of the computing units is a high resistance value, then the weight of any of the computing units is the first weight; Otherwise, the weight of any one of the calculation units is the second weight.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the control method according to any one of claims 4 to 8 is implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the control method according to any one of claims 4 to 8 is implemented.

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