UFS Device and Its Operation Method

Abstract

Embodiments of this disclosure relate to a UFS device and a method of operating the same. According to embodiments of this disclosure, the UFS device can collect state information of the UFS device, create an acknowledgment and flow control (AFC) frame including the collected state information, and transmit the AFC frame to a host performing communication with the UFS device.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0180463, filed on December 22, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments relate to a UFS (Universal Flash Memory) device and a method of operating the same. Background Technology

[0004] A memory system includes a data storage device that receives requests for data storage from a host device such as a computer, server, smartphone, tablet PC, or other electronic device. Examples of memory systems range from conventional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash memory devices (UFS), or embedded MMC (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory devices. The memory controller may receive commands from a host and, based on the received commands, execute those commands or control read / write / erase operations on the memory devices in the memory system. The memory controller may be used to control these operations by running firmware operations for performing logical operations.

[0006] A UFS device can process command UPIUs (UFS Protocol Information Units) received from the host and transmit response UPIUs to the host as a response to the command UPIU. In this case, the UFS device can transmit its status information to the host by including the UFS device's status information in the response UPIU. Summary of the Invention

[0007] The embodiments of this disclosure provide a UFS device and its operation method that can quickly transmit UFS device status information to a host.

[0008] Furthermore, embodiments of this disclosure may provide a UFS device and its operation method that enable a host to check the status information of the UFS device in real time.

[0009] On one hand, embodiments of this disclosure may provide a Universal Flash Memory (UFS) device.

[0010] UFS devices can collect status information about UFS devices.

[0011] UFS devices can create Acknowledgement and Flow Control (AFC) frames that include the collected state information.

[0012] UFS devices can transmit AFC frames to the host that performs communication with the UFS device.

[0013] In this case, the status information may include at least one of the following: 1) temperature information of the UFS device, 2) voltage change information of the UFS device, 3) information about the communication layer between the host and the UFS device, and 4) command transmission hold request information for the host.

[0014] UFS devices can create AFC frames by writing state information into one or more state information registers included in the UFS device, and then storing the state information written into the state information registers in the AFC frame.

[0015] On the other hand, embodiments of this disclosure may provide a method of operating a universal flash memory (UFS) device.

[0016] Operating a UFS device may include collecting status information about the UFS device.

[0017] Operating methods for a UFS device may include creating an acknowledgment and flow control (AFC) frame that includes collected state information.

[0018] Operating a UFS device may include transmitting AFC frames to a host that performs communication with the UFS device.

[0019] In this case, the status information may include at least one of the following: 1) temperature information of the UFS device, 2) voltage change information of the UFS device, 3) information about the communication layer between the host and the UFS device, and 4) command transmission hold request information for the host.

[0020] The operation of creating an AFC frame may include writing status information into one or more status information registers included in the UFS device, and then storing the status information written into the status information registers in the AFC frame.

[0021] On the other hand, embodiments of this disclosure may provide a method of operating a system including a host device and a universal flash memory (UFS) device.

[0022] The system's operation may include communication between the host device and the UFS device according to the Mobile Industrial Processor Interface (MIPI) standard.

[0023] The system's operation may include the UFS device providing information about its status to the host device via Acknowledgment and Flow Control (AFC) frames defined by the standard.

[0024] The system's operation may include receiving AFC frames from the host device to identify the status.

[0025] Operating a Universal Flash Memory (UFS) device may include communicating with a host device according to the Mobile Industrial Processor Interface (MIPI) standard.

[0026] Operating a Universal Flash Memory (UFS) device may include providing information about the UFS device’s status to a host device via Acknowledgment and Flow Control (AFC) frames defined by the standard.

[0027] The operation of the host device may include communicating with a Universal Flash Memory (UFS) device according to the Mobile Industrial Processor Interface (MIPI) standard.

[0028] The host device's operating method may include receiving acknowledgment and flow control (AFC) frames from the UFS device, as defined by the standard and including information about the UFS device's status, to identify the status.

[0029] According to embodiments of this disclosure, compared to existing UFS devices, higher reliability can be ensured by rapidly transmitting the status information of the UFS device to the host so that the host can check the status information of the UFS device in real time. Attached Figure Description

[0030] Figure 1 This is a schematic diagram illustrating the configuration of a memory system based on an embodiment of the disclosed technology.

[0031] Figure 2 This is a block diagram schematically illustrating a memory device based on an embodiment of the disclosed technology.

[0032] Figure 3 This is a diagram illustrating the structure of word lines and bit lines of a memory device based on an embodiment of the disclosed technology.

[0033] Figure 4 This is a schematic diagram of a UFS device according to an embodiment of the present disclosure.

[0034] Figure 5 This is a diagram illustrating an example of a UFS device transmitting an AFC frame to a host according to an embodiment of the present disclosure.

[0035] Figure 6 This is a diagram illustrating an example of status information according to an embodiment of the present disclosure.

[0036] Figure 7 It is shown Figure 6A diagram illustrating an example of the information included in the communication layer information.

[0037] Figure 8 This is a diagram illustrating an example of a UFS device including state information in an AFC frame according to an embodiment of the present disclosure.

[0038] Figure 9 This is a flowchart illustrating an example of an operation by which a UFS device includes state information in an AFC frame according to an embodiment of the present disclosure.

[0039] Figure 10 This is a diagram illustrating an example of the time it takes for a UFS device to transmit an AFC frame to a host according to an embodiment of the present disclosure.

[0040] Figure 11 This is a diagram illustrating a method of operating a UFS device according to an embodiment of the present disclosure.

[0041] Figure 12 This is a diagram illustrating the configuration of a computing system based on some embodiments of the disclosed technology. Detailed Implementation

[0042] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., are not necessarily directed to only one embodiment, and different references to any such phrases are not necessarily directed to the same embodiment. The term "various embodiments" as used herein does not necessarily refer to all embodiments.

[0043] Figure 1 This is a diagram illustrating a schematic configuration of a memory system 100 based on an embodiment of the disclosed technology.

[0044] In some embodiments, the memory system 100 may include a memory device 110 configured to store data and a memory controller 120 configured to control the memory device 110.

[0045] The memory device 110 may include multiple memory blocks, each memory block including multiple memory cells for storing data. The memory device 110 may be configured to operate in response to control signals received from the memory controller 120. Operation of the memory device 110 may include, for example, read operations, programming operations (also referred to as "write operations"), erase operations, etc.

[0046] The memory cells in memory device 110 are used to store data and can be arranged in an array of memory cells. The array of memory cells can be divided into blocks of memory cells, and each block includes different pages of memory cells. In a typical implementation of a NAND flash memory device, a page of a memory cell is the smallest unit of memory that can be programmed or written, and the data stored in a memory cell can be erased in blocks.

[0047] In some implementations, the memory device 110 may be implemented as various types such as: Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM).

[0048] The memory device 110 can be implemented as a three-dimensional array structure. Some embodiments of the disclosed technology are applicable to any type of flash memory device having a charge storage layer. In one embodiment, the charge storage layer may be formed of a conductive material, and such a charge storage layer may be referred to as a floating gate. In another embodiment, the charge storage layer may be formed of an insulating material, and such a flash memory device may be referred to as charge-fetch flash (CTF).

[0049] The memory device 110 is configured to receive commands and addresses from the memory controller 120 to access a region in the memory cell array selected using that address. In other words, the memory device 110 can perform an operation corresponding to the received command on a memory region in the memory device having a physical address corresponding to the address received from the memory controller 120.

[0050] In some implementations, the memory device 110 can perform programming operations, reading operations, erasing operations, etc. During a programming operation, the memory device 110 can write data to an address-selected region. During a reading operation, the memory device 110 can read data from an address-selected memory region. During an erasing operation, the memory device 110 can erase data stored in an address-selected memory region.

[0051] The memory controller 120 can control write (programming) operations, read operations, erase operations, and background operations performed on the memory device 110. Background operations may include, for example, operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0052] The memory controller 120 can control the operation of the memory device 110 upon request from the host. Optionally, when the memory controller 120 performs such background operation of the memory device, the memory controller 120 can control the operation of the memory device 110 even without a request from the host.

[0053] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, by way of example, the memory controller 120 and the host will be discussed as separate devices.

[0054] Reference Figure 1 The memory controller 120 may include a memory interface (I / F) 122, a control circuit 123, and a host interface (I / F) 121.

[0055] The host interface 121 can be configured to provide an interface for communicating with a host.

[0056] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and perform operations to process the received command.

[0057] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface connection to the memory device 110 and the memory controller 120, so that the memory controller 120 can perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0058] The control circuit 123 may be configured to control the operation of the memory device 110 via the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126, etc.

[0059] Processor 124 controls all operations of memory controller 120. Processor 124 can perform logical operations. Processor 124 can communicate with host via host interface 121. Processor 124 can communicate with memory device 110 via memory interface 122.

[0060] Processor 124 can be used to perform operations associated with the Flash Translation Layer (FTL) to efficiently manage memory operations on memory system 100. Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive LBAs and translate them into PBAs using a mapping table.

[0061] Based on the mapping unit, there are various address mapping methods that FTL can use. Typical address mapping methods can include page mapping, block mapping, and hybrid mapping.

[0062] Processor 124 can be configured to randomize data received from the host to write the randomized data into the memory cell array. For example, processor 124 can randomize data received from the host by using a randomization seed. The randomized data is provided to memory device 110 and written into the memory cell array.

[0063] Processor 124 can be configured to derandomize data received from memory device 110 during a read operation. For example, processor 124 can derandomize data received from memory device 110 by using a derandomization seed. The derandomized data can then be output to the host.

[0064] Processor 124 can run firmware (FW) to control the operation of memory controller 120. In other words, processor 124 can control all operations of memory controller 120, and in order to perform logical operations, it can run (drive) the firmware loaded into working memory 125 during startup.

[0065] Firmware refers to a program or software stored on a non-volatile memory and running inside the memory system 100.

[0066] In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of a flash translation layer (FTL), a host interface layer (HIL), and a flash interface layer (FIL), wherein the flash translation layer (FTL) is configured to translate a logical address in a host request into a physical address of the memory device 110, the host interface layer (HIL) is configured to interpret commands issued by the host host to a data storage device such as the memory system 100 and pass the commands to the FTL, and the flash interface layer (FIL) is configured to pass commands issued by the FTL to the memory device 110.

[0067] For example, firmware can be stored in memory device 110 and then loaded into working memory 125.

[0068] The working memory 125 may store firmware, program code, commands, or data necessary for operating the memory controller 120. The working memory 125 may include at least one of, for example, static RAM (SRAM), dynamic RAM (DRAM), and synchronous RAM (SDRAM) as volatile memory.

[0069] Error detection / correction circuit 126 can be configured to detect and correct one or more error bits in data using error detection and correction codes. In some embodiments, the data for error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110.

[0070] Error detection / correction circuit 126 can be implemented to decode data using error correction codes. Various decoding schemes can be used to implement error detection / correction circuit 126. For example, a decoder performing non-system code decoding or a decoder performing system code decoding can be used.

[0071] In some implementations, the error detection / correction circuit 126 may detect one or more error bits based on sectors. That is, each read data entry may include multiple sectors. In this disclosure, a sector may refer to a data unit smaller than a read unit of flash memory (e.g., a page). The sectors constituting each read data entry may be mapped based on addresses.

[0072] In some implementations, the error detection / correction circuit 126 can calculate the bit error rate (BER) and determine, sector by sector, whether the number of erroneous bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the erroneous bits in the corresponding sector are uncorrectable and mark the corresponding sector as "failed". If the BER is lower than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable or mark the corresponding sector as "passed".

[0073] Error detection / correction circuit 126 can sequentially perform error detection and correction operations on all read data. When a sector included in the read data is correctable, error detection / correction circuit 126 can move to the next sector to check if error correction is required for the next sector. In completing error detection and correction operations on all read data in this way, error detection / correction circuit 126 can obtain information about which sector in the read data is considered uncorrectable. Error detection / correction circuit 126 can provide this information (e.g., the address of the uncorrectable bit) to processor 124.

[0074] The memory system 100 may also include a bus 127 to provide a channel between the constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 (i.e., host interface 121, memory interface 122, processor 124, working memory 125, and error detection / correction circuitry 126). For example, bus 127 may include a control bus for transmitting various types of control signals and commands, and a data bus for transmitting various types of data.

[0075] As an example, Figure 1 The aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are shown. Note that some of the constituent elements shown may be omitted, or some of the aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. Additionally, in some embodiments, one or more other constituent elements may be added to the aforementioned constituent elements of the memory controller 120.

[0076] Figure 2 This is a block diagram schematically illustrating a memory device 110 based on an embodiment of the disclosed technology.

[0077] In some implementations, the memory device 110 based on the disclosed technology may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0078] The memory cell array 210 may include multiple memory blocks BLK1 to BLKz, where z is a natural number equal to or greater than 2.

[0079] In multiple memory blocks BLK1 to BLKz, multiple word lines WL and multiple bit lines BL can be set by row and column, and multiple memory cells MC can be arranged.

[0080] Multiple memory blocks BLK1 to BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1 to BLKz can be connected to the read / write circuitry 230 via multiple bit lines BL.

[0081] Each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. For example, the multiple memory cells are non-volatile memory cells. In some embodiments, such non-volatile memory cells may be arranged in a vertical channel configuration.

[0082] The memory cell array 210 can be configured as a memory cell array with a two-dimensional structure. In some embodiments, the memory cell array 210 can be arranged in a three-dimensional structure.

[0083] Each of the plurality of memory cells included in the memory cell array 210 may store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 may be a single-level cell (SLC) configured to store one bit of data. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a multi-level cell (MLC) configured to store two bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a three-level cell (TLC) configured to store three bits of data per memory cell. As another example, each of the plurality of memory cells included in the memory cell array 210 may be a four-level cell (QLC) configured to store four bits of data per memory cell. As another example, the memory cell array 210 may include a plurality of memory cells, each of which may be configured to store at least five bits of data per memory cell.

[0084] Reference Figure 2 The address decoder 220, read / write circuit 230, control logic 240, and voltage generation circuit 250 can operate as peripheral circuitry configured to drive the memory cell array 210.

[0085] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0086] Address decoder 220 can be configured to operate in response to commands and control signals from control logic 240.

[0087] Address decoder 220 can receive addresses through an input / output buffer within memory device 110. Address decoder 220 can be configured to decode block addresses among the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0088] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0089] During a read operation, the address decoder 220 can apply a read voltage Vread to the selected word line WL within the selected memory block, and apply a pass voltage Vpass to the remaining unselected word lines WL.

[0090] The address decoder 220 can apply a verification voltage generated by the voltage generation circuit 250 to the selected word line WL within the selected memory block during the programming verification operation, and can apply a pass voltage Vpass to the remaining unselected word lines WL.

[0091] Address decoder 220 can be configured to decode the column address of a received address. Address decoder 220 can transmit the decoded column address to read / write circuit 230.

[0092] The memory device 110 can perform read and program operations page by page. The address received when requesting a read or program operation may include at least one of a block address, a row address, and a column address.

[0093] Address decoder 220 can select a memory block and a word line based on the block address and row address. The column address can be decoded by address decoder 220 and provided to read / write circuitry 230.

[0094] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0095] The read / write circuit 230 may include multiple page buffers PB. The read / write circuit 230 may operate as a "read circuit" when the memory cell array 210 performs a read operation and as a "write circuit" when the memory cell array 210 performs a write operation.

[0096] The aforementioned read / write circuit 230 is also referred to as a page buffer circuit or data register circuit, which includes multiple page buffers PB. The read / write circuit 230 may include data buffers involved in data processing functions, and in some embodiments, may further include cache buffers for data caching.

[0097] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cell during read operations and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit line BL connected to the memory cell to detect changes in current proportional to the sensing node, and can hold or latch the corresponding voltage as sensing data, the current varying according to the programming state of the corresponding memory cell.

[0098] The read / write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0099] During a read operation, the read / write circuit 230 senses the voltage value of the memory cell and reads the voltage value as data. The read / write circuit 230 temporarily stores the retrieved data DATA and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or page register, the read / write circuit 230 may also include column select circuitry.

[0100] Control logic 240 can be connected to address decoder 220, read / write circuit 230, and voltage generation circuit 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory device 110.

[0101] Control logic 240 can be configured to control all operations of memory device 110 in response to control signal CTRL. Control logic 240 can output control signals for adjusting the voltage levels of the sensing nodes of multiple page buffers PB to precharge voltage levels.

[0102] Control logic 240 controls read / write circuit 230 to perform read operations in memory cell array 210. Voltage generation circuit 250 generates read voltage Vread and pass voltage Vpass used during read operations in response to a voltage generation circuit control signal output from control logic 240.

[0103] The memory block BLK included in the memory device 110 may include multiple pages PG. In some embodiments, multiple memory cells arranged in columns form a memory cell string, and multiple memory cells arranged in rows form a memory block. Each of the multiple pages PG is connected to one of the word lines WL, and each of the memory cell strings STR is connected to one of the bit lines BL.

[0104] In a storage block BLK, multiple word lines (WLs) and multiple bit lines (BLs) can be arranged in rows and columns. For example, each of the multiple word lines (WLs) can be arranged in a row direction, and each of the multiple bit lines (BLs) can be arranged in a column direction. As another example, each of the multiple word lines (WLs) can be arranged in a column direction, and each of the multiple bit lines (BLs) can be arranged in a row direction.

[0105] In some implementations, multiple word lines (WL) and multiple bit lines (BL) may intersect each other, thereby addressing a single memory cell in an array of multiple memory cells (MC). In some implementations, each memory cell (MC) may include a transistor (TR), which includes a layer of material capable of retaining charge.

[0106] For example, a transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of transistor TR may be connected directly or via another transistor TR to the corresponding bit line BL. The source (or drain) of transistor TR may be connected directly or via another transistor TR to a source line (which may be grounded). The gate of transistor TR may include a floating gate (FG) surrounded by an insulator, and a gate voltage is applied from word line WL to the control gate (CG).

[0107] In each of the multiple memory blocks BLK1 to BLKz, a first select line (also called a source select line or drain select line) may be arranged outside the first outermost word line closer to the read / write circuit 230 among the two outermost word lines, and a second select line (also called a drain select line or source select line) may be arranged outside the other second outermost word line.

[0108] In some implementations, at least one additional dummy character line may be arranged between the first outermost character line and the first selection line. Additionally, at least one additional dummy character line may be arranged between the second outermost character line and the second selection line.

[0109] It can perform read and write operations on storage blocks one page at a time, and can also perform erase operations on storage blocks one by one.

[0110] Figure 3 This is a diagram illustrating the structure of the word line WL and bit line BL of a memory device 110 based on an embodiment of the disclosed technology.

[0111] Reference Figure 3 The memory device 110 has a core region in which memory cells MC are arranged, and an auxiliary region, which is the remaining region outside the core region, to include circuitry for performing operations on the memory cell array 210.

[0112] In the kernel region, a specific number of memory cells arranged in one direction can be called a "page" PG, and a specific number of memory cells connected in series can be called a "memory cell string" STR.

[0113] Word lines WL1 to WL9 can be connected to row decoder 310. Bit line BL can be connected to column decoder 320. (Corresponding to...) Figure 2 The data register 330 of the read / write circuit 230 may exist between multiple bit lines BL and column decoder 320.

[0114] Multiple word lines WL1 to WL9 can correspond to multiple pages PG.

[0115] For example, such as Figure 3 As shown, each of the multiple word lines WL1 to WL9 can correspond to a page PG. When each of the multiple word lines WL1 to WL9 has a larger size, each of the multiple word lines WL1 to WL9 can correspond to at least two (e.g., two or four) page PGs. Each page PG is the smallest unit in programming and reading operations, and during programming and reading operations, all memory cells MC within the same page PG can be operated on simultaneously.

[0116] Multiple bit lines BL can be connected to column decoder 320. In some implementations, the multiple bit lines BL can be divided into odd bit lines BL and even bit lines BL, such that a pair of odd bit lines and even bit lines are connected together to column decoder 320.

[0117] When accessing a memory cell MC, the row decoder 310 and column decoder 320 are used to locate the desired memory cell based on its address.

[0118] In some implementations, the data register 330 plays a crucial role because all data processing performed by the memory device 110, including programming and reading operations, occurs via the data register 330. If data processing by the data register 330 is delayed, all other areas must wait until the data register 330 has completed its data processing, which degrades the overall performance of the memory device 110.

[0119] Reference Figure 3 In the example shown, in a memory cell string STR, multiple transistors TR1 to TR9 can be connected to multiple word lines WL1 to WL9, respectively. In some embodiments, the multiple transistors TR1 to TR9 correspond to memory cells MC. In this example, the multiple transistors TR1 to TR9 include a control gate CG and a floating gate FG.

[0120] The multiple word lines WL1 to WL9 include two outermost word lines, WL1 and WL9. A first select line DSL can be additionally arranged outside the first outermost word line WL1. Compared to the other outermost word line WL9, this first outermost word line WL1 is closer to the data register 330 and has a shorter signal path. A second select line SSL can be additionally arranged outside the other second outermost word line WL9.

[0121] The first selection transistor D-TR, controlled to be turned on / off by the first selection line DSL, has a gate electrode connected to the first selection line DSL, but does not include a floating gate FG. The second selection transistor S-TR, controlled to be turned on / off by the second selection line SSL, has a gate electrode connected to the second selection line SSL, but does not include a floating gate FG.

[0122] The first selection transistor D-TR serves as a switch circuit connecting the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR serves as a switch connecting the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0123] In some embodiments, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of a first selection transistor D-TR to turn on the first selection transistor D-TR, and applies a predetermined turn-off voltage (e.g., 0V) to the gate electrode of a second selection transistor S-TR to turn off the second selection transistor S-TR.

[0124] During a read or verify operation, the memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during a read or verify operation, current can flow through the corresponding memory cell string STR and to the source line SL corresponding to ground, making the voltage level of the bit line BL measurable. However, during a read operation, there may be a time difference in the on / off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0125] During the erase operation, the memory system 100 applies a predetermined voltage (e.g., +20V) to the substrate via the source line SL. During the erase operation, the memory system 100 applies a specific voltage to allow both the first selection transistor D-TR and the second selection transistor S-TR to float. Therefore, the applied erase voltage removes charge from the floating gate FG of the selected memory cell.

[0126] Figure 4 This is a schematic diagram of a UFS device 10 according to an embodiment of the present disclosure.

[0127] Reference Figure 4 The UFS device 10 can communicate with the host based on the UFS protocol. For example, the UFS device 10 can communicate with the host through the Mobile Industrial Processor Interface (MIPI) M-PHY and MIPI Unipro (unified protocol), which are collectively referred to as the UFS protocol below.

[0128] In addition, the UFS device 10 can collect status information of the UFS device 10 while performing communication with the host, and create acknowledgment and flow control (AFC) frames that include the collected status information.

[0129] An AFC frame is a frame used for flow control between a host and a UFS device 10 at the data link layer as defined by the UFS protocol.

[0130] After a link is created between the host and the UFS device 10 at the data link layer, AFC frames can be used while link-related operations are running.

[0131] As an example, during a link start operation or hibernation exit operation, an AFC frame can be used to check the initial state of the data link layer between the host and the UFS device 10.

[0132] As another example, during data transfer operations between the host and UFS device 10, AFC frames can be used to perform flow control on the data frames by transmitting the sequence number of the data received so far by the receiver to the transmitter. Each of the host and UFS device 10 can be either the receiver or the transmitter.

[0133] UFS device 10 can transmit AFC frames, including collected status information of UFS device 10, to the host. Therefore, UFS device 10 can transmit the collected status information of UFS device 10 to the host.

[0134] Compared to transmitting the status information of the UFS device 10 via a UPIU in response to a command received from the host, transmitting the status information of the UFS device 10 to the host via an AFC frame has the following effects.

[0135] When UFS device 10 transmits its status information via a response UPIU to a command UPIU received from the host, UFS device 10 needs to wait for the host to transmit the command UPIU back to it. After receiving the command UPIU from the host, UFS device 10 can write its status information into the device information attribute of the response UPIU, and set a bit indicating that the status information has been written into the response UPIU, before transmitting the response UPIU to the host. After receiving the response UPIU and confirming the writing of the UFS device 10's status information, the host can check the status information of UFS device 10 based on the value written into the device information attribute of the response UPIU.

[0136] In this configuration, the UFS device 10 can only transmit status information to the host when the host transmits the UPIU command; without receiving the UPIU command, the UFS device 10 itself cannot transmit its status information to the host. Therefore, if a problem occurs in the UFS device 10, the host may only recognize the problem later, potentially delaying the resolution of the issue.

[0137] On the other hand, when UFS device 10 transmits its status information using AFC frames, it can transmit this information to the host much faster. This is because once a link is established between the host and UFS device 10, AFC frames can be transmitted to the host during link-related operations, even without a request from the host. Therefore, the host can check the status information of UFS device 10 in real time via AFC frames during communication with UFS device 10 and can perform actions based on the status of UFS device 10. Thus, UFS device 10 can ensure higher reliability than conventional UFS devices.

[0138] As an example, when the host determines that the UFS device 10 is abnormal based on the status information of the UFS device 10, for example, when the temperature of the UFS device 10 exceeds the allowable limit temperature, or the voltage change of the UFS device 10 exceeds the reference range, or the error rate of the data link layer exceeds the allowable threshold ratio, the host may reduce the communication speed with the UFS device 10.

[0139] In addition, the above reference Figure 1 The described memory system 100 can be used as a UFS device 10. For example, data can be stored in memory device 110 of the memory system 100 as a UFS device 10, and the memory controller 120 of the memory system 100 as a UFS device 10 can communicate with the host according to the UFS protocol and can perform operations to read or write data to the memory device 110.

[0140] Figure 5 This is a diagram illustrating an example of a UFS device 10 transmitting an AFC frame to a host according to an embodiment of the present disclosure.

[0141] Reference Figure 5 The UFS device 10 and the host can communicate based on the UFS protocol. In this case, the UFS protocol can have a multi-layered structure including multiple communication layers.

[0142] The communication layer included in the UFS protocol can be as follows.

[0143] The UFS protocol may include a physical layer (PHY) as an L1 layer. The physical layers of the UFS device 10 and the host can exchange symbols encoded according to a specific physical format.

[0144] The UFS protocol may include a physical adapter layer as an L1.5 layer. The physical adapter layer is the layer that performs the translation between the physical layer and the data link layer, and the physical adapter layers of UFS device 10 and the host can exchange symbols with each other.

[0145] Additionally, the UFS protocol may include a data link layer as Layer 2. The data link layers of the UFS device 10 and the host can exchange frames with each other.

[0146] The UFS protocol may include a network layer as Layer 3. The network layers of UFS device 10 and the host can exchange data packets with each other.

[0147] Additionally, the UFS protocol may include a transport layer as Layer 4. The transport layers of the UFS device 10 and the host can exchange segments with each other.

[0148] Additionally, the UFS protocol may include an application-specific protocol layer. The application-specific protocol layers of the UFS device 10 and the host can exchange messages based on protocols defined for each application.

[0149] exist Figure 5 In this context, when an AFC frame is created in the data link layer, the UFS device 10 can include the collected state information of the UFS device 10 in the AFC frame. In this case, the data link layer of the UFS device 10 can collect the state information of the UFS device 10 through a device management entity (not shown).

[0150] UFS device 10 can include its status information within a preset area of ​​an AFC frame. An AFC frame can be divided into a header, a payload, and a checksum. Within the payload, the status information of UFS device 10 can be included in an area allocated for the status information.

[0151] When UFS device 10 transmits an AFC frame to the host, the host can receive the status information of UFS device 10 based on the AFC frame transmitted by UFS device 10 through the data link layer. The host can transmit the fact that it has received the status information of UFS device 10 to the dedicated protocol layer via an interrupt. In this case, the data link layer of UFS device 10 can transmit the corresponding interrupt to the dedicated protocol layer through a device management entity (not shown).

[0152] The operation of UFS device 10 transmitting AFC frames to the host has been described above.

[0153] The following section will describe specific examples of the status information of the UFS device 10 included in the AFC frame.

[0154] Figure 6 This is a diagram illustrating an example of status information according to an embodiment of the present disclosure.

[0155] Reference Figure 6The status information of the UFS device 10 may include at least one of the following: temperature information of the UFS device 10, voltage change information of the UFS device 10, information about the communication layer between the host and the UFS device 10, and command transmission hold request information for the host.

[0156] UFS device 10 can collect temperature information from a temperature sensor. In an embodiment, the temperature sensor may be located inside UFS device 10 and can measure the temperature of a specific area inside UFS device 10 or a specific module included in UFS device 10.

[0157] The UFS device 10 can detect changes in the voltage supplied to the UFS device 10 from a voltage detector. The voltage detector may be located inside the UFS device 10 and can detect whether the change in the voltage supplied to the UFS device 10 is equal to or greater than a set reference (e.g., the voltage change exceeds a first value during a reference time period).

[0158] UFS device 10 can monitor Figure 5 The state of the communication layer described in the text is used to obtain information about the communication layer. In this case, the communication layer can be, for example... Figure 5 The data link layer or physical layer in the communication layer described in the document.

[0159] To ensure stable operation of the UFS device 10, it may be necessary to handle time-critical tasks (e.g., garbage collection) urgently. When a time-critical task (e.g., garbage collection) occurs, the UFS device 10 may request a command transmission hold from the host to prevent delays in processing the time-critical task due to commands transmitted from the host. When the host receives the request to hold the command transmission from the UFS device 10, the host may temporarily hold the command transmission.

[0160] Figure 7 It is shown Figure 6 A diagram illustrating an example of the information included in the communication layer information.

[0161] Reference Figure 7 Information about the communication layer may include at least one of error accumulation information and error recovery information, wherein the error accumulation information is information about errors that have accumulated in the corresponding communication layer, and the error recovery information is information about operations that recover errors generated in the communication layer.

[0162] Error accumulation information can be the total number of errors accumulated in the communication layer starting from a set reference time point, and error repair information can be the total number of errors that have been repaired among the errors accumulated in the communication layer starting from the set reference point. The UFS device 10 can manage error accumulation information and error repair information through error-related attributes of the Unipro layer, and can include error accumulation information and error repair information in AFC frames.

[0163] The above has described an example of the state information included in an AFC frame.

[0164] The following section will describe an example of how the UFS device 10 includes state information in an AFC frame.

[0165] Figure 8 This is a diagram illustrating an example of a UFS device 10 including state information in an AFC frame according to an embodiment of the present disclosure.

[0166] Reference Figure 8 The UFS device 10 can write the collected status information of the UFS device 10 into one or more status information registers included in the UFS device 10, and then the status information written into the status information registers can be included in the AFC frame. After the status information written into the status information registers is included in the AFC frame, the UFS device 10 can transmit the AFC frame to the host.

[0167] In this case, different types of status information can be written to each status information register. For example, the temperature information of the UFS device 10 can be written to one status information register, the voltage change information of the UFS device 10 can be written to another status information register, and the communication layer information can be written to another status information register.

[0168] Figure 9 This is a flowchart illustrating an example of an operation in which a UFS device 10 includes state information in an AFC frame according to an embodiment of the present disclosure.

[0169] Reference Figure 9 The UFS device can monitor status information (S910).

[0170] For example, UFS device 10 can directly check the value of status information at each preset time period. For example, after the link between the host and UFS device 10 is established, UFS device 10 can periodically collect error accumulation information and error repair information that occur in the aforementioned communication layers (e.g., physical layer, data link layer).

[0171] As another example, the UFS device 10 can monitor for interruptions that indicate changes in the values ​​of the status information by using modules for collecting status information (e.g., temperature sensors, voltage detectors). For example, the temperature sensor can generate an interrupt when the temperature of the UFS device 10 exceeds a preset temperature range, and the voltage detector can generate an interrupt when the voltage of the UFS device 10 exceeds a preset voltage range.

[0172] UFS device 10 can determine whether an event indicating a change in status information has occurred (S920). As an example, UFS device 10 can determine that an event indicating a change in status information occurs when an interruption occurs that causes a change in the value of the status information.

[0173] When an event indicating a change in status information occurs (S920 - Yes), the UFS device 10 can write the status information to... Figure 8 One or more status information registers (S930) are described in the description. As an example, the UFS device 10 may run an interrupt service routine (ISR) to handle interrupts that indicate changes in the value of the status information, and then write the status information into the status information register.

[0174] UFS device 10 may store status information written to one or more status information registers in an AFC frame (S940). An AFC frame may include status information written to one or more status information registers.

[0175] On the other hand, if no event indicating a change in status information occurs (920-No), the UFS device 10 can enter operation S910 and monitor the status information again.

[0176] The operation of storing state information in AFC frames by UFS device 10 has been described above.

[0177] The timing of the UFS device 10 transmitting AFC frames, including status information, to the host will be described below.

[0178] As an example, when a link is created at the data link layer between the host and the UFS device 10, the UFS device 10 may transmit an AFC frame, including status information, to the host for all operations that transmit frames through the link.

[0179] As another example, UFS device 10 can transmit AFC frames, including status information, to the host only at specific times. This will be discussed below. Figure 10 The description is in the middle.

[0180] Figure 10 This is a diagram illustrating an example of the time it takes for a UFS device 10 to transmit an AFC frame to a host according to an embodiment of the present disclosure.

[0181] Reference Figure 10 The UFS device 10 can transmit AFC frames to the host when the link is started, when the host exits the hibernation state, or when data is transferred between the host and the UFS device 10.

[0182] Link startup time refers to the time when the UFS device 10 and the host are connected via a link to communicate with each other.

[0183] The sleep state exit time can be understood as the point in time when the sleep state ends to reduce power consumption.

[0184] The data transfer time between the host and the UFS device 10 can be defined as the time it takes for the host or the UFS device 10 to transfer data (including commands and responses to corresponding commands).

[0185] Figure 11 This is a diagram illustrating a method of operating a UFS device 10 according to an embodiment of the present disclosure.

[0186] Reference Figure 11 The operation method of UFS device 10 may include collecting status information of UFS device 10 (S1110).

[0187] The status information of UFS device 10 may include at least one of the following: temperature information of UFS device, voltage change information of UFS device 10, communication layer (e.g., data link layer, physical layer) information between host and UFS device 10, and command transmission hold request information for host.

[0188] In addition, the communication layer information between the host and the UFS device 10 may include at least one of error accumulation information and error repair information, wherein the error accumulation information is information about errors that have accumulated in the corresponding communication layer, and the error repair information is information about the repair operations for errors that have occurred in the corresponding communication layer.

[0189] The operation method of UFS device 10 may include creating an AFC frame (S1120) that includes state information collected in operation S1110.

[0190] In S1120, the UFS device 10 can write status information to one or more status information registers included in the UFS device 10, and then the status information written to the status information registers can be stored in an AFC frame. In this case, when an event indicating a change in status information occurs, the status information can be written to the status information registers.

[0191] Additionally, the operation method of the UFS device 10 may include transmitting the AFC frame created in operation S1120 to the host performing communication with the UFS device 10 (S1130).

[0192] As an example, AFC frames can be transmitted to the host at link startup time, hibernation exit time, or data transfer time between the host and UFS device 10.

[0193] Figure 12 This is a diagram illustrating the configuration of a computing system 1200 based on an embodiment of the disclosed technology.

[0194] Reference Figure 12 The computing system 1200 based on the disclosed technology may include: a UFS device 10 electrically connected to a system bus 1260; a CPU 1210 configured to control all operations of the computing system 1200; RAM 1220 configured to store data and information related to the operation of the computing system 1200; a user interface / user experience (UI / UX) module 1230 configured to provide a user environment to a user; a communication module 1240 configured to communicate with external devices of the wired and / or wireless type; and a power management module 1250 configured to manage the power used by the computing system 1200.

[0195] The computing system 1200 may be a personal computer (PC) or may include a mobile terminal such as a smartphone, tablet computer or various electronic devices.

[0196] The computing system 1200 may further include a battery for supplying operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and DRAM. Other components will be apparent to those skilled in the art.

[0197] UFS device 10 may include not only devices configured to store data on disks, such as hard disk drives (HDDs), but also devices configured to store data in non-volatile memory, such as solid-state drives (SSDs), general-purpose flash memory devices, or embedded MMC (eMMC) devices. This non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Furthermore, UFS device 10 can be implemented as various types of storage devices and installed inside various electronic devices.

[0198] Based on the embodiments of the disclosed technology, the operation latency of the memory system can be advantageously reduced or minimized. Furthermore, based on the embodiments of the disclosed technology, the overhead occurring in a process that calls a specific function can be advantageously reduced or minimized. Although various embodiments of the disclosed technology have been described with specific details and variations for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions can be made based on what is disclosed or shown in this disclosure.

[0199] While the foregoing embodiments have been described and detailed for clarity and understanding, the invention is not limited to the details provided. As those skilled in the art will understand from the foregoing disclosure, many alternative ways of carrying out the invention exist. Therefore, the disclosed embodiments are illustrative and not restrictive. The invention is intended to cover all modifications and substitutions falling within the scope of the appended claims.

Claims

1. A universal flash memory device, i.e., a UFS device, Collect the status information of the UFS device. Create an acknowledgment and flow control frame, i.e., an AFC frame, that includes the collected status information, and When the host communicates with the UFS device, the AFC frame is transmitted to the host, so that the host can check the status information of the UFS device in real time. in, The AFC frame is divided into a header, a payload, and a checksum, and within the payload of the AFC frame, the status information of the UFS device is included in a region allocated for the status information.

2. The UFS device according to claim 1, wherein the status information includes at least one of the following: temperature information of the UFS device, voltage change information of the UFS device, information about the communication layer between the host and the UFS device, and command transmission hold request information for the host.

3. The UFS device according to claim 2, wherein the communication layer is a data link layer or a physical layer.

4. The UFS device of claim 2, wherein the information regarding the communication layer includes at least one of error accumulation information and error repair information, the error accumulation information being information about errors that have accumulated in the communication layer, and the error repair information being information about operations for repairing the errors that have occurred in the communication layer.

5. The UFS device of claim 1, wherein the UFS device creates the AFC frame by means of the following steps: The status information is written into one or more status information registers included in the UFS device, and The status information to be written into the status information register is stored in the AFC frame.

6. The UFS device according to claim 5, wherein when an event indicating a change in the state information occurs, the UFS device writes the state information into the state information register.

7. The UFS device according to claim 1, wherein the UFS device transmits the AFC frame to the host at the link startup time, the hibernation exit time, or the data transmission time between the host and the UFS device.

8. A method for operating a universal flash memory device, i.e., a UFS device, comprising: Collect the status information of the UFS device. Create an acknowledgment and flow control frame, i.e., an AFC frame, that includes the collected status information, and When the host communicates with the UFS device, the AFC frame is transmitted to the host, so that the host can check the status information of the UFS device in real time. The AFC frame is divided into a header, a payload, and a checksum, and the status information of the UFS device is included in the area allocated for the status information within the payload of the AFC frame.

9. The operating method of claim 8, wherein the status information includes at least one of the following: temperature information of the UFS device, voltage change information of the UFS device, information about the communication layer between the host and the UFS device, and command transmission hold request information for the host.

10. The method of operation according to claim 9, wherein the communication layer is a data link layer or a physical layer.

11. The method of operation according to claim 9, wherein the information regarding the communication layer includes at least one of error accumulation information and error repair information, the error accumulation information being information about errors that have accumulated in the communication layer, and the error repair information being information about operations for repairing the errors that have occurred in the communication layer.

12. The method of operation according to claim 8, wherein creating the AFC frame comprises: Write the status information into one or more status information registers included in the UFS device; and The status information to be written into the status information register is stored in the AFC frame.

13. The operating method according to claim 12, wherein when an event indicating a change in the state information occurs, the state information is written into the state information register.

14. The operating method according to claim 8, wherein the AFC frame is transmitted to the host at the link startup time, the hibernation exit time, or the data transmission time between the host and the UFS device.

15. A method of operating a system, the system comprising a host device and a general-purpose flash memory device, i.e., a UFS device, the method comprising: The host device and the UFS device communicate with each other according to the Mobile Industrial Processor Interface (MIPI) standard. The UFS device provides the host device with information about its status via Acknowledgment and Flow Control (AFC) frames defined by the standard; and When the host device communicates with the UFS device, the host device receives the AFC frame, thereby allowing the host device to check the status information of the UFS device in real time. The AFC frame is divided into a header, a payload, and a checksum, and the status information of the UFS device is included in the area allocated for the status information within the payload of the AFC frame.

16. A method of operating a universal flash memory device, i.e., a UFS device, the method comprising: Communicates with the host device according to the Mobile Industrial Processor Interface (MIPI) standard; and The host device is provided with information about the status of the UFS device via Acknowledgment and Flow Control (AFC) frames, as defined by the standard. When the host device communicates with the UFS device, it transmits the AFC frame to the host device, thereby allowing the host device to check the status information of the UFS device in real time. The AFC frame is divided into a header, a payload, and a checksum, and the status information of the UFS device is included in the area allocated for the status information within the payload of the AFC frame.

17. A method of operating a host device, the method comprising: Communicating with Universal Flash Memory (UFS) devices according to the Mobile Industrial Processor Interface (MIPI) standard; and The system receives an Acknowledgment and Flow Control (AFC) frame, defined by the standard and including information about the state of the UFS device, to identify the state. When the host device communicates with the UFS device, it transmits the AFC frame to the host device, thereby allowing the host device to check the status information of the UFS device in real time. The AFC frame is divided into a header, a payload, and a checksum, and the status information of the UFS device is included in the area allocated for the status information within the payload of the AFC frame.

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