Memory Circuit and Memory Programming Method

Abstract

The present invention provides a memory circuit and a memory programming method, which are applicable to programming flash memory. The memory circuit includes a charge pump circuit that generates a pump voltage and a pump current; a voltage regulator coupled to the charge pump circuit and generating a programming voltage and a programming current according to the pump voltage and the pump current to program the flash memory; a voltage sensor coupled to the voltage regulator to monitor the voltage value of the programming voltage; and a plurality of switch circuits, wherein one end of each switch circuit is coupled to the voltage sensor, the other end is coupled to the flash memory, and the number of the plurality of switch circuits that are turned on is determined according to the voltage value of the programming voltage.

Description

Technical Field

[0001] The present invention relates to a circuit, and more particularly to a memory circuit and a memory programming method. Background Art

[0002] Charge pump circuits and voltage regulators are often used to program flash memories. The charge pump circuit generates a pump voltage and a pump current to the voltage regulator, and the voltage regulator then generates a programming voltage and a programming current based on the received pump voltage and pump current to program the flash memory.

[0003] However, due to the uncertainties of various combinations such as semiconductor process drift, circuit operating temperature variation, and memory leakage current, when designing a charge pump circuit, it is necessary to consider the above uncertainties and design the pump voltage and pump current provided by the charge pump circuit such that, under a predetermined programming voltage, the charge pump circuit can supply the maximum programming current consumed by the flash memory when the above uncertainties are combined in the most power-consuming situation.

[0004] Such a design method of the charge pump circuit results in a too large circuit area and an increased cost because it is necessary to provide a sufficiently large programming current.

[0005] Nothing in this document should be construed as an admission of knowledge in the prior art of any part of the present disclosure. Summary of the Invention

[0006] The present invention provides a memory circuit and a memory programming method, in which the charge pump circuit does not need to be designed considering the combination of the above uncertainties occurring in the most power-consuming situation, but only needs to be designed considering the combination of the above uncertainties occurring in a typical case to design the pump voltage and pump current of the charge pump circuit.

[0007] The memory circuit of the present invention is applicable to programming a flash memory. The memory circuit includes: a charge pump circuit that generates a pump voltage and a pump current; a voltage regulator coupled to the charge pump circuit and generating a programming voltage and a programming current based on the pump voltage and the pump current to program the flash memory; a voltage sensor coupled to the voltage regulator to monitor the voltage value of the programming voltage; and a plurality of switch circuits, one end of each of the plurality of switch circuits is coupled to the voltage sensor, and the other end is coupled to the flash memory, and the number of conducting switch circuits is determined according to the voltage value of the programming voltage.

[0008] The memory programming method of the present invention is applicable to programming a flash memory, and includes: generating a programming voltage and a programming current; setting a plurality of programming paths to be all conductive, and programming the flash memory via the plurality of programming paths during a programming pulse with the programming voltage and the programming current; after the programming pulse period ends, monitoring the voltage value of the programming voltage; determining whether the programming voltage is greater than or equal to a predetermined programming voltage; comparing the programming voltage with a plurality of predetermined voltages, and generating switching weights of the plurality of programming paths according to the comparison result; selecting to disconnect some of the plurality of programming paths according to the switching weights of the plurality of programming paths; and determining whether programming verification is passed.

[0009] The memory programming method of the present invention is applicable to programming a flash memory, and includes: generating a programming voltage and a programming current; setting a plurality of programming paths to be all conductive, and programming the flash memory via the plurality of programming paths during a programming pulse: monitoring the voltage value of the programming voltage; comparing the programming voltage with a plurality of predetermined voltages, and generating switching weights of the plurality of programming paths according to the comparison result; and selecting to disconnect some of the plurality of programming paths according to the switching weights of the plurality of programming paths, and after the programming pulse period ends, determining whether programming verification is passed.

[0010] Based on the above, the present invention provides a memory circuit and a memory programming method, which only need to design the pump voltage and pump current of the charge pump circuit by considering the above combinations of uncertainties occurring in general situations, so that the circuit area can be reduced and the cost can be reduced.

[0011] To better understand the foregoing content, several embodiments with accompanying drawings are described in detail below. Description of the Drawings

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure, and the drawings are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the embodiments, are used to explain the principles of the present disclosure.

[0013] Figure 1 A diagram showing an example of programming a flash memory by a memory circuit of the present invention with a programming voltage and a programming current;

[0014] Figure 2 A diagram showing the voltage-current load lines of the charge pump circuit and the voltage regulator in the memory circuit of the present invention respectively;

[0015] Figure 3 A diagram showing the correspondence between the monitored programming voltage and the programming current in the memory circuit of the present invention when the monitored programming voltage is less than the predetermined programming voltage;

[0016] Figure 4 A diagram showing the correspondence between the monitored programming voltage, the switching weights of the programming paths, and the disconnected programming paths in the memory circuit of the present invention;

[0017] Figure 5 A flowchart showing the memory programming method of the present invention;

[0018] Figure 6 A flowchart showing another memory programming method of the present invention.

[0019] Explanation of the reference numerals in the drawings

[0020] 100: Memory circuit;

[0021] 101: Charge pump circuit;

[0022] 102: Voltage regulator;

[0023] 103: Flash memory;

[0024] V PGM : Predetermined programming voltage;

[0025] V PUMP : Pump voltage;

[0026] G, D, S: Gate, drain, source;

[0027] I LEAK : Average leakage current;

[0028] I PGMALL : Total programming current;

[0029] V D 、V Drain : Programming voltage;

[0030] WL[0] to WL

[511] : Word lines;

[0031] I PUMP : Pump current;

[0032] I PGMCELL0 ~I PGMCELL7 : Programming current of the memory cell;

[0033] I PGMCELL : Average programming current of the memory cell;

[0034] I PGM0 ~I PGM7 : Programming current of each programming path;

[0035] I LEAK0 ~I LEAK7 : Leakage current of each programming path;

[0036] I MAX : Maximum current that the voltage regulator can output when outputting the predetermined programming voltage;

[0037] I PGMALL_TYPICAL : Total programming current under normal conditions;

[0038] I PGMALL_MAX : Total programming current under extreme conditions;

[0039] V1 to V4: Predetermined voltages;

[0040] 200, 300: Programming methods;

[0041] I2 to I4: Currents corresponding to the predetermined voltages;

[0042] S201 to S207: Steps;

[0043] Y0 to Y7: Multiple switch circuits;

[0044] S301 to S306: Steps. Detailed implementation

[0045] Embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0046] Figure 1 The memory circuit 100 of the present invention is shown with a predetermined programming voltage V PGM and a total programming current I PGMALL for programming the flash memory 103 as an example. The memory circuit 100 includes a charge pump circuit 101 and a voltage regulator 102. The charge pump circuit 101 generates a pump voltage V PUMP and a pump current I PUMP to the voltage regulator 102. The voltage regulator 102 generates a predetermined programming voltage V PUMP and a total programming current I PUMP based on the pump voltage V PGM and the pump current I PGMALL to the flash memory 103 to program the flash memory 103.

[0047] The flash memory 103 includes, as shown Figure 1 512 columns (rows) * 8 rows (columns) of memory cells, but is not limited thereto. The switches of the memory cells in the nth column are coupled to the gates (Gate, G) of the memory cells in the nth column by the word line WL[n - 1] to control the switches of the memory cells in the nth column. The drains (Drain, D) of the memory cells in the mth row share the bit line BL[m - 1] (not shown) and receive the predetermined programming voltage V PGM (V PGM ≈V D ≈V Drain ) and the programming current I corresponding to the memory cells in the mth row PGM(m-1), where n is an integer from 1 to 512, m is an integer from 1 to 8, and in addition, the source (S) of each memory cell is coupled to a reference voltage (e.g., 0V).

[0048] As Figure 1 shown, when the target cell to be programmed in the memory circuit 100 is the first column of the flash memory 103, WL[0] is set to high voltage (e.g., 10V), WL[1] to WL

[511] are set to low voltage (e.g., 0V). At this time, the total programming current I PGMALL consumed by the flash memory 103 can be expressed by Equation 1.

[0049] I PGMALL ≈ 8 * (I PGMCELL + 511 * I LEAK )... (Equation 1), where I PGMCELL is the average value of the programming currents consumed by each memory cell (I PGMCELL0 to I PGMCELL7 ) in the first column of the flash memory 103, and I LEAK is the average value of the leakage currents consumed by each memory cell in the second to 512th columns of the flash memory 103.

[0050] According to Equation 1, the total programming current I PGMALL consumed by the flash memory 103 will vary according to the number of memory cells to be programmed in the memory circuit 100, the programming current they consume, and the leakage current of the unprogrammed memory cells. The programming current of the memory cells to be programmed and the leakage current of the unprogrammed memory cells will vary due to various combinations of uncertainties such as semiconductor process drift and circuit operating temperature variation. The total programming current I PGMALL consumed by the flash memory 103 under normal conditions (e.g., normal temperature, process) can be set as I PGMALL_TYPICAL , and under extreme conditions (e.g., extremely power-consuming temperature, process), it can be set as I PGMALL_MAX .

[0051] Figure 2 FIG. shows the voltage-current load lines of the charge pump circuit 101 and the voltage regulator 102 in the memory circuit 100 of the present invention, respectively. Among them, the pump voltage V PUMP generated by the charge pump circuit 101 and the pump current I PUMP are in an inverse relationship. In other words, the larger the pump voltage V PUMP , the smaller the pump current I PUMP (as shown by the dashed line in Figure 2 ). The predetermined programming voltage V PGM generated by the voltage regulator 102 can be determined according to the design specifications. The voltage-current load line of the charge pump circuit 101 (as inFigure 2 as shown by the dashed line) and the current value I corresponding to the intersection point of the voltage V = the predetermined programming voltage V PGM MAX represents the maximum current that the voltage regulator 102 can output when the output voltage is the predetermined programming voltage V PGM .

[0052] Figure 2 The design target 1 shown in the figure sets I MAX to I PGMALL_MAX , and the design target 2 sets I MAX to I PGMALL_TYPICAL . The design target 1 enables the current output by the voltage regulator 102 when the output voltage is the predetermined programming voltage V PGM to cover the current consumed by the flash memory 103 under all conditions (including extremely power-consuming temperature and manufacturing process), while the design target 2 enables the current output by the voltage regulator 102 when the output voltage is the predetermined programming voltage V PGM to cover the current consumed by the flash memory 103 under general conditions (general temperature and manufacturing process). Compared with the design target 1, the charge pump circuit 101 adopting the design target 2 of the present invention has a smaller area and lower cost because it does not need to provide a pump current I as large as that of the design target 1 PUMP .

[0053] Refer to Figure 3 and Figure 4 , where Figure 3 represents the correspondence between the monitored programming voltage V Drain less than the predetermined programming voltage V PGM (i.e., when I PGMALL > I MAX = I PGMALL_TYPICAL ) and the total programming current I Drain in the memory circuit of the present invention. The purpose of the monitored programming voltage V PGMALL is to ensure that the flash memory 103 can be programmed with the predetermined programming voltage V Drain . PGM .

[0054] Figure 4 Y0 to Y7 of are a plurality of switching circuits. One end of each of the plurality of switching circuits Y0 to Y7 is coupled to the voltage output end of the voltage regulator 102, and the other end of each of the plurality of switching circuits Y0 to Y7 is respectively coupled to the bit lines BL[0] to BL[7] of the flash memory 103. The plurality of switching circuits Y0 to Y7 perform switching control on each programming path through the above coupling method. A voltage sensor (not shown) including a comparator monitors the programming voltage V Drain , and the mechanism by which the voltage sensor monitors the programming voltage V Drain is to sense the programming voltage V DrainIt is output to an input terminal of a comparator, and then compared with a plurality of predetermined voltages (such as V1, V2, but not limited thereto) at the other input terminal of the comparator, and a comparison result representing the switch weights of each programming path (such as a two-bit programming path switch weight [1:0], but not limited thereto) is output to a decoder. The decoder outputs a control signal to the control terminals of a plurality of switch circuits Y0 to Y7 according to the programming path switch weight [1:0] to selectively control whether the plurality of switch circuits Y0 to Y7 are turned on.

[0055] Figure 4 The following table shows an example where the voltage sensor monitors the programming voltage V Drain and performs switch control on each programming path according to the monitoring result. Set the predetermined programming voltage V PGM = 7V, the predetermined voltage V1 = 7V, and the predetermined voltage V2 = 6V. When the voltage sensor monitors the programming voltage V Drain and the voltage ≥ V1 (= 7V), the voltage sensor outputs the programming path switch weight [1:0] =

[00] to the decoder. The decoder outputs a control signal to the control terminals of a plurality of switch circuits Y0 to Y7 according to the programming path switch weight [1:0] =

[00] to turn on all the plurality of switch circuits Y0 to Y7. In other words, at this time, the total programming current I PGMALL < I MAX = I PGMALL_TYPICAL , and the flash memory 103 can be programmed with a programming voltage greater than or equal to the predetermined programming voltage V PGM .

[0056] When the voltage sensor monitors the programming voltage V Drain and the voltage is between V1 and V2 (= 6V) (i.e., V2 < programming voltage V Drain < V1), the voltage sensor outputs the programming path switch weight [1:0] =

[10] to the decoder. The decoder outputs a control signal to the control terminals of a plurality of switch circuits Y0 to Y7 according to the programming path switch weight [1:0] =

[10] to turn off some of the switch circuits Y7 to Y6 and turn on some of the switch circuits Y0 to Y5. In other words, at this time, the total programming current I PGMALL > I MAX = I PGMALL_TYPICAL , and the flash memory 103 is programmed with a programming voltage less than the predetermined programming voltage V PGM . To avoid programming errors, the memory circuit 100 must temporarily disconnect some of the programming paths to ensure that the flash memory 103 is programmed with a programming voltage greater than or equal to the predetermined programming voltage V PGM .

[0057] When the voltage sensor monitors the programming voltage V DrainWhen the voltage is less than or equal to V2 (=6V), the voltage sensor outputs the programming path switch weights [1:0]=

[11] to the decoder. The decoder outputs control signals to the control terminals of multiple switch circuits Y0~Y7 according to the programming path switch weights [1:0]=

[11] to disconnect some of the switch circuits Y7~Y2 and turn on some of the switch circuits Y0~Y1. In other words, at this time, the total programming current I PGMALL >I MAX =I PGMALL_TYPICAL (and the total programming current I at this time PGMALL is greater than the total programming current I when the programming path switch weights [1:0]=

[10] PGMALL ), the flash memory 103 is programmed with a programming voltage less than the predetermined programming voltage V PGM . To avoid programming errors, the memory circuit 100 must temporarily disconnect some of the programming paths to ensure that the flash memory 103 is programmed with a programming voltage greater than or equal to the predetermined programming voltage V PGM .

[0058] Figure 5 FIG. shows a flowchart of the memory programming method 200 of the present invention, which is applicable to programming the flash memory 103 and includes: setting all programming paths to be turned on S201; programming the flash memory 103 during the programming pulse period S202; after the end of the programming pulse period S202, monitoring the programming voltage V Drain S203; determining whether the programming voltage V Drain is greater than or equal to the predetermined programming voltage V PGM S204; comparing the programming voltage V Drain with multiple predetermined voltages to generate programming path switch weights S205; selecting to disconnect some of the programming paths according to the programming path switch weights S206; determining whether the flash memory 103 passes the programming verification S207.

[0059] Figure 6 FIG. shows a flowchart of the memory programming method 300 of the present invention, which is applicable to programming the flash memory 103 and includes: setting all programming paths to be turned on S301; programming the flash memory 103 during the programming pulse period S302; monitoring the programming voltage V Drain S303; comparing the programming voltage V Drain with multiple predetermined voltages to generate programming path switch weights S304; selecting to disconnect some of the programming paths according to the programming path switch weights S305; after the end of the programming pulse period S302, determining whether the flash memory 103 passes the programming verification S306.

[0060] In summary, for the memory circuit and the memory programming method of the present invention, only the above combinations of uncertainties need to occur under general conditions as the design consideration to design the pump voltage and pump current of the charge pump circuit. Therefore, the circuit area can be reduced and the cost can be reduced.

[0061] It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. Given the foregoing, it is intended that the disclosure cover such modifications and variations provided they come within the scope of the appended claims and their equivalents.

Claims

1. A memory circuit, applicable to programming a flash memory, the memory circuit comprises: a charge pump circuit that generates a pump voltage and a pump current; a voltage regulator coupled to the charge pump circuit and generating a programming voltage and a programming current according to the pump voltage and the pump current to program the flash memory; a voltage sensor coupled to the voltage regulator to monitor a voltage value of the programming voltage; and a plurality of switch circuits, one end of each of the plurality of switch circuits is coupled to the voltage sensor, and the other end is coupled to the flash memory, and the number of turned-on switch circuits among the plurality of switch circuits is determined according to the voltage value of the programming voltage, wherein the voltage sensor includes a comparator that compares the voltage value of the programming voltage with a plurality of predetermined voltages to generate a comparison result, and the voltage sensor generates a switch weight of the plurality of switch circuits according to the comparison result.

2. The memory circuit according to claim 1, wherein the pump voltage generated by the charge pump circuit is inversely proportional to the pump current.

3. The memory circuit according to claim 1, wherein one end of each of the plurality of switch circuits is coupled to the voltage regulator, and the other end is coupled to different bit lines of the flash memory.

4. The memory circuit according to claim 1, wherein the number of turned-on switch circuits among the plurality of switch circuits is proportional to the voltage value of the programming voltage.

5. The memory circuit according to claim 1, wherein the plurality of predetermined voltages include a predetermined programming voltage and a first predetermined voltage, and the predetermined programming voltage is greater than the first predetermined voltage. When the programming voltage is greater than or equal to the predetermined programming voltage, the voltage sensor generates a first switch weight. When the programming voltage is less than the predetermined programming voltage and greater than the first predetermined voltage, the voltage sensor generates a second switch weight. When the programming voltage is less than or equal to the first predetermined voltage, the voltage sensor generates a third switch weight.

6. The memory circuit according to claim 5, wherein the plurality of switch circuits determine the number of turned-on circuits according to the switch weight.

7. The memory circuit according to claim 6, wherein when the voltage sensor generates the first switch weight, all of the plurality of switch circuits are turned on.

8. The memory circuit according to claim 6, wherein when the voltage sensor generates the second switch weight, the plurality of switch circuits are turned on with a first number of turned-on circuits, and when the voltage sensor generates the third switch weight, the plurality of switch circuits are turned on with a second number of turned-on circuits, and the first number of turned-on circuits is greater than the second number of turned-on circuits.

9. The memory circuit according to claim 1, further comprising a decoder that generates a control signal to a control terminal of each of the plurality of switch circuits according to the switch weight.

10. A memory programming method, applicable to programming a flash memory, comprises: generating a programming voltage and a programming current; setting a plurality of programming paths to be all turned on, and programming the flash memory during a programming pulse period with the programming voltage and the programming current passing through the plurality of programming paths; after the programming pulse period ends, monitoring a voltage value of the programming voltage; Determine whether the programming voltage is greater than or equal to a predetermined programming voltage; Compare the programming voltage with a plurality of predetermined voltages and generate switching weights of the plurality of programming paths according to a comparison result; Select and disconnect some of the plurality of programming paths according to the switching weights of the plurality of programming paths; And Determine whether programming verification is passed.

11. A memory programming method applicable to programming a flash memory, comprising: Generate a programming voltage and a programming current; Set a plurality of programming paths to be all conducting, and the programming voltage and the programming current pass through the plurality of programming paths. During a programming pulse: Program the flash memory; Monitor a voltage value of the programming voltage; Compare the programming voltage with a plurality of predetermined voltages and generate switching weights of the plurality of programming paths according to a comparison result; And Select and disconnect some of the plurality of programming paths according to the switching weights of the plurality of programming paths, and After the programming pulse period ends, determine whether programming verification is passed.

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