SRAM cell, memory and electronic device including the same

Abstract

A method for manufacturing a static random access memory (SRAM) cell is disclosed. According to an embodiment, the method may include: sequentially disposing a stack of a first source / drain layer, a channel layer, and a second source / drain layer of a first group, and a stack of a first source / drain layer, a channel layer, and a second source / drain layer of a second group on a substrate; forming a hard mask layer on the stack, comprising a body portion for defining a transistor in the SRAM cell and a connecting portion between the body portions for defining an interconnect structure in the SRAM cell, wherein the line width of the connecting portion is smaller than the line width of the body portion; using the hard mask layer, defining active regions of a pull-down transistor and a pass-gate transistor in the channel layer and the second source / drain layer of the second group; using the hard mask layer, defining a first interconnect structure and a second interconnect structure in the first source / drain layer of the second group and the second source / drain layer of the first group; and using the hard mask layer, defining an active region of a pull-up transistor in the channel layer and the first source / drain layer of the first group.

Description

[0001] This application is a divisional application of invention patent application 201910902431.X filed on September 23, 2019. Technical Field

[0002] The present disclosure relates to the field of semiconductors, and more particularly, to a static random access memory (SRAM) cell and a method for manufacturing the same, as well as a memory and an electronic device including the SRAM cell. Background Art

[0003] In horizontal devices, such as metal oxide semiconductor field effect transistors (MOSFETs), the source, gate, and drain electrodes are arranged roughly parallel to the substrate surface. This arrangement makes horizontal devices difficult to scale down. In contrast, in vertical devices, the source, gate, and drain electrodes are arranged roughly perpendicular to the substrate surface. Therefore, vertical devices are easier to scale down than horizontal devices.

[0004] Furthermore, there is a desire to increase integration and storage density, so vertical devices are promising for use in memory devices such as static random access memory (SRAM). However, there is currently a lack of effective means to further improve the integration or storage density of SRAM based on vertical devices, particularly vertical nanosheet or nanowire MOSFETs. Summary of the Invention

[0005] In view of the above, an object of the present disclosure is at least in part to provide a static random access memory (SRAM) cell with improved performance, a method for manufacturing the same, and a memory and an electronic device including the SRAM cell.

[0006] According to one aspect of the present disclosure, an SRAM cell is provided, comprising a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor, arranged in two layers on a substrate. Each transistor can be a vertical transistor. The first pull-up transistor and the second pull-up transistor can be arranged on a first layer, while the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, and the second pass-gate transistor can be arranged on a second layer at a different height from the first layer. The region where the first pull-up transistor and the second pull-up transistor are located can at least partially overlap with the region where the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, and the second pass-gate transistor are located in a vertical direction relative to the upper surface of the substrate.

[0007] According to another aspect of the present disclosure, a method for manufacturing an SRAM cell is provided, comprising: sequentially arranging a stack of a first source / drain layer, a channel layer, and a second source / drain layer of a first group, and a first source / drain layer, a channel layer, and a second source / drain layer of a second group on a substrate; forming a hard mask layer on the stack, the hard mask layer comprising a main body portion and a connecting portion between the main body portions, wherein the main body portion is used to define a transistor included in the SRAM cell, the connecting portion is used to define an interconnection structure included in the SRAM cell, and a line width of the connecting portion is smaller than a line width of the main body portion; using the hard mask layer, defining active areas of a pull-down transistor and a pass-gate transistor in the transistor included in the SRAM cell in the channel layer and the second source / drain layer of the second group; using the hard mask layer, defining a first interconnection structure and a second interconnection structure in the interconnection structure included in the SRAM cell in the first source / drain layer of the second group and the second source / drain layer of the first group; and using the hard mask layer, defining an active area of ​​a pull-up transistor in the transistor included in the SRAM cell in the channel layer and the first source / drain layer of the first group.

[0008] According to another aspect of the present disclosure, an electronic device is provided, including a memory device having the above-mentioned SRAM cell.

[0009] According to embodiments of the present disclosure, the constituent transistors of an SRAM cell can be arranged in a vertically stacked manner, thereby saving area. The upper and lower transistors can be stacked in a self-aligned manner, further saving area. The active region of the transistor, especially the channel material, can be a single-crystal semiconductor material, thereby providing high mobility and thus enhancing the performance of the SRAM cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0011] Figure 1 Schematically shows an equivalent circuit diagram of a static random access memory (SRAM) cell;

[0012] Figure 2 schematically illustrates a perspective view of an SRAM cell according to an embodiment of the present disclosure;

[0013] Figure 3(a) and 3(b) Shown Figure 2 An exploded perspective view of an SRAM cell is shown;

[0014] Figure 4(a) and 4(b) Schematically shows an exploded perspective view of an SRAM cell according to another embodiment of the present disclosure;

[0015] Figure 5(a) and 5(b) Schematically shows an exploded perspective view of an SRAM cell according to another embodiment of the present disclosure;

[0016] Figure 6(a) and 6(b) Schematically shows an exploded perspective view of an SRAM cell according to another embodiment of the present disclosure;

[0017] Figure 7(a) and 7(b) Schematically shows an exploded perspective view of an SRAM cell according to another embodiment of the present disclosure;

[0018] Figures 8 to 52(c) Some stages in the process of manufacturing an SRAM cell according to an embodiment of the present disclosure are schematically shown.

[0019] Throughout the drawings, the same or similar reference numerals refer to the same or similar parts. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0021] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0022] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, it can be directly on the other layer / element or an intervening layer / element may be present therebetween. In addition, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed.

[0023] According to an embodiment of the present disclosure, a static random access memory (SRAM) cell based on vertical devices, such as vertical nanosheets or nanowire metal oxide semiconductor field effect transistors (MOSFETs), is provided. In the SRAM cell, the vertical devices, which are components of the SRAM cell, can be stacked vertically to further improve integration.

[0024] Figure 1 The equivalent circuit diagram of an SRAM cell is schematically shown.

[0025] like Figure 1 As shown, the SRAM cell can be a 6T structure, that is, it includes six component transistors M1 to M6, such as field-effect transistors (FETs). Among these six transistors, four transistors M1, M2, M3, and M4 can form two cross-coupled inverters, serving as the storage location for storing a single bit in the SRAM cell. The other two transistors M5 and M6 can control the data transmission between the storage location and the bit line BL and the complementary bit line / BL, respectively, under the control of the word line WL, to achieve reading and writing.

[0026] Of the four transistors M1, M2, M3, and M4 constituting the cross-coupled inverter, two p-type transistors M2 and M4 can be connected to the power supply voltage V DD , and therefore can be called "pull-up transistors" (PU); the two n-type transistors M1 and M3 can be connected to the ground voltage and therefore can be called "pull-down transistors" (PD). Transistors M5 and M6 (which can also be n-type) can control reading and writing or data transmission and therefore can be called "access control transistors" or "pass-gate transistors" (PG).

[0027] The following briefly describes the read and write operations of this 6T SRAM cell.

[0028] First, the read operation is described. Assume that the bit stored in the storage location is "1", that is, it is a high level at node Q and a low level at node / Q. At the beginning of the read cycle, the bit line BL and the complementary bit line / BL can be pre-charged to a logic 1, and then the word line WL can be charged to a high level to turn on the access control transistors M5 and M6. Due to the high level at Q, the pull-up transistor M2 is turned off and the pull-down transistor M1 is turned on, so the pull-down transistor M1 and the access control transistor M5 connect the complementary bit line / BL to the ground, so the pre-charged value of the complementary bit line / BL is drained, so that the complementary bit line / BL has a value of 0. On the other hand, due to the low level at / Q, the pull-up transistor M4 is turned on and the pull-down transistor M3 is turned off, so the pull-up transistor M4 and the access control transistor M6 connect the bit line BL to the power supply voltage V DD The two circuits are connected, and thus maintain the precharged value, that is, the value 1 on the bit line BL. If the stored bit is "0", the opposite circuit state will cause the value 1 on the complementary bit line / BL and the value 0 on the bit line BL. By determining which of the two lines has a higher potential, the stored bit "0" or "1" can be read.

[0029] In a write operation, at the beginning of the write cycle, the state to be written is loaded onto the bit line BL. For example, if a "0" is to be written, the bit line BL is set to "0" (and the complementary bit line / BL is set to "1"). The word line WL can then be charged high to turn on the access control transistors M5 and M6, thereby loading the state of the bit line BL into the memory location of the SRAM cell. This is achieved by designing the bit line input driver (the transistor) to be stronger than the memory location (the transistor), so that the bit line state can overwrite the previous state of the cross-coupled inverter in the memory location.

[0030] For a 6T SRAM cell, the following parameters can be defined:

[0031] - Read noise margin (RNM): β = PD (w / l) / PG (w / l);

[0032] -Write noise margin (WNM): α = PU(w / l) / PG(w / l), where PD(w / l) represents the width-to-length ratio of the pull-down transistor, PU(w / l) represents the width-to-length ratio of the pull-up transistor, and PG(w / l) represents the width-to-length ratio of the pass-gate transistor.

[0033] Different values ​​of α and β can be selected based on the design. According to the embodiments of the present disclosure, for ease of manufacturing, the PD, PU, ​​and PG can be composed of unit transistors with substantially the same width-to-length ratio w / l. To achieve different values ​​of α and β, the PD, PU, ​​and PG can include different numbers of unit transistors. The following table lists several example values ​​of α and β and the corresponding number of unit transistors.

[0034] Table 1

[0035]

[0036] Figure 2 Schematically shows a perspective view of an SRAM cell according to an embodiment of the present disclosure, Figure 3(a) and 3(b) Shown Figure 2 An exploded perspective view of an SRAM cell is shown.

[0037] In this example, β=1 and α=1, that is, PD, PU, ​​and PG can all be composed of a single unit transistor. Therefore, in a 6TSRAM cell, 6 unit transistors can be included, such as Figure 2 、 3(a) The two pull-up transistors PU-1 and PU-2, the two pull-down transistors PD-1 and PD-2, and the two pass-gate transistors PG-1 and PG-2 shown in FIG3(b) can all be vertical transistors.

[0038] A vertical transistor may include an active region extending in a vertical direction relative to the upper surface of the substrate (for example, a direction approximately perpendicular to the upper surface of the substrate). The active region may include a channel region and source / drain regions located on opposite sides of the channel region in the vertical direction. As described below, the active region of the transistor may include a first source / drain layer, a channel layer, and a second source / drain layer stacked in sequence along the vertical direction. The layers may be adjacent to each other, and of course there may be other semiconductor layers in the middle, such as a leakage suppression layer and an on-state current enhancement layer (a semiconductor layer with a band gap larger or smaller than that of the adjacent layer). The source / drain regions may be basically formed in the first source / drain layer and the second source / drain layer, respectively, and the channel region may be basically formed in the channel layer. For example, the source / drain regions may be realized by doping regions in the source / drain layer. The gate stack may be formed around at least part of the periphery or even the entire periphery of the channel region.

[0039] In the accompanying drawings, the active regions of these transistors are shown as nanowires extending in a vertical direction, but the present disclosure is not limited thereto. For example, the active regions may also be nanosheets or other forms. In addition, for the sake of convenience, the gate electrodes included in the gate stack are schematically shown in the perspective views, and the gate electrodes are shown only in cross-section.

[0040] According to an embodiment of the present disclosure, such a transistor may be a conventional FET. In the case of a conventional FET, the source / drain regions on both sides of the channel region may have doping of the same conductivity type (e.g., n-type or p-type). A conductive channel may be formed between the source / drain regions at both ends of the channel region through the channel region. Alternatively, such a transistor may be a tunneling FET. In the case of a tunneling FET, the source / drain regions on both sides of the channel region may have doping of different conductivity types (e.g., n-type and p-type, respectively). In this case, charged particles such as electrons may tunnel from the source region through the channel region into the drain region, thereby forming a conductive path between the source region and the drain region. Although the conduction mechanisms in conventional FETs and tunneling FETs are different, they both exhibit electrical properties that can control whether the source / drain regions are conductive or not by a gate. Therefore, for conventional FETs and tunneling FETs, the terms "source / drain layer (source / drain region)" and "channel layer (channel region)" are used to describe them uniformly, although there is no "channel" in the usual sense in tunneling FETs.

[0041] Unlike conventional techniques in which constituent transistors in an SRAM cell are arranged in a planar layout, according to embodiments of the present disclosure, constituent transistors in an SRAM cell may be stacked in a vertical direction to further save the area occupied by the SRAM cell.

[0042] To facilitate manufacturing, for example, to facilitate the doping of the active area and the setting of the interconnection structure, transistors of the same conductivity type can be arranged in one layer (for example, at substantially the same height from the upper surface of the substrate), and transistors of different conductivity types can be divided into two layers (for example, at different heights from the upper surface of the substrate), and these two layers can at least partially overlap in the vertical direction.

[0043] exist Figure 2 、 3(a) In the example shown in FIG3( b ), pull-up transistors PU-1 and PU-2 as p-type transistors are arranged in one layer, and pull-down transistors PD-1 and PD-2 and pass-gate transistors PG-1 and PG-2 as n-type transistors are arranged in one layer. In this example, the p-type transistors are in the lower layer and the n-type transistors are in the upper layer, but the present disclosure is not limited thereto. For example, by Figure 2 、 3(a) By turning the structure shown in FIG3(b) upside down (the substrate remains at the bottom) and adjusting the interconnect structure accordingly, the p-type transistor can be placed on the upper layer and the n-type transistor can be placed on the lower layer.

[0044] Because the electrical connections to the n-type pull-down transistors PD-1 and PD-2 and the pass-gate transistors PG-1 and PG-2 are relatively complex, it is advantageous to place the n-type transistors in the upper layer, for example, to facilitate the fabrication of the electrical connections. The drawings and the following description illustrate the n-type transistors being placed in the upper layer.

[0045] These transistors may be electrically connected to each other according to the above-described 6T layout.

[0046] like Figure 2 、 3(a) As shown in FIG3( b ), the source / drain region (e.g., drain region) on the upper side of the first pull-up transistor PU- 1 may be connected to the source / drain region (e.g., drain region) on the lower side of the first pull-down transistor PD- 1 , and a first node therebetween corresponds to, for example, Figure 1 The source / drain region on the lower side of the first pass-gate transistor PG-1 can be connected to the first node, while the source / drain region on the upper side can be connected to the first bit line (eg, Figure 1 Here, the connection between the source / drain regions of the first pull-up transistor PU-1, the first pull-down transistor PD-1, and the first pass-gate transistor PG-1 is shown as a first interconnect structure SD-1. Similarly, the source / drain region (e.g., drain region) on the upper side of the second pull-up transistor PU-2 can be connected to the source / drain region (e.g., drain region) on the lower side of the second pull-down transistor PD-2, and the second node therebetween corresponds to, for example, Figure 1The source / drain region on the lower side of the second pass-gate transistor PG-2 can be connected to the second node, while the source / drain region on the upper side can be connected to the second bit line (eg, Figure 1 Here, the connection between the source / drain regions of the second pull-up transistor PU-2, the second pull-down transistor PD-2, and the second pass-gate transistor PG-2 is shown as a second interconnect structure SD-2. As described below, the first interconnect structure SD-1 and the second interconnect structure SD-2 do not necessarily need to be a separate conductive layer. They can also be implemented by the material layer where the source / drain regions of the transistors are located (for example, the source / drain layer described above).

[0047] The gate electrodes of the first pull-up transistor PU-1 and the first pull-down transistor PD-1 can be electrically connected to each other via a third interconnect structure V-1, and the third interconnect structure V-1 can be electrically connected to the second interconnect structure SD-2 (for example, by direct contact with each other) (equivalent to being commonly connected to node / Q). Similarly, the gate electrodes of the second pull-up transistor PU-2 and the second pull-down transistor PD-2 can be electrically connected to each other via a fourth interconnect structure V-2, and the fourth interconnect structure V-2 can be electrically connected to the first interconnect structure SD-1 (for example, by direct contact with each other) (equivalent to being commonly connected to node Q). As described below, the third interconnect structure V-1 and the fourth interconnect structure V-2 can be implemented by a material layer for the active region of the transistor (for example, the channel layer described above).

[0048] The source / drain regions (eg, source regions) on the lower sides of the first pull-up transistor PU-1 and the second pull-up transistor PU-2 can be disposed on the substrate and receive the power supply voltage V through contact plugs to the substrate. DD The source / drain regions (e.g., source regions) on the upper sides of the first pull-down transistor PD-1 and the second pull-down transistor PD-2 can receive the ground voltage GND through corresponding contact plugs. The gate electrodes of the first pass-gate transistor PG-1 and the second pass-gate transistor PG-2 can be electrically connected to the word lines (e.g., Figure 1 The word line WL shown in FIG.

[0049] like Figure 3(a) and 3(b)As shown, based on the first node and the second node, the six constituent transistors can be divided into two groups: a first pull-up transistor PU-1, a first pull-down transistor PD-1, and a first pass-gate transistor PG-1 commonly connected to the first node (see FIG3(a)), and a second pull-up transistor PU-2, a second pull-down transistor PD-2, and a second pass-gate transistor PG-2 commonly connected to the second node (see FIG3(b)). The two groups can have the same or symmetrical layout (the layout shown in FIG3(a) can be rotated 180° to obtain the layout shown in FIG3(b)). However, the present disclosure is not limited to this. The two groups can have different or asymmetrical layouts.

[0050] The two layers can be fabricated separately. For example, a p-type transistor can be fabricated on the lower layer first, followed by an n-type transistor on the upper layer. Specifically, an active material layer for the p-type transistor (e.g., the source / drain layer and channel layer described above) can be provided on the substrate, and the active area of ​​the p-type transistor can be defined therein. Furthermore, the active material layer can be used to define the pattern of the interconnect structure. Subsequently, the p-type transistor can be fabricated according to the vertical transistor fabrication process. The gaps in the lower layer can then be filled with insulating material. An active material layer for the n-type transistor (e.g., the source / drain layer and channel layer described above) can be provided at least partially above the region where the p-type transistor is located, and the active area of ​​the n-type transistor can be defined therein. Similarly, the active material layer can be used to define the pattern of the interconnect structure. The interconnect patterns defined twice have the necessary connections or contacts to achieve the electrical connection described above. Subsequently, the n-type transistor can be fabricated according to the vertical transistor fabrication process. Since the n-type transistor is fabricated above the region where the p-type transistor is located, the upper and lower layers at least partially overlap, thereby saving area. For example, the active regions of at least a portion of the transistors (particularly the first pull-up transistor and the first pull-down transistor, and / or the second pull-up transistor and the second pull-down transistor, whose source / drain regions need to be connected to each other) can overlap or even align in the vertical direction. However, this approach may make it difficult to form a single-crystal active region, especially a single-crystal channel region, in the upper layer, which is not conducive to further improving the performance of the SRAM cell.

[0051] According to other embodiments of the present disclosure, an active material layer for a p-type transistor and an active material layer for an n-type transistor may be sequentially arranged on a substrate. For example, the active material layer may be arranged by epitaxial growth, for example, a first source / drain layer, a channel layer, and a second source / drain layer for a p-type transistor and a first source / drain layer, a channel layer, and a second source / drain layer for an n-type transistor may be sequentially grown. Thus, the active material layer may be formed of a single-crystal semiconductor material. Single-crystal semiconductor materials contribute to high mobility.

[0052] According to embodiments of the present disclosure, for example, through a self-aligned process as described below, the gate length can be determined by the thickness of the channel layer itself, and the channel layer can be formed by epitaxial growth so that its thickness can be well controlled. Therefore, the gate length can be well controlled, for example, the gate length can be controlled to be relatively small (e.g., less than about 10 nm).

[0053] The active area of ​​the n-type transistor and the interconnection pattern of the upper layer can be defined in the active material layer for the n-type transistor from top to bottom, and the active area of ​​the p-type transistor and the interconnection pattern of the lower layer can be defined in the active material layer for the p-type transistor. In order to achieve vertical overlap between transistors in order to save area, the same mask pattern or mask layer can be used to define the active patterns of the upper and lower layers. According to an embodiment of the present disclosure, the first interconnection structure and the second interconnection structure can be defined by the source / drain layer between the upper and lower layers (for example, the second source / drain layer for the p-type transistor and the first source / drain layer for the n-type transistor), and the third interconnection structure and the fourth interconnection structure can be defined by the channel layer in the upper and lower layers. Then, the p-type transistor can be made in the lower layer. When the p-type transistor is made, the placeholder layer can be used to cover the active area of ​​the n-type transistor in the upper layer. When the p-type transistor is made, the isolation layer can be used to cover the lower layer, and then the n-type transistor can be made in the upper layer.

[0054] To facilitate the gate replacement process, the placeholder layer for the gate stack (also called a "sacrificial gate") can be made of a different material than the placeholder layers at other locations. This way, the sacrificial gate can be removed later and the gate stack can be formed in the space left by the removal of the sacrificial gate.

[0055] In order to facilitate the formation of such a sacrificial gate or placeholder layer, when defining the active area, it can be done separately for the channel layer and the source / drain layer. For example, the active area can be defined in the channel layer first (for example, the channel layer is separated into the channel area for each transistor and the part for defining the third and fourth interconnect structures, which can be in the form of nanowires, for example). Then, a placeholder layer (sacrificial gate) can be formed. Since the source / drain layers on the upper and lower sides of the channel layer still extend continuously at this time, the placeholder layer (sacrificial gate) formed in this way can be self-aligned to the channel layer, so that a self-aligned gate stack can be formed subsequently by replacing the gate process. The pattern of the placeholder layer (sacrificial gate) can also be further adjusted to achieve the electrical connection and / or electrical isolation required for the gate stack subsequently formed by replacing it. Then, the active area can be defined in the source / drain layer, and a placeholder layer can also be formed.

[0056] According to an embodiment, the first interconnect structure and the second interconnect structure can be realized by a source / drain layer between the two layers. Therefore, when patterning the active area, the second source / drain layer for the p-type transistor and the first source / drain layer for the n-type transistor can be patterned according to the layout of the first interconnect structure and the second interconnect structure. In view of this, the mask pattern used to define the active area may include a portion for defining the transistor active area (e.g., a circular portion), a portion for defining the third and fourth interconnect structures (e.g., a circular portion), and a portion for defining the first and second interconnect structures (the connection line between the above-mentioned circular portions). As described below, such a mask pattern may be in the form of a grid.

[0057] Figures 4(a) to 7(b) Schematically shows an exploded perspective view of an SRAM cell according to other embodiments of the present disclosure. Figure 2 、 3(a) The main difference between the SRAM cell described in 3(b) and the SRAM cell described in 3(b) is that the number of unit transistors constituting the pull-up transistor or pull-down transistor is different to achieve different values ​​of α and β. The unit transistors constituting the same pull-up transistor or pull-down transistor can have the same connection method, and their gate electrodes can be connected together. The following will focus on the differences from the above embodiment.

[0058] like Figure 4(a) and 4(b) As shown, in this embodiment, the first pull-up transistor PU-1 and the second pull-up transistor PU-2 can each include two unit transistors (β=1, α=2). To save area, the four (unit) transistors in each of the upper and lower layers can be aligned in the vertical direction.

[0059] like Figure 5(a) and 5(b) As shown, in this embodiment, the first pull-down transistor PD-1 and the second pull-down transistor PD-2 can each include two unit transistors (β=2, α=1). To save area, the first pull-up transistor PU-1 can be aligned with one unit transistor of the first pull-down transistor PD-1 in the vertical direction, and the second pull-up transistor PU-2 can be aligned with one unit transistor of the second pull-down transistor PD-2 in the vertical direction.

[0060] like Figure 6(a) and 6(b)As shown, in this embodiment, the first pull-up transistor PU-1 and the second pull-up transistor PU-2 can each include two unit transistors, and the first pull-down transistor PD-1 and the second pull-down transistor PD-2 can each include two unit transistors (β=2, α=2). The two unit transistors of the first pull-up transistor PU-1 and the first pull-down transistor PD-1 can be in a vertical direction, and the two unit transistors of the second pull-up transistor PU-2 and the second pull-down transistor PD-2 can be in a vertical direction.

[0061] like Figure 7(a) and 7(b) As shown, in this embodiment, the first pull-up transistor PU-1 and the second pull-up transistor PU-2 can each include three unit transistors, and the first pull-down transistor PD-1 and the second pull-down transistor PD-2 can each include two unit transistors (β=2, α=3). To save area, the six (unit) transistors in each of the upper and lower layers can be aligned in the vertical direction.

[0062] In the above example, all unit transistors in one layer (in the above example, the lower layer) of the upper and lower layers are aligned in the vertical direction with the corresponding unit transistors in the other layer. However, the present disclosure is not limited to this. For example, only some unit transistors in the layer, rather than all unit transistors, may be aligned in the vertical direction with the corresponding transistors in the other layer.

[0063] Figures 8 to 52(c) Some stages in the process of manufacturing an SRAM cell according to an embodiment of the present disclosure are schematically shown.

[0064] In the following description, materials for various layers are listed. However, these are merely examples. The material for each layer is primarily determined based on the function of that layer (e.g., semiconductor material to provide the active region, dielectric material to provide gap filling and electrical isolation, etc.) and the desired etch selectivity. In the description, it may not be explicitly stated that a material of a particular layer has an etch selectivity relative to the materials of other layers, or only a "desired etch selectivity" may be mentioned. This "desired etch selectivity" can be at least partially determined based on the relevant etching process.

[0065] like Figure 8 As shown, a substrate 1001 is provided. The substrate 1001 can be a substrate of various forms. The substrate 1001 can include a semiconductor material, for example, but not limited to, a bulk semiconductor material such as bulk Si, a semiconductor on insulator (SOI), a compound semiconductor material such as SiGe, etc. In the following description, for convenience of explanation, a bulk Si substrate is used as an example. In the substrate 1001, a well region (not shown) can be formed as needed, for example, by implanting impurities. In the example where a p-type transistor is provided in the lower layer, the implanted impurities can be n-type impurities.

[0066] A contact layer 1003 may be formed on the substrate 1001 to facilitate connection of the source / drain regions of the transistor (e.g., a p-type pull-up transistor) in the lower layer of the SRAM cell on the side close to the substrate. The contact layer 1003 may be formed by implanting impurities into the upper portion of the substrate 1001. In the example where the p-type transistor is provided in the lower layer, the implanted impurities may be p-type impurities such as B or In, and the concentration may be, for example, approximately 1E18-1E21 cm -3 Of course, the contact layer 1003 may be further formed on the substrate 1001 by epitaxial growth.

[0067] An isolation auxiliary layer 1005 can be formed on the contact layer 1003, for example, by epitaxial growth. This isolation auxiliary layer 1005 can help achieve electrical isolation between the third and fourth interconnect structures and the contact layer at desired locations, as described in further detail below. Furthermore, to ensure electrical connection between the contact layer 1003 and the source / drain regions of the p-type transistor formed thereon, the isolation auxiliary layer 1005 can be given p-type conductivity by in-situ doping during growth or by post-growth impurity implantation.

[0068] An active material layer may be provided on the isolation auxiliary layer 1005. For example, a first source / drain layer 1007, a channel layer 1009, and a second source / drain layer 1011 for a p-type transistor, and a first source / drain layer 1013, a channel layer 1015, and a second source / drain layer 1017 for an n-type transistor may be sequentially formed by epitaxial growth. These layers may have the desired conductivity by in-situ doping during growth or by implanting impurities after growth.

[0069] Adjacent layers of the semiconductor material layers formed on substrate 1001 may have etching selectivity relative to each other. Except for the second source / drain layer 1011 for the p-type transistor and the first source / drain layer 1013 for the n-type transistor, these layers may have no etching selectivity or low etching selectivity relative to each other because, in subsequent processing, they are treated as almost the same layer, except for being doped with different conductivity types to serve as the source / drain regions of the p-type transistor and the n-type transistor, respectively. Furthermore, for the p-type transistor, the first source / drain layer 1007 and the second source / drain layer 1011 may comprise the same material. Similarly, for the n-type transistor, the first source / drain layer 1013 and the second source / drain layer 1017 may comprise the same material.

[0070] In one example, these semiconductor material layers may include alternating stacks of Si and SiGe. For example, in the case where the substrate 1001 (including the contact layer 1003 formed therein) is Si, the isolation auxiliary layer 1005 may include SiGe with a thickness of about 5nm-20nm. For a p-type transistor, the first source / drain layer 1007 may include Si with a thickness of about 20-50nm; the channel layer 1009 may include SiGe (the atomic percentage of Ge is, for example, about 10-40%) with a thickness of about 10-100nm; and the second source / drain layer 1011 may include Si with a thickness of about 10-30nm. The first source / drain layer 1007 and the second source / drain layer 1011 may be p-type doped, with a doping concentration of, for example, about 1E19-1E21 cm -3 Similarly, for an n-type transistor, the first source / drain layer 1013 may include Si with a thickness of approximately 10-30 nm; the channel layer 1015 may include SiGe (the atomic percentage of Ge is, for example, approximately 10-70%) with a thickness of approximately 10-100 nm; and the second source / drain layer 1017 may include Si with a thickness of approximately 20-50 nm. The first source / drain layer 1013 and the second source / drain layer 1017 may be n-type doped, with a doping concentration of, for example, approximately 1E19-1E21 cm -3 .

[0071] In addition, the channel layer can also be doped to adjust the threshold voltage of the transistor (V t For a p-type transistor, the channel layer 1009 may be n-doped, and the doping concentration may be about 1E17-2E18 cm -3 For n-type transistors, the channel layer 1015 may be p-type doped, with a doping concentration of about 1E17-2E18 cm -3 For a tunneling FET, the channel layer can be doped to the same conductivity type as the corresponding first source / drain layer or second source / drain layer. Of course, the channel layer may also be undoped intentionally.

[0072] A hard mask can be provided on the active material layer to subsequently define the active area and the interconnect pattern. For example, an aluminum oxide (Al2O3) layer 1019 (or a silicon carbide layer) with a thickness of about 2-10 nm, a nitride (e.g., silicon nitride) layer 1021 with a thickness of about 10-100 nm, and an oxide (e.g., silicon oxide) layer 1023 with a thickness of about 10-100 nm can be formed in sequence by deposition. The hard mask is provided to provide appropriate pattern definition, etching stop, etc. in subsequent processes. The number of hard mask layers and the materials of each layer can vary according to the process. In this example, the layer configuration of the hard mask can be such that the hard mask (at least one layer thereof) can be retained at least until the transistor fabrication is completed.

[0073] As shown in FIG9( a ), a photoresist 1025 can be formed on the hard mask. The photoresist 1025 can be formed into a specific pattern through exposure and development. Here, the pattern can include a portion defining the transistor active region (circular in the case of nanowires, or square or rectangular in the case of nanosheets), portions defining the third and fourth interconnect structures (e.g., circular or square), and portions defining the first and second interconnect structures (e.g., the lines connecting the aforementioned portions). The following description uses the circular portion as an example.

[0074] The pattern can be divided into two columns corresponding to the two groups mentioned above. In the example of Figure 9(a), the lower column corresponds to the first pull-up transistor PU-1, the first pull-down transistor PD-1, and the first pass-gate transistor PG-1 connected to the first node, while the upper column corresponds to the second pull-up transistor PU-2, the second pull-down transistor PD-2, and the second pass-gate transistor PG-2 connected to the second node.

[0075] In the case of β=2 (α=1, 2, or 3), one column may have 5 circular portions, and another column may have 6 circular portions. More specifically, the following may include, from left to right: a circular portion for defining the third interconnect structure V-1, two circular portions for defining two unit transistors (β=2) of the first pull-down transistor PD-1, a circular portion for defining the first pass-gate transistor PG-1, a circular portion for defining the contact plug WL-1, and a circular portion for defining the applied power supply voltage V DD A circular portion of the contact plug. The circular portion used to define the pull-down transistor and the pass-gate transistor can both be used to define the pull-down transistor. In this example, it is shown that a circular portion used to define the first pull-down transistor PU-1 (the one on the left in the figure, α=1) is also used to define the first pull-up transistor PU-1. Similarly, the upper column can include, from right to left: a circular portion for defining the fourth interconnect structure V-2, two circular portions for defining the two unit transistors (β=2) of the second pull-down transistor PD-2, a circular portion for defining the second pass-gate transistor PG-2, and a circular portion for defining the contact plug WL-2. The circular portion used to define the pull-down transistor and the pass-gate transistor can both be used to define the pull-down transistor. In this example, it is shown that a circular portion used to define the second pull-down transistor PU-2 (the one on the right in the figure, α=1) is also used to define the second pull-up transistor PU-2.

[0076] These circular portions are connected by linear portions. These linear portions can define first and second interconnect structures. More specifically, the lower and right sides of the closed quadrilateral in the figure can define the first interconnect structure SD-1, and the upper and left sides can define the second interconnect structure SD-2.

[0077] The line width (eg, diameter) of the circular portion may be greater than the line width of the linear portion. The intervals between the circular portions may be substantially the same, but the present disclosure is not limited thereto.

[0078] The two columns may extend parallel to each other along a first direction (horizontal in the figure), and the corresponding circular portions in the two columns may be aligned in a second direction (vertical in the figure) that intersects, for example, is perpendicular to, the first direction. However, the present disclosure is not limited thereto. For example, the two columns may not extend parallel to each other. Furthermore, the circular portions in the two columns do not necessarily need to be aligned in the second direction, but may be offset.

[0079] Here, the mask pattern is also combined with a pattern for defining the applied power supply voltage V DD However, the present disclosure is not limited thereto. The contact plug may be formed in another manner. In this case, the mask pattern may be substantially quadrilateral (in this example, rectangular).

[0080] In addition, portions for defining contact plugs WL-1 and WL-2 are incorporated into the mask pattern. This facilitates forming contact plugs that are self-aligned with the gate stack of the through-gate transistor. However, the present disclosure is not limited thereto. For example, contact plugs to the gate stack of the through-gate transistor can be formed separately. In this case, one circular portion can be reduced in each of the two columns.

[0081] In the example of FIG9(a), the intersecting linear portions can form a substantially right angle, thereby forming a substantially rectangular shape. However, the present disclosure is not limited thereto. For example, as shown in FIG9(b), the intersecting linear portions can form other angles, such as approximately 60° or 120°. This can further save area while maintaining the spacing between the circular portions.

[0082] In addition, when β=1 (α=1 or 2), one column can have 4 circular sections and the other column can have 5 circular sections (relative to the above example, each column has one less circular section because each pull-down transistor only requires a single unit transistor, while each pull-down transistor in the above example requires two unit transistors), as shown in Figure 9(c). Similarly, although the intersecting linear sections in the example of Figure 9(c) can form a substantially right angle, they can also form other angles, such as an angle of approximately 60° or 120°, as shown in Figure 9(d).

[0083] In the following description, the pattern shown in FIG9(a) is mainly described as an example. When necessary, the pattern shown in FIG9(c) will be mentioned.

[0084] In addition, Figure 9(a) and 9(c)1 and 2 show positions where the following cross-sectional views are taken, ie, line AA′, line BB′, line CC′, and line II′.

[0085] The pattern of the photoresist 1025 can be transferred to the hard mask and then to the underlying active material layer.

[0086] like Figure 10(a) 、 10(b) As shown in Figures 10(c) and 10(c) (a top view, a cross-sectional view along line AA′, and a cross-sectional view along line BB′, respectively), the hard mask (including the oxide layer 1023, the nitride layer 1021, the aluminum oxide layer 1019), the second source / drain layer 1017 for the n-type transistor, and the channel layer 1015 can be sequentially etched using, for example, reactive ion etching (RIE) using the photoresist 1025 as an etching mask. RIE can be performed in a direction substantially perpendicular to the substrate surface and can stop at the first source / drain layer 1013 for the n-type transistor. In this example, the patterning of the active material layer for the n-type transistor does not proceed to the first source / drain layer 1013. This is primarily for the following reasons. On the one hand, in this example, the first source / drain layer 1013 for the n-type transistor can maintain substantially the same pattern as the second source / drain layer 1011 for the p-type transistor, thereby allowing for subsequent patterning together with the second source / drain layer 1011 for the p-type transistor. On the other hand, the second source / drain layer 1017 will be separated later. If the first source / drain layer 1013 is also etched here, the first source / drain layer 1013 will also be separated into separate parts, which is not conducive to forming the first and second interconnect structures. Afterwards, the photoresist 1025 can be removed.

[0087] In this way, the positions of the active regions of the n-type transistors and the third and fourth interconnect structures are basically defined in the upper layer (the circular portions in the top view of FIG10( a)), but these circular portions are currently connected together by linear portions, as shown in the cross-sectional view of FIG10( b). These circular portions can be separated to define the active regions of the n-type transistors and the third and fourth interconnect structures separately.

[0088] For example, Figure 11(a) 、 11(b) As shown in Figures 11(c) and 11(c) (cross-sectional views along lines AA′, BB′, and CC′, respectively), due to the etching selectivity of the channel layer 1015 relative to the source / drain layers 1013 and 1017, the channel layer 1015 can be further selectively etched. The selective etching can use an atomic layer etching (ALE) method to perform precise and controllable etching. The degree of etching can be selected so that the linear portion can be removed, while a portion of the circular portion (e.g., the center portion) can be left. Thus, the channel layer 1015 can be divided into a number of separate columnar portions corresponding to the circular portions in the mask pattern, i.e., nanowires.

[0089] In this example, anisotropy is not considered and it is assumed that the selective etching of the channel layer 1015 is substantially isotropic. Therefore, in a top view, the channel layer 1015 after etching still has a substantially circular shape and is substantially (centrally) aligned with the circular portion of the mask pattern in the vertical direction.

[0090] At the locations where the contact plugs WL-1 and WL-2 are located, the nanowires in the channel layer 1015 are unnecessary because the nanowires may connect the contact plugs WL-1 and WL-2 to the source / drain layer below. Therefore, the channel layer nanowires at the locations where the contact plugs WL-1 and WL-2 are located can be removed. For example, Figure 12(a) 、 12(b) As shown in Figures 12(c) (a top view, a cross-sectional view along line AA', and a cross-sectional view along line CC', respectively), a photoresist 1027 can be formed on the above structure and patterned to expose the channel layer nanowires to be removed (the leftmost nanowire in the upper column and the second nanowire from the right in the lower column in the top view of Figure 12(a)), while covering the remaining channel layer nanowires. The photoresist 1027 can be used as an etching mask to selectively etch the exposed channel layer nanowires to remove them. Thereafter, the photoresist 1027 can be removed.

[0091] A gate stack will be formed later in the recess formed by each nanowire in the channel layer 1015 relative to the periphery of the hard mask. To prevent subsequent processing from affecting the channel layer 1015 or leaving unnecessary materials in the recess, thereby affecting the formation of the subsequent gate stack, a placeholder layer can be formed in the recess to occupy the space of the gate stack (therefore, this material layer can be called a "sacrificial gate"). For example, Figure 13(a) 、 13(b) As shown in Figures 13(c) and 13(c) (cross-sectional views taken along lines AA', BB', and CC', respectively), a sacrificial gate 1029 can be formed by depositing a material having a desired etch selectivity (e.g., relative to a hard mask, a placeholder layer described below, etc.) such as nitride oxide (e.g., silicon oxynitride) on the above structure, and then etching back the deposited material, such as by RIE. RIE can be performed in a direction substantially perpendicular to the substrate surface, so that the sacrificial gate 1029 can remain only within the recess of the channel layer nanowire relative to the outer periphery of the hard mask. In this case, the sacrificial gate 1029 can substantially fill the recess.

[0092] Similar to the treatment of the channel layer 1015, the second source / drain layer 1017 can be further selectively etched to separate it into a number of separated columnar portions, i.e., nanowires, corresponding to the circular portions of the mask pattern, as shown in FIG. Figure 14(a) 、 14(b)and 14(c) (cross-sectional views taken along line AA′, line BB′, and line CC′, respectively). Except for the different etching recipes, the selective etching of the second source / drain layer 1017 can be substantially the same as the selective etching of the channel layer 1015, and will not be described in detail here. Furthermore, in this example, the first source / drain layer 1013 having the same material as the second source / drain layer 1017 can also be affected by the etching recipe, thereby forming an undercut, and in particular, a gap can be formed under the sacrificial gate 1029. This helps to reduce the capacitance between the gate and the source / drain.

[0093] Similarly, a placeholder layer can be formed in the gaps below the hard mask to prevent subsequent processing from affecting the source / drain layer (for example, to prevent gate stacks from being formed in these gaps in a subsequent replacement gate process). Figure 15(a) 、 15(b) As shown in Figures 15(c) and 15(c) (cross-sectional views along lines AA′, BB′, and CC′, respectively), a placeholder layer 1031 can be formed by depositing a material such as a nitride having a desired etching selectivity (e.g., relative to a hard mask, sacrificial gate 1029, etc.) on the above structure by, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD), and then etching back the deposited material by, for example, RIE. Before etching back, the deposited dielectric can be planarized by, for example, chemical mechanical polishing (CMP) (which can stop at the hard mask). RIE can be performed in a direction substantially perpendicular to the substrate surface, so that the placeholder layer can remain only under the hard mask, and the peripheral sidewalls can remain substantially coplanar with the peripheral sidewalls of the hard mask. Figure 15(a) and 15(c) As shown, the placeholder layer 1031 can be embedded in the undercut below the sacrificial gate 1029. Due to the etch selectivity, in the subsequent process of removing the sacrificial gate 1029 and replacing it with a gate stack, the placeholder layer 1031 can be left, thereby reducing the overlap between the gate stack and the source / drain layer and thus reducing the capacitance between them.

[0094] The active region of the p-type transistor and the locations of the third and fourth interconnect structures may be defined in a similar manner in the lower layer.

[0095] For example, Figure 16(a) 、 16(b)As shown in Figures 16(c) and 16(c) (cross-sectional views taken along lines AA′, BB′, and CC′, respectively), a hard mask can be used as an etching mask to sequentially etch the first source / drain layer 1013 for the n-type transistor, the second source / drain layer 1011 for the p-type transistor, the channel layer 1009, and the first source / drain layer 1007, for example, by RIE. RIE can be performed in a direction substantially perpendicular to the substrate surface. Thus, the pattern of the hard mask can be transferred to these layers. In this example, RIE is performed into the first source / drain layer 1007, but not to the bottom surface of the first source / drain layer 1007. This is because, in this example, the isolation auxiliary layer 1005 can include the same material as the channel layer 1009, such as SiGe. Temporarily keeping the first source / drain layer 1007 covering the isolation auxiliary layer 1005 can help prevent the isolation auxiliary layer 1005 from being affected when processing the channel layer 1009.

[0096] like Figure 17(a) 、 17(b) As shown in FIG17 (c) (cross-sectional views along lines AA′, BB′, and CC′, respectively), the channel layer 1009 may be further selectively etched, such as ALE, to separate it into a number of separate columnar portions, i.e., nanowires, corresponding to the central portion of the mask pattern. Figure 11(a) 、 11(b) and 11(c) description.

[0097] Figure 18(a) 、 18(b) and 18(c) (cross-sectional views along line AA′, line BB′, and line CC′, respectively) show the case where β=1 (α=1 or 2). As described above in conjunction with FIG9(c), in this case, one column in the mask pattern can have 4 circular portions and the other column can have 5 circular portions. Accordingly, as shown in FIG18(a), in the cross-sectional view at line AA′, 5 nanowires can be present in the lower channel layer 1009 and 4 nanowires can be present in the upper channel layer 1015 (one nanowire corresponding to the contact plug WL-1, i.e., the second nanowire from the right is removed). In addition, as shown in FIG18(c), in the cross-sectional view at line CC′, 4 nanowires can be present in the lower channel layer 1009 and 3 nanowires can be present in the upper channel layer 1015 (one nanowire corresponding to the contact plug WL-2, i.e., the nanowire on the far left is removed).

[0098] As described above, for the case of β = 2 shown in Figures 17(a), 17(b), and 17(c), different configurations of α, such as 1, 2, or 3, may exist. Different configurations of α correspond to different numbers of channel layer nanowires in the lower layer. The number of channel layer nanowires in the lower layer can be adjusted based on different configurations of α.

[0099] For example, when α=1, a single unit transistor can be used to form a p-type pull-up transistor. Therefore, in the lower layer, one column (the lower column in the top view) can have three channel layer nanowires (corresponding to the third interconnect structure V-1, the first pull-up transistor PU-1, and the channel layer for applying the power supply voltage V DD The other column (the upper column in the top view) may have two channel layer nanowires (corresponding to the fourth interconnect structure V-2 and the second pull-up transistor PU-2, respectively). Figure 19(a) 、 19(b) , 19(c) and 19(d) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, and a cross-sectional view along line CC′, respectively), a photoresist 1033 can be formed on the above structure and patterned to expose the channel layer nanowires that need to be removed (the three nanowires on the left side of the upper column and the three nanowires in the middle of the lower column in the top view of FIG. 19(a)), while covering the remaining channel layer nanowires. The photoresist 1033 can be used as an etching mask to selectively etch the exposed channel layer nanowires to remove them. Thereafter, the photoresist 1033 can be removed.

[0100] Similarly, when α=2, two unit transistors can be used to form a p-type pull-up transistor. Therefore, in the lower layer, one column (the lower column in the top view) can have four channel layer nanowires (corresponding to the third interconnect structure V-1, the two unit transistors of the first pull-up transistor PU-1, and the unit transistor for applying the power supply voltage V DD The other column (the upper column in the top view) may have three channel layer nanowires (corresponding to the fourth interconnect structure V-2 and the two unit transistors of the second pull-up transistor PU-2, respectively). Figure 20(a) 、 20(b) As shown in Figures 20(c), 20(d) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, and a cross-sectional view along line CC′, respectively), the channel layer nanowires can be selectively removed using the photoresist 1033′ that exposes two channel layer nanowires in the upper and lower columns in the top view. The photoresist 1033′ can then be removed.

[0101] Similarly, when α=3, three unit transistors can be used to form a p-type pull-up transistor. Therefore, in the lower layer, one column (the lower column in the top view) can have five channel layer nanowires (corresponding to the third interconnect structure V-1, the three unit transistors of the first pull-up transistor PU-1, and the unit transistor for applying the power supply voltage V DD The other column (the upper column in the top view) may have four channel layer nanowires (corresponding to the fourth interconnect structure V-2 and the three unit transistors of the second pull-up transistor PU-2, respectively). Figure 21(a)、 21(b) , 21(c) and 21(d) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, and a cross-sectional view along line CC′, respectively), the channel layer nanowires can be selectively removed using the photoresist 1033″ that exposes one channel layer nanowire in each of the upper and lower columns in the top view. Thereafter, the photoresist 1033″ can be removed.

[0102] In the above examples, the unit transistors constituting the same pull-up or pull-down transistor can be defined by directly adjacent circular portions in the mask pattern. However, the present disclosure is not limited thereto. In particular, for the pull-up transistor in the lower layer, its unit transistors can be defined by circular portions in the mask pattern that are not directly adjacent. This can be achieved by adjusting the pattern of the photoresist 1033' or 1033".

[0103] The following description is made by taking the case where β = 2 and α = 1 as an example. It should be clear to those skilled in the art that the technology described below can be applied to different configurations of α and β.

[0104] Similar to the upper layer, a sacrificial gate can also be formed around the channel layer 1009 (which has been formed into a nanowire). In addition, considering the electrical isolation between the gate stacks of the two p-type transistors in the lower layer and the gate stack and the power supply voltage V DD To electrically isolate the contact plugs, a placeholder layer may be formed first. Figure 22(a) 、 22(b) As shown in Figures 22(c) and 22(d) (cross-sectional views taken along lines AA′, BB′, CC′, and II′, respectively), a placeholder layer 1035 may be formed in the recess formed by each nanowire in the channel layer 1009 relative to the periphery of the hard mask. For example, the placeholder layer 1035 may include a material having a desired etch selectivity (e.g., relative to the sacrificial gate 1029, the placeholder layer 1031, etc.), such as an oxide or a low-k dielectric. The placeholder layer 1035 may be formed by deposition followed by etching back, similar to the process of forming the sacrificial gate 1029 or the placeholder layer 1031. In the case where the placeholder layer 1035 is an oxide, the oxide layer 1023 in the hard mask may be removed during the etching back process.

[0105] Next, the placeholder layer 1035 may be patterned to leave space for forming a gate stack of a p-type transistor. Figure 23(a) 、 23(b), 23(c), 23(d), and 23(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively), a photoresist 1037 can be formed on the above structure and patterned to expose the area where the gate stack of the p-type transistor is to be formed. Specifically, in this example, as shown in the top view of FIG. 23(a), in the lower row, a gate stack can be formed around the two channel layer nanowires on the left (corresponding to the third interconnect structure V-1 and the first pull-up transistor PU-1, respectively); in the upper row, a gate stack can be formed around the two channel layer nanowires on the right (corresponding to the fourth interconnect structure V-2 and the second pull-up transistor PU-2, respectively). In addition, in this example, the photoresist 1037 also exposes the area where the rightmost channel layer nanowire is located. This is so that in subsequent processes, the channel layer nanowires can be silicided simultaneously at the locations of the third and fourth interconnect structures and the contact plugs for applying the power supply voltage VDD. Of course, the rightmost channel layer nanowire may not be exposed and may be processed separately later. The placeholder layer 1035 may be selectively etched using the photoresist 1037 as an etching mask.

[0106] Figure 24(a) 、 24(b) , 24(c), 24(d) and 24(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively) show an example of patterning the placeholder layer 1035 when β=2 and α=2. In this example, except that the pattern of the photoresist 1037′ is different from the pattern of the photoresist 1037, the rest of the processes are the same. Specifically, in this case, as shown in the top view of FIG. 24(a), in the lower column, a gate stack can be formed around the three channel layer nanowires on the left (corresponding to the two unit transistors of the third interconnect structure V-1 and the first pull-up transistor PU-1, respectively); in the upper column, a gate stack can be formed around the three channel layer nanowires on the right (corresponding to the two unit transistors of the fourth interconnect structure V-2 and the second pull-up transistor PU-2, respectively).

[0107] Figure 25(a) 、 25(b), 25(c), 25(d) and 25(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively) show an example of patterning the placeholder layer 1035 when β=2 and α=3. In this example, except that the pattern of the photoresist 1037″ is different from the pattern of the photoresist 1037, the rest of the processes are the same. Specifically, in this case, as shown in the top view of FIG. 25(a), in the lower column, a gate stack can be formed around the four channel layer nanowires on the left (corresponding to the three unit transistors of the third interconnect structure V-1 and the first pull-up transistor PU-1, respectively); in the upper column, a gate stack can be formed around the four channel layer nanowires on the right (corresponding to the three unit transistors of the fourth interconnect structure V-2 and the second pull-up transistor PU-2, respectively).

[0108] Figure 26(a) 、 26(b) , 26(c), 26(d) and 26(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively) show an example of patterning the placeholder layer 1035 when β=1 and α=1. In this example, except that the pattern of the photoresist 1037′″ is different from the pattern of the photoresist 1037, the rest of the processes are the same. Specifically, in this case, as shown in the top view of FIG. 26(a), in the lower column, a gate stack can be formed around the two channel layer nanowires on the left (corresponding to the third interconnect structure V-1 and the first pull-up transistor PU-1, respectively); in the upper column, a gate stack can be formed around the two channel layer nanowires on the right (corresponding to the fourth interconnect structure V-2 and the second pull-up transistor PU-2, respectively).

[0109] Figure 27(a) 、 27(b) , 27(c), 27(d) and 27(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively) show an example of patterning the placeholder layer 1035 when β=1 and α=2. In this example, except that the pattern of the photoresist 1037″″ is different from the pattern of the photoresist 1037, the rest of the processes are the same. Specifically, in this case, as shown in the top view of FIG. 27(a), in the lower column, a gate stack can be formed around the three channel layer nanowires on the left (corresponding to the two unit transistors of the third interconnect structure V-1 and the first pull-up transistor PU-1, respectively); in the upper column, a gate stack can be formed around the three channel layer nanowires on the right (corresponding to the two unit transistors of the fourth interconnect structure V-2 and the second pull-up transistor PU-2, respectively).

[0110] The following description still takes the case where β=2 and α=1 as an example. It should be clear to those skilled in the art that the technology described below can be applied to different configurations of α and β.

[0111] Then, a sacrificial gate may be formed around the channel layer 1009 (which has been formed into nanowires). Figure 28(a) 、 28(b) As shown in Figures 28(c) and 28(d) (cross-sectional views taken along lines AA′, BB′, CC′, and II′, respectively), a sacrificial gate 1039 can be formed in a recess formed in each nanowire in the channel layer 1009 relative to the periphery of the hard mask (wherein a placeholder layer 1035 has been partially formed). The sacrificial gate 1039 can be formed by deposition followed by etching back, similar to the process for forming the sacrificial gate 1029. The sacrificial gate 1039 may include a material having a desired etch selectivity (for example, relative to the placeholder layers 1031 and 1035), such as the same nitride oxide as the sacrificial gate 1029.

[0112] In the above example, the placeholder layer 1035 is formed first, and then the sacrificial gate 1039 is formed. However, the present disclosure is not limited thereto. For example, the sacrificial gate 1039 may be formed first, and then the placeholder layer 1035 may be formed.

[0113] In addition, in this example, the lower sacrificial gate 1039 is patterned before the replacement gate process is performed. This is because it is not easy to pattern the lower gate stack after the replacement gate process. As for the upper sacrificial gate 1029, patterning can be performed after the replacement gate process to achieve proper electrical isolation. Of course, similar to the lower sacrificial gate 1039, the upper sacrificial gate 1029 can also be patterned before the replacement gate process. In this case, similar to the process of forming the lower sacrificial gate 1039, before forming the sacrificial gate 1029, a placeholder layer can be formed and patterned, and then the sacrificial gate 1029 can be formed.

[0114] Next, the lower source / drain layer can be separated similarly.

[0115] It should be noted that in this example, the first source / drain layer 1013 of the n-type transistor and the second source / drain layer 1011 of the p-type transistor do not need to be divided into separate parts for each transistor, because they can be used to form the first and second interconnect structures later.

[0116] The first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor may be patterned according to the layout of the first and second interconnect structures. Figure 29(a) 、 29(b), 29(c), 29(d) and 29(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively), a photoresist 1041 can be formed on the above structure. The photoresist 1041 can be patterned to expose the region to be isolated between the first interconnection structure and the second interconnection structure and the region between the first and second interconnection structures and the region for applying the power supply voltage V DD The areas that need to be isolated between the contact plugs are then separated by selective etching, such as ALE, using the photoresist 1041 as an etching mask to cut off the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor. Thus, in a top view, the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor can form two opposing L-shaped layers spaced apart from each other. The first source / drain layer 1007 for the p-type transistor may also be affected by the etching, thereby forming an undercut.

[0117] In the gap formed under the hard mask due to the above etching, a placeholder layer can be formed. Figure 30(a) and 30(b) As shown in FIG. 1 (a cross-sectional view taken along lines AA′ and CC′, respectively), a placeholder layer 1043 can be formed by, for example, deposition followed by etching back. The placeholder layer 1043 can include a material having a desired etch selectivity (e.g., relative to the sacrificial gates 1029 and 1039), such as an oxide or a low-k dielectric. The placeholder layer 1043 and the placeholder layer 1035 can include the same material.

[0118] In addition, in order to avoid affecting the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor in the following process of separating the first source / drain layer 1007 for the p-type transistor, a protective layer can be formed on the sidewalls of the above structure. Figure 31(a) 、 31(b) As shown in Figures 31(c) and 31(d) (cross-sectional views taken along lines AA′, BB′, CC′, and II′, respectively), a protective layer 1045 can be formed on the sidewalls of the above structure by a spacer formation process. The protective layer 1045 can include a material having a desired etching selectivity (for example, relative to the first source / drain layer 1007, etc.), such as a nitride. The spacer formation process can include forming a thin nitride layer on the above structure in a substantially conformal manner, for example, by anisotropically etching the deposited thin nitride layer by RIE along the vertical direction to remove its lateral extension portion and leave its vertical extension portion.

[0119] Afterwards, the first source / drain layer 1007 may be subjected to a separation process. This separation process may be the same as the above separation process. For example, a hard mask may be used as an etching mask to selectively etch the first source / drain layer 1007, such as RIE along the vertical direction. The RIE of the first source / drain layer 1007 may stop at the isolation auxiliary layer 1005. In this way, the pattern of the hard mask is transferred to the first source / drain layer 1007. Then, as shown in FIG. Figure 32(a) 、 32(b) As shown in Figures 32(c) and 32(d) (cross-sectional views along lines AA′, BB′, CC′, and II′, respectively), the first source / drain layer 1007 can be further selectively etched, such as by ALE, to separate it into a number of separated columnar portions corresponding to the circular portions of the mask pattern, i.e., nanowires. In order to ensure proper electrical isolation, it is desirable that the first source / drain layer 1007 is completely divided into a number of portions or nanowires separated from each other. Since the sidewalls of the first source / drain layer 1013 for n-type transistors and the second source / drain layer 1011 for p-type transistors, which are also SiGe, are surrounded by the protective layer 1045, they are substantially unaffected by the etching, thereby maintaining the patterns of the first and second interconnect structures.

[0120] At this point, the active area of ​​each transistor has been basically defined.

[0121] In addition, the isolation auxiliary layer 1005 can also be subjected to the same separation process to separate it into separate parts or nanowires. By separating the isolation auxiliary layer 1005 into parts corresponding to the circular parts of the mask pattern, the first source / drain layer 1007 can be separated from the underlying contact layer 1003 at the desired location (specifically, the location of the third and fourth interconnect structures). This helps to isolate the third and fourth interconnect structures (connected to the gate stack of the p-type transistor) from the contact layer 1003 (electrically contacting the source / drain region on the lower side of the p-type transistor). Undercuts may be formed in the contact layer 1003.

[0122] For example, Figure 33(a) 、 33(b), 33(c), 33(d) and 33(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively), a photoresist 1047 can be formed on the above structure. The photoresist 1047 can be patterned to expose the areas where the third and fourth interconnect structures are located (the leftmost circular portion below and the rightmost circular portion above in the top view of FIG. 33(a)). Then, the photoresist 1047 can be used as an etching mask to selectively etch the isolation auxiliary layer 1005 to remove the exposed portion thereof. Thus, the first source / drain layer 1007 can be separated from the contact layer 1003 where the third and fourth interconnect structures are located. The first source / drain layer 1007 and the contact layer 1003 (both Si in this example) can be further selectively etched to increase the gap between them (see Figure 35(a) 、 35(b) , 35(c) and 35(d)) to ensure good electrical isolation and reduce capacitance. Afterwards, the photoresist 1047 can be removed.

[0123] In this example, the isolation auxiliary layer 1005 is used to separate the first source / drain layer 1007 from the contact layer 1003. However, the present disclosure is not limited thereto. According to other embodiments of the present disclosure, the isolation auxiliary layer 1005 may not be provided. In this case, for example, Figure 34(a) 、 34(b) , 34(c), 34(d) and 34(e) (respectively a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′), it is possible to Figure 32(a) 、 32(b) , 32(c), and 32(d) (without the isolation auxiliary layer 1005). Photoresist 1047' can have the same pattern as photoresist 1047. Photoresist 1047' can then be used as an etching mask to selectively etch the first source / drain layer 1007 to remove the exposed portion thereof. Thus, the first source / drain layer 1007 is removed where the third and fourth interconnect structures are located. Thereafter, photoresist 1047' can be removed.

[0124] The following description will still be made by taking the case where the isolation auxiliary layer 1005 exists as an example.

[0125] At this point, the layout definition of the SRAM cell (including transistors and interconnect structures) has been basically completed. Next, a replacement gate process can be performed to complete the fabrication of the transistors, and interconnections between these transistors can be formed to complete the fabrication of the SRAM cell.

[0126] In order to facilitate the replacement gate process, a placeholder layer may be formed in the gap below the hard mask. Figure 35(a) 、 35(b) As shown in FIG35( c ), FIG35( c ), and FIG35( d ) (cross-sectional views taken along lines AA′, BB′, CC′, and II′, respectively), a placeholder layer 1049 may be formed by deposition followed by etching back. The placeholder layer 1049 may include a material having a desired etching selectivity (e.g., relative to the sacrificial gates 1029, 1039, etc.), such as an oxide or a low-k dielectric. Before forming the placeholder layer 1049, a silicide process may be performed. The placeholder layer 1049 may be helpful (e.g., in the subsequent reference to FIG35 ). Figure 36(a) 、 36(b) , 36(c) and 36(d)) to support the nanostructures and prevent the nanostructures from collapsing and sticking.

[0127] To enhance contact and / or reduce resistance, the source / drain layers may be silicided.

[0128] For example, Figure 36(a) 、 36(b) As shown in Figures 36(c), 36(d) (cross-sectional views taken along lines AA′, BB′, CC′, and II′, respectively), the placeholder layer 1031 (nitride) and the placeholder layers 1035, 1043, and 1049 (oxide) can be removed relative to the sacrificial gates 1029 and 1039 (and the aluminum oxide layer 1019 in the hard mask) by selective etching, such as wet etching using hot phosphoric acid. During the selective etching process, the nitride layer 1021 and the nitride protection layer 1045 in the hard mask can also be removed. As a result, the sidewalls of the source / drain layers can be at least partially exposed, but the sidewalls of the channel layer are surrounded by the sacrificial gates 1029 and 1039. A silicidation process can be performed to at least partially or even completely silicide the exposed source / drain layers. The silicidation process may include, for example, depositing a metal such as a NiPt alloy and performing a heat treatment at a temperature of, for example, approximately 200-600° C. to cause the deposited metal to react with semiconductor elements such as Si and / or Ge in the source / drain layer, thereby forming a compound of the metal and the semiconductor element, such as silicide, germanide, or silicon-germanide (hereinafter referred to as silicide). Unreacted excess metal may then be removed.

[0129] Then, if Figure 37(a) 、 37(b)As shown in FIG37( c ), FIG37( d ) (cross-sectional views taken along lines AA′, BB′, CC′, and II′, respectively), a placeholder layer 1051 may be re-formed in the void below the hard mask (currently comprising only the aluminum oxide layer 1019). As described above, the placeholder layer 1051 may be formed by deposition followed by etching back. The placeholder layer 1051 may include a material having a desired etch selectivity (e.g., relative to the sacrificial gates 1029 and 1039 and the hard mask, etc.), such as a nitride.

[0130] As described above, each channel layer may have two nanowires (at opposite corners of the rectangular pattern) for forming the third and fourth interconnect structures, respectively, and another nanowire for forming a gate for applying a power supply voltage V DD To reduce resistance, these nanowires can be silicided.

[0131] For example, Figure 38(a) 、 38(b) , 38(c), 38(d) and 38(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively), a photoresist 1053 may be formed on the above structure. The photoresist 1053 may be patterned to expose the areas where the third and fourth interconnect structures are located (the leftmost circular portion in the bottom row and the rightmost circular portion in the top row in the top view of FIG. 38(a) ) and the areas for applying the power supply voltage V DD The sacrificial gates 1029 and 1039 are selectively etched (relative to the placeholder layer 1051 and the channel layers and source / drain layers) in the region where the contact plugs are located (the rightmost circular portion in the top view of FIG. 38( a )). The photoresist 1053 can be used as an etching mask to selectively etch the sacrificial gates 1029 and 1039 (relative to the placeholder layer 1051 and the channel layers and source / drain layers) to expose the nanowires to be silicided.

[0132] Then, if Figure 39(a) 、 39(b) As shown in FIG39( c ), FIG39( d ) (cross-sectional views along lines AA′, BB′, CC′, and II′, respectively), the exposed channel layer nanowires may be subjected to silicide treatment to form silicide 1055. The silicide treatment may be performed as described above. Thus, the third and fourth interconnect structures and the circuit for applying the power supply voltage V may be formed. DD contact plugs.

[0133] Specifically, as shown in FIG39( a ), the leftmost channel layer nanowires in the upper and lower layers are converted into silicide 1055. These nanowires form a third interconnect structure and are connected to a second interconnect structure formed by source / drain layers 1011 and 1013 (which have also been partially or completely converted into silicide). Furthermore, the rightmost channel layer nanowires in the upper and lower layers are converted into silicide 1055. These nanowires form contact plugs with source / drain layers 1007, 1011, 1013, and 1017 (which have also been partially or completely converted into silicide) and are connected to contact layer 1003 (via isolation auxiliary layer 1005). Furthermore, as shown in FIG39( c ), the rightmost channel layer nanowires in the upper and lower layers are converted into silicide 1055. These nanowires form a fourth interconnect structure and are connected to the first interconnect structure formed by source / drain layers 1011 and 1013 (which have also been partially or completely converted into silicide).

[0134] Next, a replacement gate process may be performed.

[0135] For example, Figure 39(a) 、 39(b) As shown in Figures 39(c) and 39(d), the sacrificial gates 1029 and 1039 can be removed by selective etching (relative to the aluminum oxide layer 1019, the placeholder layer 1051, and the channel layers and source / drain layers or the silicide formed therein). As a result, the sidewalls of each nanowire in the channel layer can be at least partially exposed. A gate dielectric layer 1057 can be formed on the sidewalls of each nanowire in the channel layer by deposition, such as atomic layer deposition (ALD). The gate dielectric layer 1057 can be formed in a substantially conformal manner. The gate dielectric layer 1057 can include a suitable dielectric, such as a high-k dielectric such as HfO2, with a thickness of approximately 0.5-4 nm.

[0136] However, a gate dielectric layer is also formed on the surface of the third and fourth interconnect structures, which will hinder the electrical connection between the third and fourth interconnect structures and the gate electrode layer formed subsequently. To this end, the third and fourth interconnect structures (and optionally the gate electrode layer for applying the power supply voltage V DD The gate dielectric layer is formed on the surface of the contact plug. Figure 40(a) 、 40(b) , 40(c), 40(d) and 40(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively), a photoresist 1059 may be formed on the above structure. The photoresist 1059 may be patterned to expose the third and fourth interconnect structures (and optionally for applying the power supply voltage V DDThe photoresist 1059 can be used as an etching mask to selectively etch the gate dielectric layer 1057 (relative to the placeholder layer 1051 and the silicide) to remove the exposed portion. The photoresist 1059 can then be removed.

[0137] Then, if Figure 41(a) 、 41(b) As shown in Figures 41(c) and 41(d) (cross-sectional views along lines AA′, BB′, CC′ and II′, respectively), a gate electrode layer 1061 can be formed in the gap below the aluminum oxide layer 1019 by deposition and then etching back. For example, the gate electrode layer 1061 can include a work function layer and a conductive filling layer. For example, for a p-type transistor, the work function layer can include TiN, TiNa or a combination thereof with a thickness of about 1-7 nm; the conductive filling layer can include W and / or Ti with a thickness sufficient to fill the gap below the hard mask. As shown in Figure 41(a), the gate electrodes of the p-type pull-up transistor and the n-type pull-down transistor of the first group can be electrically connected to each other through a third interconnect structure. Similarly, as shown in Figure 41(c), the gate electrodes of the p-type pull-up transistor and the n-type pull-down transistor of the second group can be electrically connected to each other through a fourth interconnect structure.

[0138] To further improve performance, different gate electrode layers can be formed for p-type transistors and n-type transistors, for example, gate electrode layers with different effective work functions. For example, the gate electrode layer 1061 formed above, especially the work function layer therein, can be for p-type transistors. Next, a gate electrode layer can be formed for the n-type transistors in the upper layer. For example, the gate electrode layer 1061 formed in the upper layer can be removed, and a gate electrode layer for the n-type transistor can be formed separately.

[0139] In order to avoid affecting the lower gate electrode layer 1061, the lower gate electrode layer 1061 may be shielded. Figure 42(a) 、 42(b)As shown in Figures 42(c) and 42(d) (cross-sectional views along lines AA′, BB′, CC′ and II′, respectively), a shielding layer 1063 can be formed on the above structure by deposition and then etching back. The shielding layer 1063 can also play a role of electrical isolation, and therefore can include a dielectric material, such as an oxide, having a desired etching selectivity (for example, relative to the gate electrode layer 1061). Before etching back, the deposited material can also be subjected to a planarization process such as CMP, and the CMP can stop at the placeholder layer 1031. In order to fully shield the lower layer and expose the upper layer, the top surface of the shielding layer 1063 after etching back can be located between the upper and lower layers, such as at or near the interface between the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor. In addition, the aluminum oxide layer 1019 can also be removed during the etching back process. Subsequently, the upper gate electrode layer 1061 can be removed by selective etching, and a gate electrode layer 1061′ for an n-type transistor can be formed thereon in the same manner as the gate electrode layer 1061. For example, the gate electrode layer 1061′ can include a work function layer and a conductive filler layer. For example, for an n-type transistor, the work function layer can include TiN, TiNa, TiAlC, or a combination thereof, with a thickness of approximately 1-7 nm; the conductive filler layer can include W and / or Ti, with a thickness sufficient to fill the gap below the hard mask.

[0140] Currently, the upper gate electrode layer 1061' continuously extends between the upper channel layer nanowires (three of which have been converted into silicides), and needs to be isolated between the pull-down transistor and the pass-gate transistor, and between the transistors of the first group and the transistors of the second group. Figure 43(a) 、 43(b) , 43(c), 43(d) and 43(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively), a photoresist 1065 can be formed on the above structure, and the photoresist 1065 can be patterned to expose the area that needs to be isolated. Specifically, in the top view of Figure 43(a), in the lower column, the area between the pull-down transistor (the second and third nanowires from the left) and the pass-gate transistor (the fourth nanowire from the left) can be exposed; in the upper column, the area between the pull-down transistor (the second and third nanowires from the right) and the pass-gate transistor (the fourth nanowire from the right) can be exposed. In addition, the area between the two groups (corresponding to the upper and lower columns, respectively) can also be exposed. In addition, in this example, the gate electrode is also formed in the region for applying the power supply voltage V DD and the contact plug WL-1, so the area between the two contact plugs can also be exposed.

[0141] Then, if Figure 44(a) 、 44(b)As shown in Figures 44(c), 44(d), and 44(e) (a top view, a cross-sectional view along line AA′, a cross-sectional view along line BB′, a cross-sectional view along line CC′, and a cross-sectional view along line II′, respectively), the photoresist 1065 can be used as an etching mask to etch downwardly through each layer (e.g., the placeholder layer 1031, the gate dielectric layer 1057, and the gate electrode layer 1061′) such as in the RIE process until the gate electrode layer 1061′ is cut off. When the device size is small or the opening in the photoresist 1065 is small, isotropic etching can be performed when etching the gate electrode layer 1061′ to cut off the gate electrode layer 1061′ below the placeholder layer 1031 by undercutting.

[0142] As shown in the top view of Figure 44(a), the gate electrode layer 1061' is divided into: a part for the first pull-down transistor (the lower left part in the figure), a part for the first pass-gate transistor (the lower middle part in the figure), a part for the second pull-down transistor (the upper right part in the figure), and a part for the second pass-gate transistor (the upper left part in the figure).

[0143] At this point, the fabrication of the SRAM cell is essentially complete. An isolation layer can be formed in the gap on the substrate by deposition followed by planarization, such as CMP (which can stop at the placeholder layer 1031). This isolation layer can include a suitable dielectric material, such as an oxide, and can therefore be shown as isolation layer 1067 together with the previous shielding layer 1063.

[0144] Here, contact plugs WL- 1 and WL- 2 may be formed.

[0145] For example, Figure 45(a) 、 45(b) and 45(c) (a top view, a cross-sectional view along line AA′, and a cross-sectional view along line CC′, respectively), a photoresist 1069 can be formed on the above structure, and the photoresist 1069 is patterned to expose the areas where the contact plugs WL-1 and WL-2 are located (the opposite corners of the rectangular pattern), as shown by the opening OP1 in the figure.

[0146] Then, if Figure 46(a) 、 46(b)As shown in Figures 46(c) and 46(c) (a top view, a cross-sectional view along line AA′, and a cross-sectional view along line CC′, respectively), the various layers (e.g., the second source / drain layer 1017, which may have been partially or completely converted into silicide, and the gate dielectric layer 1057) can be etched downward through the opening OP1 until the gate electrode layer 1061′ is exposed. In this way, a contact hole to the gate electrode layer 1061′ is formed. The contact hole is defined by the corresponding nanowire in the second source / drain layer 1017 and is therefore self-aligned to the gate electrode layer 1061′. A conductive material, such as a metal such as W, Ru, Co, or a combination thereof, can be filled in the contact hole to form a contact plug 1071 (i.e., contact plugs WL-1, WL-2).

[0147] Next, various contacts can be made.

[0148] For example, Figure 47(a) 、 47(b) As shown in Figures 47(c) (a top view, a cross-sectional view along line AA′, and a cross-sectional view along line CC′, respectively), an isolation layer can be formed on the above structure by depositing a dielectric material such as an oxide and performing a planarization process such as CMP. This isolation layer can be shown as 1073 together with the isolation layer 1067. Contact holes can be formed in the isolation layer 1073 by etching and then filled with a conductive material to form various contact portions 1075.

[0149] As shown in Figure 47(b), the power supply voltage V DD The voltage can be applied to the corresponding contact plugs through the corresponding contacts 1075 and to the source / drain regions of the first pull-up transistor through the (isolation auxiliary layer 1005 and) contact layer 1003. The word line WL can be connected to the gate electrode of the first pass-gate transistor through the corresponding contacts 1075 and the contact plug WL-1, and the bit line BL can be connected to the source / drain regions of the first pass-gate transistor through the corresponding contacts 1075. The ground voltage GND can be applied to the source / drain regions of each unit transistor of the first pull-down transistor through the corresponding contacts 1075. The gate electrodes of each unit transistor of the first pull-down transistor are electrically connected to the gate electrode of the first pull-up transistor through the third interconnect structure.

[0150] As shown in FIG47( c ), the word line WL can be connected to the gate electrode of the second pass-gate transistor through the corresponding contact portion 1075 and the contact plug WL-2, and the complementary bit line / BL can be connected to the source / drain region of the second pass-gate transistor through the corresponding contact portion 1075. The ground voltage GND can be applied to the source / drain region of each unit transistor of the second pull-down transistor through the corresponding contact portion 1075. The gate electrode of each unit transistor of the second pull-down transistor is electrically connected to the gate electrode of the second pull-up transistor through the fourth interconnect structure.

[0151] According to another embodiment of the present disclosure, upper source / drain regions of each unit transistor of the same pull-down transistor may be connected together to facilitate the layout of word lines and / or bit lines.

[0152] For example, Figure 48(a) 、 48(b) and 48 (c) (respectively, a top view, a cross-sectional view along line AA', and a cross-sectional view along line CC'), in combination with the above Figure 44(a) 、 44(b) After electrical isolation is formed in the gate electrode layer 1061′ as described in 44(c), 44(d) and 44(e), a photoresist 1069′ can be formed on the resulting structure, and the photoresist 1069′ can be patterned to expose the area between the unit transistors of each pull-down transistor, as shown by the opening OP2 in the figure. The range of the opening OP2 includes part of the source / drain region of the unit transistor of the pull-down transistor. The photoresist 1069′ can be used as an etching mask to etch each layer (for example, the placeholder layer 1031, the isolation layer 1067 and the second source / drain layer 1017 that may have been partially or completely converted into silicide) to form a groove corresponding to the opening OP2. The etching can be stopped before reaching the gate stack.

[0153] Afterwards, if Figure 49(a) and 49(b) (Sectional views along line AA′ and line CC′, respectively) as shown, it is possible to combine the above Figure 45(a) 、 45(b) and 45(c) and Figure 46(a) 、 46(b) 46(c) to form a contact plug 1071. When forming the contact plug 1071, an interconnection 1071' between the source / drain regions of the respective unit transistors of the pull-down transistor can be formed in the trench formed as described above.

[0154] Then, if Figure 50(a) 、 50(b) and 50(c) (a top view, a cross-sectional view along line AA′, and a cross-sectional view along line CC′, respectively), the above combination can be used to obtain the Figure 47(a) 、 47(b) 47( c ) to form a contact 1075. Since the source / drain regions of the respective unit transistors of the pull-down transistors are electrically connected to each other via the interconnect 1071 ′, only one ground contact may be formed for the two unit transistors of the same pull-down transistor, rather than forming two ground contacts as in the above embodiment.

[0155] Next, a metallization stack may be formed.

[0156] For example, Figure 51(a) 、 51(b)As shown in Figures 51(c) and 51(c) (a top view, a cross-sectional view along line AA′, and a cross-sectional view along line CC′, respectively), an isolation layer can be formed on the isolation layer 1073 by depositing a dielectric material such as an oxide and planarizing it, such as by CMP. The isolation layer can be shown as 1073′ together with the isolation layer 1073. In the isolation layer 1073′, a first metal layer 1077 can be formed, including metal patterns connected to corresponding contacts, such as patterns WL1 and WL2 for word lines, patterns BL1 and BL2 for bit lines, a pattern GND for a ground voltage, and a pattern V for a power supply voltage. DD As shown in the top view of FIG. 51( a ), since the ground contact portion is reduced, the bit line patterns BL1 and BL2 can be formed as straight lines, which is advantageous for patterning.

[0157] Then, if Figure 52(a) 、 52(b) As shown in Figures 52(c) and 52(c) (a top view, a cross-sectional view along line AA′, and a cross-sectional view along line CC′, respectively), an isolation layer can be formed on the isolation layer 1073′ by depositing a dielectric material such as an oxide and planarizing it, such as by CMP. The isolation layer can be shown as 1073″ together with the isolation layer 1073′. In the isolation layer 1073″, a second metal layer 1079 can be formed, including patterns WL1 and WL2 for word lines. As shown in the top view in Figure 52(a), the word line patterns WL1 and WL2 can be formed as straight lines, which is advantageous for composition.

[0158] The SRAM cell according to the embodiment of the present disclosure can be applied to various electronic devices. For example, a memory can be formed based on such an SRAM cell, and an electronic device can be constructed therefrom. Therefore, the present disclosure also provides a memory including the above-mentioned SRAM cell and an electronic device including such a memory. The electronic device may also include components such as a processor that cooperates with the memory. Such electronic devices include smartphones, computers, tablet computers (PCs), wearable smart devices, mobile power supplies, and the like.

[0159] The present disclosure also relates to the following aspects.

[0160] 1. A method of manufacturing a static random access memory (SRAM) cell, comprising:

[0161] sequentially arranging a first source / drain layer, a channel layer, and a second source / drain layer of a first group and a stack of a first source / drain layer, a channel layer, and a second source / drain layer of a second group on a substrate;

[0162] forming a hard mask layer on the stack, the hard mask layer comprising a main portion and a connecting portion between the main portions, wherein the main portion is used to define a transistor included in the SRAM cell, the connecting portion is used to define an interconnect structure included in the SRAM cell, and a line width of the connecting portion is smaller than a line width of the main portion;

[0163] defining active regions of a pull-down transistor and a pass-gate transistor among transistors included in the SRAM cell in the channel layer and the second source / drain layer of the second group using the hard mask layer;

[0164] defining a first interconnect structure and a second interconnect structure among interconnect structures included in the SRAM cell in the first source / drain layer of the second group and the second source / drain layer of the first group using the hard mask layer; and

[0165] An active region of a pull-up transistor among transistors included in the SRAM cell is defined in the channel layer and the first source / drain layer of the first group using the hard mask layer.

[0166] 2. The method according to clause 1, wherein the hard mask layer further comprises an additional body portion for defining a third interconnect structure and a fourth interconnect structure in the interconnect structure.

[0167] 3. The method according to clause 1 or 2, wherein the hard mask layer further comprises an additional body portion for defining a contact plug to a gate electrode of the through-gate transistor.

[0168] 4. The method according to any one of the preceding aspects, wherein the hard mask layer is generally rectangular or parallelogram-shaped.

[0169] 5. The method according to any preceding aspect, wherein the hard mask layer further comprises an additional body portion for defining a contact plug for applying a supply voltage to the first source / drain layer of the first group.

[0170] 6. The method according to any one of the preceding aspects, wherein, when defining the active regions in the channel layers of the second group and the channel layers of the first group, portions of the channel layers at unnecessary locations are removed.

[0171] 7. The method according to any preceding aspect, wherein defining an active area in the channel layer of the second group comprises:

[0172] Using the hard mask layer as an etching mask, selectively etching the second source / drain layer and the channel layer of the second group in sequence;

[0173] further selectively etching the second group of channel layers so that the channel layers are divided into separate portions corresponding to the main body portions in the hard mask layer; and

[0174] Based on the hard mask layer, a sacrificial gate is formed around each separated portion of the channel layer.

[0175] 8. The method according to clause 7, wherein defining an active region in the second source / drain layer of the second group comprises:

[0176] further selectively etching the second source / drain layer of the second group so that the second source / drain layer is divided into separate portions corresponding to the main portions in the hard mask layer; and

[0177] Based on the hard mask layer, a placeholder layer is formed around each separated portion of the second source / drain layer.

[0178] 9. The method of clause 7 or 8, wherein defining the first interconnect structure and the second interconnect structure in the second set of first source / drain layers and the first set of second source / drain layers comprises:

[0179] The hard mask layer is used as an etching mask to selectively etch the first source / drain layer of the second group and the second source / drain layer of the first group in sequence.

[0180] 10. The method according to any one of aspects 7 to 9, wherein defining an active area in the channel layer of the first group comprises:

[0181] selectively etching the first group of channel layers using the hard mask layer as an etching mask;

[0182] The channel layer is further selectively etched so that the channel layer is divided into separate portions corresponding to the main body portions in the hard mask layer.

[0183] 11. The method according to clause 10, further comprising:

[0184] forming a placeholder layer on the periphery of each separated portion of the channel layer based on the hard mask layer according to the layout of the pull-up transistor in the SRAM cell; and

[0185] Based on the hard mask layer, a sacrificial gate is formed at the periphery of each separated portion of the channel layer.

[0186] 12. The method according to clause 10, wherein defining the first interconnect structure and the second interconnect structure in the second group of first source / drain layers and the first group of second source / drain layers further comprises:

[0187] Electrical isolation is achieved in the first source / drain layer of the second group and the second source / drain layer of the first group, so as to divide them into electrically isolated portions corresponding to the first interconnect structure and the second interconnect structure.

[0188] 13. The method according to any one of aspects 7 to 12, wherein defining an active area in the first source / drain layer of the first group comprises:

[0189] selectively etching the first source / drain layer using the hard mask layer as an etching mask;

[0190] further selectively etching the first source / drain layer so that the first source / drain layer is divided into separate portions corresponding to the main portions in the hard mask layer; and

[0191] A placeholder layer is formed on the periphery of each separated portion of the first source / drain layer based on the hard mask layer.

[0192] 14. The method according to any of the preceding aspects, further comprising: providing an isolation auxiliary layer on the substrate, wherein the stack is provided on the isolation auxiliary layer,

[0193] The method further includes:

[0194] selectively etching the isolation auxiliary layer using the hard mask layer as an etching mask; and

[0195] The portion of the isolation auxiliary layer where the third and fourth interconnect structures are located is removed.

[0196] 15. The method according to any of the preceding aspects, further comprising:

[0197] The placeholder layer is removed, and the exposed source / drain layer portion is subjected to silicide treatment.

[0198] 16. The method according to any of the preceding aspects, further comprising:

[0199] The sacrificial gate is partially removed at the locations of the third and fourth interconnect structures and the contact plugs for applying a power supply voltage to the first source / drain layer of the first group, and the exposed channel layer portion is silicided.

[0200] 17. The method according to any one of the preceding aspects, further comprising:

[0201] The sacrificial gate is replaced with a gate stack.

[0202] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0203] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A method for manufacturing a static random access memory (SRAM) cell, comprising: sequentially arranging a first source / drain layer, a channel layer, and a second source / drain layer of a first group and a stack of a first source / drain layer, a channel layer, and a second source / drain layer of a second group on a substrate; forming a hard mask layer on the stack, the hard mask layer comprising a main portion and a connecting portion between the main portions, wherein the main portion is used to define a transistor included in the SRAM cell, the connecting portion is used to define an interconnect structure included in the SRAM cell, and a line width of the connecting portion is smaller than a line width of the main portion; defining active regions of a pull-down transistor and a pass-gate transistor among transistors included in the SRAM cell in the channel layer and the second source / drain layer of the second group using the hard mask layer; defining a first interconnect structure and a second interconnect structure among interconnect structures included in the SRAM cell in the first source / drain layer of the second group and the second source / drain layer of the first group using the hard mask layer; and An active region of a pull-up transistor among transistors included in the SRAM cell is defined in the channel layer and the first source / drain layer of the first group using the hard mask layer.

2. The method according to claim 1, wherein The hard mask layer further includes an additional body portion for defining a third interconnect structure and a fourth interconnect structure among the interconnect structures.

3. The method according to claim 1 or 2, wherein The hard mask layer also includes a further body portion for defining a contact plug to a gate electrode of the through-gate transistor.

4. The method according to claim 1, wherein The hard mask layer is rectangular in shape as a whole.

5. The method according to claim 2, wherein: The hard mask layer further includes another body portion for defining a contact plug for applying a supply voltage to the first source / drain layer of the first group.

6. The method according to claim 1, wherein When defining active regions in the channel layers of the second group and the channel layers of the first group, portions of the channel layers at unnecessary locations are removed.

7. The method according to claim 1, wherein Defining an active area in the channel layer of the second group includes: Using the hard mask layer as an etching mask, selectively etching the second source / drain layer and the channel layer of the second group in sequence; further selectively etching the second group of channel layers so that the channel layers are divided into separate portions corresponding to the main body portions in the hard mask layer; and Based on the hard mask layer, a sacrificial gate is formed around each separated portion of the channel layer.

8. The method according to claim 7, wherein: Defining an active region in the second source / drain layer of the second group includes: further selectively etching the second source / drain layer of the second group so that the second source / drain layer is divided into separate portions corresponding to the main portions in the hard mask layer; and Based on the hard mask layer, a placeholder layer is formed around each separated portion of the second source / drain layer.

9. The method according to claim 7 or 8, wherein Defining a first interconnect structure and a second interconnect structure in the first source / drain layer of the second group and the second source / drain layer of the first group includes: The hard mask layer is used as an etching mask to selectively etch the first source / drain layer of the second group and the second source / drain layer of the first group in sequence.

10. The method according to claim 7, wherein: Defining an active area in the channel layer of the first group includes: selectively etching the first group of channel layers using the hard mask layer as an etching mask; The channel layer is further selectively etched so that the channel layer is divided into separate portions corresponding to the main body portions in the hard mask layer.

11. The method according to claim 10, further comprising: forming a placeholder layer on the periphery of each separated portion of the channel layer based on the hard mask layer according to the layout of the pull-up transistor in the SRAM cell; as well as Based on the hard mask layer, a sacrificial gate is formed at the periphery of each separated portion of the channel layer.

12. The method according to claim 10, wherein: Defining a first interconnect structure and a second interconnect structure in the first source / drain layer of the second group and the second source / drain layer of the first group further includes: Electrical isolation is achieved in the first source / drain layer of the second group and the second source / drain layer of the first group, so as to divide them into electrically isolated portions corresponding to the first interconnect structure and the second interconnect structure.

13. The method according to claim 7, wherein: Defining an active region in a first source / drain layer of the first group includes: selectively etching the first source / drain layer using the hard mask layer as an etching mask; further selectively etching the first source / drain layer so that the first source / drain layer is divided into separate portions corresponding to the main portions in the hard mask layer; and A placeholder layer is formed on the periphery of each separated portion of the first source / drain layer based on the hard mask layer.

14. The method according to claim 2, further comprising: An isolation auxiliary layer is provided on the substrate, wherein the stack is provided on the isolation auxiliary layer, The method further includes: selectively etching the isolation auxiliary layer using the hard mask layer as an etching mask; and The portion of the isolation auxiliary layer where the third and fourth interconnect structures are located is removed.

15. The method according to claim 8 or 13, further comprising: The placeholder layer is removed, and the exposed source / drain layer portion is subjected to silicide treatment.

16. The method according to claim 5, further comprising: The sacrificial gate is partially removed at the locations of the third and fourth interconnect structures and the contact plugs for applying a power supply voltage to the first source / drain layer of the first group, and the exposed channel layer portion is silicided.

17. The method according to claim 11, further comprising: The sacrificial gate is replaced with a gate stack.

18. The method according to claim 1, wherein The hard mask layer is generally in the shape of a parallelogram.

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