Image sensor and method for manufacturing the same

Abstract

The present disclosure relates to an image sensor and a method for manufacturing the same. A pixel array for a high-definition (HD) image sensor is disclosed. The pixel array includes a plurality of split pixel units, each split pixel unit including a first photodiode and a second photodiode that is more sensitive to incident light than the first photodiode. The first photodiode can be used to sense bright or high-intensity light conditions, while the second photodiode can be used to sense low to medium-intensity light conditions. In the disclosed pixel array, the sensitivity of one or more photodiodes is reduced by applying a light attenuation layer over the first photodiode of each split pixel unit. According to the method of the present disclosure, the light attenuation layer can be formed before forming a metal optical isolation grid structure. This may result in better control of the thickness and uniformity of the light attenuation layer.

Description

Technical Field

[0001] The present disclosure relates generally to image sensors, and particularly, but not exclusively, to image sensors, such as high dynamic range (HDR) image sensors, that employ a split pixel design with reduced LED flicker. Background Art

[0002] CMOS image sensors (CIS) have become ubiquitous. They are widely used in digital still cameras, cellular phones, surveillance cameras, and in medical, automotive, and other applications. A typical image sensor operates in response to image light reflected from an external scene being incident on the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate an image charge after absorbing the image light. The image charge of each of the pixels can be measured as an output voltage of each photosensitive element that varies with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, and the image charge is used to generate a digital image (i.e., image data) representing the external scene.

[0003] A typical image sensor operates as follows. Image light from an external scene is incident on the image sensor. The image sensor includes a plurality of photosensitive elements such that each photosensitive element absorbs a portion of the incident image light. The photosensitive elements, such as photodiodes, included in the image sensor each generate an image charge after absorbing the image light. The amount of the generated image charge is proportional to the intensity of the image light. The generated image charge can be used to generate an image representing the external scene.

[0004] In particular, as the demand for higher resolution and lower power consumption continues to grow, integrated circuit (IC) technology for image sensors continues to improve. Such improvements generally involve shrinking device geometries to achieve lower manufacturing costs, higher device integration density, higher speed, and better performance.

[0005] However, as the miniaturization of image sensors progresses, defects within the image sensor architecture become more apparent and can degrade the image quality of the image. For example, excessive current leakage within certain areas of the image sensor can cause high dark current, sensor noise, white pixel defects, etc. These defects can significantly degrade the image quality from the image sensor, which can result in reduced yield and higher production costs.

[0006] High dynamic range (HDR) image sensors may present other challenges. For example, some HDR image sensor layouts are not space efficient and difficult to miniaturize to a smaller pitch to achieve higher resolution. In addition, due to the asymmetric layout of many of these HDR image sensors, reducing the size and pitch of the pixels to achieve a high-resolution image sensor can lead to crosstalk or other undesirable side effects, such as diagonal spots that may appear in these image sensors as the pitch decreases. In addition, many HDR image sensors require structures with very large full well capacity (FWC) to accommodate the large dynamic range. However, the larger FWC requirement causes hysteresis, white pixels (WP), dark current (DC), and other unnecessary problems. Summary of the invention

[0007] On the one hand, the present disclosure relates to a split pixel unit, which includes: a semiconductor substrate having a light receiving surface; a first photodiode, which is disposed in the semiconductor substrate and photogenerates image charge in response to incident light; a second photodiode, which is disposed in the semiconductor substrate adjacent to the first photodiode, the second photodiode photogenerates image charge in response to incident light, wherein the second photodiode is more sensitive to the incident light than the first photodiode; first and second optical isolation grid segments, which are disposed on the light receiving surface of the semiconductor substrate and surround an exposure area of ​​the first photodiode, the first and second optical isolation grid segments having a top surface facing the incident light, and inner and outer side walls; a light attenuation layer, which is disposed adjacent to the inner side walls of the first and second optical isolation grid segments and optically aligned with the first photodiode; and a barrier film, which is directly disposed on the inner or outer side walls of the first and second optical isolation grid segments.

[0008] On the other hand, the present disclosure relates to a method for manufacturing an image sensor, comprising: providing a semiconductor substrate having a plurality of first photodiodes and a plurality of second photodiodes, wherein each of the first photodiodes is arranged to be surrounded by the second photodiode, wherein each of the second plurality of photodiodes has greater sensitivity to incident light than the first plurality of photodiodes; forming a light attenuation layer over a first surface of the semiconductor substrate, the light attenuation layer covering the first surface across the plurality of first photodiodes and the plurality of second photodiodes; thereafter forming an optical isolation grid structure over the semiconductor substrate, the optical isolation grid structure being disposed over and between each of the plurality of first photodiodes and the plurality of second photodiodes, the optical isolation grid structure defining a plurality of optical isolation grid sections each having a top surface and inner and outer side walls; thereafter removing sections of the light attenuation layer over the plurality of second photodiodes, thereby leaving only a first photodiode section of the light attenuation layer over the plurality of first photodiodes; forming a buffer layer over the optical isolation grid structure and the first photodiode section of the light attenuation layer, wherein the buffer layer is disposed directly on the top surface of the optical isolation grid section. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of an image sensor according to an embodiment of the present disclosure is described.

[0010] Figure 2 is an explanatory diagram of an example of a pixel unit according to an embodiment of the present disclosure.

[0011] Figure 3 is a top schematic partial view of one example of a pixel array according to an embodiment of the present disclosure.

[0012] Figure 4 It is taken along line 4-4 Figure 3 Schematic cross-sectional view of a pixel array.

[0013] Figure 5 According to an embodiment of the present disclosure, Figure 3 An example flow chart of a pixel array.

[0014] Figures 6A-6H is based on a manufacturing process, e.g. Figure 5 Schematic partial view of the manufacturing process of a pixel array.

[0015] Throughout the several views of the accompanying drawings, corresponding reference characters indicate corresponding components. It will be appreciated by those skilled in the art that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve understanding of the various embodiments of the present disclosure. Moreover, common but well-understood elements that are useful or necessary in commercially feasible embodiments are generally not depicted in order to facilitate a clearer viewing of these various embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] An example of a device having a split pixel unit with a light attenuation layer is provided. A method of manufacturing such a device is also provided. Therefore, in the following description, numerous specific details are set forth to provide a thorough understanding of the examples. Those skilled in the relevant art will recognize; however, the techniques described herein can be practiced without one or more of the specific details or with other methods, components, materials, etc. In other examples, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0017] References throughout this specification to "one example" or "one embodiment" indicate that a particular feature, structure, or characteristic described in conjunction with the example is included in at least one example of the present invention. Thus, the phrases "in one example" or "in one embodiment" that appear throughout this specification do not necessarily all refer to the same example. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0018] For ease of description, spatially relative terms such as "below," "beneath," "under," "under," "above," "over," and the like may be used herein to describe the relationship of one element or feature to another element or feature, as illustrated in the figures. It will be understood that in addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, then elements described as "below other elements or features," "below other elements or features," or "under other elements or features" will be oriented as "above other elements or features." Thus, the exemplary terms "below" and "under" may cover both orientations of "above" and "below." The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] Additionally, it will be understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intervening layers may also be present. Similarly, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe relationships between elements or layers (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," "on" versus "directly on") should be interpreted in a similar manner.

[0020] Throughout the specification, several technical terms are used. These terms should have their ordinary meaning in the art, unless explicitly defined herein or the context of their use clearly indicates otherwise. It should be noted that throughout this document, element names and symbols are used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0021] Example embodiments may be described herein with reference to cross-sectional illustrations of schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Therefore, example embodiments should not be construed as limited to the specific shapes of the regions described herein, but rather include shape deviations, for example, due to manufacturing. For example, an implanted region described as a rectangle may have rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in a certain implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the example embodiments.

[0022] As will be shown, examples of pixel cells for high dynamic range imaging are disclosed. In various examples, the example split pixel cell includes several photodiode regions (e.g., four, nine, sixteen, etc.). In an example, at least one photodiode region is configured to form a small photodiode and several photodiode regions (e.g., the remaining photodiode regions) surrounding the small photodiode are configured to form a large photodiode. In some examples, the small photodiode can be used to sense bright or high intensity light conditions, while the large photodiode can be used to sense low to medium intensity light conditions. One or more of these example pixel cells can be arranged in a pixel array and used, for example, for high dynamic range imaging. In some examples, the pixel cells of the pixel array can adopt a 3T, 4T, or 5T pixel architecture. In some examples, a shared pixel cell architecture is adopted, in which the photodiodes are coupled to a common floating diffusion region via several transfer gates.

[0023] In the automotive industry, image sensors are used for backup cameras, advanced driver assistance systems (ADAS), camera-based mirrors, sometimes referred to as electronic rearview mirrors, etc. As LED lighting becomes more prevalent in vehicles, there is a need for HDR image sensors with low LED flicker. Typically, due to the on / off nature of LED light generation, continuous LED light to the human eye may appear to flicker in images captured by cameras employing HDR image sensors. Flickering LEDs in images presented to the driver by one or more of these systems may cause driver confusion, driver distraction, etc.

[0024] Techniques for addressing LED flicker in image capture and the like have been proposed. For example, U.S. Patent No. 9,590,005 and U.S. Patent Publication No. 2018 / 0366513, both assigned to Omnivision Technologies Inc., employ a light attenuation layer positioned above a small photodiode of a split pixel unit. The light attenuation layer reduces the sensitivity of the photodiode, which can allow for longer integration times of the small photodiode, prevent saturation during integration, and the like.

[0025] However, the continued demand for higher resolution image sensors with low power consumption has resulted in ever-decreasing pixel sizes. As pixel size decreases, it becomes more challenging to remove the light attenuation layer from the large photodiodes of the split pixel cells. For example, current processing schemes have difficulty in cleanly etching away the light attenuation layer in the narrow spaces associated with the large photodiodes in the optical isolation grid. Additionally, current processing schemes have difficulty in uniformly depositing the light attenuation layer between the narrowly spaced optical isolation grid structures typically employed by these sensor types.

[0026] The methods and techniques of the present disclosure seek to address these issues associated with split pixel cells employed, for example, in automotive environments, etc. For example, examples of the disclosed subject matter are intended to reduce associated LED flicker in HDR image sensors by reducing the sensitivity of one or more photodiodes of, for example, 3T, 4T, or 5T pixel cells (including those of split pixel designs) so that longer integration times can be achieved, saturation during integration can be prevented, etc., in order to improve the dynamic range of the image sensor. In some examples, the sensitivity of one or more photodiodes is reduced by applying a light attenuation layer over the small photodiodes of the split pixel cell. According to the methods of the present disclosure, the light attenuation layer can be formed prior to forming a metal optical isolation grid structure. By forming the light attenuation layer prior to forming the metal optical isolation grid structure, the light attenuation layer is not formed on the metal optical isolation grid structure (which would degrade subsequent photolithography processes) and the thickness of the light attenuation layer can be better controlled.

[0027] As will be described in more detail below, in an example embodiment, the transistor of the pixel unit may be of N-channel metal oxide semiconductor (NMOS) type, wherein the metal may be polycrystalline silicon (poly-Si), tungsten (W), etc., the oxide may be a dielectric, such as SiO2 (e.g., thermally grown or deposited on a semiconductor material), and the semiconductor may correspond to a portion of a semiconductor material, such as silicon (e.g., single crystal or polycrystalline Si), silicon on insulator (SOI), etc.

[0028] To illustrate, Figure 1 A block diagram illustrating an example image sensor 100 that uses a pixel array having, for example, split pixel cells to detect low / medium and high intensity illumination in accordance with techniques and methods of the present disclosure is shown. Image sensor 100 may be implemented as a complementary metal oxide semiconductor ("CMOS") image sensor. Figure 1 As shown in the example illustrated in , image sensor 100 includes a pixel array 102 coupled to control circuitry 108 and readout circuitry 104 , which is coupled to function logic 106 .

[0029] The illustrated embodiment of pixel array 102 is a two-dimensional ("2D") array of imaging sensors or pixel cells 110 (e.g., pixel cells P1, P2, ..., Pn). In one example, each pixel cell includes one or more sub-pixels or pixel regions that can be used for imaging, in accordance with the techniques and methods of this disclosure. As illustrated, each pixel cell 110 is arranged into rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, or object, etc., which can then be used to reproduce an image of the person, place, or object, etc. As will be described in more detail below, in accordance with the techniques and methods of this disclosure, each pixel cell 110 (e.g., pixel cells P1, P2, ..., Pn) can include, for example, a small photodiode adjacent to one or more large photodiodes, wherein a light attenuation layer is placed over the small photodiode.

[0030] In one example, after each pixel cell 110 has acquired its image data or image charge, the image data is read out by readout circuitry 104 through readout column bit lines 112 and then transferred to function logic 106. In various examples, readout circuitry 104 may include amplification circuitry (not illustrated), column readout circuitry including analog-to-digital conversion (ADC) circuitry, or other circuitry. Function logic 106 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or otherwise). In one example, readout circuitry 104 may read out image data one row at a time along a readout column line (illustrated) or may use a variety of other techniques to read out image data (not illustrated), such as serial readout or fully parallel readout of all pixels at the same time.

[0031] In one example, the control circuit system 108 is coupled to the pixel array 102 to control the operating characteristics of the pixel array 102. For example, in one example, the control circuit system 108 generates a transfer gate signal and other control signals to control the transfer and readout of image data from the sub-pixels or pixel areas of the shared pixel unit 110 of the pixel array 102. In addition, the control circuit system 108 can generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for simultaneously enabling all pixels within the pixel array 102 to simultaneously capture their corresponding image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal so that each row of pixels, each column of pixels, or each group of pixels is sequentially enabled during continuous acquisition windows. The shutter signal can also establish an exposure time, which is the length of time the shutter remains open. In one embodiment, the exposure time is set to be the same for each of the frames.

[0032] In one example, the control circuit system 108 may control the timing of various control signals provided to the pixel cells 110 to reduce the dark current associated with the floating diffusion region of each of the pixel cells 110. In some non-limiting embodiments, the pixel cells 110 may be so-called 4T pixel cells, e.g., four-transistor pixel cells. In other non-limiting embodiments, the pixel cells 110 may be so-called 3T pixel cells, e.g., three-transistor pixel cells. In other non-limiting embodiments, the pixel cells 110 may be so-called 5T pixel cells, e.g., five-transistor pixel cells. In some other non-limiting embodiments, the pixel cells are split pixel types regardless of the number of transistors (e.g., 3, 4, 5, etc.).

[0033] In one example, the image sensor 100 may be included in a digital camera, a cell phone, a laptop computer, etc. In addition, the image sensor 100 may be coupled to other hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, a wireless transmitter, an HDMI port, etc.), an illumination device / flash, an electrical input (keyboard, a touch display, a trackpad, a mouse, a microphone, etc.), and / or a display. The other hardware may deliver instructions to the image sensor 100, extract image data from the image sensor 100, or manipulate the image data supplied by the image sensor 100.

[0034] Figure 2 2 is an illustrative diagram of an example pixel cell 210 having a split pixel design according to the teachings of the present disclosure. However, it should be understood that the embodiments of the present disclosure are not limited to Figure 2 pixel architecture; on the contrary, a person of ordinary skill in the art having the benefit of the present disclosure will understand that the present teachings are also applicable to 3T designs, 5T designs, shared and non-shared pixel designs, and various other pixel architectures.

[0035] It should be understood that Figure 2 The pixel unit 210 may be Figure 1 10, and similarly named and numbered elements referenced below may be coupled and function similarly as described above. For example, pixel cell 210 may be coupled to a bit line (e.g., a readout column) that may provide image data to a readout circuitry such as readout circuitry 104, and pixel cell 210 may receive control signals from control circuitry such as control circuitry 108 to control the operation of various transistors of pixel cell 210. Control circuitry 108 may control the operation of the transistors in a desired sequence relative to timing in order to, for example, reset a pixel to a dark state, and read out image data, for example, after integration.

[0036] The illustrated example of pixel cell 210 includes a first photoelectric conversion element or photodiode region 212, such as a small photodiode (PD l ), and a plurality (shown as three) of second photoelectric conversion elements or photodiode regions 214, 216, 218 that together constitute a large photodiode (PD2-PD4). The illustrated example of pixel cell 210 may be referred to as a 4C pixel cell. In operation, the small photodiode (PD1) and the large photodiodes (PD2-PD4) are coupled to photogenerate image charge in response to incident light. In an embodiment, the large and small photodiodes may be used to provide image data for a high dynamic range (HDR) image. For example, the small photodiode (PD1) may be used to sense bright or high intensity light conditions, while the large photodiodes (PD2-PD4) may be used to sense dimmer low to medium intensity light conditions to provide image data for a high dynamic range (HDR) image.

[0037] In an example embodiment, the large photodiode formed collectively by the photodiode regions 214, 216, 218 has an exposure area that is larger than the exposure area of ​​the small photodiode (e.g., photodiode region 212). In another example embodiment, the small photodiode has a smaller full well capacity (FWC) than the large photodiode (e.g., the combined full well capacity of the photodiode regions 214, 216, 218). In another example embodiment, the small photodiode includes a short integration and the large photodiode includes a long integration. In another example embodiment, the large photodiode includes a long integration and the small photodiode includes an even longer integration to ensure, for example, LED capture in each frame.

[0038] In one example embodiment, as will be described in more detail below, an LED flicker reduction (LFR) film or light attenuation layer is disposed only over a small photodiode (PD l ) to reduce the small photodiode (PD l ) sensitivity, while the large photodiode (PD 2-4 ) remains unchanged. Therefore, the photodiode regions 214, 216, 218 of the large photodiode have a higher sensitivity to incident light and can therefore be used for lower light intensity sensing. On the other hand, since the small photodiode (PD1) has, for example, a smaller exposure area, a smaller FWC, etc., and because there is a light attenuation layer disposed above the small photodiode (PD1), it is more sensitive to the incident light than the large photodiode (PD1). 2-4 ) is less sensitive to high intensity light than the large photodiode and is therefore used for higher light intensity sensing. HDR imaging sensing is achieved by utilizing both large and small photodiodes in the pixel unit 210. As will be described in more detail below, for example, a small photodiode with reduced sensitivity may result in an increased integration time before saturation.

[0039] Pixel cell 210 also includes a first transfer gate 220 of a first transfer transistor associated with small photodiode 212, second to fourth transfer gates 222, 224, 226 of second, third and fourth transfer transistors associated with photodiodes 214, 216, 218 of large photodiodes, respectively, and a floating diffusion region (FD) 228. First transfer gate 220 is coupled to transfer image charge from small photodiode 212 to floating diffusion region 228 in response to control signal TX1. Second, third and fourth transfer gates 222, 224, 226 are coupled to transfer image charge from respective large photodiodes 214, 216, 218 to floating diffusion region 228 in response to control signals TX2, TX3, TX4. In the depicted arrangement, floating diffusion region 228 is common to photodiodes 212, 214, 216, 218 and may be referred to as common floating diffusion region 228.

[0040] Reset transistor 230 is coupled to common floating diffusion region 228 to reset pixel cell 210 in response to reset signal RST (e.g., discharge or charge photodiode regions 212, 214, 216, 218 and floating diffusion region 228 to a preset voltage). A gate terminal of amplifier transistor 232 is also coupled to floating diffusion region 228 to generate an image data signal in response to image charge in floating diffusion region 228. In the illustrated example, amplifier transistor 232 is coupled as a source follower (SF) coupled transistor. Row select transistor 234 is coupled to amplifier transistor SF 232 to output the image data signal to an output bit line in response to row select signal SEL, which is coupled to, for example, a plurality of floating diffusion regions 228. Figure 1 The readout circuit system 104 is a readout circuit system.

[0041] Control signal TX l and TX 2-4 Transfer gates 220, 222, 224, 226 are enabled to transfer charge from photodiode regions 212, 214, 216, 218 to common floating diffusion region 228. The amount of charge transferred from the photodiodes to floating diffusion region 228 may depend on the current operation of pixel cell 210. For example, during a reset operation, the charge may be the charge generated in the dark state of the photodiode(s), but during integration, the charge may be the photogenerated image charge. At the end of integration, the image charge may be read out twice to perform correlated double sampling (CDS), with one or more dark readings occurring between the two readouts.

[0042] Figure 3 3 is a schematic diagram or a top view schematic diagram of a portion of an example pixel array 302 including one or more pixel units 310A-310N according to the techniques and methods of the present disclosure. It should be understood that Figure 3 The unit 310 may be Figure 2 An example of a pixel unit 210, or Figure 1 An example of a pixel unit 110 is shown, and similarly named and numbered elements referenced below may be coupled and function similarly as described above.

[0043] For the sake of brevity and clarity, pixel cell 310B of pixel array 302 will now be described in greater detail. It will be appreciated that the other pixel cells 310 of pixel array 302 are constructed substantially identically to pixel cell 310B and therefore will not be described separately.

[0044] exist Figure 3In an example embodiment of the present invention, pixel cell 310B includes a first photodiode region 312, which is configured to form a small photodiode adjacent to a plurality of photodiode regions 314, 316, 318 that are configured to collectively form a large photodiode. Thus, a pixel array, such as pixel array 302, includes a semiconductor substrate 338 having a plurality of small photodiodes, such as photodiode region 312, each of which is surrounded by a plurality of photodiode regions 314, 316, 318 of a large photodiode. Each photodiode of the pixel cell is adapted to photogenerate image charge in response to incident light. Of course, pixel cell 310B or pixel array 302 may have other photodiode layouts according to embodiments of the present disclosure. Embodiments of pixel cell 310 that include more than one photodiode or sub-pixel region "share" the pixel transistor region (not shown) of pixel cell 310B, and therefore, may be referred to as a shared pixel cell.

[0045] In the illustrated example, the photodiode regions 314, 316, 318 of the large photodiode (referred to as large photodiode regions 314, 316, 318 for brevity) have greater sensitivity to incident light than the photodiode region 312 of the small photodiode (referred to as small photodiode region 312 for brevity). Figure 3 , a light attenuation layer 340, such as a metal film layer (e.g., a Ti / TiN stack), is disposed over the surface of the semiconductor substrate 338. In the example embodiment, the light attenuation layer 340 is optically aligned with the small photodiode region 312 so that it blocks or attenuates some of the incoming incident light directed onto the small photodiode region 312. For example, it should be understood that when the light attenuation layer 340 is aligned along the incident light 368 ( Figure 4 ) to the small photodiode region 312 of the pixel unit 310, the photosensitivity of the small photodiode region 312 is further reduced. Reducing the photosensitivity of the small photodiode by attenuating the incoming incident light can prevent the small photodiode from saturating during the integration period. Preventing saturation during the integration period can result in longer integration times, which can address, for example, LED flicker issues.

[0046] In one example embodiment, light absorption by the small photodiode region 312 can be reduced by the light attenuation layer 340, for example, to 1 / 10 or less. Figure 4 ) through the light attenuation layer 340 is responsive to the thickness of the light attenuation layer 340. Therefore, the transmittance of incident light into the small photodiode region 312 can be adjusted by controlling the thickness of the light attenuation layer 340. In practice, the final thickness of the light attenuation layer 340 can be selected based on the transparency and thickness map. As will be described in more detail below, the thickness of the light attenuation layer 340 can be better controlled via the method of the present disclosure.

[0047] According to the teachings of the present disclosure, pixel array 302 also includes an optical isolation grid structure 344, such as a light barrier grid, disposed adjacent to a plurality of photodiodes of semiconductor substrate 338. Optical isolation grid structure 344 defines a plurality of openings disposed above the photodiodes of semiconductor substrate 338. In one example, optical isolation grid structure 344 may be composed of aluminum, titanium nitride, or another other suitable material to fabricate a metal grid to guide incident light 368 ( Figure 4 ) through multiple openings into corresponding photodiodes in the semiconductor substrate 338.

[0048] As will be described in more detail below, optical isolation grid structure 344 is placed between adjacent color filters (not shown) to inhibit transmission of light between adjacent color filters. It will be appreciated that in the absence of optical isolation grid structure 344, light from a scene may enter one color filter associated with one sub-pixel of pixel array 302 and propagate to an adjacent color filter before reaching the light receiving surface of the photodiode. This process causes crosstalk (e.g., optical crosstalk) between adjacent sub-pixels. Therefore, in general, optical isolation grid structure 344 is provided for inhibiting this crosstalk to provide improved color clarity and resolution.

[0049] As will be described in more detail below, a variety of materials and manufacturing techniques may be utilized to form pixel array 302. Semiconductor substrate 338 may have a composition of Si (e.g., single crystal or polycrystalline Si). The gate may have a composition comprising tungsten or polycrystalline silicon. The dielectric layer (not shown) may have a composition of SiO2, HfO2, or any other suitable dielectric medium known to those of ordinary skill in the art. The contacts may be composed of any doped material having a low ohmic resistance. Other metals, semiconductors, and insulating materials may also be used for pixel array 302, as known to those of ordinary skill in the art. Doped regions of semiconductor material may be formed by implantation, thermal diffusion, and the like. It will be appreciated that the doping polarity or doping type (P-type, N-type, etc.) in the illustrative embodiments may be reversed in alternative embodiments. As known to those of ordinary skill in the art, manufacturing techniques such as photolithography, masking, chemical etching, ion implantation, thermal evaporation, plasma vapor deposition, chemical vapor deposition, atomic layer deposition, sputtering, and the like may be utilized to manufacture pixel unit 310, pixel array 302, and / or image sensor 100.

[0050] Figure 4 It is along Figure 34-4 of FIG. 4 , a partial cross-sectional view of a pixel array, such as pixel array 302, is shown. Pixel array 302 is composed of a plurality of pixel cells, such as pixel cell 310, arranged in rows and columns. It should be appreciated that pixel array 302 is provided for purposes of explanation and thus represents only one possible cross-sectional illustration for implementing a pixel array, and that examples in accordance with the teachings of the present disclosure are not limited to the specific pixel array cross-sectional illustration example as shown.

[0051] exist Figure 4 , pixel array 302 includes a semiconductor substrate 338 having a first or light receiving surface 354 (e.g., backside 354) and an opposing second surface 356 (e.g., frontside 356). A color filter layer 360 is disposed on the light receiving surface 354 of semiconductor substrate 338. Semiconductor substrate 338 includes an array of photodiodes (PDs), each of which generates an electric charge in response to incident light 368. In an example embodiment, color filter layer 360 includes an array of color filters 364 (shown as color filters 364A, 364B, 364C) separated by optical isolation grid structures 344 (shown as grid segments 344A, 344B). The array of color filters 364 can be registered to the array of photodiodes (PDs) such that each color filter 364 cooperates with a corresponding photodiode to form a color sub-pixel, i.e., a sub-pixel that is sensitive to light within a certain wavelength range.

[0052] The array of photodiodes (PDs) includes small photodiodes (PDs) formed of a photodiode region 312 disposed adjacent to one or more photodiode regions 316 of corresponding adjacent large photodiodes. l ). In the example embodiment, the photodiode region 316 of the large photodiode is in a surrounding relationship with respect to the photodiode region 312 of the small photodiode. In the illustrated example, the large photodiode region 316 has a higher sensitivity to incident light than the small photodiode region 312.

[0053] exist Figure 4 , each photodiode region 312, 316 is separated at least in part by a trench isolation structure, such as a deep trench isolation (DTI) structure 374. The deep trench isolation structure 374 is disposed within a trench formed in the backside or light receiving surface 354 of the semiconductor substrate 338. For example, the deep trench isolation structure 374 may be used to electrically and / or optically isolate the photodiodes by reflecting light back into the photodiodes and preventing charge from traveling through the semiconductor substrate 338 and on the surface of the semiconductor substrate 338 into other photodiodes.

[0054] In an example embodiment, the deep trench isolation structure 374 includes a dielectric fill material (e.g., silicon oxide) deposited into a trench formed in the semiconductor substrate 338. In some embodiments, a dielectric layer (not shown) lining the sides and bottom of the trench may be provided. For example, a high-k liner oxide or the like (e.g., hafnium oxide, silicon oxide, etc.) may create an interface between the deposited dielectric fill material (e.g., silicon oxide) and the photodiode regions 312, 316, etc. In some example embodiments, the deep trench isolation structure 374 may instead include a metal core surrounded by a high-k liner oxide.

[0055] exist Figure 4 , the passivation layer 348 may be disposed over the deep trench isolation structure 374 and proximate to the light receiving surface 354 of the semiconductor substrate 338. The color filter layer 360 is also disposed proximate to the light receiving surface 354 of the semiconductor substrate 338 and interfaces with the passivation layer 348. The passivation layer 348 may be, for example, a silicon oxide film layer, etc. In an example embodiment, the pixel array 302 further includes an array of microlenses 370 disposed on the color filter array 360 to assist in focusing the incident light 368 on the photodiodes.

[0056] As briefly described above, the pixel array 302 further includes an optical isolation grid structure 344 disposed above the passivation layer 348 and dividing the color filter array 360 into color filters 364A, 364B, 364C, shown as grid sections 344A, 344B. The optical isolation grid structure 344 may, for example, include a reflective material, such as a metal, that can reflect light into the appropriate photodiode. For example, in one example embodiment, the optical isolation grid structure 344 may be composed of aluminum, titanium nitride, or another other suitable material to make a metal grid to guide incident light 368 into the corresponding photodiode in the semiconductor substrate 338. In some embodiments, the optical isolation grid structure 344 is substantially aligned (e.g., vertically aligned) with the deep trench isolation structure 374. In the illustrated embodiment, the optical isolation grid structure 344 is substantially aligned (e.g., optically aligned) with the deep trench isolation structure 374. In some example embodiments, the optical isolation grid structure 344 may be formed in a self-aligned process. In some embodiments, each grid segment 344A, 344B of the optical isolation grid structure 344 is vertically aligned with a corresponding deep trench isolation structure 374 .

[0057] According to one aspect of the present disclosure, the pixel array 302 further includes a light attenuation layer 340 that is optically aligned only with the small photodiode region 312 and between the grid sections 344A, 344B of the optical isolation grid structure 344 such that it blocks or attenuates some of the incoming incident light 368 that enters the small photodiode region 312, thereby reducing the sensitivity of the small photodiode region 312. For clarity, the light attenuation layer 340 covers only the exposed area of ​​the small photodiode region 312 of the pixel array 302 and does not cover the adjacent large photodiodes of the pixel array 302 (i.e., the light attenuation layer 340 does not cover the photodiode regions 314, 316, 318 (see also FIG. 1 ). Figure 3 )), thereby reducing the light intensity received by the small photodiode.

[0058] exist Figure 4 , the light attenuation layer 340 is disposed between the color filter 364B and the passivation layer (e.g., oxide layer) 348, and is in close proximity to (e.g., directly adjacent to) the inner walls of the grid segments 344A, 344B of the optical isolation grid structure 344. In an example embodiment, the light attenuation layer 340 may be composed of aluminum, tungsten, titanium, titanium nitride, combinations thereof, such as Ti / TiN, or another suitable thin metal layer film to adjust the transmittance of the incident light 368 in accordance with the teachings of the present disclosure.

[0059] In an example embodiment, the bottom of each grid segment associated with the small photodiode region 312, such as the grid segments 334A, 344B, is aligned (e.g., horizontal, flush, etc.) with the light attenuation layer 340, which may, for example, provide improved optical performance (e.g., better shielding of large angles of incidence, etc.). In an embodiment, the grid segments 334A, 344B are disposed over the photodiode regions 312, 314, 316, 318 and surround the exposed areas of the small photodiode regions 312. In another example embodiment, the optical isolation grid structure 344 and the light attenuation layer 340 are structurally connected for each pixel due to the example formation method, as will be described in more detail below, and thus may be offset together when considering the chief ray angle of the pixel.

[0060] The pixel array 302 further includes a barrier film 378, such as a titanium nitride film, disposed directly on the sidewall surfaces of the grid segments 344A, 344B of the optical isolation grid structure 344. In an example embodiment, the barrier film 378 is disposed directly on the entire inner and outer sidewall surfaces of the grid segments 344A, 344B of the optical isolation grid structure 344. In the illustrated embodiment, the barrier film 378 is also disposed directly between the bottom surfaces of the grid segments 344A, 344B and the light receiving surface 354 (e.g., the passivation layer 348) of the semiconductor substrate 338. Alternatively, in some example embodiments, the light attenuation layer 340 may be formed before the optical isolation grid structure 344, and thus the light attenuation layer 340 may extend below and directly contact the bottom surfaces of the grid segments 344A, 344B in place of the barrier film 378.

[0061] In an example embodiment, the thickness of the barrier film 378 is approximately half the thickness of the light attenuation layer 340. In an example embodiment, neither the barrier film 378 nor the light attenuation layer 340 is formed on or otherwise in direct contact with the outward-facing (e.g., incident light) surface of the optical isolation structure 344. This lack of a barrier film 378 or light attenuation layer 340 on top of the grid segments 344A, 344B enables the optical isolation grid structure 344 to have a substantially flat top surface, improving any subsequent photolithography processes during fabrication of the pixel cell 310.

[0062] In some example embodiments, the oxide layer 380 surrounds the top (e.g., incident light facing) surface of the optical isolation grid structure 344, such as the entire top surface, to provide isolation between the grid segments 344A, 344B of the optical isolation grid structure 344 and the color filters 364 of the color filter array 360. Figure 4 , the oxide layer 380 is also formed over other portions of the optical isolation grid structure 344, including over the barrier film 378, and over the light attenuation layer 340. In some example embodiments, the oxide layer 380 may also be formed over the passivation layer 348 in order to increase the thickness of the buffer zone between the color filter array 360 and the semiconductor substrate 338.

[0063] Pixel array 302 may further include electrical connections (not shown) connecting the large and small photodiodes to readout electronics, such as readout circuitry 104. The electrical connections are on the side of the photodiodes opposite the light receiving surface 354 so that incident light 368 propagating from the scene toward the photodiodes does not pass through the electrical connection layer.

[0064] exist Figure 4, the photodiode regions PD1, PD3 are formed on the back side of the semiconductor substrate 338, and thus, the pixel array 302 may be referred to as a back side illuminated (BSI) pixel array. Although examples have been described herein with respect to a back side illuminated (BSI) pixel cell or pixel array of an image sensor, the methods and techniques of the present disclosure may likewise be employed in a front side illuminated (FBI) pixel cell or pixel array of an image sensor, and the like.

[0065] Figure 5 1 is a flow chart illustrating one example of a method for manufacturing a pixel array, such as pixel array 302, according to the teachings of the present disclosure. It will be appreciated that the following method steps may be performed in any order or simultaneously unless otherwise stated in an explicit manner or understood in light of the context of the various operations (several). Additional process steps may also be performed, including chemical mechanical polishing, masking, additional doping, etc. Of course, some method steps may be combined or omitted in example embodiments. To aid in the description Figure 5 One or more steps of the method described in Figures 6A-6H .

[0066] At the beginning of the manufacturing process, a semiconductor substrate is provided, such as semiconductor substrate 338, which has a plurality of first photodiodes, such as small photodiode region 312, and a plurality of second photodiodes, such as a large photodiode formed collectively by photodiode regions 314, 316, 318. In some example embodiments, the first photodiodes provided with the semiconductor substrate are arranged to be surrounded by the region of the second photodiodes. In an example embodiment, the first plurality of photodiodes (e.g., small photodiodes) have less sensitivity to incident light than the second plurality of photodiodes (e.g., large photodiodes).

[0067] Next, a passivation layer (e.g., a planarization layer) may be formed on the surface of the semiconductor substrate 338. In an example embodiment, a passivation layer, such as the passivation layer 348, is formed on the back side of the semiconductor substrate 338 and over the plurality of first and second photodiodes. The passivation layer is formed of an oxide material, such as silicon oxide. Once the passivation layer 348 is formed, a light attenuation layer (LAL) is formed on the passivation layer, such as Fig. 6A . In some example embodiments, the light attenuation layer LAL may be a single layer or a multi-layer stack and include a material or materials selected from aluminum, tungsten, titanium, titanium nitride, etc. In an embodiment, the light attenuation layer is formed as a titanium / titanium nitride stack. Because the light attenuation layer LAL is formed directly on the flat passivation layer 348, the thickness of the light attenuation layer LAL can be controlled and the light attenuation layer LAL can be deposited more uniformly.

[0068] A sacrificial material layer SML (eg, amorphous silicon) is deposited on the light attenuation layer LAL. Fig. 6A, the sacrificial material layer SML is then patterned and etched to form an opening extending directly adjacent to the passivation layer 348 between the plurality of first and second photodiodes, as shown in FIG. Figure 6B . In another example embodiment, the opening extends into the passivation layer 348 to a depth such that the bottom of the opening is below the light attenuation layer LAL. In an alternative embodiment, the opening extends into the light attenuation layer LAL but does not extend completely so as not to expose the passivation layer 348. Amorphous silicon may be advantageously employed because it exhibits high etch selectivity compared to silicon oxide. In an exemplary embodiment, amorphous silicon is deposited at a low temperature of about 390 degrees Celsius so that the step does not cause damage to the already formed structures, such as metal interconnect structures, negative charges inherent in high-k pad oxides, etc.

[0069] In an example embodiment, openings are also disposed over deep trench isolation trench structures, such as deep trench isolation trench structure 374, which may be provided with semiconductor substrate 338 prior to depositing the passivation layer. As will be described in more detail below, the openings formed in the passivation layer will subsequently be used for optical isolation grid formation.

[0070] Next, a barrier film, such as barrier film 378, is deposited on the sidewalls of the opening formed in the previous process. Figure 6B . In an example embodiment where the opening extends to the passivation layer, a barrier film is also deposited on the bottom of the opening (e.g., directly on the passivation layer). In an example embodiment, the barrier film is a non-silicon based film, such as a titanium nitride film. Similar to amorphous silicon, titanium nitride (TiN) may be advantageously employed because it exhibits high etching selectivity compared to silicon oxide. In an example embodiment, the barrier film is deposited such that its thickness is less than or equal to about half (1 / 2) of the thickness of the light attenuation layer.

[0071] Next, a metal grid material, such as tungsten, is deposited into the opening. Figure 6C . A metal grid material is also deposited so as to cover any exposed sacrificial material. After the metal grid material is deposited, chemical mechanical polishing may be performed on the deposited metal grid material.

[0072] The manufacturing method further includes patterning and etching the metal grid material to form an optical isolation barrier grid structure, such as the optical isolation barrier grid structure 344. For example, the process first removes the metal grid material to the level (e.g., height) of the sacrificial material. The process then removes the sacrificial material to expose both the light attenuation layer and the barrier film (on the inner and outer sidewalls of the metal grid material), such as Fig.6DIn an example embodiment, ammonium hydroxide (NH4OH) may be used in the sacrificial material removal process. In an example embodiment, since the light attenuation layer LAL is deposited first, the optical isolation grid structure may be formed in a self-aligned process. Due to the example method, the optical isolation grid structure and the light attenuation layer are structurally connected. In an example, the optical isolation grid structure and the light attenuation layer may be offset together depending on the pixel position in the pixel array in consideration of the chief ray angle.

[0073] Once the sacrificial material is removed to expose the light attenuation layer LAL, such as by a photoresist and etching process, those portions of the light attenuation layer disposed over the area of ​​the second photodiode (eg, the large photodiode) are removed. Fig. 6F Of course, a photoresist PR may be used to protect a light attenuation layer (eg, light attenuation layer 340) disposed above a plurality of first photodiodes (eg, small photodiodes), as shown in FIG. Fig. 6E As shown in .

[0074] The method may also include other process steps. For example, an additional dielectric buffer layer, such as an oxide layer 380, may be formed to surround the exposed surface of the metal grid material, such as the optical isolation grid structure 344, such as Figure 6G This includes forming an additional buffer oxide layer on the sidewalls of the optical isolation grid structure directly above the barrier film 378. An additional buffer oxide layer is also formed over the remaining light attenuation layer 340 (i.e., the light attenuation layer over the small photodiode). In some example embodiments, a buffer layer may also be formed over and coupled to the passivation layer 348 in order to increase the buffer thickness between the photodiode and other structures of the pixel cell. Other process steps may be performed, such as color filter array formation and microlens formation, which results in Figure 6H In some example embodiments, the buffer layer and the passivation layer may be formed of the same material, such as silicon dioxide.

[0075] The present application may quote quantity and number. Unless specifically stated, such quantity and number should not be considered as restrictive, but rather illustrate possible quantities or numbers associated with the present application. In addition, in this regard, the present application may use the term "multiple" to refer to quantity or number. In this regard, the term "multiple" means any number greater than one, for example, two, three, four, five, etc. The terms "approximately", "approximately", "close to", etc. represent the positive or negative 5% of the stated value. For the purposes of this disclosure, the phrase "at least one of A, B, and C" for example represents (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C), including all further possible arrangements when listing more than three elements. And as used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0076] The above description of the illustrated examples of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to be limiting to the precise form disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure as claimed. In fact, it should be understood that specific example voltages, currents, frequencies, power range values, times, etc. are provided for explanation purposes and other values ​​may also be employed in other embodiments and examples according to the teachings of the present disclosure.

[0077] These modifications may be made to the examples of the disclosed subject matter in light of the above detailed description. The terms used in the appended claims should not be construed to limit the claimed subject matter to the specific embodiments disclosed in the specification and the claims. Instead, the scope is to be determined entirely by the appended claims, which are to be interpreted in accordance with established principles of claim interpretation. The specification and drawings are therefore to be regarded as illustrative rather than restrictive.

Claims

1. A split pixel unit, comprising: a semiconductor substrate having a light receiving surface; a first photodiode disposed in the semiconductor substrate and capable of photogenerating image charge in response to incident light; a second photodiode disposed in the semiconductor substrate adjacent to the first photodiode, the second photodiode capable of photogenerating image charge in response to the incident light, wherein the second photodiode is more sensitive to the incident light than the first photodiode; A first optical isolation grid section and a second optical isolation grid section are disposed on the light receiving surface of the semiconductor substrate to surround an exposure region of the first photodiode, the first optical isolation grid section and the second optical isolation grid section having a top surface facing the incident light, and inner and outer sidewalls; a light attenuating layer disposed adjacent to the inner sidewalls of the first optical isolation grid segment and the second optical isolation grid segment and optically aligned with the first photodiode, wherein the first optical isolation grid segment and the second optical isolation grid segment extend directly to the vicinity of the light attenuating layer, partially extend through the light attenuating layer, or extend completely through the light attenuating layer, such that the light attenuating layer is structurally connected to the first optical isolation grid segment and the second optical isolation grid segment, covering the exposure area of ​​the first photodiode; and A barrier film is directly disposed on the inner side walls and bottom surfaces of the first optical isolation grating segment and the second optical isolation grating segment, wherein the barrier film is at least partially disposed between the light attenuation layer and the inner side walls of the first optical isolation grating segment and the second optical isolation grating segment, wherein the light attenuation layer is a planar layer directly contacting the barrier film.

2. The split pixel unit according to claim 1 further comprises a buffer layer and a color filter, each of the buffer layer and the color filter being disposed between the inner side walls of the first optical isolation grating segment and the second optical isolation grating segment and optically aligned with the first photodiode, wherein the buffer layer directly contacts the barrier film and the light attenuation layer, and wherein the buffer layer is disposed between the light attenuation layer and the color filter.

3. The split pixel unit according to claim 1 further comprises a first trench isolation structure and a second trench isolation structure disposed in the semiconductor substrate between the first photodiode and the second photodiode, wherein the first optical isolation grid segment and the second optical isolation grid segment are substantially aligned with the first trench isolation structure and the second trench isolation structure. 4 . The split pixel unit of claim 1 , wherein the light attenuation layer is adjacent to the barrier film disposed directly on the inner sidewalls of the first optical isolation grid segment and the second optical isolation grid segment. 5 . The split pixel cell of claim 4 , wherein the split pixel cell further comprises a second barrier film disposed directly on the outer sidewalls of the first optical isolation grid section and the second optical isolation grid section.

6. The split pixel unit of claim 5, further comprising a buffer layer disposed over the first optical isolation grid segment and the second optical isolation grid segment and the light attenuation layer, wherein the buffer layer is disposed directly on the top surfaces of the first optical isolation grid segment and the second optical isolation grid segment. 7 . The split pixel cell of claim 1 , further comprising a passivation layer disposed directly on the light receiving surface of the semiconductor substrate, a section of the passivation layer disposed between the first photodiode and the light attenuation layer.

8. The split pixel unit according to claim 1 further comprises a plurality of photodiode regions, wherein one photodiode region included in the plurality of photodiode regions is configured as the first photodiode and the remaining photodiode regions included in the plurality of photodiode regions are each configured as the second photodiode, wherein the second photodiode has a full well capacity greater than a full well capacity of the first photodiode. 9 . The split pixel cell of claim 8 , wherein the remaining photodiode regions configured as the second photodiode are arranged to surround the photodiode region configured as the first photodiode.

10. The split pixel cell of claim 1 , further comprising a color filter layer disposed on the light receiving surface of the semiconductor substrate, wherein the first optical isolation grid segment and the second optical isolation grid segment divide the color filter layer into a plurality of color filters, wherein the light attenuating layer is in close proximity to the barrier film disposed directly on the inner sidewalls of the first optical isolation grating section and the second optical isolation grating section, wherein the barrier film is close to the entire inner sidewall and the bottom surface of the first optical isolation grid section and the second optical isolation grid section, and Wherein a buffer layer is further disposed directly over the barrier film and over the top surfaces of the first optical isolation grating segment and the second optical isolation grating segment.

11. The split pixel unit according to claim 1 further comprises a color filter disposed between the first optical isolation grid segment and the second optical isolation grid segment, wherein the barrier film is disposed between the first optical isolation grid segment and the color filter, and wherein the barrier film is further disposed between the second optical isolation grid segment and the color filter. 12 . The split pixel unit of claim 1 , wherein the barrier film is further disposed at least partially between the light receiving surface of the semiconductor substrate and the bottom surface of the first optical isolation grid segment or the second optical isolation grid segment. 13 . The split pixel unit according to claim 1 , wherein a thickness of the barrier film is less than or equal to half a thickness of the light attenuation layer covering the exposure area of ​​the first photodiode.

14. The split pixel unit of claim 1, wherein the barrier film and the light attenuation layer each comprise a common material.

15. The split pixel cell of claim 14, wherein the common material comprises titanium or titanium nitride.

16. The split pixel cell of claim 1, wherein the light attenuating layer is aligned with a bottom of the first optical isolation grid segment and the second optical isolation grid segment.

17. A method for manufacturing an image sensor, comprising: forming a light attenuation layer over a first surface of a semiconductor substrate, wherein the semiconductor substrate includes a plurality of first photodiodes and a plurality of second photodiodes, wherein each of the first photodiodes is arranged to be surrounded by the second photodiode, wherein each of the plurality of second photodiodes has a greater sensitivity to incident light than the plurality of first photodiodes, wherein the light attenuation layer covers the first surface across the plurality of first photodiodes and the plurality of second photodiodes, wherein the first surface corresponds to a light receiving surface of the semiconductor substrate; Afterwards depositing a sacrificial material layer on the light attenuation layer; forming an opening in the sacrificial material, the opening being positioned over and between each photodiode of the plurality of first photodiodes and the plurality of second photodiodes; depositing an optical isolation grid material into the opening to form an optical isolation grid structure over the semiconductor substrate, the optical isolation grid structure being disposed over and between each of the plurality of first photodiodes and the plurality of second photodiodes, the optical isolation grid structure defining a plurality of optical isolation grid segments each having a top surface arranged to surround an exposure region of the plurality of first photodiodes and inner and outer sidewalls, wherein the light attenuation layer is disposed adjacent to the inner sidewalls of the plurality of optical isolation grid segments and optically aligned with the plurality of first photodiodes, wherein forming the optical isolation grid structure over the semiconductor substrate further includes, before depositing the optical isolation grid material, depositing a barrier film material on the sidewalls and bottom of the opening to form the barrier film, wherein the barrier film is disposed between the light attenuation layer and the inner sidewalls of a first optical isolation grid segment and a second optical isolation grid segment included in the plurality of optical isolation grid segments; removing a section of the light attenuating layer above the plurality of second photodiodes, thereby leaving only a first photodiode section of the light attenuating layer above the plurality of first photodiodes, such that the light attenuating layer is optically aligned with the plurality of first photodiodes, and wherein the light attenuating layer is structurally connected to the first optical isolation grid section and the second optical isolation grid section, covering the exposure area of ​​a first photodiode included in the plurality of first photodiodes; as well as A buffer layer is formed over the optical isolation grid structure and the first photodiode segment of the light attenuation layer, wherein the buffer layer is disposed directly on the top surfaces of the first and second optical isolation grid segments.

18. The method of claim 17, further comprising, before forming the light attenuation layer over the first surface of the semiconductor substrate, forming a passivation layer on the first surface of the semiconductor substrate, wherein the opening extends directly adjacent to the passivation layer toward the first surface of the semiconductor substrate. The method of claim 18 , wherein the opening extends to a depth D into the passivation layer.

20. The method of claim 17, wherein the semiconductor substrate includes a deep trench isolation structure disposed between each photodiode of the plurality of first photodiodes and each of the plurality of second photodiodes, wherein the plurality of optical isolation grid segments are optically aligned with the deep trench isolation structure.

21. A split pixel unit, comprising: a semiconductor substrate having a light receiving surface; a first photodiode disposed in the semiconductor substrate and capable of photogenerating image charge in response to incident light; a second photodiode disposed in the semiconductor substrate adjacent to the first photodiode, the second photodiode capable of photogenerating image charge in response to the incident light, wherein the second photodiode is more sensitive to the incident light than the first photodiode; A first optical isolation grid section and a second optical isolation grid section are disposed on the light receiving surface of the semiconductor substrate to surround an exposure region of the first photodiode, the first optical isolation grid section and the second optical isolation grid section having a top surface facing the incident light, and inner and outer sidewalls; a light attenuating layer disposed adjacent to the inner sidewalls of the first and second optical isolation grid segments and optically aligned with the first photodiode, wherein the light attenuating layer is structurally connected to the first and second optical isolation grid segments, covering the exposure area of ​​the first photodiode; a barrier film disposed directly on the inner sidewalls and bottom surfaces of the first and second optical isolation grating segments, wherein the barrier film is at least partially disposed between the light attenuation layer and the inner sidewalls of the first and second optical isolation grating segments; and A buffer layer and a color filter, each of which is disposed between the inner side walls of the first optical isolation grating segment and the second optical isolation grating segment and optically aligned with the first photodiode, wherein the buffer layer directly contacts the barrier film and the light attenuation layer, and wherein the buffer layer is disposed between the light attenuation layer and the color filter.

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