Array substrate and display panel

Abstract

The application provides an array substrate and a display panel. The array substrate comprises a substrate, a conductive layer and a power supply signal line which are sequentially stacked. An auxiliary conductive layer is further arranged in the array substrate. The power supply signal line is electrically connected with the auxiliary conductive layer. The auxiliary conductive layer is of the same layer and material as the conductive layer. The auxiliary conductive layer can increase the thickness of the power supply signal line, increase the cross-sectional area of the power supply signal line and reduce the voltage drop on the power supply signal line. Therefore, the array substrate and the display panel provided by the application can reduce the voltage drop of the level signal line, so that the power supply effect of the array substrate is better, thereby improving the display effect of the display panel.

Description

Technical Field

[0001] This application relates to the field of display panel technology, and in particular to an array substrate and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) display panels are increasingly widely used due to their advantages such as light weight, self-illumination, wide viewing angle, low driving signal, high luminous efficiency, low power consumption, and fast response speed.

[0003] In related technologies, the display panel includes an array substrate and a device layer. The array substrate has a low-level signal line. One end of the low-level signal line is electrically connected to a power chip, and the other end of the low-level signal line is electrically connected to a cathode in the device layer, thereby providing a low-level signal to the cathode.

[0004] However, the voltage drop of the aforementioned low-level signal lines is relatively large, which affects the display effect of the display panel. Summary of the Invention

[0005] In view of at least one of the above-mentioned technical problems, embodiments of this application provide an array substrate and a display panel that can reduce the voltage drop of the level signal lines, thereby improving the power supply effect of the array substrate and thus improving the display effect of the display panel.

[0006] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0007] A first aspect of this application provides an array substrate, including a substrate, a conductive layer, and power supply signal lines stacked sequentially. An auxiliary conductive layer is also provided in the array substrate. The power supply signal lines are electrically connected to the auxiliary conductive layer, and the auxiliary conductive layer is made of the same material as the conductive layer.

[0008] The array substrate provided in this application embodiment may include a substrate, a conductive layer, and power supply signal lines stacked sequentially. The substrate provides support for subsequent structural film layers, and the power supply signal lines provide voltage signals to the device layers on the array substrate. An auxiliary conductive layer is also provided in the array substrate. The power supply signal lines are electrically connected to the auxiliary conductive layer. The auxiliary conductive layer increases the thickness of the power supply signal lines, thereby increasing the cross-sectional area (the cross-sectional area perpendicular to the length extension direction of the power supply signal lines) and reducing the voltage drop on the power supply signal lines. This results in better power supply performance of the array substrate, reducing the impact on the uniformity of display brightness of the display panel and ensuring the display effect of the display panel. The auxiliary conductive layer and the conductive layer are fabricated in the same layer and with the same material, allowing for simultaneous fabrication of both the auxiliary conductive layer and the conductive layer, simplifying the fabrication process of the array substrate and the display panel. Since the auxiliary conductive layer and the power supply signal lines are stacked along the thickness direction of the array substrate, increasing the thickness of the power supply signal lines increases their cross-sectional area. Compared to increasing the width of the power supply signal lines, this avoids excessively wide power supply signal lines, ensuring the screen-to-body ratio of the display panel and facilitating the achievement of narrow bezels.

[0009] In one possible implementation, a transistor is also included, which is located on a substrate; the transistor includes an active layer, a gate layer, a source layer and a drain layer stacked together, a gate insulating layer is disposed between the gate layer and the active layer, and the source layer and the drain layer are electrically connected to the source region and the drain region of the active layer, respectively.

[0010] In this way, transistors are used to control the light emission of the device layer on the array substrate.

[0011] In one possible implementation, the conductive layer is located between the active layer and the substrate, and the orthographic projection of the conductive layer on the substrate covers the orthographic projection of the active layer on the substrate.

[0012] It is possible for the conductive layer to include a shielding layer.

[0013] In this way, the conductive layer can be used to shield the charge on the side of the substrate away from the transistor, preventing the charge from affecting the transistor.

[0014] In one possible implementation, the gate layer forms a conductive layer.

[0015] In this way, the gate layer and the auxiliary conductive layer can be fabricated simultaneously, simplifying the fabrication process.

[0016] In one possible implementation, the source layer and drain layer form a conductive layer.

[0017] In this way, the source layer, drain layer, and auxiliary conductive layer can be fabricated simultaneously, simplifying the fabrication process.

[0018] In one possible implementation, the array substrate includes a display area and a non-display area, with the non-display area surrounding the outer periphery of the display area;

[0019] The power supply signal lines include low-level signal lines, which are located in the non-display area, and at least part of the auxiliary conductive layer is located in the non-display area;

[0020] It is possible to have part of the auxiliary conductive layer located in the display area, and the auxiliary conductive layer located in the non-display area electrically connected to the auxiliary conductive layer located in the display area.

[0021] This allows for various power supply signal line configurations, making it suitable for a wide range of scenarios.

[0022] In one possible implementation, an insulating layer is also included, located between the auxiliary conductive layer and the power supply signal line. The insulating layer has vias, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the power supply signal line on the substrate. The auxiliary conductive layer and the power supply signal line are electrically connected through the vias.

[0023] This makes it easier and more convenient to connect the auxiliary conductive layer to the power supply signal line.

[0024] In one possible implementation, the auxiliary conductive layer comprises multiple layers, which are stacked and electrically connected along the thickness direction of the array substrate.

[0025] In this way, the auxiliary conductive layer is thicker and the power supply signal line has lower resistance, which can better ensure the display effect of the display panel.

[0026] In one possible implementation, a barrier is also included, which is located in the non-display area and on the side of the low-level signal line away from the substrate.

[0027] The orthographic projection of the auxiliary conductive layer onto the substrate at least partially overlaps with the orthographic projection of the enclosure onto the substrate.

[0028] In this way, the auxiliary conductive layer can increase the height of the enclosure, and the enclosure has a better blocking effect.

[0029] A second aspect of this application provides a display panel, including a device layer and an array substrate as described in the first aspect, wherein the device layer is stacked on the array substrate.

[0030] The display panel provided in this application embodiment includes an array substrate, which may include a substrate, a conductive layer, and power supply signal lines stacked sequentially. The substrate provides support for subsequent structural film layers, and the power supply signal lines provide voltage signals to the device layers on the array substrate. An auxiliary conductive layer is also provided in the array substrate, and the power supply signal lines are electrically connected to the auxiliary conductive layer. The auxiliary conductive layer increases the thickness of the power supply signal lines, thereby increasing the cross-sectional area (the cross-sectional area perpendicular to the length extension direction of the power supply signal lines), reducing the voltage drop on the power supply signal lines, and improving the power supply effect of the array substrate. This reduces the impact on the uniformity of the display brightness of the display panel and ensures the display effect of the display panel. The auxiliary conductive layer and the conductive layer are fabricated in the same layer and with the same material, allowing for simultaneous fabrication of both the auxiliary conductive layer and the conductive layer, simplifying the fabrication process of the array substrate and the display panel. Since the auxiliary conductive layer and the power supply signal lines are stacked along the thickness direction of the array substrate, increasing the thickness of the power supply signal lines increases their cross-sectional area. Compared to increasing the width of the power supply signal lines, this avoids excessively wide power supply signal lines, ensuring the screen-to-body ratio of the display panel and facilitating the achievement of narrow bezels.

[0031] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A top view of the display panel provided in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of the structure of the array substrate and device layer of the display area provided in the embodiments of this application;

[0035] Figure 3 This is a schematic diagram of the structure of the array substrate for the non-display area provided in an embodiment of this application.

[0036] Explanation of reference numerals in the attached figures:

[0037] 100 - Display panel; 100a - Display area; 100b - Non-display area;

[0038] 101 - Array substrate; 102 - Device layer; 103 - LTPS thin-film transistor;

[0039] 104 - MO thin-film transistor; 105 - capacitor structure; 111 - first active layer;

[0040] 112 - First gate layer; 113 - First source / drain layer; 121 - Second active layer;

[0041] 123 - Bottom gate layer; 124 - Top gate layer; 125 - Second source / drain layer;

[0042] 131 - First capacitor electrode; 132 - Second capacitor electrode; 140 - Substrate;

[0043] 141-First flexible substrate; 142-First barrier layer; 143-Second flexible substrate;

[0044] 144 - Second barrier layer; 150 - Insulating layer; 151 - First insulating layer;

[0045] 152 - Second insulating layer; 153 - Third insulating layer; 154 - Fourth insulating layer;

[0046] 155 - Fifth insulating layer; 156 - Buffer layer; 157 - Planarization layer;

[0047] 158 - First planarization layer; 159 - Second planarization layer; 160 - ELVSS signal line;

[0048] 171-Anode layer; 172-Auxiliary conductive layer; 173-Shielding layer;

[0049] 174 - Enclosure component; 175 - Scan line; 176 - Launch control line;

[0050] 177 - Reset line; 178 - Connector line; 181 - Pixel limiting layer;

[0051] 182 - Encapsulation layer. Detailed Implementation

[0052] In related technologies, a display panel may include an array substrate and a device layer stacked on the array substrate. The array substrate contains an ELVSS signal line, one end of which is electrically connected to an ELVSS power supply, and the other end of which is electrically connected to a cathode layer in the device layer, thereby enabling the ELVSS power supply to provide an ELVSS signal to the device layer.

[0053] However, due to the resistance of the ELVSS signal line, there is a significant voltage drop (IR-drop) along the direction from near to far from the ELVSS power supply. This results in poor power supply performance of the array substrate, significantly impacting the uniformity of display brightness and thus affecting the display effect. Increasing the width of the ELVSS signal line can reduce its resistance and thus the voltage drop. However, increasing the width of the ELVSS signal line results in it occupying a larger area of ​​the display panel, reducing the screen-to-body ratio and hindering the achievement of narrow bezels.

[0054] Based on at least one of the aforementioned technical problems, embodiments of this application provide an array substrate and a display panel. The array substrate may include a substrate, a conductive layer, and power supply signal lines stacked sequentially. The substrate provides support for subsequent structural film layers, and the power supply signal lines provide voltage signals to the device layers on the array substrate. An auxiliary conductive layer is also provided in the array substrate. The power supply signal lines are electrically connected to the auxiliary conductive layer. The auxiliary conductive layer increases the thickness of the power supply signal lines, thereby increasing the cross-sectional area (cross-sectional area perpendicular to the length extension direction of the power supply signal lines) and reducing the voltage drop on the power supply signal lines. This results in better power supply performance of the array substrate, reducing the impact on the uniformity of display brightness of the display panel and ensuring the display effect of the display panel. The auxiliary conductive layer and the conductive layer are fabricated in the same layer and with the same material, allowing for simultaneous fabrication of both the auxiliary conductive layer and the conductive layer, simplifying the fabrication process of the array substrate and the display panel. Since the auxiliary conductive layer and the power supply signal lines are stacked along the thickness direction of the array substrate, increasing the thickness of the power supply signal lines increases their cross-sectional area. Compared to increasing the width of the power supply signal lines, this avoids excessively wide power supply signal lines, ensuring a high screen-to-body ratio and facilitating the achievement of narrow bezels.

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] The following will combine Figures 1-3 The display panel 100 provided in the embodiments of this application will be described.

[0057] like Figure 1As shown, this embodiment provides a display panel 100, which can be applied to display devices such as electronic paper, mobile phones, tablet computers, televisions, monitors, laptops, digital photo frames, smart bracelets, smartwatches, supercomputers, navigators, and other mobile or fixed terminals with display panels 100.

[0058] The display panel 100 can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro LED or μLED) display panel, or a liquid crystal display (LCD) display panel.

[0059] This application uses an OLED display panel as an example to illustrate the embodiments.

[0060] The display panel 100 may include a light-emitting surface and a backlight surface that are arranged opposite to each other. The light-emitting surface is used to display images, and the backlight surface is the surface opposite to the light-emitting surface along the thickness direction of the display panel 100.

[0061] like Figure 1 As shown, the display panel 100 may include a display area 100a and a non-display area 100b, and the non-display area 100b may surround the outer periphery of the display area 100a.

[0062] like Figure 2 As shown, the display panel 100 may include an array substrate 101 and a device layer 102 located on the array substrate 101. The array substrate 101 has multiple driving units disposed therein, which can be arranged in an array. The driving units are electrically connected to the device layer 102 and are used to control the light emission of the device layer 102. Each driving unit may include a thin-film transistor (TFT) and a capacitor structure 105. The thin-film transistor may also be simply referred to as a transistor.

[0063] The thin-film transistors can include at least one of metal oxide (MO) thin-film transistors and low-temperature polycrystalline silicon (LTPS) thin-film transistors. For example, low-temperature polycrystalline oxide (LTPO) technology can be used, simultaneously utilizing LTPS thin-film transistor 103 and MO thin-film transistor 104 as thin-film transistors in the driving unit. LTPS thin-film transistor 103 can serve as a driving thin-film transistor, exhibiting high mobility, reducing driving voltage, and achieving high refresh rates and high resolutions; MO thin-film transistor 104 can serve as a switching thin-film transistor, exhibiting low leakage current, enabling the display panel 100 to maintain good display performance at low frame rates and reducing the power consumption of the display panel 100. LTPO combines the advantages of both types of thin-film transistors.

[0064] This application uses an example of having both LTPS thin-film transistor 103 and MO thin-film transistor 104 for illustration.

[0065] The device layer 102 provided in the embodiments of this application will be described below.

[0066] like Figure 2 As shown, device layer 102 may include an anode layer 171 and a cathode layer (not shown in the figure), with the anode layer 171 located on the side of the cathode layer facing the array substrate 101. The anode layer 171 may be a pixel electrode, and the cathode layer may be a common electrode.

[0067] Device layer 102 also includes a pixel layer and a pixel defining layer 181. The pixel layer is located between the anode layer 171 and the cathode layer. The pixel layer generally includes multiple pixels, which can be arranged in an array. The multiple pixels can include, but are not limited to, red pixels, green pixels, and blue pixels. In other examples, the multiple pixels may also include white pixels. The pixel defining layer 181 is located between two adjacent pixels and can be disposed around the periphery of the pixel.

[0068] Device layer 102 may further include at least one of hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer.

[0069] The array substrate 101 provided in the embodiments of this application will be described below.

[0070] like Figure 2 As shown, the array substrate 101 may include a substrate 140 and thin-film transistors located on the substrate 140, with the thin-film transistors located on the side of the device layer 102 facing the substrate 140.

[0071] Substrate 140 can provide support for subsequent structural film layers. In some examples, substrate 140 can be a rigid substrate, for example, the material of the rigid substrate can be glass. In other examples, substrate 140 can be a flexible substrate, and the material of the flexible substrate can include at least one selected from polyimide (PI), polyethylene terephthalate, polyethylene naphthalate, polyethylene, polyacrylate, polyetherimide, polycarbonate, polyarylate, and polyethersulfone.

[0072] The embodiments in this application are illustrated using a flexible substrate as an example.

[0073] Specifically, the substrate 140 can be a single-layer structure or a multi-layer structure.

[0074] For example, substrate 140 may include a first flexible substrate 141 and a first barrier layer 142 stacked sequentially; alternatively, substrate 140 may include a first flexible substrate 141, a first barrier layer 142, and a second flexible substrate 143 stacked sequentially; or alternatively, substrate 140 may include a first flexible substrate 141, a first barrier layer 142, a second flexible substrate 143, and a second barrier layer 144 stacked sequentially. The materials of the first barrier layer 142 and the second barrier layer 144 may be silicon oxide, silicon nitride, silicon oxynitride, etc., used to prevent substances such as water vapor and oxygen from entering the thin-film transistor on substrate 140, thus avoiding any impact on the performance of the thin-film transistor.

[0075] A thin-film transistor may include an active layer, a gate layer, a source layer, and a drain layer, wherein the source layer and the drain layer together form a source-drain layer, and the source layer and the drain layer are electrically connected to the source region and the drain region of the active layer, respectively.

[0076] like Figure 2 As shown, the active layer, gate layer, and source / drain layer of the LTPS thin-film transistor 103 are a first active layer 111, a first gate layer 112, and a first source / drain layer 113. The first active layer 111 can be a low-temperature polycrystalline silicon semiconductor layer. The first gate layer 112 is located on the side of the first active layer 111 that is away from the substrate 140, and the first source / drain layer 113 is located on the side of the first gate layer 112 that is away from the substrate 140.

[0077] The active layer, gate layer, and source / drain layer of the MO thin-film transistor 104 are a second active layer 121, a second gate layer, and a second source / drain layer 125, respectively. The second active layer 121 can be formed of at least one of indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and aluminum zinc oxide (AZO). The second gate layer can include at least one of a bottom gate layer 123 and a top gate layer 124, wherein the bottom gate layer 123 is located on the side of the second active layer 121 facing the substrate 140, the second source / drain layer 125 is located on the side of the second active layer 121 away from the substrate 140, and the top gate layer 124 is located between the second source / drain layer 125 and the second active layer 121. This application uses an MO thin-film transistor 104 having both a bottom gate layer 123 and a top gate layer 124 as an example for illustration.

[0078] A buffer layer 156 is disposed between the substrate 140 and the first active layer 111. The buffer layer 156 can prevent water and oxygen from penetrating through the substrate 140 and entering the thin-film transistor to cause corrosion. The buffer layer 156 may include a first buffer layer and a second buffer layer stacked together, with the first buffer layer located on the side of the second buffer layer closer to the substrate 140.

[0079] like Figure 2 As shown, a shielding layer 173 can be disposed between the buffer layer 156 and the substrate 140. The shielding layer 173 can be formed of a conductive material and is used to shield the charge on the substrate 140 side, preventing the charge from affecting the active layers (first active layer 111 and / or second active layer 121) of the thin-film transistor. For example, the orthographic projection of the first active layer 111 onto the substrate 140 can lie within the orthographic projection of the shielding layer 173 onto the substrate 140, thereby preventing the charge from affecting the first active layer 111. Similarly, the orthographic projection of the second active layer 121 onto the substrate 140 can lie within the orthographic projection of the shielding layer 173 onto the substrate 140, thereby preventing the charge from affecting the second active layer 121.

[0080] A first insulating layer 151 is disposed between the first active layer 111 and the first gate layer 112. A bottom gate layer 123 is located on the side of the first gate layer 112 facing away from the substrate 140, and a second insulating layer 152 is disposed between the bottom gate layer 123 and the first gate layer 112. A third insulating layer 153 is disposed between the bottom gate layer 123 and the second active layer 121. A fourth insulating layer 154 is disposed between the second active layer 121 and the top gate layer 124. A fifth insulating layer 155 is disposed on the side of the top gate layer 124 facing away from the substrate 140. A first source / drain layer 113 and a second source / drain layer 125 are disposed on the side of the fifth insulating layer 155 facing away from the substrate 140. The first source / drain layer 113 and the second source / drain layer 125 can be fabricated in the same layer and with the same material, thereby simplifying the fabrication process. In addition, since the second active layer 121 is located on the side of the first active layer 111 away from the substrate 140, the high-temperature process during the fabrication of the first active layer 111 is avoided from affecting the second active layer 121.

[0081] It should be noted that "same layer, same material" in the embodiments of this application refers to forming a base film layer from the same material, and then, after patterning and / or other processing of the base film layer, forming various structural film layers from different parts of the base film layer. The processing processes for the different structural film layers can be the same or different, and the different structural film layers can have the same or different thicknesses, and can also be on the same horizontal plane or different horizontal planes.

[0082] like Figure 2 As shown, a planarization layer 157 may be disposed on the side of the first source / drain layer 113 and the second source / drain layer 125 facing away from the substrate 140. The device layer 102 is located on the side of the planarization layer 157 facing away from the substrate 140. The planarization layer 157 provides good planar support for the subsequent formation of the device layer 102. The material of the planarization layer 157 can be inorganic materials such as silicon oxide and silicon nitride, or organic materials such as polyimide (PI), polyacrylate, epoxy resin, polyethylene (PE), polypropylene, polystyrene, polyethylene terephthalate, polymethyl methacrylate (PMMA), polyethylene terephthalate, or polyimide, etc.

[0083] like Figure 2As shown, the capacitor structure 105 includes a first capacitor electrode 131 and a second capacitor electrode 132 stacked and insulated from each other. The second capacitor electrode 132 is located on the side of the first capacitor electrode 131 facing away from the substrate 140. Any two of the first gate layer 112, bottom gate layer 123, top gate layer 124, first source / drain layer 113, and second source / drain layer 125 can be fabricated in the same layer and with the same material as the first capacitor electrode 131 and the second capacitor electrode 132. For example, the first capacitor electrode 131 can be fabricated in the same layer and with the same material as the first gate layer 112, and the second capacitor electrode 132 can be fabricated in the same layer and with the same material as the bottom gate layer 123, thereby simplifying the fabrication process.

[0084] In this embodiment, a power supply signal line may be provided in the array substrate 101. The power supply signal line is used to electrically connect to an external power supply, thereby providing a voltage signal to the device layer 102 to control the device layer 102 to emit light. For example, the external power supply may include an ELVDD power supply and an ELVSS power supply. The ELVDD power supply and the ELVSS power supply can be used as a high-level voltage source and a low-level voltage source, respectively, to drive the device layer 102 to emit light.

[0085] The ELVDD power supply can be electrically connected to the driving unit via a high-level (ELVDD) signal line. The driving unit is electrically connected to the anode layer 171 of the device layer 102, thereby providing a high-level signal to the anode layer 171. The ELVDD signal line can be located in the display area 100a and the non-display area 100b of the display panel 100. The ELVDD signal line located in the display area 100a is used to electrically connect to the driving unit, and the ELVDD signal line located in the non-display area 100b is used to electrically connect the ELVDD signal line located in the display area 100a to an external ELVDD power supply.

[0086] The ELVSS power supply can be electrically connected to a low-level (ELVSS) signal line, and the ELVSS signal line 160 is electrically connected to the cathode layer of device layer 102, thereby providing a low-level signal to the cathode layer. For example... Figure 1 and Figure 3 As shown, the ELVSS signal line 160 can be located in the non-display area 100b. It can be electrically connected to the cathode layer by preparing an overlap layer of the same material as the anode layer 171. The overlap layer extends from the display area 100a to the non-display area 100b. The ELVSS signal line 160 located in the non-display area 100b is electrically connected to the cathode layer through the overlap layer.

[0087] like Figure 2As shown, the driving unit and the anode layer 171 can be electrically connected by a connecting line 178. The planarization layer 157 may include a first planarization layer 158 and a second planarization layer 159. The first planarization layer 158 is located on the side of the second planarization layer 159 facing the substrate 140, and the connecting line 178 is located between the first planarization layer 158 and the second planarization layer 159.

[0088] In some examples, the power supply signal line can be fabricated in the same layer and with the same material as the first source / drain layer 113 and the second source / drain layer 125, thereby simplifying the fabrication process. In other examples, the power supply signal line can be fabricated in the same layer and with the same material as the connecting line 178, thereby simplifying the fabrication process. In still other examples, the power supply signal line may include a first sub-signal line and a second sub-signal line that are stacked and electrically connected, with the first sub-signal line located on the side of the second sub-signal line facing the substrate 140. The first sub-signal line can be fabricated in the same layer and with the same material as the first source / drain layer 113 and the second source / drain layer 125, and the second sub-signal line can be fabricated in the same layer and with the connecting line 178, thereby increasing the thickness of the power supply signal line to reduce the voltage drop of the power supply signal line.

[0089] It is understandable that, such as Figure 3 As shown, the array substrate 101 may also include scan lines 175, transmit control lines 176, reset lines 177, etc., which can be fabricated in the same layer and with the same material as the first source / drain layer 113 and the second source / drain layer 125 and / or the connecting line 178. The principle is similar to that of the power supply signal line, and will not be described in detail here.

[0090] This application uses the ELVSS signal line 160, which includes a first sub-signal line and a second sub-signal line, as an example for illustration.

[0091] It is understood that the shielding layer 173, the first gate layer 112, the first capacitor electrode 131, the second capacitor electrode 132, the bottom gate layer 123, and the top gate layer 124 in the embodiments of this application are all conductive layers formed of conductive materials. An auxiliary conductive layer 172 can be prepared at the same time as any one or more conductive layers. The auxiliary conductive layer 172 is electrically connected to the ELVSS signal line 160. The auxiliary conductive layer 172 can increase the thickness of the ELVSS signal line 160, thereby increasing the cross-sectional area of ​​the ELVSS signal line 160, so as to reduce the voltage drop of the ELVSS signal line 160, so as to improve the power supply effect of the array substrate 101, reduce the impact of the ELVSS signal line 160 on the uniformity of the display brightness of the display panel 100, and thus ensure the display effect of the display panel 100. Furthermore, since the auxiliary conductive layer 172 is fabricated in the same layer and with the same material as any one or more of the aforementioned conductive layers, both the auxiliary conductive layer 172 and the conductive layer can be fabricated simultaneously, thereby simplifying the fabrication process of the array substrate 101 and the display panel 100. The auxiliary conductive layer 172 is disposed in the same layer as any one or more of the aforementioned conductive layers, meaning it reuses the existing conductive layer, thus not increasing the thickness of the array substrate 101. This ensures that the resistance of the ELVSS signal line 160 is reduced without affecting the thickness of the array substrate 101. Secondly, the auxiliary conductive layer 172 and the ELVSS signal line 160 are stacked along the thickness direction of the display panel 100, which is equivalent to increasing the cross-sectional area of ​​the ELVSS signal line 160 by increasing its thickness. Compared to increasing the width of the ELVSS signal line 160, this avoids the ELVSS signal line 160 becoming too wide, ensuring the screen-to-body ratio of the display panel 100 and facilitating the achievement of a narrow bezel.

[0092] Understandably, since the shielding layer 173 is mainly distributed in the display area 100a, a portion of the shielding layer 173 extends from the display area 100a into the non-display area 100b to be electrically connected to the ELVDD signal line of the non-display area 100b through vias, thereby providing a voltage signal to the shielding layer 173 and ensuring its shielding effect. The area of ​​the shielding layer 173 distributed in the non-display area 100b is relatively small (the width extending from the display area 100a to the non-display area 100b is narrow), therefore, a larger area can be provided for the auxiliary conductive layer 172 in the non-display area 100b. The auxiliary conductive layer 172 and the shielding layer 173 do not interfere with each other, thus effectively reducing the resistance of the ELVSS signal line 160 without affecting the shielding effect of the shielding layer 173 or the bezel width of the display panel 100.

[0093] For example, the auxiliary conductive layer 172 can be a single layer, and any one of the shielding layer 173, the first gate layer 112, the bottom gate layer 123, and the top gate layer 124 can be fabricated in the same layer and with the same material as the auxiliary conductive layer 172.

[0094] For example, the auxiliary conductive layer 172 can be multilayered. At least two of the shielding layer 173, the first gate layer 112, the bottom gate layer 123, and the top gate layer 124 can be fabricated in the same layer and with the same material as the auxiliary conductive layer 172, thereby forming at least two auxiliary conductive layers 172. The multilayered auxiliary conductive layers 172 are stacked and electrically connected along the thickness direction of the array substrate 101, thereby further increasing the thickness of the ELVSS signal line 160, better reducing the voltage drop of the ELVSS signal line 160, and ensuring the display effect of the display panel 100. For example, one auxiliary conductive layer 172 can be fabricated in the same layer and with the same material as the shielding layer 173, and the remaining auxiliary conductive layers 172 can be fabricated in the same layer and with the same material as any one or more of the first gate layer 112, the bottom gate layer 123, and the top gate layer 124.

[0095] In some embodiments, at least a portion of the auxiliary conductive layer 172 may be located in the non-display area 100b, and the auxiliary conductive layer 172 may be partially or entirely located in the non-display area 100b. The orthographic projection of the auxiliary conductive layer 172 located in the non-display area 100b onto the substrate 140 at least partially overlaps with the orthographic projection of the ELVSS signal line 160 onto the substrate 140, thereby facilitating the electrical connection between the auxiliary conductive layer 172 and the ELVSS signal line 160. Figure 2 and Figure 3 As shown, an insulating layer 150 is provided between the auxiliary conductive layer 172 and the ELVSS signal line 160. The insulating layer 150 can be formed by any one or more of the buffer layer 156, the first insulating layer 151, the second insulating layer 152, the third insulating layer 153, the fourth insulating layer 154, and the fifth insulating layer 155. Vias can be provided in the insulating layer 150. The auxiliary conductive layer 172 and the ELVSS signal line 160 are electrically connected through the vias. The orthographic projection of the vias on the substrate 140 can be located in the overlapping portion of the orthographic projections of the auxiliary conductive layer 172 and the ELVSS signal line 160 on the substrate 140.

[0096] In some embodiments, at least a portion of the auxiliary conductive layer 172 is located in the display area 100a. The auxiliary conductive layer 172 may be partially or entirely located in the display area 100a. The display area 100a has a large area, allowing for more and more flexible placement of the auxiliary conductive layer 172. In some examples, the auxiliary conductive layer 172 can be located in the display area 100a, and an overlap structure can be fabricated on the conductive layer in the array substrate 101. The ELVSS signal line 160 is electrically connected to the auxiliary conductive layer 172 in the display area 100a through the overlap structure. In other examples, the auxiliary conductive layer 172 can be located simultaneously in the display area 100a and non-display area 100b, further increasing the area of ​​the auxiliary conductive layer 172, better reducing the voltage drop of the ELVSS signal line 160, and ensuring the display effect of the display panel 100. The auxiliary conductive layer 172 located in the non-display area 100b is electrically connected to the auxiliary conductive layer 172 located in the display area 100a. The ELVSS signal line 160 is electrically connected to the auxiliary conductive layer 172 located in the non-display area 100b through a via, and then electrically connected to the auxiliary conductive layer 172 located in the display area 100a.

[0097] It should be noted that the configuration of the ELVDD signal line is similar to that of the ELVSS signal line 160, and will not be described again. The above embodiment mainly uses the electrical connection between the ELVSS signal line 160 and the auxiliary conductive layer 172 as an example. Of course, the ELVDD signal line can also be electrically connected to the auxiliary conductive layer 172. For example, the auxiliary conductive layer 172 can be electrically connected to the ELVSS signal line 160, thereby reducing the voltage drop of the ELVSS signal line 160 to ensure the display effect of the display panel 100. Alternatively, the auxiliary conductive layer 172 can be electrically connected to the ELVDD signal line, thereby reducing the voltage drop of the ELVDD signal line to ensure the display effect of the display panel 100. The configuration of the auxiliary conductive layer 172 is similar to that in the above embodiment, and will not be described again. Alternatively, the auxiliary conductive layer 172 may include a first auxiliary conductive layer and a second auxiliary conductive layer. The first auxiliary conductive layer is electrically connected to the ELVSS signal line 160, and the second auxiliary conductive layer is electrically connected to the ELVDD signal line, thereby simultaneously reducing the voltage drop of both the ELVSS and ELVDD signal lines. The arrangement of the first and second auxiliary conductive layers is similar to that of the auxiliary conductive layer 172 in the above embodiments, and will not be described again.

[0098] In this embodiment, as Figure 3As shown, an encapsulation layer 182 is disposed on the side of device layer 102 opposite to substrate 140. Encapsulation layer 182 can employ thin film encapsulation (TFE) technology and may include multiple encapsulation sub-film layers. Encapsulation layer 182 may include inorganic layers and / or organic layers. For example, encapsulation layer 182 may employ a film layer structure of overlapping inorganic / organic / inorganic layers. The inorganic layers are used to effectively block water and oxygen, while the organic layers are used to buffer stress within the inorganic layers.

[0099] In some embodiments, such as Figure 3 As shown, the array substrate 101 may include a barrier 174 located in the non-display area 100b. The barrier 174 may be annular. The barrier 174 is located on the side of the ELVSS signal line 160 facing away from the substrate 140. The barrier 174 is used to prevent material from the organic layer in the encapsulation layer 182 from overflowing to the outside of the barrier 174, thereby preventing water and oxygen intrusion caused by the overflow of organic layer material and improving the encapsulation effect.

[0100] The orthographic projection of the auxiliary conductive layer 172 onto the substrate 140 can at least partially overlap with the orthographic projection of the barrier member 174 onto the substrate 140. In this case, the auxiliary conductive layer 172 is located directly below the barrier member 174, which increases the height of the barrier member 174, improves its ability to block the organic layer material, reduces the risk of overflow, and improves the reliability of the package. For example, the orthographic projection of the auxiliary conductive layer 172 onto the substrate 140 can partially or completely overlap with the orthographic projection of the barrier member 174 onto the substrate 140.

[0101] The enclosure 174 may include at least one. When there is only one enclosure 174, its structure is relatively simple. When there are multiple enclosures 174, multiple annular enclosures 174 are sequentially nested from the inside out and spaced apart. In this case, multiple auxiliary conductive layers 172 can also be provided, with the orthographic projection of one auxiliary conductive layer 172 on the substrate 140 at least partially overlapping the orthographic projection of one enclosure 174 on the substrate 140. This increases the height of each enclosure, further reduces the risk of overflow, and improves the reliability of the package.

[0102] It should be noted that the shielding layer 173, connecting line 178, ELVDD signal line, ELVSS signal line 160, auxiliary conductive layer 172, anode layer 171, cathode layer, gate layer, source / drain layer, first capacitor electrode 131 and second capacitor electrode 132, etc., can be made of metals such as silver, copper, aluminum, and molybdenum, or alloys, or conductive oxides (such as indium tin oxide, indium zinc oxide, zinc oxide, and zinc aluminum oxide) or any one or more of these materials.

[0103] The buffer layer 156, the first insulating layer 151, the second insulating layer 152, the third insulating layer 153, the fourth insulating layer 154, and the fifth insulating layer 155 can be silicon nitride, silicon oxynitride, silicon oxide, or various novel organic insulating materials, or metal oxides with high dielectric constants such as aluminum oxide, tantalum oxide, etc.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes a substrate, a conductive layer, and power supply signal lines stacked sequentially. An auxiliary conductive layer is also provided in the array substrate. The power supply signal lines are electrically connected to the auxiliary conductive layer. The auxiliary conductive layer and the conductive layer are made of the same material and layer. The array substrate includes a display area and a non-display area; It also includes an insulating layer located between the auxiliary conductive layer and the power supply signal line; The power supply signal line includes a low-level signal line, which is located in the non-display area; The low-level signal line is located on the side of the insulating layer away from the substrate; It also includes a barrier, which is located in the non-display area, on the side of the low-level signal line away from the substrate, and is in direct contact with the low-level signal line; the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the barrier on the substrate. The number of the enclosure components is at least one; When there are multiple enclosure components, there are multiple auxiliary conductive layers. The multiple enclosure components are sequentially nested from the inside to the outside and spaced apart. The orthographic projection of one of the auxiliary conductive layers on the substrate at least partially overlaps with the orthographic projection of one of the enclosure components on the substrate, so as to increase the height of the enclosure components. The sides of the low-level signal line and the top surface not covered by the enclosure are covered by the encapsulation layer; the top surface and sides of the enclosure are covered by the encapsulation layer.

2. The array substrate according to claim 1, characterized in that, It also includes a transistor located on the substrate; the transistor includes an active layer, a gate layer, a source layer and a drain layer stacked together, a gate insulating layer is disposed between the gate layer and the active layer, and the source layer and the drain layer are electrically connected to the source region and the drain region of the active layer, respectively.

3. The array substrate according to claim 2, characterized in that, The conductive layer is located between the active layer and the substrate, and the orthogonal projection of the conductive layer on the substrate covers the orthogonal projection of the active layer on the substrate.

4. The array substrate according to claim 3, characterized in that, The conductive layer includes a shielding layer.

5. The array substrate according to claim 2, characterized in that, The gate layer forms the conductive layer.

6. The array substrate according to claim 2, characterized in that, The source layer and the drain layer form the conductive layer.

7. The array substrate according to any one of claims 1-6, characterized in that, The non-display area is located around the outer periphery of the display area; At least a portion of the auxiliary conductive layer is located in the non-display area.

8. The array substrate according to claim 7, characterized in that, A portion of the auxiliary conductive layer is located in the display area, and the auxiliary conductive layer located in the non-display area is electrically connected to the auxiliary conductive layer located in the display area.

9. The array substrate according to any one of claims 1-6, characterized in that, The insulating layer has a via, and the orthographic projection of the auxiliary conductive layer on the substrate at least partially overlaps with the orthographic projection of the power supply signal line on the substrate. The auxiliary conductive layer and the power supply signal line are electrically connected through the via.

10. The array substrate according to any one of claims 1-6, characterized in that, The auxiliary conductive layer comprises multiple layers, which are stacked and electrically connected along the thickness direction of the array substrate.

11. A display panel, characterized in that, It includes a device layer and an array substrate as described in any one of claims 1-10, wherein the device layer is stacked on the array substrate.

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