Planar high electron mobility transistor

Abstract

The application discloses a planar high electron mobility transistor, comprising: a heterojunction composed of a first semiconductor epitaxial layer and a second semiconductor epitaxial layer and a two-dimensional electron gas located at the interface of the heterojunction; a gate trench bottom surface of a trench gate is located at the bottom of the two-dimensional electron gas to cut off the two-dimensional electron gas; when a gate-source voltage is greater than or equal to a threshold voltage, a surface of the first semiconductor epitaxial layer covered by a gate conductive material layer side and a bottom surface forms an inversion layer, a source-drain two-dimensional electron gas is turned on to turn on the device; when the gate-source voltage is less than the threshold voltage, the source-drain two-dimensional electron gas is turned off to turn off the device. The application can realize the control of the on channel of the HEMTs by using the trench gate of the MOSFET, thereby facilitating the independent adjustment of the threshold voltage, the realization of the normally-off planar high electron mobility transistor, the adjustment of the drift region electric field, the uniform distribution of the drift region electric field, the improvement of the breakdown voltage of the device and the reduction of the specific on resistance and the size.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, in particular to a planar high electron mobility transistor (HEMT). BACKGROUND

[0002] Gallium nitride as a typical wide band gap semiconductor material, often as the manufacture of power semiconductor devices in various studies. Especially in the high temperature and high pressure field, because of its 3.4eV larger band gap, with 3MV / cm high breakdown field strength, high electron mobility and high thermal conductivity, gallium nitride material has a more obvious advantage. So far, the mainstream gallium nitride device is still concentrated in the research of planar HEMTs, the manufacturing process of such devices has gradually matured and has entered the market stage. However, the industry has not reached a consensus on the way to realize the normally-off gallium nitride HEMTs.

[0003] The existing power device has a relationship between specific on-resistance (Ron,sp) and breakdown voltage (Breakdown Voltage). The higher the breakdown voltage, the higher the specific on-resistance. For traditional power semiconductor devices, there is a physical limit of Ron,sp vs. BV, also known as the one-dimensional physical limit (1-D limit). SUMMARY

[0004] The technical problem to be solved by the present application is to provide a planar high electron mobility transistor which can cut off the two-dimensional electron gas, thereby facilitating independent adjustment of the threshold voltage and facilitating the realization of normally-off planar high electron mobility transistor; it can also facilitate the adjustment of the drift region electric field to make the drift region electric field distribution uniform, can improve the breakdown voltage of the device or reduce the specific on-resistance of the device under the condition of maintaining the breakdown voltage, and reduce the size of the device, thereby greatly reducing the energy loss of the device when turned on; it can be applied to gallium nitride material, fully exerting the advantages of gallium nitride material, reducing the cost of gallium nitride device manufacturing and simplifying the process flow.

[0005] To solve the above technical problems, the device unit of the planar high electron mobility transistor provided by the present application comprises:

[0006] A first semiconductor epitaxial layer and a second semiconductor epitaxial layer formed on the surface of the first semiconductor epitaxial layer, the first semiconductor epitaxial layer and the second semiconductor epitaxial layer form a first heterojunction and form a two-dimensional electron gas at the first heterojunction interface.

[0007] A trench gate, including a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filling the gate trench.

[0008] The gate trench passes through the second semiconductor epitaxial layer so that the bottom surface of the gate trench is in the first semiconductor epitaxial layer at the bottom of the two-dimensional electron gas, and the trench gate cuts the two-dimensional electron gas into a source-end two-dimensional electron gas and a drain-end two-dimensional electron gas.

[0009] The source metal layer and the first side surface of the gate trench have a spacing and form an ohmic contact with the source-end two-dimensional electron gas.

[0010] The drain metal layer and the second side surface of the gate trench have a spacing and form an ohmic contact with the drain-end two-dimensional electron gas.

[0011] The gate conductive material layer is connected to a gate metal layer.

[0012] When the gate-source voltage between the gate metal layer and the source metal layer is greater than or equal to a threshold voltage, the surface of the first semiconductor epitaxial layer covered by the side surface and the bottom surface of the gate conductive material layer forms an inversion layer, the inversion layer makes the source-end two-dimensional electron gas and the drain-end two-dimensional electron gas conductive and together form a conductive channel that makes the source metal layer and the drain metal layer conductive and thus makes the device conductive.

[0013] When the gate-source voltage between the gate metal layer and the source metal layer is less than the threshold voltage, the source-end two-dimensional electron gas and the drain-end two-dimensional electron gas are disconnected and the device is turned off.

[0014] Further improvement is that the planar high electron mobility transistor is an enhancement device, and the threshold voltage is greater than 0V.

[0015] Further improvement is that the first semiconductor epitaxial layer adopts a wide-bandgap semiconductor material, and the second semiconductor epitaxial layer adopts a wide-bandgap semiconductor material.

[0016] Further improvement is that the material of the first semiconductor epitaxial layer includes gallium nitride, and the material of the second semiconductor epitaxial layer includes aluminum gallium nitride.

[0017] Further improvement is that the first semiconductor epitaxial layer is formed on a buffer layer, and the buffer layer is formed on a substrate.

[0018] Further improvement is that the material of the substrate includes silicon or sapphire.

[0019] Further improvement is that a drift region is located between the drain metal layer and the second side surface of the gate trench, and a charge balancing structure is arranged in the drift region, and the charge balancing structure makes the drift region electric field distribution uniform when reverse biased.

[0020] Further improvement is that the charge balancing structure includes:

[0021] A third semiconductor epitaxial layer is arranged on the surface of the second semiconductor epitaxial layer of the drift region, and the material of the third semiconductor epitaxial layer comprises gallium nitride.

[0022] The interface of the second heterojunction formed by the third semiconductor epitaxial layer and the second semiconductor epitaxial layer can form bound charges, and the drift region electric field distribution is adjusted and made uniform by the bound charges at the interface of the second heterojunction.

[0023] Further improvement is that the third semiconductor epitaxial layer continuously covers the surface of the second semiconductor epitaxial layer of the drift region.

[0024] Further improvement is that the third semiconductor epitaxial layer on the surface of the second semiconductor epitaxial layer of the drift region is divided into one or more third semiconductor epitaxial layer sub-sections and one or more third semiconductor epitaxial layer interval regions, and the third semiconductor epitaxial layer sub-sections and the third semiconductor epitaxial layer interval regions are arranged alternately on the surface of the second semiconductor epitaxial layer of the drift region.

[0025] Further improvement is that the number of the third semiconductor epitaxial layer sub-sections is one, and the number of the third semiconductor epitaxial layer interval regions is one.

[0026] From the second side of the gate trench to the drain metal layer, the third semiconductor epitaxial layer sub-sections and the third semiconductor epitaxial layer interval regions are arranged in sequence; or from the second side of the gate trench to the drain metal layer, the third semiconductor epitaxial layer interval regions and the third semiconductor epitaxial layer sub-sections are arranged in sequence.

[0027] Further improvement is that the number of the third semiconductor epitaxial layer sub-sections is more than one, and the number of the third semiconductor epitaxial layer interval regions is less than the number of the third semiconductor epitaxial layer sub-sections by one.

[0028] From the second side of the gate trench to the drain metal layer, the third semiconductor epitaxial layer sub-sections and the third semiconductor epitaxial layer interval regions are arranged in sequence.

[0029] Further improvement is that the third semiconductor epitaxial layer sub-sections are formed by selective etching of the third semiconductor epitaxial layer after the third semiconductor epitaxial layer is formed by epitaxial growth.

[0030] Further improvement is that the thickness of the third semiconductor epitaxial layer is 5 nm or less.

[0031] Further improvement is that the charge balance structure comprises:

[0032] The thickness of the second semiconductor epitaxial layer in the direction from the second side of the gate trench to the drain metal layer has a varying structure, the bound charge density at the interface of the first heterojunction and thus the drift region electric field distribution are adjusted by adjusting the thickness of the second semiconductor epitaxial layer and the drift region electric field distribution is made uniform.

[0033] Further improvement is that the second semiconductor epitaxial layer is divided into two or more second semiconductor epitaxial layer sub-sections according to the thickness in the direction from the second side of the gate trench to the drain metal layer.

[0034] Further improvement is that the thickness of each of the second semiconductor epitaxial layer sub-sections increases in turn or decreases in turn or first increases in turn and then decreases in turn after increasing to the maximum value or first decreases in turn and then increases in turn after decreasing to the minimum value in the direction from the second side of the gate trench to the drain metal layer.

[0035] Further improvement is that each of the second semiconductor epitaxial layer sub-sections is obtained by etching process after the first formation of the second semiconductor epitaxial layer.

[0036] Alternatively, each of the second semiconductor epitaxial layer sub-sections is formed by multiple epitaxial and etching processes.

[0037] Further improvement is that the length of each of the second semiconductor epitaxial layer sub-sections is the same or different.

[0038] Further improvement is that the thickness of the second semiconductor epitaxial layer gradually increases according to a linear function or gradually decreases according to a linear function or first gradually increases according to a linear function and then gradually decreases according to a linear function after increasing to the maximum value or first gradually decreases according to a linear function and then gradually increases according to a linear function after decreasing to the minimum value in the direction from the second side of the gate trench to the drain metal layer.

[0039] Further improvement is that the material of the gate dielectric layer includes silicon oxide or aluminum oxide.

[0040] The gate conductive material layer includes a polysilicon gate or a metal gate.

[0041] Further improvement is that the first semiconductor epitaxial layer has a first conductivity type doping or a second conductivity type doping or is non-doped.

[0042] The present application can realize the truncation of the two-dimensional electron gas by forming the trench gate and penetrating the bottom of the gate trench of the trench gate under the two-dimensional electron gas, so that the formation of the conduction channel between the source and the drain is not controlled by the two-dimensional electron gas, but is controlled by the trench gate, and the control of the conduction and the turn-off of the conduction channel is realized by the inversion layer formed by the inversion of the first semiconductor epitaxial layer by the trench gate, that is, the present application can realize the control of the conduction channel of the HEMTs by the trench gate of the MOSFET, so that the planar high electron mobility transistor and the MOSFET can control the conduction and the turn-off of the conduction channel by the trench gate, thereby facilitating the independent adjustment of the threshold voltage of the planar high electron mobility transistor, such as adjusting the work function of the gate conductive material layer of the trench gate, the thickness of the gate dielectric layer, and the doping type and the doping concentration of the first semiconductor epitaxial layer to adjust the threshold voltage of the device, and the normally-off planar high electron mobility transistor is easily realized. The two-dimensional electron gas of the existing planar high electron mobility transistor is always on, which is a normally-on device, and the normally-off planar high electron mobility transistor is easily realized by the present application.

[0043] In addition, the present application can form a charge balance structure in the drift region between the trench gate and the drain metal layer and adjust the electric field distribution of the drift region through the charge balance structure, so that a uniform drift region electric field can be easily obtained, thereby improving the breakdown voltage of the device or reducing the specific on-resistance of the device while maintaining the breakdown voltage, and reducing the size of the device, thereby greatly reducing the energy loss of the device when turned on. The present application can be applied to gallium nitride material, fully exerting the advantages of gallium nitride material, reducing the cost of gallium nitride device manufacturing and simplifying the process flow.

[0044] The gallium nitride power device structure of the present application can easily adjust the threshold voltage, thereby manufacturing an enhancement mode transistor, making its application scenarios more widely used. Compared with the traditional high electron mobility transistor, the specific on-resistance of the existing power device is greatly reduced under the same breakdown voltage, the power loss of the power semiconductor device can be greatly reduced, energy saving and emission reduction are achieved, the advantages of gallium nitride device are fully exerted, the process flow is simplified, and the manufacturing cost is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0045] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0046] Figure 1 is a structure schematic diagram of the first embodiment of the planar high electron mobility transistor of the present application;

[0047] Figure 2 is a structure schematic diagram of the second embodiment of the planar high electron mobility transistor of the present application;

[0048] Figure 3is a structural schematic diagram of a planar high electron mobility transistor of a third embodiment of the present application;

[0049] Figure 3A is Figure 3 is a first structural schematic diagram corresponding to a case where the number of the third semiconductor epitaxial layer sub-sections is one and the number of the third semiconductor epitaxial layer interval regions is one;

[0050] Figure 3B is Figure 3 is a second structural schematic diagram corresponding to a case where the number of the third semiconductor epitaxial layer sub-sections is one and the number of the third semiconductor epitaxial layer interval regions is one;

[0051] Figure 3C is Figure 3 is a structural schematic diagram corresponding to a case where the number of the third semiconductor epitaxial layer sub-sections is two and the number of the third semiconductor epitaxial layer interval regions is one;

[0052] Figure 4 is a structural schematic diagram of a planar high electron mobility transistor of a fourth embodiment of the present application;

[0053] Figure 4A is Figure 4 is a structural schematic diagram corresponding to a case where the number of the second semiconductor epitaxial layer sub-sections is two;

[0054] Figure 5 is a structural schematic diagram of a planar high electron mobility transistor of a fifth embodiment of the present application;

[0055] Figure 5A is Figure 5 is a structural schematic diagram corresponding to a case where the number of the second semiconductor epitaxial layer sub-sections is two;

[0056] Figure 6 is a structural schematic diagram of a planar high electron mobility transistor of a sixth embodiment of the present application;

[0057] Figure 7 is a structural schematic diagram of a planar high electron mobility transistor of a seventh embodiment of the present application;

[0058] Figure 8 is a structural schematic diagram of a planar high electron mobility transistor of an eighth embodiment of the present application;

[0059] Figure 9 is a structural schematic diagram of a planar high electron mobility transistor of a ninth embodiment of the present application;

[0060] Figure 10 is a structural schematic diagram of a planar high electron mobility transistor of a tenth embodiment of the present application;

[0061] Figure 11is a structural schematic diagram of a planar high electron mobility transistor of an eleventh embodiment of the present application. DETAILED DESCRIPTION

[0062] A planar high electron mobility transistor of a first embodiment of the present application:

[0063] As shown in Figure 1 is a structural schematic diagram of a planar high electron mobility transistor of a first embodiment of the present application; a device unit of the planar high electron mobility transistor of the first embodiment of the present application includes:

[0064] A first semiconductor epitaxial layer 3 and a second semiconductor epitaxial layer 4 formed on a surface of the first semiconductor epitaxial layer 3, the first semiconductor epitaxial layer 3 and the second semiconductor epitaxial layer 4 constitute a first heterojunction and form a two-dimensional electron gas at an interface of the first heterojunction.

[0065] A trench gate, including a gate trench, a gate dielectric layer 7 formed on an inner side surface of the gate trench, and a gate conductive material layer 8 filling the gate trench.

[0066] The gate trench passes through the second semiconductor epitaxial layer 4 so that a bottom surface of the gate trench is located in the first semiconductor epitaxial layer at a bottom of the two-dimensional electron gas, and the trench gate cuts off the two-dimensional electron gas into a source-end two-dimensional electron gas and a drain-end two-dimensional electron gas.

[0067] A source metal layer 5 and a first side surface of the gate trench have a spacing and form an ohmic contact with the source-end two-dimensional electron gas.

[0068] A drain metal layer 6 and a second side surface of the gate trench have a spacing and form an ohmic contact with the drain-end two-dimensional electron gas.

[0069] The gate conductive material layer 8 is connected to a gate metal layer.

[0070] When a gate-source voltage between the gate metal layer and the source metal layer 5 is greater than or equal to a threshold voltage, a surface of the first semiconductor epitaxial layer 3 covered by a side surface and a bottom surface of the gate conductive material layer 8 forms an inversion layer, the inversion layer makes the source-end two-dimensional electron gas and the drain-end two-dimensional electron gas conductive and together constitute a conductive channel that makes the source metal layer 5 and the drain metal layer 6 conductive and thus makes the device conductive.

[0071] When the gate-source voltage between the gate metal layer and the source metal layer 5 is less than the threshold voltage, the source-end two-dimensional electron gas and the drain-end two-dimensional electron gas are disconnected and the device is turned off.

[0072] In the first embodiment of the present application, the planar high electron mobility transistor is an enhancement device, and the threshold voltage is greater than 0V.

[0073] The first semiconductor epitaxial layer 3 adopts a wide band gap semiconductor material, and the second semiconductor epitaxial layer 4 adopts a wide band gap semiconductor material.

[0074] The material of the first semiconductor epitaxial layer 3 comprises gallium nitride, and the material of the second semiconductor epitaxial layer 4 comprises aluminum gallium nitride.

[0075] The first semiconductor epitaxial layer 3 is formed on a buffer layer 2, and the buffer layer 2 is formed on a substrate 1. The material of the substrate 1 comprises silicon or sapphire.

[0076] The material of the gate dielectric layer 7 comprises silicon oxide or aluminum oxide.

[0077] The gate conductive material layer 8 comprises a polysilicon gate or a metal gate.

[0078] The first semiconductor epitaxial layer 3 has a first conductive type doping or has a second conductive type doping or is non-doped.

[0079] In the first embodiment of the present application, the threshold voltage can be set by the doping structure of the first semiconductor epitaxial layer 3, the thickness of the gate dielectric layer 7 and the work function of the gate conductive material layer 8.

[0080] The buffer layer 2 mainly functions to release stress and reduce defects of the gallium nitride epitaxial layer. Since the lattice constant of the gallium nitride epitaxial layer, i.e. the first semiconductor epitaxial layer 3, and the material of the substrate 1 are often different, the buffer layer 2 is needed to eliminate defects caused by lattice mismatch. Common types include superlattice or gradually doped types.

[0081] The thickness of the aluminum gallium nitride (Al x Ga 1-x N) epitaxial layer, i.e. the second semiconductor epitaxial layer 4, and the molar composition of aluminum atoms determine the concentration of the two-dimensional electron gas at the interface, and the thickness of the second semiconductor epitaxial layer 4 is designed as required.

[0082] The position of the gate dielectric layer 7 is deeper than that of the two-dimensional electron gas to ensure that the two-dimensional electron gas is broken; in the manufacturing process, etching process is needed to realize that the bottom of the gate trench is deeper than the bottom of the second semiconductor epitaxial layer 4. The gate dielectric layer 7 is an insulator thin film formed by deposition process, and the thickness thereof determines the threshold voltage of the device, which needs to be well controlled; at the same time, it is necessary to ensure that the trench bottom is well filled during the deposition process, and the thickness is uniform.

[0083] In addition, the top of the gate conductive material layer 8 is also connected with a gate metal layer composed of a metal layer. It is also necessary to form an interlayer film or a passivation layer to realize the isolation between the source metal layer 5, the drain metal layer 6 and the gate metal layer.

[0084] The first embodiment of the present application can realize the truncation of the two-dimensional electron gas by forming the trench gate and penetrating the bottom of the gate trench of the trench gate under the two-dimensional electron gas, so that the formation of the conduction channel between the source and the drain is not controlled by the two-dimensional electron gas, but is controlled by the trench gate, and the control of the conduction and the turn-off of the conduction channel is realized by the inversion layer formed by the inversion of the first semiconductor epitaxial layer 3 by the trench gate, so that the planar high electron mobility transistor and the MOSFET can control the conduction and the turn-off of the conduction channel by the trench gate, thereby facilitating the independent adjustment of the threshold voltage of the planar high electron mobility transistor, such as adjusting the work function of the gate conductive material layer 8 of the trench gate, the thickness of the gate dielectric layer 7, and the doping type and the doping concentration of the first semiconductor epitaxial layer 3 to adjust the threshold voltage of the device, and the normally-off planar high electron mobility transistor is easily realized; the two-dimensional electron gas of the existing planar high electron mobility transistor is always on, which is a normally-on device, and the normally-off planar high electron mobility transistor is easily realized by the first embodiment of the present application.

[0085] The second embodiment of the planar high electron mobility transistor of the present application:

[0086] The difference between the second embodiment of the planar high electron mobility transistor of the present application and the first embodiment of the planar high electron mobility transistor of the present application is that the second embodiment of the planar high electron mobility transistor of the present application further comprises the following features:

[0087] As shown in Figure 2 , it is a structure schematic diagram of the second embodiment of the planar high electron mobility transistor of the present application; the drift region is located between the drain metal layer 6 and the second side of the gate trench, and the charge balance structure is arranged in the drift region, which makes the electric field distribution of the drift region uniform under reverse bias. Figure 2 In the drift region, the corresponding lateral region is indicated by the curly brackets of the mark 201.

[0088] In the second embodiment of the present application, the charge balance structure comprises:

[0089] A third semiconductor epitaxial layer 101 is arranged on the surface of the second semiconductor epitaxial layer 4 in the drift region, and the material of the third semiconductor epitaxial layer 101 comprises gallium nitride.

[0090] The third semiconductor epitaxial layer 101 and the second heterojunction formed by the second semiconductor epitaxial layer 4 form a bound charge at the interface, which adjusts and makes the electric field distribution of the drift region uniform.

[0091] The third semiconductor epitaxial layer 101 continuously covers the second semiconductor epitaxial layer 4 surface of the drift region.

[0092] The thickness of the third semiconductor epitaxial layer 101 is 5 nm or less.

[0093] In addition, the second embodiment of the present application can form a charge balance structure in the drift region between the trench gate and the drain metal layer 6 and adjust the electric field distribution of the drift region through the charge balance structure, so that a uniform drift region electric field can be easily obtained, thereby improving the breakdown voltage of the device or reducing the specific on-resistance of the device while maintaining the breakdown voltage and reducing the size of the device, thereby greatly reducing the energy loss of the device when turned on; the second embodiment of the present application can be applied to gallium nitride material, fully exerting the advantages of gallium nitride material, reducing the cost of gallium nitride device manufacturing and simplifying the process flow.

[0094] The gallium nitride power device structure of the second embodiment of the present application can conveniently regulate the threshold voltage, thereby manufacturing an enhancement mode transistor, making its application scenarios more widely; compared with the traditional high electron mobility transistor, the specific on-resistance of the existing power device is greatly reduced under the same breakdown voltage, the power loss of the power semiconductor device can be greatly reduced, energy saving and emission reduction; at the same time, the advantages of gallium nitride device are fully exerted, the process flow is simplified, and the manufacturing cost is reduced.

[0095] The third embodiment of the present application is a planar high electron mobility transistor:

[0096] The difference between the third embodiment of the planar high electron mobility transistor of the present application and the second embodiment of the planar high electron mobility transistor of the present application is that the third embodiment of the planar high electron mobility transistor of the present application further comprises the following features:

[0097] As shown in Figure 3 , it is a structure schematic diagram of the third embodiment of the planar high electron mobility transistor of the present application; the third semiconductor epitaxial layer 101 on the second semiconductor epitaxial layer 4 surface of the drift region is divided into one or more third semiconductor epitaxial layer sub-sections 101a and one or more third semiconductor epitaxial layer interval regions 101b, and the third semiconductor epitaxial layer sub-sections 101a and the third semiconductor epitaxial layer interval regions 101b are alternately arranged on the second semiconductor epitaxial layer 4 surface of the drift region.

[0098] In the third embodiment of the present application, the number of the third semiconductor epitaxial layer 101 can be limited, or it can be extended to infinite, i.e. having infinite elements.

[0099] As shown in Figure 3A , it is Figure 3The diagram illustrates a first structure when there is one third semiconductor epitaxial layer segment and one third semiconductor epitaxial layer spacer region. The number of third semiconductor epitaxial layer segments 101a and 1 third semiconductor epitaxial layer spacer region 101b is one. The third semiconductor epitaxial layer segments 101a and 101b are arranged sequentially from the second side of the gate trench to the drain metal layer 6.

[0100] like Figure 3B As shown, is Figure 3 The diagram illustrates a first structure when there is one third semiconductor epitaxial layer segment and one third semiconductor epitaxial layer spacer region. The number of third semiconductor epitaxial layer segments 101a is one, and the number of third semiconductor epitaxial layer spacers 101b is one. The third semiconductor epitaxial layer spacers 101b and the third semiconductor epitaxial layer segments 101a are arranged sequentially from the second side of the gate trench to the drain metal layer 6.

[0101] Alternatively, the number of third semiconductor epitaxial layer segments 101a is greater than one, and the number of third semiconductor epitaxial layer spacer regions 101b is one less than the number of third semiconductor epitaxial layer segments 101a. The third semiconductor epitaxial layer segments 101a and the third semiconductor epitaxial layer spacer regions 101b are arranged sequentially from the second side of the gate trench to the drain metal layer 6. For example... Figure 3C As shown, is Figure 3 The diagram shows the structure when there are two corresponding third semiconductor epitaxial layer segments and one third semiconductor epitaxial layer spacer region. It can be seen that the third semiconductor epitaxial layer segment 101a and the third semiconductor epitaxial layer spacer region 101b are arranged sequentially from the second side of the gate trench to the drain metal layer 6.

[0102] Fourth embodiment of the present invention: planar high electron mobility transistor:

[0103] The difference between the planar high electron mobility transistor of the fourth embodiment of the present invention and the planar high electron mobility transistor of the first embodiment of the present invention is that the planar high electron mobility transistor of the fourth embodiment of the present invention further includes the following features:

[0104] like Figure 4 The diagram shown is a schematic diagram of the planar high electron mobility transistor according to the fourth embodiment of the present invention. The drift region is located between the drain metal layer 6 and the second side of the gate trench. A charge balance structure is provided in the drift region. When reverse biased, the charge balance structure makes the electric field distribution of the drift region uniform. Figure 4In the embodiment, the lateral region corresponding to the drift region is shown as the brackets of mark 201.

[0105] The charge balance structure comprises:

[0106] The thickness of the second semiconductor epitaxial layer 4 in the direction from the second side of the gate trench to the drain metal layer 6 has a variable structure, the bound charge density at the interface of the first heterojunction and thus the drift region electric field distribution are adjusted by adjusting the thickness of the second semiconductor epitaxial layer 4, and the drift region electric field distribution is made uniform.

[0107] In the direction from the second side of the gate trench to the drain metal layer 6, the second semiconductor epitaxial layer 4 is divided into two or more second semiconductor epitaxial layer subsegments 4a according to the thickness.

[0108] In the fourth embodiment of the present application, in the direction from the second side of the gate trench to the drain metal layer 6, the thickness of each of the second semiconductor epitaxial layer subsegments 4a decreases in turn.

[0109] Each of the second semiconductor epitaxial layer subsegments 4a is obtained by etching process after the second semiconductor epitaxial layer 4 is formed once. Alternatively, each of the second semiconductor epitaxial layer subsegments 4a is formed by multiple epitaxial and etching processes.

[0110] The lengths of each of the second semiconductor epitaxial layer subsegments 4a are the same or different.

[0111] As shown in Figure 4A As shown in Figure 4 The structure diagram when the number of corresponding second semiconductor epitaxial layer subsegments is 2; it can be seen that two second semiconductor epitaxial layer subsegments 4a with thickness decreasing in turn in the direction from the second side of the gate trench to the drain metal layer 6 are included.

[0112] The number of the second semiconductor epitaxial layer subsegments 4a can be extended from a finite number to an infinite number.

[0113] The fifth embodiment of the present application is a planar high electron mobility transistor:

[0114] The difference between the fifth embodiment of the present application and the fourth embodiment of the present application is that the fifth embodiment of the present application further comprises the following features:

[0115] As shown in Figure 5The diagram shown is a schematic diagram of the planar high electron mobility transistor according to the fifth embodiment of the present invention; the thickness of each second semiconductor epitaxial layer segment 4a increases sequentially from the second side of the gate trench to the drain metal layer 6.

[0116] like Figure 5A As shown, is Figure 5 The diagram shows the structure when the number of corresponding second semiconductor epitaxial layer segments is 2; it can be seen that it includes two second semiconductor epitaxial layer segments 4a with progressively increasing thickness from the second side of the gate trench to the drain metal layer 6.

[0117] The sixth embodiment of the present invention is a planar high electron mobility transistor:

[0118] The difference between the planar high electron mobility transistor of the sixth embodiment of the present invention and the planar high electron mobility transistor of the fourth embodiment of the present invention is that the planar high electron mobility transistor of the sixth embodiment of the present invention further includes the following features:

[0119] like Figure 6 The diagram shown is a schematic diagram of the planar high electron mobility transistor according to the sixth embodiment of the present invention. From the second side of the gate trench to the drain metal layer 6, the thickness of each second semiconductor epitaxial layer segment 4a increases sequentially and then decreases sequentially after reaching the maximum value.

[0120] The seventh embodiment of the present invention is a planar high electron mobility transistor:

[0121] The difference between the planar high electron mobility transistor of the seventh embodiment of the present invention and the planar high electron mobility transistor of the fourth embodiment of the present invention is that the planar high electron mobility transistor of the seventh embodiment of the present invention further includes the following features:

[0122] like Figure 7 The diagram shown is a schematic diagram of the planar high electron mobility transistor according to the seventh embodiment of the present invention. From the second side of the gate trench to the drain metal layer 6, the thickness of each second semiconductor epitaxial layer segment 4a decreases sequentially and then increases sequentially after reaching a minimum value.

[0123] Eighth embodiment of the present invention: planar high electron mobility transistor

[0124] The difference between the planar high electron mobility transistor of the eighth embodiment of the present invention and the planar high electron mobility transistor of the fourth embodiment of the present invention is that the planar high electron mobility transistor of the eighth embodiment of the present invention further includes the following features:

[0125] like Figure 8The diagram shown is a schematic representation of the planar high electron mobility transistor according to the eighth embodiment of the present invention; the charge balance structure includes:

[0126] The thickness of the second semiconductor epitaxial layer 4 varies from the second side of the gate trench to the drain metal layer 6. By adjusting the thickness of the second semiconductor epitaxial layer 4, the bound charge density at the interface of the first heterojunction is adjusted, thereby distributing the electric field in the drift region and making the electric field distribution in the drift region uniform. Figure 8 In the diagram, the second semiconductor epitaxial layer in region 201 is marked separately with label 4b.

[0127] In the eighth embodiment of the present invention, the thickness of the second semiconductor epitaxial layer 4b gradually decreases according to a linear function from the second side of the gate trench to the drain metal layer 6. A linear function is also known as a linear function.

[0128] Ninth embodiment of the present invention: planar high electron mobility transistor:

[0129] The difference between the planar high electron mobility transistor of the ninth embodiment of the present invention and the planar high electron mobility transistor of the eighth embodiment of the present invention is that the planar high electron mobility transistor of the ninth embodiment of the present invention further includes the following features:

[0130] like Figure 9 The diagram shown is a schematic diagram of the planar high electron mobility transistor according to the ninth embodiment of the present invention; the thickness of the second semiconductor epitaxial layer 4 gradually increases according to a linear function from the second side of the gate trench to the drain metal layer 6.

[0131] Tenth embodiment of the present invention: planar high electron mobility transistor:

[0132] The difference between the planar high electron mobility transistor of the tenth embodiment of the present invention and the planar high electron mobility transistor of the eighth embodiment of the present invention is that the planar high electron mobility transistor of the tenth embodiment of the present invention further includes the following features:

[0133] like Figure 10 The diagram shown is a schematic diagram of the planar high electron mobility transistor according to the tenth embodiment of the present invention. From the second side of the gate trench to the drain metal layer 6, the thickness of the second semiconductor epitaxial layer 4 first increases gradually according to a linear function and then gradually decreases according to a linear function after reaching the maximum value.

[0134] Eleventh embodiment of the present invention: planar high electron mobility transistor:

[0135] The difference between the planar high electron mobility transistor of the eleventh embodiment of the present application and the planar high electron mobility transistor of the eighth embodiment of the present application is that the planar high electron mobility transistor of the eleventh embodiment of the present application further comprises the following features:

[0136] As shown in Figure 11 Fig. 11 is a structure diagram of the planar high electron mobility transistor of the eleventh embodiment of the present application; the thickness of the second semiconductor epitaxial layer 4 gradually decreases according to a linear function and then gradually increases according to a linear function again from the second side of the gate trench to the direction of the drain metal layer 6.

[0137] The device structure of the embodiment of the present application has important value in power semiconductor devices based on gallium nitride. However, the device structure of the embodiment of the present application is not limited to gallium nitride material, and any material used for manufacturing power semiconductor devices can be applicable.

[0138] The embodiment of the present application is based on some innovative structures of a typical gallium nitride high electron mobility transistor, and the core of the embodiment of the present application comprises designing the drift region of the planar device by using the charge balance concept. Through this structure, the electric field distribution can be optimized to be more uniform, so as to achieve the purpose of optimizing the breakdown voltage and reliability of the device.

[0139] The device structure of the embodiment of the present application is an innovative structure of a gallium nitride high electron mobility transistor. Such a device mainly relies on the heterostructure of aluminum gallium nitride (AlGaN) and gallium nitride (GaN), and uses the two-dimensional electron gas (2DEG) at the device as a conductive channel. However, the structure of the device proposed in the embodiment of the present application is not only limited to the heterostructure of gallium nitride, but also can be used for other heterostructures.

[0140] The device of the embodiment of the present application first uses the MOS structure as a channel to realize a normally-off device, which combines the traditional MOSFETs and HEMTs and fully gives the advantages of the two kinds of device structures.

[0141] Secondly, the concept of charge balance is applied to the high electron mobility device, and regrowing a thin layer of GaN, i.e., the third semiconductor epitaxial layer 101, on the surface of the AlGaN epitaxial layer can introduce charges of opposite polarity, which can have the effect of charge balance. This structure can be expanded, such as locally removing the top GaN layer to change the local electric field distribution, which can make the device design have higher freedom and can add many kinds of changed structures.

[0142] Third, besides introducing a top GaN layer, local etching of the AlGaN, i.e. the second semiconductor epitaxial layer 4, can also achieve interface charge engineering. Since the thickness of the AlGaN changes the density of the interface charge, local removal of the AlGaN layer can change the distribution of the charge density of the entire drift region. The following extension can be made: if the drift region is divided into a finite number of small units, and the AlGaN layer of each small unit is treated specifically, the charge distribution of the entire drift region can be designed as needed, so that the electric field distribution is further improved. The following extension can be further made: if the drift region is divided into an infinite number of small units, the AlGaN thickness of each unit can achieve a gradual effect, and the concept of calculus is used to achieve the effect of continuous function of the charge distribution of the drift region, so that the electric field distribution is optimized.

[0143] The above has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered within the scope of protection of the present application.

Claims

1. A planar high electron mobility transistor, characterized by, The device unit comprises: a first semiconductor epitaxial layer and a second semiconductor epitaxial layer formed on the surface of the first semiconductor epitaxial layer, the first semiconductor epitaxial layer and the second semiconductor epitaxial layer form a first heterojunction and form a two-dimensional electron gas at the interface of the first heterojunction; a trench gate, comprising a gate trench, a gate dielectric layer formed on the inner surface of the gate trench, and a gate conductive material layer filling the gate trench; the gate trench passes through the second semiconductor epitaxial layer, so that the bottom surface of the gate trench is located in the first semiconductor epitaxial layer at the bottom of the two-dimensional electron gas, and the trench gate cuts off the two-dimensional electron gas into a source-end two-dimensional electron gas and a drain-end two-dimensional electron gas; a source metal layer and a first side surface of the gate trench have a spacing, the source metal layer passes through the second semiconductor epitaxial layer, and the bottom region of the source metal layer forms an ohmic contact with the source-end two-dimensional electron gas; a drain metal layer and a second side surface of the gate trench have a spacing, the drain metal layer passes through the second semiconductor epitaxial layer, and the bottom region of the drain metal layer forms an ohmic contact with the drain-end two-dimensional electron gas; the gate conductive material layer is connected to a gate conductive material layer; when the gate-source voltage between the gate conductive material layer and the source metal layer is greater than or equal to a threshold voltage, the surface of the first semiconductor epitaxial layer covered by the side surface and the bottom surface of the gate conductive material layer forms an inversion layer, the inversion layer makes the source-end two-dimensional electron gas and the drain-end two-dimensional electron gas conductive and together form a conductive channel that makes the source metal layer and the drain metal layer conductive and thus makes the device conductive; when the gate-source voltage between the gate conductive material layer and the source metal layer is less than the threshold voltage, the source-end two-dimensional electron gas and the drain-end two-dimensional electron gas are disconnected and the device is turned off; a drift region is located between the drain metal layer and the second side surface of the gate trench, and a charge balance structure is arranged in the drift region, which makes the electric field distribution of the drift region uniform under reverse bias; the charge balance structure comprises: a third semiconductor epitaxial layer is arranged on the surface of the second semiconductor epitaxial layer in the drift region, and the material of the third semiconductor epitaxial layer comprises gallium nitride; the interface of the second heterojunction formed by the third semiconductor epitaxial layer and the second semiconductor epitaxial layer forms a bound charge, and the bound charge at the interface of the second heterojunction adjusts and makes the electric field distribution of the drift region uniform; the third semiconductor epitaxial layer is divided into one or more third semiconductor epitaxial layer sub-segments and one or more third semiconductor epitaxial layer spacing regions on the surface of the second semiconductor epitaxial layer in the drift region, and the third semiconductor epitaxial layer sub-segments and the third semiconductor epitaxial layer spacing regions are arranged alternately on the surface of the second semiconductor epitaxial layer in the drift region; the number of the third semiconductor epitaxial layer sub-segments is 1, and the number of the third semiconductor epitaxial layer spacing regions is 1. The third semiconductor epitaxial layer sub-section and the third semiconductor epitaxial layer interval region are arranged in sequence from the second side of the gate trench to the drain metal layer; or the third semiconductor epitaxial layer interval region and the third semiconductor epitaxial layer sub-section are arranged in sequence from the second side of the gate trench to the drain metal layer. Alternatively, the charge balance structure comprises: The thickness of the second semiconductor epitaxial layer has a variable structure from the second side of the gate trench to the drain metal layer, the thickness of the second semiconductor epitaxial layer is adjusted to adjust the bound charge density at the interface of the first heterojunction and thereby the drift region electric field distribution and make the drift region electric field distribution uniform; The second semiconductor epitaxial layer is divided into two or more second semiconductor epitaxial layer sub-sections according to the thickness from the second side of the gate trench to the drain metal layer; Alternatively, the thickness of the second semiconductor epitaxial layer gradually increases according to a linear function or gradually decreases according to a linear function or gradually increases according to a linear function first and then gradually decreases according to a linear function after increasing to a maximum value or gradually decreases according to a linear function first and then gradually increases according to a linear function after decreasing to a minimum value from the second side of the gate trench to the drain metal layer.

2. The planar high electron mobility transistor of claim 1, wherein: The planar high electron mobility transistor is an enhancement type device, and the threshold voltage is greater than 0V.

3. The planar high electron mobility transistor of claim 2, wherein: The first semiconductor epitaxial layer adopts a wide bandgap semiconductor material, and the second semiconductor epitaxial layer adopts a wide bandgap semiconductor material.

4. The planar high electron mobility transistor of claim 3, wherein: The material of the first semiconductor epitaxial layer comprises gallium nitride, and the material of the second semiconductor epitaxial layer comprises aluminum gallium nitride.

5. The planar high electron mobility transistor of claim 4, wherein: The first semiconductor epitaxial layer is formed on a buffer layer, and the buffer layer is formed on a substrate.

6. The planar high electron mobility transistor of claim 5, wherein: The material of the substrate comprises silicon or sapphire.

7. The planar high electron mobility transistor of claim 4, wherein: The material of the third semiconductor epitaxial layer comprises gallium nitride.

8. The planar high electron mobility transistor of claim 7, wherein: The third semiconductor epitaxial layer continuously covers the surface of the second semiconductor epitaxial layer of the drift region.

9. The planar high electron mobility transistor of claim 7, wherein: The third semiconductor epitaxial layer sub-section is formed by selectively etching the third semiconductor epitaxial layer after epitaxial growth.

10. The planar high electron mobility transistor of claim 7, wherein: The thickness of the third semiconductor epitaxial layer is less than or equal to 5nm.

11. The planar high electron mobility transistor of claim 1, wherein: The thickness of each second semiconductor epitaxial layer sub-section increases or decreases or increases first and then decreases or decreases first and then increases from the second side of the gate trench to the drain metal layer.

12. The planar high electron mobility transistor of claim 1, wherein: Each second semiconductor epitaxial layer sub-section is obtained by etching process after the first formation of the second semiconductor epitaxial layer to obtain the thickness of the corresponding second semiconductor epitaxial layer sub-section. Alternatively, each second semiconductor epitaxial layer sub-section is formed by multiple epitaxial and etching processes.

13. The planar high electron mobility transistor of claim 1, wherein: The lengths of each second semiconductor epitaxial layer sub-section are the same or different.

14. The planar high electron mobility transistor of claim 4, wherein: The material of the gate dielectric layer comprises silicon oxide or aluminum oxide. The gate conductive material layer comprises a polysilicon gate or a metal gate.

15. The planar high electron mobility transistor of claim 4, wherein: The first semiconductor epitaxial layer has a first conductivity type doping or a second conductivity type doping or is non-doped.

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