Vertical field effect transistor and method for constructing the same

Abstract

A vertical field effect transistor (200, 300, 400, 500, 600) is provided, having a drift region (204), a semiconductor fin (230) on or above the drift region (204), and a connection end region (212) on or above the semiconductor fin (230), a gate electrode (220) configured next to at least one sidewall of the semiconductor fin (230), wherein the semiconductor fin (230) has a smaller lateral extension in a first section (208) laterally arranged next to the gate electrode (220) than in a second section (206) contacting the drift region (204) and / or than in a third section (210) contacting the connection end region (212).

Description

Technical Field

[0001] The present invention relates to a vertical field-effect transistor and a method for constructing the same. Background Technology

[0002] In the automotive sector, with the advancement towards electric vehicles, solutions for power semiconductors that enable fast and lossless switching are highly sought after. Here, the simultaneous trend from lateral to vertical components, along with the established trend in recent decades towards silicon technology using so-called "wide-bandgap" materials (i.e., semiconductor materials with wide band gaps, such as silicon carbide (SiC) or gallium nitride (GaN)), has led to the development of new component concepts and manufacturing processes.

[0003] For applications involving semiconductors with wide band gaps, the use of so-called power FinFETs (Fin = Finne, FET = Feldeffekttransistor, field-effect transistor) can be advantageous. In conventional MOSFETs or MISFETs, the active, switchable component is provided by an inverting channel, for example, by a p-region in an npn junction, where an electron path is constructed by applying a gate voltage. Conversely, in a power FinFET, the switchable component is composed of narrow semiconductor fins that are switchable due to the choice of their geometry and the matching of the gate metallization. The channel resistance of a power FinFET is much smaller than that of a conventional SiC or GaN-based MOSFET or MISFET. This results in a lower on-resistance overall.

[0004] In a power FinFET, the channel region is formed in the region of the semiconductor fin at the height of the gate metal. Since the width of this region essentially determines the threshold voltage of the power FinFET, this region should not exceed a predetermined value in terms of its width to ensure complete depletion. Figure 1The structure of the power FinFET 100, which involves the technology, is illustrated visually. A conventional power FinFET 100 has an n-type doped drift region 104, a drain electrode 106, a source electrode 108, a gate electrode 110, a semiconductor fin 112, a gate dielectric 114, and an insulating portion 116 on a substrate 102. The semiconductor fin 112 is connected to the source electrode 108 via an n+ type dopant 118. In the power FinFET 100, the switchable component is constituted by a narrow semiconductor fin 112, which is switchable due to the choice of its geometry and the matching of the gate metallization 110. The width of the semiconductor fin depends particularly on the semiconductor material used for the semiconductor fin and the work function of the gate metal. Such narrow semiconductor fins may no longer be manufacturable using conventional photolithography techniques (as is typically used in the mass production of power transistors). Furthermore, the thin semiconductor fin makes electrical connection to the front metallization, which has low resistance, difficult. Summary of the Invention

[0005] The objective of this invention is to provide a vertical field-effect transistor and a method for constructing the same, wherein the vertical field-effect transistor / method realizes a vertical field-effect transistor with improved front contacts.

[0006] According to one aspect of the invention, this task is solved by a vertical field-effect transistor (VFET). The VFET has: a drift region, a semiconductor fin on or above the drift region, a connection terminal region on or above the semiconductor fin, and a gate electrode constructed adjacent to at least one sidewall of the semiconductor fin, wherein the semiconductor fin has a smaller lateral extension in a first section laterally arranged adjacent to the gate electrode than in a second section contacting the drift region and / or a third section contacting the connection terminal region. The wider region above and / or below the channel region (first section) achieves a larger contact area on the semiconductor fin, and thus reduces the parasitic electrical contact resistance of the contact regions of the semiconductor fin (the second and / or third sections of the semiconductor fin). The widened semiconductor fin in the region above and / or below the channel region reduces the contact resistance of the front contacts (e.g., the source electrode).

[0007] In another aspect, semiconductor pillars can be constructed instead of semiconductor fins.

[0008] According to another aspect of the invention, this task is solved by a method for constructing a vertical field-effect transistor. The method comprises: constructing a drift region; constructing a semiconductor fin on or above the drift region; constructing a connection region on or above the semiconductor fin; and constructing a gate electrode disposed adjacent to at least one sidewall of the semiconductor fin, wherein the semiconductor fin is configured in a first segment laterally arranged adjacent to the gate electrode to have a smaller lateral extension than in a second segment contacting the drift region and / or than in a third segment contacting the connection region. This achieves that, in terms of investment and operating costs, a more cost-effective facility configuration compared to other concepts can be used to manufacture a vertical field-effect transistor. Attached Figure Description

[0009] Extensions to these aspects are set forth in the dependent claims and the specification. Embodiments of the invention are illustrated in the accompanying drawings and explained in more detail below. The drawings show:

[0010] Figure 1 A schematic diagram of a vertical field-effect transistor of the technology involved is shown.

[0011] Figures 2 to 6 A schematic cross-sectional view of a vertical field-effect transistor according to different embodiments is shown;

[0012] Figure 7 A to Figure 7 F shows schematic diagrams of method steps for manufacturing vertical field-effect transistors according to different embodiments;

[0013] Figure 8 A to Figure 8 C shows schematic top views of semiconductor fins, semiconductor pillars, or networks of interconnected semiconductor fins according to different embodiments; and

[0014] Figure 9 A flowchart is shown for methods of constructing vertical field-effect transistors according to different embodiments. Detailed Implementation

[0015] In the following detailed description, reference is made to the accompanying drawings, which form part of this specification, and in which specific embodiments are shown for visual illustration, in which the invention can be practiced. It is self-evident that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of protection of the invention. It is self-evident that features of the different embodiments described herein can be combined with each other unless specifically indicated otherwise. Therefore, the following detailed description should not be construed as limiting, and the scope of protection of the invention is defined by the supplementary claims. In the drawings, the same or similar elements are given the same reference numerals, as is appropriate for the purpose.

[0016] Figure 2 A schematic cross-sectional view of a vertical field-effect transistor 200 according to different embodiments is shown. In different embodiments, the vertical field-effect transistor 200 has: a drift region 204 on a semiconductor substrate 202; a semiconductor fin 230 (extending longitudinally perpendicular to the drawing plane) having a connection terminal region 212 on or above the drift region 204; a first source / drain electrode (e.g., source electrode 214); and a second source / drain electrode (e.g., drain electrode 216). Hereinafter, it is exemplarily assumed that the first source / drain electrode is the source electrode 214, and the second source / drain electrode is the drain electrode 216. Furthermore, the vertical field-effect transistor 200 has a gate electrode 220 laterally adjacent to at least one sidewall of the semiconductor fin 230, wherein the gate electrode 220 is electrically insulated from the source electrode 214 by means of an insulating layer 222. A gate dielectric 218 is disposed between the gate electrode 220 and at least one sidewall of the semiconductor fin 230.

[0017] The semiconductor fin 230 is constructed such that it has a smaller lateral extension in the first section 208, which is laterally arranged next to the gate electrode 220, than in the second section 206 of the contact drift region 204 and / or than in the third section 210, which contacts the source electrode 214. This achieves a several-fold increase in the contact area for carrying current on the front side of the substrate. Consequently, a significantly lower and more reliable ohmic contact area can be fabricated for the vertical field-effect transistor.

[0018] In other words, the semiconductor fin 230 is laterally widened relative to the first segment 208 in the second segment 206 and / or the third segment 210, and thus has a reduced total resistance. The widened portions in the second segment 206 and the third segment 210 can not only be configured to have the same lateral extension, but can also be configured to have different lateral extensions from each other. In different embodiments, the semiconductor fin 230 has a larger lateral extension in the second segment 206, but not in the third segment 210, than in the first segment 208 (see [link to relevant documentation]). Figure 3 Alternatively, the semiconductor fin 230 has a greater lateral extension in the third segment 210, but not in the second segment 206, than in the first segment 208. Alternatively, the semiconductor fin 230 has a greater lateral extension in both the second and third segments 206 and 210 than in the first segment 208. The semiconductor fin 230 may have at least one substantially linear, or straight or perpendicular-plane, sidewall. The semiconductor fin 230 may, for example, have a straight first sidewall and a straight second sidewall, the second sidewall being opposite the first sidewall. The first and second sidewalls may be parallel to each other.

[0019] Figure 2 A schematic cross-sectional view of a single FinFET cell according to different embodiments is shown. Generally, hundreds to thousands of such cells are connected in parallel, and this structure extends into the plane in the third dimension. The combination of multiple cells creates a two-dimensional extended field of the FinFET cell. The vertical field-effect transistor can be a power semiconductor component. As an example, the semiconductor substrate 202 can be a GaN substrate 202 or a SiC substrate 202. A weakly n-type conductive semiconductor drift region 204, such as a GaN drift region 204 or a SiC drift region 204, can be formed (e.g., applied) on the semiconductor substrate 202. The n-type conductive semiconductor region can be formed above the drift region 204 in the form of semiconductor fins 230, such as GaN fins or SiC fins. The connection region 212 can have or be formed of an n-type doped (e.g., n+ doped) semiconductor material.

[0020] For the vertical field-effect transistor 200 to function as a transistor or switch, the semiconductor fin 230 in the first section 208 has, for example, a lateral extension in the presented drawing plane in the range of about 100 nm to about 200 nm and a vertical extension in the presented drawing plane in the range of about 0.3 μm to about 3 μm.

[0021] Without applying a gate voltage, the field-effect transistor 200 can be latched because the electron gas can be depleted in the drift region 204 below the semiconductor fin 230. By applying a positive voltage at the gate electrode 220, electrons can accumulate in the region of the semiconductor fin adjacent to the gate electrode 220. Electrons can flow from the source electrode 214 through the semiconductor fin 230 to the bottom of the semiconductor fin 230 and from there to the drift region 204, and further through the drift region 204 and the substrate 202 to the drain electrode 216.

[0022] In different implementations, the connection end region 212 is constructed above the third segment 210 at its full depth (into the drawing plane).

[0023] In different implementations, the gate dielectric 218, drift region 204, and / or semiconductor fin 230 can be configured such that the interface with the gate dielectric 218 has rounded corners and / or edges, or in other words, has the largest possible radius of curvature. This reduces field spikes.

[0024] In different embodiments, the connection end region 212 has a greater lateral extension than the lateral extension of the semiconductor fin 230 in the third segment 210, such as in Figure 3 As illustrated intuitively in the text, Figure 3 A vertical field-effect transistor 300 according to different embodiments is shown.

[0025] The semiconductor fin 230 may have a connection region 402 in the second segment 206, which has a greater conductivity than the semiconductor fin 230 in the first segment 208 and / or than the drift region 204, as in Figure 4 As illustrated intuitively in the text, Figure 4 A vertical field-effect transistor 400 according to different embodiments is shown.

[0026] In different embodiments, a shielding structure 404 may be provided, which is laterally constructed next to the connection region 402, wherein the shielding structure 404 has a different conductivity type than the connection region 402, such as in Figure 4 This is illustrated intuitively. The connection region 402 in the second segment may have or be formed of an n-type doped (e.g., n+ type doped) semiconductor material. The shielding structure 404 has or is formed of, for example, a p-type doped or intrinsic semiconductor material.

[0027] Semiconductor fin 230 can be more strongly n-type doped in the second section 206 than in the first section 208. This achieves better current bifurcation. A shielding structure 404 can also be provided, which is arranged below the gate electrode 220 in the drift region 204. This achieves shielding of the gate dielectric 218 against field spikes. In the second section 206, semiconductor fin 230 can have increased n-type doping. Alternatively, the increased n-type doping can be constructed to the lower edge of the shielding structure 404. The shielding structure 404 with p-type doping can be electrically connected to the source electrode 214. Alternatively or additionally, electric field spikes that appear vertically at the gate dielectric 218 between the gate electrode 220 and the drift region 204 can be reduced by means of a second insulating layer 223 arranged in the bottom between the drift region 204 and the gate electrode 220, next to the semiconductor fin 230, as shown in Figure 5 As illustrated intuitively in the text, Figure 5A vertical field-effect transistor 500 according to a different embodiment is shown. For example, a second insulating layer 223 may be disposed between the gate dielectric 218 and the drift region 204. This improves the breakdown strength of the gate dielectric 218 in this region and thus improves the breakdown voltage of the vertical field-effect transistor. The second insulating layer 223 may have a greater thickness than the gate dielectric 218.

[0028] In different embodiments, at least one sidewall of the semiconductor fin 230 may be arched or curved, as in... Figure 6 As illustrated intuitively in the text, Figure 6 A vertical field-effect transistor 600 according to different embodiments is shown.

[0029] Multiple semiconductor fins 230 can be arranged side by side (see Figure 8 A). Instead of semiconductor fin ground, one or more semiconductor pillars 240 can be provided (see...). Figure 8 B). Alternatively, a network consisting of two or more interconnected semiconductor fins 230 can be provided (see [link]). Figure 8 C).

[0030] Figure 9 A flowchart illustrating intuitively a method 900 for constructing a vertical field-effect transistor according to various embodiments is provided. Method 900 includes: constructing a drift region 910; constructing a semiconductor fin 920 on or above the drift region; constructing a connection region 930 on or above the semiconductor fin; and constructing a gate electrode 940 adjacent to at least one sidewall of the semiconductor fin. The semiconductor fin is constructed in a first segment laterally arranged adjacent to the gate electrode to have a smaller lateral extension than in a second segment contacting the drift region and / or a third segment contacting the connection region. For example, a smaller lateral extension of the semiconductor fin can be constructed using an etch stop mask and anisotropic etching. The etch stop mask can be constructed on or above the semiconductor fin.

[0031] In cases where it is impossible to construct thermal oxide semiconductor materials (such as gallium nitride (GaN), gallium oxide (GaOx), aluminum nitride (AlN), and diamond) on them, anisotropic etching processes can provide the means to achieve... Figure 2 The possibility of the form of semiconductor fin 230 shown in the figure. Figure 7 A to Figure 7 F is a schematic cross-sectional view that visually illustrates an example of a method for constructing GaN-based vertical field-effect transistors.

[0032] Figure 7A illustrates an n+-doped semiconductor material (212) provided on or above the drift region 204 and the substrate 202 by means of epitaxy or (ion) implantation. Flat semiconductor fins are constructed in the n+-doped semiconductor material, thereby structurally constructing the connection terminal region 212. The structuring can be achieved by means of wet chemical etching or dry etching. For gallium nitride, gallium oxide, and aluminum nitride, dry etching can be applied, for example, in a chlorine-containing plasma. For diamond, a similar etching can be applied in an oxygen-containing plasma. Wet chemical etching processes for gallium nitride are feasible, for example, in potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) at different concentrations and temperatures.

[0033] Figure 7 B illustrates the masking or construction of a mask 702 and the structuring or construction of a trench structure on or above the connection end region 212 to expose or construct the semiconductor fins. Nitrogen compounds and / or oxygen compounds can be used as masking materials.

[0034] Figure 7 C illustrates an anisotropic wet etching process, for example, using KOH or TMAH, to construct the first segment of a semiconductor fin.

[0035] Figure 7 D indicates that a mask 704 is further masked or constructed on or above the semiconductor fin.

[0036] Figure 7 E illustrates the construction of another trench structure around the masked semiconductor fin to construct the widened portion of the semiconductor fin 230, or the second segment of the semiconductor fin.

[0037] Figure 7 F shows the structure of the gate electrode, source electrode, drain electrode, and insulating portion.

[0038] The embodiments described and shown in the accompanying drawings are merely exemplary selections. Different embodiments may be combined with each other entirely or in individual features. An embodiment may also be supplemented by features of another embodiment. Furthermore, the described method steps may be repeated and performed in a sequence different from that described. In particular, the invention is not limited to the indicated methods.

Claims

1. A vertical field-effect transistor (200, 300, 400, 500, 600), comprising: Drift area (204); Semiconductor fins (230) on or above the drift region (204); On or above the semiconductor fin (230), in a connection terminal region (212), the semiconductor fin (230) is connected to the source / drain electrodes (214, 216) of the vertical field-effect transistors (200, 300, 400, 500, 600) via the connection terminal region; and A gate electrode (220) is constructed next to at least one sidewall of the semiconductor fin (230). in, The semiconductor fin (230) has a smaller lateral extension in a first section (208) laterally arranged next to the gate electrode (220) than in a second section (206) contacting the drift region (204) and / or than in a third section (210) contacting the connection end region (212). The connection end region (212) has a greater lateral extension than the lateral extension of the semiconductor fin (230) in the third segment (210).

2. The vertical field-effect transistor (200, 300, 400, 500, 600) according to claim 1, in, The semiconductor fin (230) has at least one straight sidewall.

3. The vertical field-effect transistor (200, 300, 400, 500, 600) according to any one of claims 1 or 2. in, The semiconductor fin (230) has a straight first sidewall and a straight second sidewall, the second sidewall being opposite to the first sidewall.

4. The vertical field-effect transistor (200, 300, 400, 500, 600) according to any one of claims 1 or 2. in, The semiconductor fin (230) has a connection region (402) in the second section (206), the connection region having greater conductivity than the semiconductor fin (230) in the first section (208) and / or than the drift region (204).

5. The vertical field-effect transistor (200, 300, 400, 500, 600) according to claim 4, wherein the vertical field-effect transistor further comprises a shielding structure (404) laterally disposed beside the connection region (402), wherein, The shielding structure (404) has a different conductivity type than the connection area (402).

6. The vertical field-effect transistor (200, 300, 400, 500, 600) according to any one of claims 1 or 2, wherein the vertical field-effect transistor further comprises an insulating layer (223) disposed between the gate electrode (220) and the drift region (204).

7. The vertical field-effect transistor (200, 300, 400, 500, 600) according to any one of claims 1 or 2, wherein, The drift region (204) and the semiconductor fin (230) have gallium nitride or silicon carbide, or are formed of gallium nitride or silicon carbide.

8. The vertical field-effect transistor (200, 300, 400, 500, 600) according to any one of claims 1 or 2. in, The semiconductor fin (230) is constructed as a network of two or more semiconductor fins (230) connected to each other.

9. A vertical field-effect transistor (200, 300, 400, 500, 600) having: Drift area (204); Semiconductor pillars (240) on or above the drift region (204); On or above the semiconductor pillar (240), in a connection terminal region (212), the semiconductor pillar (240) is connected to the source / drain electrodes (214, 216) of the vertical field-effect transistors (200, 300, 400, 500, 600) via the connection terminal region; and A gate electrode (220) is constructed next to at least one sidewall of the semiconductor pillar (240). in, The semiconductor pillar (240) has a smaller lateral extension in a first segment (208) laterally arranged next to the gate electrode (220) than in a second segment (206) contacting the drift region (204) and / or than in a third segment (210) contacting the connection terminal region (212). The connection end region (212) has a greater lateral extension than the lateral extension of the semiconductor pillar (240) in the third segment (210).

10. A method (900) for constructing a vertical field-effect transistor (200, 300, 400, 500, 600), the method (900) comprising: Construct the drift region (204); Semiconductor fins are constructed on or above the drift region (204); A connection terminal region (212) is constructed on or above the semiconductor fin (230), and the semiconductor fin (230) is connected to the source / drain electrodes (214, 216) of the vertical field-effect transistors (200, 300, 400, 500, 600) via the connection terminal region; and A gate electrode (220) is constructed next to at least one sidewall of the semiconductor fin (230). in, The semiconductor fin (230) is configured in a first section (208) laterally arranged next to the gate electrode (220) to have a smaller lateral extension than in a second section (206) contacting the drift region (204) and / or than in a third section (210) contacting the connection end region (212). The connection end region (212) is configured to have a greater lateral extension than the lateral extension of the semiconductor fin (230) in the third segment (210).

11. The method (900) according to claim 10, in, A smaller lateral extension of the semiconductor fin (230) is constructed using an etch stop mask and anisotropic etching, wherein the etch stop mask is constructed on or above the semiconductor fin (230).

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