Gate drive circuit

Abstract

The present application provides a kind of gate drive circuit, realize the precision improvement of shielding time and the improvement of the tolerance of misoperation.The gate drive circuit of the present application drives power semiconductor switch, comprising: comparison circuit, the collector-emitter voltage of the power semiconductor switch is compared with the threshold voltage specified;And time measurement circuit, after the comparison circuit detects that the collector-emitter voltage exceeds the threshold voltage, start measuring time, and the gate drive circuit comprises: output circuit, after the time measurement circuit measures standby retention time (shielding time), output abnormal signal indicating that power semiconductor switch is abnormal state.

Description

TECHNICAL FIELD

[0001] The present application relates to a gate drive circuit including a short-circuit detection function (circuit) that detects a short circuit of a semiconductor device such as an Insulated Gate Bipolar Transistor (IGBT). Further, the present application relates to a gate drive circuit including a function (circuit) that detects an overcurrent of a semiconductor device. BACKGROUND

[0002] If an IGBT that switches a high voltage and a large current is destroyed, it causes a large obstacle to a peripheral machine, and thus it is necessary to avoid the destruction as much as possible. Therefore, for a gate drive circuit that drives an IGBT, a function of protecting the IGBT in anticipation of such an event becomes important. The present application relates to a function of protecting an IGBT when a load of the IGBT becomes a short-circuit state or a state close to the short-circuit state.

[0003] Generally, as a method of detecting an abnormality such as a short circuit of a load, a method of detecting a rise in Vce (collector voltage) when an IGBT is in an ON state is adopted.

[0004] In the conventional method, a certain time is sometimes provided from when an abnormality is detected until an abnormality signal is sent out. This certain time is a time for which sending out of the abnormality signal is put on standby, and is sometimes referred to as a masking time. This masking time is required to have a certain precision from the viewpoint of preventing a false operation and preventing overloading of the IGBT.

[0005] <Details of the Conventional Method>

[0006] <Problem 1 of the Conventional Method>

[0007] FIG. 17 A circuit diagram in which the conventional method is adopted. FIG. 17 A circuit in which a gate driver 10 drives an IGBT 12. Further, the gate driver 10 adopts a form of a drive integrated circuit (IC), FIG. 17 which is written as Drive IC in the figure.

[0008] An operation in a case where the IGBT 12 normally repeats an ON operation and an OFF operation will be described. During an OFF operation of the IGBT 12, a value of an output of an OUT terminal 14 of the gate driver 10 (Drive IC) becomes LOW, and a transistor Q1 of the gate driver 10 performs an ON operation, and discharges a charge of a capacitor Cdesat to 0.

[0009] If the IGBT 12 becomes an ON operation, the value of the OUT terminal 14 becomes High, and thus a Low signal is input to the base of the transistor Ql via the inverter 16. As a result, although the transistor Ql becomes an OFF operation, the collector-emitter voltage of the IGBT 12 becomes a saturation voltage, and thus the current of the current source Idesat flows to the collector terminal of the IGBT 12 via the diode Ddesat.

[0010] As a result, the capacitor Cdesat is charged to a voltage that is the sum of the forward voltage of the diode Ddesat and the saturation voltage of the collector-emitter of the IGBT 12. That is, the voltage between the terminals of the capacitor Cdesat becomes the saturation voltage + the forward voltage of the diode Ddesat.

[0011] The voltage of the DESAT terminal of the gate driver 10 is maintained at a lower voltage than the reference voltage Vdesat, and thus in the comparator 18 in the gate driver 10, the value of the output signal does not invert, and thus an abnormal signal is not output. If the voltage between the terminals of the capacitor Cdesat is expressed by an equation, it is expressed as the following equation (1).

[0012] [Equation 1]

[0013] V Cdesat (0) = VF Ddesat + VCE sat (1)

[0014] Here, VCdesat(0) is the voltage between the terminals of the capacitor Cdesat when the IGBT 12 normally operates. VFDdesat is the forward voltage of the diode Ddesat. VCEsat is set to the saturation voltage of the collector-emitter when the IGBT 12 normally performs an ON operation.

[0015] In this state, if the load of the IGBT 12 becomes abnormal and the collector-emitter voltage VCE of the IGBT 12 rises to the level of the positive-side power supply VCC, the diode Ddesat becomes in an off state, the current of the current source Idesat flows to the capacitor Cdesat, and the voltage between the terminals of the capacitor Cdesat rises to the reference voltage Vdesat built in the gate driver 10. As a result, the comparator 18 in the gate driver 10 inverts, and an abnormal signal is sent out.

[0016] Further, the output signal of the comparator 18 becomes High if the voltage between the terminals of the capacitor Cdesat is higher than the reference voltage Vdesat, which indicates an abnormal signal.

[0017] At this time, the masking time Tmask from when the load in which the IGBT 12 is provided becomes abnormal until the abnormality signal is sent from the gate driver 10 is represented by Expression (2).

[0018] [Equation 2]

[0019]

[0020] Here, VCdesat(0) is the initial voltage of the capacitor Cdesat.

[0021] Further, Cdesat represents the electrostatic capacity of the capacitor Cdesat, and Idesat represents the current value of the current Idesat.

[0022] On the other hand, in a case where the abnormality of the IGBT 12 occurs immediately after the IGBT 12 has shifted from the OFF operation to the ON operation, the capacitor Cdesat does not have a time to be charged by the Idesat current, and thus becomes VCdesat(0) = 0. In this case, the masking time Tmask is represented by Expression (3).

[0023] [Equation 3]

[0024]

[0025] Thus, the masking time Tmask varies by Δt given by Expression (4) according to the timing at which the abnormality of the IGBT 12 occurs.

[0026] [Equation 4]

[0027]

[0028] Thus, there is a problem that the masking time Tmask varies according to the timing at which the abnormality occurs, and the like.

[0029] Problem 2 of the Conventional Method

[0030] Further, FIG. 17 The low reference voltage Vdesat means that the tolerance for the malfunction is small, and thus, as necessary, it is sometimes necessary to increase the voltage value of the reference voltage Vdesat. However, since it is a voltage built into the gate driver 10, there is a problem that it is usually difficult to change the voltage value, and the like.

[0031] Prior Art Patent

[0032] For example, Patent Literature 1 (Japanese Patent Laid-Open No. 2004-140891) described later discloses a power conversion device capable of reliably detecting a failure of a part of elements constituting an overvoltage protection circuit. Specifically, there is described a circuit that measures a time at which a voltage of the overvoltage protection circuit changes when a semiconductor element as an object of protection becomes an OFF state, and determines that a part of elements constituting the overvoltage protection circuit has failed when the time exceeds a set time length.

[0033] Prior Art Documents

[0034] Patent Literature

[0035] Patent Literature 1: Japanese Patent Laid-Open No. 2004-140891 SUMMARY

[0036] Problems to be Solved by the Invention

[0037] Thus, the conventional method has the following problems.

[0038] Problem 1: Variation of the masking time due to the condition at the time of short circuit

[0039] As described above, if the load of the IGBT becomes a short-circuit state, a large current flows, and the Vce of the IGBT rises and is broken, but it is necessary to make the masking time, which is a delay of detection, in a period of several microseconds. The masking time needs a certain precision, and in particular, it is necessary to be as constant as possible even if the condition at the time of load short circuit varies.

[0040] Here, the variation of the condition at the time of load short circuit can be exemplified by, for example, a variation in the size of the inductance connected to the IGBT at the time of short circuit. For example, it is desirable that the masking time does not vary in the case where the inductance of the load is very small (for example, 200 nH) and in the case where the inductance of the load is relatively large (for example, 2 μH).

[0041] However, in the case where a general-purpose control IC is used as a gate driver to drive the IGBT, the masking time varies mainly due to the variation of the condition at the time of load short circuit as described above.

[0042] Problem 2: Tolerance to malfunction

[0043] Further, the gate driver disposed in the vicinity of the IGBT under a large current and a high voltage requires a large tolerance to malfunction. However, the threshold voltage of the gate driver using a general-purpose control IC is sometimes low, and sometimes a sufficient tolerance to malfunction cannot be obtained.

[0044] The present application has been made in view of the above-described problems, and has an object to provide a gate drive circuit which realizes an increase in accuracy of a masking time and an increase in tolerance to a malfunction.

[0045] Technical means for solving the problems

[0046] First, regarding the increase in accuracy of the masking time, the following method is adopted: the initial charge of a capacitor which determines a time constant is controlled, and variation in the masking time is reduced. The present inventors have made intensive studies on methods such as controlling the initial charge of the capacitor to 0 or controlling the initial charge to a certain value, and as a result, the present application has been completed.

[0047] Further, regarding the increase in tolerance to a malfunction, the following method is adopted: a circuit in which a threshold voltage can be set separately is constructed. The present inventors have made intensive studies on various circuits in which a threshold voltage can be set separately, and as a result, the present application has been completed.

[0048] Specifically, the present application adopts the following means.

[0049] (1) The present application is a gate drive circuit which drives a power semiconductor switch, and includes: a comparison circuit which compares a collector-emitter voltage of the power semiconductor switch with a prescribed threshold voltage; and a time measurement circuit which starts measuring time after the comparison circuit detects that the collector-emitter voltage exceeds the threshold voltage, and the gate drive circuit includes: an output circuit which outputs an abnormality signal indicating that the power semiconductor switch is in an abnormal state after the time measurement circuit measures a standby retention time.

[0050] (2) Further, the present application is the gate drive circuit described in (1), wherein the comparison circuit compares the collector-emitter voltage with the prescribed threshold voltage in a case where the power semiconductor switch is in a state of saturation, or in a case where the power semiconductor switch becomes a desaturation state due to an increase in collector current caused by a prescribed obstacle or abnormality after the power semiconductor switch has just shifted from an OFF operation to an ON operation.

[0051] (3) Further, the present application is the gate drive circuit described in (1) or (2), wherein the abnormality signal is a signal indicating that the power semiconductor switch is in a desaturation state in accordance with a change in a prescribed output signal to a prescribed value.

[0052] (4) Furthermore, the gate drive circuit according to any one of (1) to (3), wherein the time measuring circuit includes a charging capacitor that is a capacitor to which a charging current of a certain current value is applied, and that sets a time until a voltage between terminals of the capacitor rises to a predetermined voltage value along with charging as the standby reservation time, and a charging current bypass circuit that bypasses the charging current of the certain current value when the power semiconductor switch is in a saturated state and a value of a collector-emitter voltage is below a threshold voltage of the comparator, does not flow the charging current into the charging capacitor, sets an initial charge of the charging capacitor to 0, and that, when the power semiconductor switch becomes a desaturated state and it is detected that the collector-emitter voltage exceeds the threshold voltage of the comparator, causes the charging current bypass circuit to block, and causes the charging current of the certain current value to flow into the capacitor from a state in which the initial charge of the capacitor is 0.

[0053] (5) Furthermore, the gate drive circuit according to (4), wherein it includes a first initial charge charging circuit that, in a case where a delay time is generated until the power semiconductor switch actually becomes an ON state after outputting a signal that causes the power semiconductor switch that is a drive target to transition from an OFF state to an ON state, causes an initial charge to remain in the charging capacitor, generates the standby reservation time to the extent that a charging time of the initial charge is short, and the output circuit outputs an abnormal signal that indicates that the power semiconductor switch is in a desaturated state after the time measuring circuit measures the short standby reservation time.

[0054] (6) Furthermore, the gate drive circuit according to (4), wherein, in a case where a delay time is generated until the power semiconductor switch actually becomes an ON state after outputting a signal that causes the power semiconductor switch that is a drive target to transition from an OFF state to an ON state, the charging current bypass circuit includes a bypass switch that bypasses the charging current, and a series circuit of a resistance that is directly connected to the bypass switch, causes an initial charge to remain in the charging capacitor to the extent of an initial charge resistance even in a case where the charging current is bypassed by the charging current bypass circuit, generates the standby reservation time to the extent that a charging time of the initial charge is short, and the output circuit outputs an abnormal signal that indicates that the power semiconductor switch is in a desaturated state after the time measuring circuit measures the short standby reservation time.

[0055] (7) Furthermore, the gate drive circuit according to any one of (1) to (6), comprising: a diode having a cathode terminal connected to the comparison circuit and an anode terminal connected to a collector terminal of the power semiconductor switch, the comparison circuit detecting the collector voltage of the power semiconductor switch via the diode.

[0056] Effects of the Invention

[0057] According to the present application, a gate drive circuit can be provided which drives a power semiconductor switch and achieves an improvement in accuracy of standby retention time (masking time) and an improvement in tolerance to a malfunction. BRIEF DESCRIPTION OF DRAWINGS

[0058] FIG. 1 Circuit diagram of the gate drive circuit 100 of Embodiment 1.

[0059] FIG. 2 Circuit diagram of the gate drive circuit 100 of Embodiment 1. FIG. 1 Functional block diagram of the circuit shown in FIG. 1.

[0060] FIG. 3 Circuit diagram of the gate drive circuit 200 of Embodiment 2.

[0061] FIG. 4 Circuit diagram of the equivalent circuit of the transition state of the IGBT from OFF operation to ON operation.

[0062] FIG. 5 Graph showing the voltage waveform of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 in the case where the diode D1 is not inserted.

[0063] FIG. 6 Graph showing the voltage waveform of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 in the case where the diode D1 is inserted.

[0064] FIG. 7 Time chart showing the condition of variation of the masking time when a load abnormality occurs after the ON operation of the IGBT 12 is completed in the case where the transition operation of the IGBT 12 to ON operation is delayed.

[0065] FIG. 8 Time chart showing the condition of variation of the masking time when a load abnormality occurs before the ON operation of the IGBT 12 is completed in the case where the transition operation of the IGBT 12 to ON operation is delayed.

[0066] FIG. 9 Circuit diagram of the gate drive circuit 300 of Embodiment 3.

[0067] FIG. 10 A time chart showing the state of the variation of the blocking time in the case where the load is abnormal after the ON operation of the IGBT 12.

[0068] FIG. 11 A circuit diagram of the gate drive circuit 400 for showing an example of another structure of the circuit for generating the initial charge.

[0069] FIG. 12 A circuit diagram of the gate drive circuit 500 for one of the specific embodiments.

[0070] FIG. 13 A chart of the blocking time for showing the case where the abnormality occurs after 20 μsec after the ON operation of the IGBT 12.

[0071] FIG. 14 A chart of the blocking time for showing the case where the abnormality occurs immediately after the ON operation of the IGBT 12.

[0072] FIG. 15 A circuit diagram of the gate drive circuit 600 for another of the specific embodiments.

[0073] FIG. 16 A circuit diagram of the gate drive circuit 700 for still another of the specific embodiments.

[0074] FIG. 17 A circuit diagram of the circuit structure for showing the case where the conventional gate driver 10 drives the IGBT 12.

[0075] [Explanation of Symbols]

[0076] 10, 110: Gate driver

[0077] 12: IGBT

[0078] 14, 114: OUT terminal

[0079] 16, 116: Inverter

[0080] 18, 118: Comparator

[0081] 100, 200, 300, 400, 500, 600, 700: Gate drive circuit

[0082] 120: Buffer

[0083] 130: Time measuring circuit

[0084] 132: Comparison circuit

[0085] C1, C2, C3, Cdesat: Capacitor

[0086] CMP1, CMP2, IC1: Comparators

[0087] D1, D2, D3, D4, Ddesat: Diodes

[0088] Idesat: Current source

[0089] Rb, R1, R2, R3, R4, R5, R6, Rdesat, Rb: Resistors

[0090] Q1, Q2: Transistors

[0091] Vb: Voltage source

[0092] VCC: Positive power supply

[0093] Vce: Collector-emitter voltage

[0094] Vdesat: Reference voltage

[0095] Vdesat-1: First reference voltage

[0096] Vdesat-2: Second reference voltage

[0097] Vhi: Collector voltage Detailed Implementation

[0098] Hereinafter, suitable embodiments of the present invention will be described with reference to the accompanying drawings.

[0099] 1. Embodiment 1

[0100] FIG. 1 The diagram shown below illustrates the gate drive circuit 100 of this embodiment. FIG. 1 In this circuit, the portion other than IGBT12 becomes the characteristic part of the gate drive circuit 100.

[0101] like FIG. 1 As shown, for the same as FIG. 17 The conventional circuit shown also utilizes the gate driver 110 circuitry, and the structure and operation of this gate driver 110 are the same as those of the conventional circuit. FIG. 17 The gate driver 10 shown has the same structure and operation. This gate driver 110 can also be used with... FIG. 17 The gate driver 10 shown also includes the specified IC, etc.

[0102] The OUT terminal 114 of the gate driver 110 is connected to the gate terminal of the IGBT 12 via the buffer 120, and drives the IGBT 12. Between the GND terminal and the DESAT terminal of the gate driver 110, the capacitor Cdesat is connected. This capacitor Cdesat is an element that plays an important role in the determination of the blocking time by the charging operation thereof, as will be described later.

[0103] Here, the IGBT 12 corresponds to a suitable example of the power semiconductor switch of the claim. The gate drive circuit 100 corresponds to a suitable example of the gate drive circuit of the claim. Further, the gate drive circuits 200, 300, 400, 500, 600, 700 to be described later also correspond to suitable examples of the gate drive circuit of the claim.

[0104] The collector terminal of the transistor Q2 is connected to the DESAT terminal, and the emitter terminal is connected to the GND terminal. The base terminal of the transistor Q2 is connected to the output terminal of the comparator CMP2. The transistor Q2 plays a role of discharging the charge of the capacitor Cdesat, as will be described later. The inverting input terminal of the comparator CMP2 is connected to the positive side power supply VCC via the resistor Rdesat. Further, the inverting input terminal is connected to the anode terminal of the diode Ddesat.

[0105] The anode terminal of the diode Ddesat is connected to the inverting input terminal of the comparator CMP2, and the cathode terminal is connected to the collector terminal of the IGBT 12.

[0106] The non-inverting input terminal of the comparator CMP2 is connected to the positive terminal of the second reference voltage Vdesat-2. The other (negative side) terminal of the second reference voltage Vdesat-2 is connected to the GND terminal.

[0107] Further, the emitter terminal of the IGBT 12 is connected to the GND terminal.

[0108] Further, the transistor Q2 corresponds to a suitable example of the charging current bypass circuit of the claim.

[0109] When the IGBT 12 is in the OFF operation state, the collector voltage of the IGBT 12 becomes a high voltage, and thus the positive side power supply VCC is applied to the inverting input terminal of the comparator CMP2. The output signal of the comparator CMP2 becomes Low, and the transistor Q2 becomes the OFF state.

[0110] At this time, the output signal of the OUT terminal of the gate drive 110 (applied to the gate terminal of the IGBT 12) is Low, and this output signal is inverted by the inverter 116 to become High, and is applied to the base terminal of the transistor Ql. Therefore, the transistor Ql of the gate drive 110 maintains the ON operation state, and discharges the charge of the capacitor Cdesat. Therefore, the initial voltage of the capacitor Cdesat becomes 0 V.

[0111] The capacitor Cdesat corresponds to a suitable example of the charge capacitor of the claim. In addition, the capacitor C3 of the following FIG. 12 The capacitor C3 of the following

[0112] If the output signal of the OUT terminal 114 becomes High, the IGBT 12 becomes the ON operation state. At this time, the output signal of the OUT terminal 114 is inverted by the inverter 116 and is applied to the base terminal of the transistor Al, and thus the transistor Ql becomes the OFF state.

[0113] The collector-emitter voltage (collector voltage) of the IGBT 12 becomes the saturation voltage, and thus the voltage applied to the inverting input terminal of the comparator CMP2 becomes the sum of the forward voltage of the diode Ddesat and the saturation voltage of the collector-emitter of the IGBT 12, that is, VFDdesat + VCEsat, and is lower than the second reference voltage Vdesat-2, and thus the transistor Q2 becomes the ON state.

[0114] In the present embodiment, it is characteristic that even if the IGBT 12 becomes the ON operation state, the ON operation is performed by the transistor Q2, and thus the charge of the capacitor Cdesat is not performed. As a result, the voltage between the terminals of the capacitor Cdesat can be maintained in the state of 0 V. That is, the initial voltage of the capacitor Cdesat can be fixed to 0.

[0115] Here, if the load of the IGBT 12 becomes abnormal, the collector-emitter voltage of the IGBT 12 rises and exceeds the second reference voltage Vdesat-2 - VFDdesat, and thus the voltage of the inverting input terminal of the comparator CMP2 exceeds the second reference voltage Vdesat-2. Therefore, the output signal of the comparator CMP2 becomes Low, and the transistor Q2 performs the OFF operation, and the charge of the capacitor Cdesat is started by the current source Idesat in the gate drive 110.

[0116] If the inter-terminal voltage VCdesat of capacitor Cdesat exceeds the first reference voltage Vdesat-1 due to the charging, the output signal of comparator CMP1 in gate driver 110 is reversed to high, and an abnormal signal is sent out.

[0117] The blocking time from when the collector-emitter voltage of IGBT12 becomes abnormal and exceeds Vdesat-2-VFDdesat until the abnormal signal is sent is expressed by the following formula (5).

[0118] [Number 5]

[0119]

[0120] Thus, in equation (5), the VCdesat(0) term accompanying the initial charge of the capacitor Cdesat is irrelevant as in equation (2) of the prior art, and therefore a certain blocking time can be achieved without depending on the timing of the anomaly.

[0121] Furthermore, the second reference voltage Vdesat-2 can be arbitrarily selected as long as it is below the positive voltage VCC, thus further increasing the tolerance for malfunctions such as noise. Therefore, the disadvantage of conventional methods in that it is difficult to ensure noise tolerance can be eliminated. The second reference voltage Vdesat-2 corresponds to a suitable example of the threshold voltage specified in the claims.

[0122] Functional block diagram

[0123] This embodiment 1 FIG. 1 The functional block diagram of the circuit is shown in FIG. 2 .

[0124] FIG. 2 In the functional block diagram, in addition to the gate driver 110, a time measurement circuit 130 and a comparison circuit 132 are shown.

[0125] Comparator circuit 132 is equivalent to FIG. 1 The circuitry of comparator CMP2 and the second reference voltage Vdesat-2 corresponds to a suitable example of the comparator circuit of the claim. Therefore, comparator circuit 132 compares the collector-emitter voltage of IGBT 12 with the second reference voltage Vdesat-2 and outputs the comparison result.

[0126] Moreover, the second reference voltage corresponds to a suitable example of the threshold voltage specified in the claim.

[0127] Time measurement circuit 130 is equivalent to FIG. 1 The circuit of capacitor Cdesat and transistor Q2 is a suitable example of the time measurement circuit of the claim.

[0128] The transistor Q2 constitutes a charging current bypass circuit of the claim, and performs an operation of bypassing or not bypassing the charging current of the capacitor Cdesat based on the output signal of the comparison circuit 132 to charge the capacitor Cdesat.

[0129] One of the characteristic matters in the present embodiment is that a charging current bypass circuit (transistor Q2) is provided. Thereby, the charge of the capacitor Cdesat at the charging start time point can be set to 0 in advance, and thus the measurement of the shading time can be made more accurate.

[0130] The gate driver 110 corresponds to a suitable example of the output circuit of the claim. In particular, the output signal of the comparator CMP1 corresponds to a suitable example of the abnormal signal of the claim.

[0131] 2. Embodiment 2

[0132] The circuit diagram of the gate drive circuit 200 of Embodiment 2 is shown in FIG. 3 . FIG. 3 A diode D1 is inserted between the inverting input terminal of the comparator CMP2 and the anode of the diode Ddesat and a capacitor Cl is additionally provided in the circuit of FIG. 1 . The capacitor Cl indicates a capacitor inserted in order to absorb the parasitic capacitance of the inverting input terminal of the comparator CMP2 or noise that causes a malfunction. The structures other than these additional structures are the same as those of FIG. 1 .

[0133] Further, the diode D1 corresponds to a suitable example of the diode of the claim.

[0134] Thus, when the capacitor Cl is present, sometimes due to the transition phenomenon of the IGBT 12 from the OFF operation to the ON operation, the charge of the capacitance present between the terminals of the diode Ddesat charges the capacitor Cl in the negative direction, and the shading time fluctuates. The diode D1 is a diode for preventing such a phenomenon.

[0135] When the IGBT 12 is in the OFF state, the diode Ddesat is subjected to a reverse bias, and thus can be considered as a capacitor equivalently. A voltage close to the collector voltage when the IGBT 12 is in the OFF state is applied to the equivalent capacitor, and if the IGBT 12 transitions from the OFF state to the ON state, immediately thereafter, as shown in the equivalent circuit of FIG. 4 , the capacitor Cl is charged in the negative direction, and the detection operation of the comparator CMP2 is delayed in time until it recovers. FIG. 4 The equivalent circuit of the transition state of the IGBT 12 from the OFF operation to the ON operation is shown in

[0136] Here, FIG. 4 Vhi is the collector voltage of the IGBT 12 when the OFF operation is performed, and is set to a voltage sufficiently higher than the positive-side power supply VCC. Therefore, the transition waveform of the voltage between the terminals of the capacitor Cl when the IGBT 12 performs the ON operation from the OFF operation is considered as Vhi - VCC « Vhi, and can be represented by Equation (6).

[0137] [Equation 6]

[0138]

[0139] According to Equation (6), at the instant when the IGBT 12 performs the ON operation, the voltage between the terminals of the capacitor Cl is charged to -Vhi x (CDdesat / (Cl + CDdesat)) in the negative direction. Then, it is restored to 0 V with the time constant Rdesat (Cl + CDdesat). This restoration time results in a difference in the masking time between a case where the load abnormality occurs immediately after the IGBT 12 performs the ON operation and a case where the load abnormality occurs after the restoration time ends.

[0140] Further, CDdesat represents the capacitance of the equivalent capacitor of the diode Ddesat, Cl represents the capacitance of the capacitor Cl, and Rdesat 1 represents the resistance value of the resistor Rdesat.

[0141] That is, if the load abnormality occurs immediately after the IGBT 12 performs the ON operation, the detection of the rise of the collector-emitter voltage Vce of the IGBT 12 is delayed by the extent of the restoration time, and thus the final masking time is lengthened by the extent of the restoration time. Therefore, as shown in the graph of FIG. 10 of Embodiment 2, FIG. 3 the phenomenon can be suppressed by inserting the diode Dl.

[0142] The voltage waveform of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 in the case where the diode Dl is not inserted and in the case where the diode Dl is inserted is shown in the graphs of FIGS. 11 and 12, respectively. In each graph, the horizontal axis represents the time elapse, and the voltage waveform of the non-inverting input terminal and other various signal waveforms are shown on the vertical axis. FIG. 5 FIG. 6

[0143] In the case where the diode Dl is not inserted (FIG. 11), FIG. 5 the potential of the non-inverting input terminal of the comparator CMP1 of the gate driver 110 decreases in the negative direction at the instant when the IGBT 12 performs the ON operation, and then the value of the potential is gradually restored. FIG. 5 In the example of FIG. 11, FIG. 4 ​​with a label of "increased time". Thus, the blocking time is lengthened by the degree of the "increased time", resulting in variation of the blocking time. That is, the time until the charging voltage of the capacitor Cdesat exceeds the first reference voltage Vdesat-1 becomes the blocking time, but the variation of the blocking time is eliminated by FIG. 5 indicating that the blocking time is lengthened (varies) by the degree of the "increased time".

[0144] On the other hand, in the case where the diode D1 is inserted, the voltage variation at the non-inverting input terminal of the comparator CMP1 of the gate driver 110 is eliminated, indicating that there is no reason for variation of the blocking time (refer to FIG. 6 ).

[0145] As described above, according to the present embodiment, noise that causes a malfunction can be effectively removed, and variation of the blocking time is suppressed.

[0146] 3. Embodiment 3

[0147] According to the characteristics of the IGBT 12 or requirements of the object setting side where power control is performed by the IGBT 12, sometimes, after an ON signal is generated from a control circuit that outputs a control signal of the IGBT 12, a long delay time occurs until the IGBT 12 actually becomes an ON operation. The characteristics of the IGBT 12 are, for example, a case where the gate resistance is very large, and the like.

[0148] In such a case, the blocking time in the load circuit shown in Embodiment 1 FIG. 1 ) also sometimes varies due to the timing of occurrence of an abnormality.

[0149] FIG. 7 、 FIG. 8 A time chart indicating a case where a load abnormality occurs after the IGBT 12 completes an ON operation is shown in FIG. 12. In other words, a time chart of a case where a load abnormality occurs after a delay time of an ON operation of the IGBT 12 is shown. FIG. 1 In the circuit of the gate drive circuit 100 described in Embodiment 1, in a case where a transition operation of the IGBT 12 to an ON operation is delayed, the blocking time varies due to the timing of occurrence of a load abnormality.

[0150] FIG. 7 A case where a load abnormality occurs after the IGBT 12 completes an ON operation is shown in FIG. 12. In other words, a time chart of a case where a load abnormality occurs after a delay time of an ON operation of the IGBT 12 is shown. FIG. 7 In FIG. 12, the horizontal axis indicates the passage of time, and the vertical axis indicates various signals. Specifically, the voltage across the capacitor Cdesat, the ON / OFF state of the IGBT 12, the gate-source voltage of the IGBT 12, and a control signal from a control circuit that controls the IGBT 12 are shown.

[0151] First, if the control signal from the control circuit becomes a value that causes the IGBT 12 to perform the ON operation, the gate-source voltage of the IGBT 12 starts to rise, and the voltage across the capacitor Cdesat also starts to rise.

[0152] FIG. 7 In the example of FIG. 10, the response speed of the IGBT 12 is slow, and the IGBT 12 transitions to the ON operation after the delay time td elapses. Then, the voltage across the capacitor Cdesat is reset to 0. However, if an abnormality occurs, such as a short-circuit abnormality of the load, the charging of the capacitor Cdesat starts, and the timing of the shield time starts.

[0153] The shield time at this time is t1 (refer to FIG. 9). FIG. 7 The charging of the capacitor Cdesat starts from the initial charge of 0, and the charging time until the voltage across the capacitor Cdesat reaches Vdesat from 0 V becomes the shield time.

[0154] On the other hand, FIG. 8 is an example in which an abnormality of the load occurs before the IGBT 12 performs the ON operation. In other words, it is a time chart of a case in which an abnormality of the load occurs within the delay time of the ON operation of the IGBT 12.

[0155] FIG. 8 As with FIG. 7 , the horizontal axis indicates the elapse of time, and the same kinds of signals as in FIG. 7 are plotted on the vertical axis.

[0156] If the control circuit, which specifies the operation of the normal gate driver 110, sets the value of the control signal to a value that causes the IGBT 12 to perform the ON operation (if an instruction to perform the ON operation occurs), at substantially the same time, the bypass circuit of the charging current inside the gate driver 110 is blocked (the transistor Q1 performs the OFF operation).

[0157] That is, FIG. 1 , the output signal of the OUT terminal becomes High, and this signal is applied to the base terminal of the transistor Q1 via the inverter 116, and thus the transistor Q1, which is the bypass circuit of the charging current, is turned off.

[0158] FIG. 8 In the example of FIG. 10, the ON operation of the IGBT 12 is delayed, and thus FIG. 1The voltage at the inverting input terminal of comparator CMP2 is higher than Vdesat-2, therefore transistor Q2 also remains off. Thus, approximately simultaneously with the control signal issuing the command to turn IGBT12 on, charging of the charging capacitor Cdesat begins. This situation is shown in... FIG. 8 The time diagram shows that the gate-source voltage of IGBT12 gradually increases during this period. However, due to the delay in the ON operation of IGBT12, the OFF state of IGBT12 persists for a certain period (see reference). FIG. 8 ).

[0159] Specifically, the IGBT12 is in the OFF state for a period of time td.

[0160] FIG. 8 In the example described, an obstacle such as a short circuit occurs before the IGBT12 performs an ON operation.

[0161] Then, after FIG. 8 After a delay time td, IGBT12 transitions to the ON position. However, when IGBT12 transitions to the ON position (after the delay time td), a load anomaly has already occurred. Therefore, even after IGBT12 transitions to the ON position, the voltage at the inverting input terminal of comparator CMP2 remains higher than Vdesat-2, and transistor Q2 remains in the OFF state, allowing capacitor Cdesat to continue charging. Therefore, the time it takes for the voltage between the terminals of capacitor Cdesat to rise from 0V to Vdesat-1 is t2 (refer to...). FIG. 8 ).

[0162] This time t2 is... FIG. 7 The blocking time t1 is the same as the time. However, the time measurement of the unsaturated state (Desaturation state, hereinafter referred to as the Desat state) must begin after the IGBT12 actually enters the Desat state. That is, at this time, it must be measured immediately after the IGBT12 transitions to the ON operation (after... FIG. 8 The time point td in the time measurement is the starting point of the time measurement. The reason for this is that the protection of Desat detection (detection of unsaturated state) must determine the blocking time from the point of view of preventing the protection circuit from malfunctioning while protecting IGBT12, and therefore a balance between the two must be considered as much as possible.

[0163] If the occlusion time is defined in this way, then the so-called FIG. 8 The occlusion time under the described conditions is FIG. 8 The t3 shown has a ratio of FIG. 7the delay time td of the shorted IGBT 12, and the like.

[0164] In this case, as FIG. 9 indicated, with regard to the discharge of the capacitor Cdesat by the transistor Q2, it is preferable to take the following method: at the start of the discharge of the capacitor Cdesat, the capacitor Cdesat is given an initial charge. FIG. 9 The Vb functions as follows: if the IGBT 12 completes the transition to the ON operation, the discharge of the capacitor Cdesat is performed by the transistor Q2, but the charge of the capacitor Cdesat is not discharged completely, and the voltage between the terminals of the capacitor Cdesat remains Vb. That is, even if the transistor Q2 performs the ON operation, the voltage between the terminals of the capacitor Cdesat does not become 0 V, but becomes Vb. The value of Vb is set to be equal to the voltage between the terminals of the capacitor Cdesat at the time when the IGBT 12 transitions to the ON operation with its own delay time. FIG. 7

[0165] Thus, Vb is set to Vb( FIG. 9 ) = Vd( FIG. 7 ). As a result, the blocking time can be set to be constant regardless of the timing of the occurrence of the load abnormality, as FIG. 9 indicated.

[0166] Further, the circuit shown in FIG. 9 is the same as the circuit shown in FIG. 1 except for the aspect that a new voltage source Vb is provided. That is, FIG. 9 the gate drive circuit 300 shown in FIG. 1 is the same circuit as the gate drive circuit 100 shown in except for the voltage source Vb.

[0167] Moreover, Vb corresponds to a suitable example of the first initial charge charging circuit.

[0168] The operation of the circuit (gate drive circuit 300) shown in FIG. 9 will be described with reference to a time chart shown in FIG. 10 . FIG. 10 In FIG. 7 , FIG. 8 , a time chart substantially the same as that shown in FIG. 7 , FIG. 8 is shown. The horizontal axis indicates the passage of time, and the same kinds of signals as those shown in FIG. 10 , FIG. 7 are shown on the vertical axis. If this time chart is compared with the time chart shown in ,

[0169] at the time point when the IGBT 12 starts the ON operation, FIG. 7 In this case, the voltage between the terminals of the capacitor Cdesat is reset to 0, but FIG. 10 In the time chart of this case, the voltage Vd at this time point is maintained. This is due to the voltage source Vb of the new structure shown in FIG. 6, and since Vb = Vd is set, this time chart results. FIG. 9

[0170] FIG. 10 In this case, the voltage between the terminals of the capacitor Cdesat is reset to 0, but FIG. 7 The example in which the short-circuit failure occurs after the ON operation of the IGBT 12 is explained in the same manner. In the aspect of starting the charging of the capacitor Cdesat after the short-circuit failure occurs, FIG. 8 is the same as FIG. 7 However, FIG. 10 In the example shown in FIG. 7, the voltage Vb (= Vd) is already charged in the capacitor Cdesat at the charging start time point, and thus the initial voltage at the charging start time point is different. As a result of this, FIG. 7 The blocking time of the example of FIG. 7 becomes t4, and as explained above, this time is the same time as the blocking time t3 of the example of FIG. 6. FIG. 10

[0171] FIG. 8

[0172] Another circuit structure for creating the initial charge is shown in FIG. 8. Another example of setting of initial value of charge As shown in this figure, a method of inserting a resistance Rb in series to the collector of the transistor Q2 is used. At this time, the initial charge Vd becomes Vd = IdesatRb. In this equation, Rb is the resistance value of the resistance Rb, and the voltage generated by the current of the current source Idesat in the resistance Rb is used.

[0173] Therefore, Rb corresponds to a suitable example of the initial charge resistance of the claim. Also, the transistor Q2 corresponds to a suitable example of the bypass switch of the claim.

[0174] As explained above, according to Embodiment 2, the voltage value at the charging start time point of the capacitor Cdesat is set to a prescribed value, and thus the blocking time can be maintained at a certain value regardless of the time point at which the load abnormality occurs, before or after the ON operation of the IGBT 12. FIG. 11

[0176] 4. Specific Embodiment

[0177] 4.1 First Specific Embodiment A circuit diagram of a gate drive circuit 500 as a specific example of the application is shown in FIG. 9. The gate driver 110 is FIG. 12 ,​​FIG. 1 FIG. 2 FIG. 8 The gate driver used for driving the IGBT can also include an IC or the like. The comparator IC 1 is a comparator that outputs an open collector output. A divided voltage of VCC obtained by resistors Rl and R2 and a capacitor C2 constitute a hysteresis circuit of the comparator IC 1. The divided voltage of VCC is input to the non-inverting input terminal of the comparator IC 1, and the voltage of the capacitor C2 is input to the inverting input terminal of the comparator IC 1. The capacitor C2 is charged by the resistor Rl and the resistor R2. The resistor R3 is a resistor for reducing the impedance of the input terminal of the comparator IC 1. The resistor R4 and the capacitor Cl are for increasing the tolerance of false operation, and thus are a resistor and a capacitor for reducing the impedance of the input terminal of the comparator IC 1. The capacitor C3 is a capacitor for making a dead time. The diode Dl corresponds to the diode Ddesat of the comparator CMP 2 and the transistor Q2 of the embodiment 1. The resistor R5 is a resistor corresponding to the Rb of the comparator CMP 2 and the transistor Q2 of the embodiment 3. FIG. 10 FIG. 1 FIG. 3 FIG. 9 The second reference voltage Vdesat-2 of the comparator IC 1 is higher than the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 in the case where the IGBT 12 is turned on in a normal range. The second reference voltage Vdesat-2 and the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 are in the following relationship of formula (8). FIG. 11 The diode Dl corresponds to the diode Ddesat of the comparator CMP 2 and the transistor Q2 of the embodiment 1. The resistor R5 is a resistor corresponding to the Rb of the comparator CMP 2 and the transistor Q2 of the embodiment 3. FIG. 3

[0178] The comparator IC 1 is a comparator corresponding to the comparator CMP 2 and the transistor Q2 of the embodiment 1. That is, the output transistor of the comparator IC 1 is an open collector, and functions as the transistor Q2 of the embodiment 1. Therefore, the structure corresponding to the transistor Q2 of the embodiment 1 is not directly depicted in the embodiment 2. FIG. 11 The comparator IC 1 is a comparator corresponding to the comparator CMP 2 and the transistor Q2 of the embodiment 1. That is, the output transistor of the comparator IC 1 is an open collector, and functions as the transistor Q2 of the embodiment 1. Therefore, the structure corresponding to the transistor Q2 of the embodiment 1 is not directly depicted in the embodiment 2. FIG. 1 The comparator IC 1 is a comparator corresponding to the comparator CMP 2 and the transistor Q2 of the embodiment 1. That is, the output transistor of the comparator IC 1 is an open collector, and functions as the transistor Q2 of the embodiment 1. Therefore, the structure corresponding to the transistor Q2 of the embodiment 1 is not directly depicted in the embodiment 2. FIG. 1 The comparator IC 1 is a comparator corresponding to the comparator CMP 2 and the transistor Q2 of the embodiment 1. That is, the output transistor of the comparator IC 1 is an open collector, and functions as the transistor Q2 of the embodiment 1. Therefore, the structure corresponding to the transistor Q2 of the embodiment 1 is not directly depicted in the embodiment 2.

[0179] The diodes D2, D3, and D4 correspond to the diode Ddesat of the comparator CMP 2 and the transistor Q2 of the embodiment 1. FIG. 12 FIG. 1 FIG. 3 FIG. 9 The second reference voltage Vdesat-2 of the comparator IC 1 is higher than the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 in the case where the IGBT 12 is turned on in a normal range. The second reference voltage Vdesat-2 and the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 are in the following relationship of formula (8). FIG. 11 FIG. 1 FIG. 3 FIG. 9 The second reference voltage Vdesat-2 of the comparator IC 1 is higher than the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 in the case where the IGBT 12 is turned on in a normal range. The second reference voltage Vdesat-2 and the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 are in the following relationship of formula (8). FIG. 11

[0180] [Num 7]

[0181]

[0182] The second reference voltage Vdesat-2 of the comparator IC 1 is higher than the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 in the case where the IGBT 12 is turned on in a normal range. The second reference voltage Vdesat-2 and the maximum value of the voltage of the non-inverting input terminal of the comparator IC 1 are in the following relationship of formula (8).

[0183] ​​​​​​​​​​​​​VFD1+VFD2+VFD3+VFD4 (8)

[0184] [Num 8]

[0185] V SON = VCE SAT + VF D2-4 - VF D1 < V desat-2 (8)

[0186] When the output signal of the OUT terminal 114 of the gate driver 110 is Low, the IGBT 12 performs OFF operation. At this time, the diodes D2, D3, D4 are subjected to reverse bias and become in an off state. Therefore, the diode Dl is in a forward bias state, and the voltage of the non-inverting input terminal of the comparator IC1 becomes higher than the second reference voltage Vdesat-2.

[0187] Therefore, although the output transistor of the comparator IC1 becomes in an OFF state, the transistor Ql of the gate driver 110 becomes in an ON state, and thus the current source Idesat does not charge the capacitor C3 but flows to VEE via the transistor Ql. As a result, the voltage of the DESAT terminal of the gate driver 110 does not rise in this state and is always maintained at a voltage lower than the first reference voltage Vdesat-1, and thus the comparator CMP1 does not output an abnormal signal (the output signal does not become High).

[0188] If the IGBT 12 continues to operate normally while becoming in an ON operation, the collector-emitter voltage of the IGBT 12 is maintained at a saturation voltage VSAT or less. Therefore, the voltage of the non-inverting input terminal of the comparator IC1 becomes a voltage lower than VSON given by the above equation (8), and thus the output transistor of the comparator IC1 becomes in an ON operation. Therefore, the current source Idesat of the gate driver 110 flows to VEE via the output transistor of the comparator IC1 and does not charge the capacitor C3. Therefore, if the IGBT 12 is maintained in this state (in an ON state), an abnormal signal is not output (the output signal does not become High).

[0189] If an abnormality occurs in the load while IGBT12 is in ON mode and IGBT12 becomes in Desat state (desaturation state), the collector-emitter voltage of IGBT12 will rise. If the collector-emitter voltage of IGBT12 at this time is denoted as VCEDSAT, then the voltage VSONDESAT at the non-inverting input terminal of comparator IC1 is given by the following equation (9).

[0190] [Number 9]

[0191] V SONDESAT =VCE DESAT +VF D2-4 -VF D1 (9)

[0192] If VSONDESAT exceeds the second reference voltage Vdesat-2, the output transistor of comparator IC1 is turned off, and the current source Idesat flows to capacitor C3, starting the charging of capacitor C3. If the voltage between the terminals of capacitor C3 reaches the first reference voltage Vdesat-1 due to charging, comparator CMP1 reverses and sends out an abnormal signal (the output signal becomes high).

[0193] Therefore, the collector-emitter voltage VCEDET that indicates the IGBT12 is in a Desat state due to a load abnormality can be represented by the following equation (10). The blocking time Tmask from the time the IGBT12 is in a Desat state due to a load abnormality until the abnormal signal is sent is represented by the equation (5) described above.

[0194] [Number 10]

[0195] VCE DET =V desat-2 -VF D2-4 +VF D1 (10)

[0196] When the collector-emitter voltage of IGBT12 reaches VCEDET of equation (10) due to abnormal load or other reasons immediately after IGBT12 changes from OFF to ON, the equivalent capacitor between the terminals of diodes D2 to D4 is charged. FIG. 12 The high voltage of Ddesat) FIG. 4 The diode (Vhi) attempts to charge capacitor C1 in the negative direction, but diode D1 becomes reverse biased, preventing charging in the negative direction.

[0197] Therefore, as a suitable embodiment of the present invention FIG. 4The circuit can keep the delay time, i.e. the blocking time, from the detection of the Desat state of IGBT12 until the abnormal signal is sent out, constant.

[0198] Experimental data on the blocking time of the IGBT12 after it is turned on (ON) and then turns off (Desat) after approximately 20 μsec are presented below, along with the blocking time of the IGBT12 immediately after it is turned on (ON) and then turns off (Desat). FIG. 12 , FIG. 13 The occlusion time can be confirmed to be approximately 4.6 μsec, with almost no difference in occlusion time between the two, indicating that a certain amount of occlusion time can be obtained. FIG. 14 , FIG. 13 The horizontal axis represents the passage of time, and the vertical axis represents the voltage or current value.

[0199] FIG. 14 The graph depicts the gate voltage, collector current, and collector-emitter voltage. At the moment the IGBT12 transitions to the ON state, the gate voltage rises instantaneously, and the collector-emitter voltage drops instantaneously. Furthermore, from the moment the IGBT12 transitions to the ON state, the collector current gradually increases.

[0200] FIG. 13 In the chart, the IGBT12 became abnormal after 20μsec when it was turned on, and started sending out an abnormal signal after a blocking time of 4.7μsec.

[0201] FIG. 13 Although the charts have different time scales, they are similar in purpose to... FIG. 14 Charts of the same type show the same type of signals.

[0202] Furthermore, if the delay time from when IGBT12 receives the ON signal until it is actually ON is long, then if the delay time is adjusted accordingly... FIG. 13 If the output of comparator IC1 is inserted with resistor Rd, the blocking time can be kept constant.

[0203] FIG. 12

[0204] 4.2 Second Specific Embodiment The diagram shows a circuit diagram of a gate drive circuit 600 as a second specific embodiment of the invention. FIG. 15 The gate drive circuit 500 differs in one aspect: the connection position of resistor R3.

[0205] FIG. 14 In the gate drive circuit 500, resistor R3 is configured to connect the positive power supply VCC to the anode side of diode D1. In contrast,FIG. 14 In the gate drive circuit 600, the resistor R3 is provided in a manner to connect the output signal of the OUT terminal 114 to the anode side of the diode Dl. Actually, as FIG. 15 that, the output signal of the buffer 120 is connected, not the output signal of the OUT terminal 114. The reason for this is that the output current of the output signal of the buffer 120 is large, and it can be considered that even if the resistor R3 is connected, it hardly has an influence on the drive of the IGBT 12.

[0206] According to this connection, in the case where the IGBT 12 is in the OFF state, it can be considered that the non-inverting input terminal of the comparator IC1 can be maintained at Low, and a circuit with high noise resistance can be constituted.

[0207] FIG. 15

[0208] 4.3 Third Specific Embodiment A circuit diagram of a gate drive circuit 700 as a third specific embodiment of the application is shown in FIG. 7. The gate drive circuit 700 is different from the gate drive circuit 600 of FIG. 16 the aspect that the resistor R6 is provided. Due to the presence of the resistor R6, a circuit with further improved noise resistance can be constituted.

[0209] FIG. 15 5. Effects, Modified Examples, and Others

[0210] As explained above, according to the present embodiment, a gate drive circuit can be provided in which the shielding time after the occurrence of an abnormality can be maintained at a certain value, and the noise resistance is improved, and stable abnormality occurrence detection can be performed.

[0211] Moreover, the above-described embodiments are examples of a means for achieving the present application, and should be appropriately modified or changed according to the structure of the device to which the present application is applied or various conditions, and the present application is not limited to the modes of the embodiments. For example, in the embodiments, with respect to the power semiconductor switch as the drive object, mainly the IGBT was explained, but it can also be applied to a gate drive circuit that drives other power semiconductor switches (for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET)). Moreover, in the above-described embodiments and examples, the gate driver 110 and each individual element and circuit structure attached thereto were explained, but it can also be constituted using an IC, a Large-Scale Integration (LSI), or the like.

[0212] Industrial applicability

[0213] According to the present application, a gate drive circuit can be provided which drives a power semiconductor switch and achieves an improvement in accuracy of a standby retention time (masking time) and an improvement in tolerance to a malfunction.

Claims

1. A gate drive circuit which drives a power semiconductor switch, characterized by, comparing circuit that compares a collector-emitter voltage of the power semiconductor switch with a prescribed threshold voltage; and a time measuring circuit that starts measuring time after the comparing circuit detects that the collector-emitter voltage exceeds the threshold voltage, and the gate drive circuit includes: an output circuit that outputs an abnormality signal indicating that the power semiconductor switch is in an abnormal state after the time measuring circuit measures the standby retention time, the time measuring circuit includes: a charging capacitor that is a capacitor to which a charging current of a certain current value is applied, and that is used to set a time during which a voltage across the terminals of the capacitor rises accompanying charging until it becomes a prescribed voltage value as the standby retention time; and a charging current bypass circuit that causes the charging current of the certain current value to bypass when the power semiconductor switch is in a saturation state and the value of the collector-emitter voltage is below the threshold voltage of the comparing circuit, does not cause the charging current to flow into the charging capacitor, and sets an initial charge of the charging capacitor to 0, the comparing circuit causes the charging current bypass circuit to block, causing the charging current of the certain current value to flow into the charging capacitor from a state in which the initial charge of the charging capacitor is 0, in a case in which the power semiconductor switch is in a desaturation state and it is detected that the collector-emitter voltage exceeds the threshold voltage of the comparing circuit.

2. The gate drive circuit according to claim 1, wherein the comparing circuit compares the collector-emitter voltage with a prescribed threshold voltage in a case in which the power semiconductor switch becomes a desaturation state due to an increase in collector current caused by a prescribed obstacle or abnormality after the power semiconductor switch has just transitioned from an off operation to an on operation or in a case in which the power semiconductor switch is in a saturation state.

3. The gate drive circuit according to claim 1 or 2, wherein the abnormality signal is a signal indicating that the power semiconductor switch is in a desaturation state in accordance with a prescribed output signal changing to a prescribed value.

4. The gate drive circuit according to claim 1 or 2, wherein in a case in which a delay time occurs until the power semiconductor switch actually becomes an on operation after outputting a signal that causes the power semiconductor switch that is a drive target to transition from an off state to an on state, includes a first initial charge charging circuit that causes an initial charge to remain in the charging capacitor, and that causes the standby retention time to be a degree in which a charging time that is shorter by the initial charge is generated, the output circuit outputs an abnormality signal indicating that the power semiconductor switch is in a desaturation state after the time measuring circuit measures the standby retention time that is shorter.

5. The gate drive circuit according to claim 1 or 2, wherein in a case in which a delay time occurs until the power semiconductor switch actually becomes an on operation after outputting a signal that causes the power semiconductor switch that is a drive target to transition from an off state to an on state, the charging current bypass circuit includes: ​ a series circuit including a detour switch that detours the charging current and an initial charge resistor directly connected to the detour switch, even in a case where the charging current is detoured by the charging current detour circuit, an initial charge remains in the charging capacitor to an extent of the initial charge resistor, a standby retention time that is short to an extent of a charging time of the initial charge is generated, the output circuit outputs an abnormal signal indicating that the power semiconductor switch is in a desaturated state after the time measurement circuit measures the standby retention time that is short.

6. The gate drive circuit according to claim 1 or 2, characterized by comprises: a diode whose cathode terminal is connected to the comparison circuit and whose anode terminal is connected to the collector terminal of the power semiconductor switch, the comparison circuit detects the collector voltage of the power semiconductor switch via the diode.

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