A micro planar chip inductor test positioning module and its manufacturing method

Abstract

A micro planar chip inductor test and positioning module and its manufacturing method belong to the field of electronic component testing. The test and positioning module includes a substrate, a surface electrode underlayer, a positioning cavity, an end face electrode underlayer, and a plating layer. The surface electrode underlayer is located on the surface of the substrate. The positioning cavity is located in the middle region of the ceramic substrate 1. The shape of the positioning cavity is basically the same as that of the planar chip inductor, with a planar size slightly larger than that of the planar chip inductor and a depth less than the thickness of the ceramic substrate and greater than the thickness of the planar chip inductor. The end face electrode underlayer is located on the two symmetrical end faces of the substrate. The plating layer is a gold plating layer that covers the surface electrode underlayer and the end face electrode underlayer to form the surface and end face electrodes. The manufacturing method is thin film lithography, thick film printing and sintering, vacuum sputtering, or metal electroplating. It solves the problem that the prior art cannot be used to test planar structure chip inductors. It is widely used in the testing of small-size planar chip inductors or the electrical performance testing of other planar two-port electronic devices.

Description

Technical Field

[0001] The present invention belongs to the field of electronic component testing, and more particularly to the field of planar chip inductor testing. Specifically, it relates to a micro planar chip inductor testing and positioning module and a manufacturing method thereof. Background Art

[0002] The planar structure schematic diagram of the planar chip inductor is as shown in Figure 1 Currently, the common method for testing chip inductors is as follows: Select a two-port microstrip line circuit board fixture. The end of the microstrip line is connected to a coaxial adapter, and the adapter of the fixture is connected to the adapter of the vector network analyzer. The matching impedance of the two ends of the microstrip line is 50Ω, which is matched with the network analyzer. It is necessary to perform coaxial calibration on the vector network analyzer and then de-embed the circuit board fixture to eliminate the influence of the circuit board fixture. After calibration, the device under test is bonded to the circuit board test fixture, and then the two pads of the device under test are respectively wire-bonded to the microstrip line (gold plating layer) of the test fixture by using gold wires, and the microstrip line is grounded. Perform S-parameter testing, and then calculate electrical properties such as inductance and Q value according to the formula from the S-parameters. Processes such as gluing, wire-bonding, and calculation seriously affect the test efficiency.

[0003] Another common testing method is as follows: A test system is composed of a probe station, probes, and a vector network analyzer to perform S-parameter testing, and then electrical properties such as inductance and Q value are derived from the S-parameters. This testing method omits destructive testing processes such as wire-bonding and gluing, but the GSG structure RF probes are only applicable to the testing of planar chip inductors with a ground plane. Chip inductors with only two ports, namely the signal input end and the output end, and no ground end cannot adopt this testing method.

[0004] When using an LCR meter and an impedance analyzer for testing, although the inductance, Q value, and other electrical properties of the inductor can be directly read out, the existing test fixtures are only for testing discrete inductors and SMD inductors with leads, and cannot test planar structure chip inductors.

[0005] In view of this, the present invention is specifically proposed. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to solve the problem that the existing LCR meter or impedance analyzer cannot be used to test planar structure chip inductors.

[0007] The present invention provides a micro planar chip inductor testing and positioning module, as shown in Figures 2 - 4 which includes: a substrate 1, a surface electrode underlayer 2, a positioning cavity 3, an end face electrode underlayer 4, and a plating layer 5.

[0008] The substrate 1 is a low dielectric constant insulating substrate. The insulating material can be, but is not limited to, fused silica glass, alumina, aluminum nitride ceramic, and other materials.

[0009] The surface electrode underlayer 2 is located on the surface of the substrate 1. The material of the surface electrode underlayer 2 is TiW-Au, nickel chromium-gold or other composite metal layers. The thickness of the composite metal layer is 200nm - 500nm.

[0010] The positioning cavity 3 is located in the middle area of the ceramic substrate 1. The shape of the positioning cavity 3 is consistent with that of the planar chip inductor, and the planar size is slightly larger than that of the planar chip inductor, facilitating the picking and placing of the planar chip inductor. The depth of the positioning cavity 3 is less than the thickness of the ceramic substrate 1 and greater than the thickness of the planar chip inductor, facilitating the bonding of test leads.

[0011] The end face electrode underlayer 4 is located at the symmetric two end faces (sides) of the substrate 1. The material of the end face electrode underlayer 4 is TiW-Au, nickel chromium-gold or other composite metal layers. The thickness of the composite metal layer is 200nm - 500nm.

[0012] The plating layer 5 is a gold plating layer, which completely covers the surface electrode underlayer 2 and the end face electrode underlayer 4. The thickness of the plating layer 5 is 5μm - 10μm.

[0013] The top surface of the plating layer 5 is connected to the device under test through a bonding wire, and the end face is connected to a high-frequency test fixture through a microstrip. The high-frequency test fixture is then connected to an LCR meter or an impedance analyzer.

[0014] The length and width dimensions of the positioning cavity 3 are 15μm - 30μm larger than the dimensions of the device under test, so that the chip inductor can be placed in the positioning cavity 3.

[0015] The depth of the positioning cavity 3 is 300μm - 600μm greater than the height of the device under test, so that while the length of the gold wire is as short as possible (close to a straight line) during the gold wire bonding process, it prevents the gold wire from contacting the product coil and causing an open circuit.

[0016] The surface electrode underlayer 2 and the surface plating layer 5 constitute the surface electrode, and the width of the surface electrode is 50μm - 100μm.

[0017] The present invention provides a preparation method for the above-mentioned micro planar chip inductor test positioning module, including the following preparation processes:

[0018] (1) Select an insulating substrate made of a double-sided polished low dielectric constant material as the substrate. The insulating material can be, but is not limited to, fused silica glass, alumina, aluminum nitride ceramic and other materials.

[0019] (2) Sputter a surface metal underlayer on the substrate.

[0020] (3) Fabricate a mask plate. The mask plate pattern consists of a cutting line pattern that can cut the substrate into single test positioning modules and a surface electrode pattern of a single test positioning module.

[0021] (4) Lithographically pattern the cutting lines and surface electrodes on the substrate.

[0022] (5) Singulate the wafer into individual test positioning module bodies by dicing.

[0023] (6) Fabricate a positioning cavity in the middle region of the surface of each individual test positioning module body.

[0024] The length, width, and height dimensions of the individual test positioning module body are larger than those of the positioning cavity. The length and width dimensions of the positioning cavity are slightly larger than those of the device under test, so that the chip inductor can be placed within the positioning cavity. The depth of the positioning cavity is slightly larger than the height of the device under test, so that while the length of the bonding wire is as short as possible (close to a straight line) during the wire bonding process, it also prevents the bonding wire from contacting the product coil and causing an open circuit. The positioning cavity causes the gold electrode conductor to be disconnected at the positioning cavity and is divided into front, rear, left, and right symmetric gold electrode conductors.

[0025] (7) Using a patented sputtering fixture that can block non-sputtered areas, place each individual test positioning module body in the sputtering fixture in sequence, and sputter a metal underlayer on two opposite sides of the individual test positioning module body. The two side metal underlayers and the surface metal underlayer are connected and conduct electricity.

[0026] (8) Electroplate gold on the two side metal underlayers and the surface metal underlayer, thus completing the fabrication of the test positioning module.

[0027] The surface gold electrodes of the test positioning module are used for wire bonding with the chip inductor pads, and the two side gold conductors are used to connect to a high-frequency test fixture that matches an LCR meter or impedance analyzer.

[0028] The present invention provides another preparation method for the above-mentioned micro planar chip inductor test positioning module, including the following preparation processes:

[0029] (1) Select an insulating substrate made of a low dielectric constant material as the base substrate. The insulating material can be, but is not limited to, materials such as alumina and aluminum nitride ceramics.

[0030] (2) Score the base substrate according to the planar dimensions of the test positioning module, and divide it into several cells for standby.

[0031] (3) Fabricate a silk screen mask, and the silk screen pattern is the surface electrode pattern of the test positioning module.

[0032] (3) Print the electrode pattern on the base substrate with gold paste. The electrode pattern is a gold electrode line that penetrates the individual test positioning module body from left to right and is symmetric front and back.

[0033] (4) Singulate the wafer along the scoring direction of the base substrate to obtain individual test positioning module bodies.

[0034] (5) Fabricate a positioning cavity at the middle area on the surface of the single - chip test positioning module body.

[0035] The length, width, and height dimensions of the single - chip test positioning module body are larger than those of the positioning cavity. The length and width dimensions of the positioning cavity are slightly larger than the dimensions of the device under test, so that the chip inductor can be placed in the positioning cavity. The depth of the positioning cavity is slightly larger than the height of the device under test, so that while the length of the gold wire is as short as possible (close to a straight line) during the gold wire bonding process, it can prevent the gold wire from contacting the product coil and causing an open circuit. The positioning cavity causes the gold electrode conductor to be disconnected at the positioning cavity and is divided into front, back, left, and right symmetric gold electrode conductors.

[0036] (6) Use a special sputtering fixture that can block non - sputtering areas. Place the single - chip test positioning module body in the sputtering fixture in sequence, and sputter a metal underlayer on two opposite sides of the single - chip test positioning module body. The two - side metal underlayers and the surface metal underlayer are connected and conduct electricity.

[0037] (7) Electroplate gold on the two - side metal underlayers and the surface metal underlayer, and thus complete the fabrication of the test positioning module.

[0038] The surface gold electrodes of the test positioning module are used for gold wire bonding with the chip inductor pads, and the two - side gold conductors are used to connect to a high - frequency test fixture that matches an LCR meter or an impedance analyzer.

[0039] The present invention provides a test method using the above - mentioned micro - planar chip inductor test positioning module, which includes the following steps:

[0040] (1) Select test parameters and a high - frequency test fixture. The high - frequency test fixture includes an Agilent fixture.

[0041] (2) Perform an open - circuit calibration on the LCR meter or the impedance analyzer.

[0042] (3) Bond the two - end gold electrodes on the surface of the test positioning module with gold wires to make them conduct, and connect the high - frequency test fixture of the LCR meter or the impedance analyzer for short - circuit calibration. This method eliminates the test error brought by the test positioning module of the present invention and plays a role of "zeroing".

[0043] (4) After the calibration is completed, remove the test positioning module.

[0044] (5) Place the device under test in the positioning cavity of the test positioning module of the present invention, and bond the two pads of the device under test with the corresponding gold electrodes of the test positioning module with gold wires respectively.

[0045] (6) Place the test positioning module of the present invention in the high - frequency test fixture of the LCR meter or the impedance analyzer, and perform electrical performance tests on the device under test.

[0046] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0047] (1) It can be directly connected to the high-frequency test fixture attached to the LCR meter and impedance analyzer to directly read the electrical performance parameters such as the inductance and Q value of the chip inductor. The operation is simple, without processes such as calculation, improving the test efficiency.

[0048] (2) It does not require an expensive vector network analyzer, saving the test cost.

[0049] (3) When testing small inductance inductors, it maintains a high test accuracy, and the test error < ±10%.

[0050] (4) When testing the chip inductor, first place it in the positioning cavity, and then use gold wire bonding to bond the pads of the chip inductor to the gold layer of the test fixture. It can measure small-size chip inductors with pad sizes < 50μm.

[0051] (5) It can test planar chip inductors with only two ports, namely the signal input terminal and the output terminal, and no ground terminal.

[0052] The test positioning module of the present invention has the characteristics of precise positioning, high repeatability, high consistency, and high reliability, and can perform batch and large-scale tests. It is also applicable to the electrical performance tests of other planar two-port electronic devices. Description of the Drawings

[0053] Figure 1 It is a schematic structural diagram of a planar chip inductor.

[0054] Figure 2 It is a schematic structural diagram of the test positioning module.

[0055] Figure 3 It is a schematic structural diagram of the short-circuit calibration state of the test positioning module.

[0056] Figure 4 It is a schematic structural diagram of the usage state of the test positioning module.

[0057] In the figure, 1 is the substrate, 2 is the surface electrode underlayer, 3 is the positioning cavity, 4 is the end face electrode underlayer, 5 is the plating layer, 6 is the calibration inductor wire, 7 is the device under test, and 8 is the test bonding lead of the device under test. Detailed Embodiments

[0058] As Figures 2 - 4 shown, the detailed embodiments of the technical solution of the present invention are as follows:

[0059] Embodiment 1: The preparation method of the described micro planar chip inductor test positioning module is as follows:

[0060] (1) Select an alumina insulating substrate made of double-sided polished low-dielectric constant material as the substrate.

[0061] (2) Sputter a TiW-Au composite metal layer on the substrate in sequence as the underlayer, and the thickness of the composite metal layer is 200nm - 500nm.

[0062] (3) Fabricate a mask plate (i.e., a photolithography mask), and the mask plate pattern consists of a cutting line pattern that can cut the substrate into single test positioning modules and a surface electrode pattern of a single test positioning module.

[0063] (4) Spin-coat the photoresist (a positive photoresist is selected).

[0064] (5) Expose (the exposure time is 10s - 20s).

[0065] (6) Develop (the development time is 1min - 2min).

[0066] (7) Etch (the etching time is 1min - 2min). Only the cutting lines and the surface electrodes of the fixture are left on the substrate.

[0067] (8) Use a cutting method to cut the substrate according to the cutting line pattern (the cutting speed is 0.6mm / s - 1mm / s) into the main body of a single test positioning module.

[0068] (9) Use a grooving method to fabricate a positioning cavity in the middle area on the surface of the main body of a single test positioning module.

[0069] Cut according to the cutting line so that the length, width, and height of the main body of a single test positioning module are 1mm - 2mm larger than the length, width, and height of the positioning cavity.

[0070] The length and width dimensions of the positioning cavity are 15μm - 30μm larger than the dimensions of the device under test, so that the chip inductor can be placed in the positioning cavity.

[0071] The depth of the positioning cavity is 300μm - 600μm larger than the height of the device under test, so that while the length of the gold wire is as short as possible (close to a straight line) during the gold wire bonding process, it can prevent the gold wire from contacting the coil of the device under test and causing an open circuit.

[0072] The positioning cavity disconnects the gold electrode conductor at the positioning cavity and divides it into front, back, left, and right symmetric gold electrode conductors with a width of 50μm - 100μm.

[0073] (10) Fabricate a special sputtering fixture that can block non-sputtering areas, and place the main body of a single test positioning module in the sputtering fixture in sequence. The sputtering area is two side partial areas of the main body of a single fixture, and its position is where it can be connected and conduct with the metal lines on the surface of the main body of a single test positioning module. The rest is the part that blocks sputtering.

[0074] (11) Sputter a TiW-Au composite metal layer on the left and right sides of the single test positioning module body in sequence as the underlayer. The thickness of the composite metal layer is 200 nm - 500 nm, the height is the same as that of the single test positioning module body, and the width is the same as the width of the surface electrode lines of the single test positioning module body.

[0075] (12) By means of gold plating on the gold conductor electrodes, the gold conductors on the left and right sides are respectively connected and conducted with the gold electrodes on the surface of the single test positioning module body, and the thickness of the surface gold conductor and the electrodes on the left and right sides is increased by 5 μm - 10 μm, thus completing the production of the single test positioning module of the present invention.

[0076] The gold electrodes on the surface of the single test positioning module body of the present invention are used for wire bonding with the chip inductor pads, and the gold conductors on the two sides are used to connect to the high-frequency test fixtures matching with the LCR meter or impedance analyzer.

[0077] Embodiment 2: Another preparation method of the described micro planar chip inductor test positioning module is as follows:

[0078] (1) Select an aluminum nitride insulating substrate with a low dielectric constant as the substrate.

[0079] (2) Mark lines on the substrate according to the planar size of the test positioning module, and divide it into several cells for standby.

[0080] (3) Make a silk screen stencil, and the silk screen pattern is the surface electrode pattern of the test positioning module.

[0081] (3) Print the electrode pattern on the substrate with gold paste. The electrode pattern is a gold electrode line that penetrates through the left and right of the single test positioning module body and is symmetrical front and back. After sintering, its width is 50 μm - 100 μm, the thickness is about 5 μm, and the length is the length of the single test positioning module body.

[0082] (4) Perform die cutting along the marking direction of the substrate to split it into single test positioning module bodies.

[0083] (5) Make a positioning cavity at the middle area position on the surface of the single test positioning module body.

[0084] Die cutting makes the length, width, and height dimensions of the single test positioning module body 1 mm - 2 mm larger than those of the positioning cavity. The length and width dimensions of the positioning cavity are slightly larger than the dimensions of the component to be measured by 15 μm - 30 μm, so that the chip inductor can be placed in the positioning cavity. The depth of the positioning cavity is slightly larger than the height of the component to be measured by about 300 μm - 600 μm, so that while the wire length is as short as possible (close to a straight line) during the wire bonding process, it can prevent the wire from contacting the product coil and causing an open circuit. The positioning cavity makes the gold electrode conductor disconnected at the positioning cavity and divided into front, back, left, and right symmetrical gold electrode conductors.

[0085] (6) Adopt a patented sputtering fixture that can block non-sputtering areas, and place the single-test positioning module body in the sputtering fixture in sequence. Sputter the TiW-Au composite metal layer as the underlayer on the two opposite sides of the single-test positioning module body in sequence, with a thickness of 200 nm - 500 nm, a height equal to that of the single-test positioning module body, and a width the same as the surface electrode line width of the single-test positioning module body. The metal underlayers on the two sides are connected and conduct electricity with the surface metal underlayer.

[0086] (7) By plating gold on the gold conductor electrodes, connect the gold conductors on the left and right sides to the gold electrodes on the surface of the single-test positioning module body respectively and make them conduct electricity, and increase the thickness of the electrodes on the left and right sides by 5 μm - 10 μm, thus completing the production of the single-test positioning module.

[0087] The gold electrodes on the surface of the test positioning module of the present invention are used for wire bonding with the chip inductor pads, and the gold conductors on the two sides are used to connect to the high-frequency test fixtures matching the LCR meter or impedance analyzer.

[0088] Example 3: A test method using the non-destructive planar chip inductor test assembly is as follows:

[0089] (1) Select Agilent fixtures of models such as 16192A (DC - 2 GHz), 16194A (DC - 2 GHz), 16197A (DC - 3 GHz), 16092A (DC - 500 MHz) as the high-frequency test fixtures.

[0090] (2) Perform open-circuit calibration on the LCR meter or impedance analyzer.

[0091] (3) Wire bond the two end gold electrodes on the surface of the test positioning module to make them conduct electricity, and connect the end electrodes to the high-frequency test fixture of the LCR meter or impedance analyzer for short-circuit calibration. This method eliminates the test errors brought by the test positioning module of the present invention and plays a role of "zero clearing".

[0092] (4) After calibration, remove the test positioning module used for calibration.

[0093] (5) Place the device under test in the positioning cavity of the test positioning module of the present invention, and wire bond the two pads of the device under test to the corresponding gold electrodes of the test positioning module respectively.

[0094] (6) Place the test positioning module of the present invention in the high-frequency test fixture of the LCR meter or impedance analyzer to perform electrical performance tests on the device under test. It is found during the test process that the test errors such as inductance and Q value caused by the difference in the length of the bonding wires during wire bonding during calibration and testing can be ignored.

[0095] The small-sensing inductance in the test can maintain a high test accuracy. For the chip inductance with a nominal value of 150 nH @ 250 MHz and a nominal Q value of 18 @ 250 MHz, 5 samples are randomly selected for measurement, and the inductance error is < ±1%. The measured Q value is 18 - 20, slightly larger than the nominal value (the larger the Q value, the smaller the loss. Generally, the nominal Q value is the minimum Q value of the inductance, and the measured Q value of general samples is larger than the nominal value); for the chip inductance with nominal values of 2 nH @ 250 MHz and 5 nH @ 250 MHz, 5 samples are randomly selected for measurement, and the inductance error is < ±10%.

[0096] Since the chip inductance is first placed in the positioning cavity of the test positioning module during the test, and then wire bonded to the gold layer of the test fixture using gold wires, small-sized chip inductors with pad sizes < 50 μm can be measured.

[0097] When the test positioning module of the present invention is not placed with a product, it is connected to the high-frequency test fixture of the LCR meter or impedance analyzer for short-circuit calibration, which can greatly reduce the error brought by the test fixture. While improving the test accuracy, the chip inductance can also be tested for electrical performance such as inductance and Q value in the frequency ranges of DC - 500 MHz, DC - 2 GHz, and DC - 3 GHz. The sweep function of the impedance analyzer can also read the resonance frequency points of the chip inductance within the test frequency range of the fixture.

[0098] In summary, 5 samples of chip inductors with nominal values of 2 nH, 5 nH, 20 nH, 30 nH, and 150 nH are randomly selected respectively. Using the fixture of the present invention, the inductance and Q value are tested at frequencies of 10 MHz, 30 MHz, 100 MHz, 250 MHz, and 1 GHz. The test accuracy of the inductance is high at different frequencies, and the error between the measured inductance value of the chip inductance and the simulation value or nominal value is < ±10% at different frequencies.

[0099] Finally, it should be noted that the above embodiments are merely examples clearly described. The present invention includes but is not limited to the above embodiments, and it is not necessary and impossible to enumerate all implementation manners here. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. All implementation manners that meet the requirements of the present invention fall within the protection scope of the present invention.

Claims

1. A micro planar chip inductor test and positioning module, characterized in that, it includes: a substrate, a surface electrode underlayer, a positioning cavity, an end face electrode underlayer, and a plating layer; The surface electrode underlayer is located on the surface of the substrate; The positioning cavity is located in the central region of the substrate. The shape of the positioning cavity is basically the same as that of the planar chip inductor, the planar size is slightly larger than that of the planar chip inductor, the depth is less than the thickness of the substrate, and greater than the thickness of the planar chip inductor; The end face electrode underlayer is located on the two symmetric end faces of the substrate; The plating layer is a gold plating layer, which completely covers the surface electrode underlayer and the end face electrode underlayer to form two surface electrodes and two end face electrodes; The surface electrode underlayer and the surface plating layer constitute the surface electrode; The surface electrode is connected to the chip inductor pad through a bonding wire, and the end face electrode is connected to a high-frequency test fixture matched with an LCR meter or an impedance analyzer through a microstrip; The substrate is a low dielectric constant insulating substrate.

2. A micro planar chip inductor test and positioning module according to claim 1, characterized in that, the insulating substrate is made of quartz glass, alumina ceramic or aluminum nitride ceramic.

3. A micro planar chip inductor test and positioning module according to claim 1, characterized in that, the surface electrode underlayer is a TiW-Au or NiCr-Au composite metal layer, and the thickness of the composite metal layer is 200nm - 500nm.

4. A micro planar chip inductor test and positioning module according to claim 1, characterized in that, the length, width and height dimensions of the positioning cavity are 1mm - 2mm smaller than the length, width and height dimensions of the test and positioning module body; the length and width dimensions of the positioning cavity are 15μm - 30μm larger than the dimensions of the device under test, and the depth is 300μm - 600μm larger than the height of the device under test; the positioning cavity disconnects the surface electrode at the positioning cavity and divides it into front, rear, left and right symmetric electrode conductors.

5. A micro planar chip inductor test and positioning module according to claim 1, characterized in that, the width of the surface electrode is 50μm - 100μm.

6. A micro planar chip inductor test and positioning module according to claim 1, characterized in that, the thickness of the plating layer is 5μm - 10μm.

7. A manufacturing method of a micro planar chip inductor test and positioning module according to claim 1, characterized in that, it includes the following preparation processes: (1) Select a double-sided polished insulating substrate made of low dielectric constant material such as fused quartz glass, alumina or aluminum nitride ceramic as the substrate; (2) Sputter a composite metal layer on the surface of the substrate as the underlayer; (3) Make a mask plate, and the mask plate pattern consists of a cutting line pattern for cutting the substrate into single test and positioning modules and a surface electrode pattern of single test and positioning modules; (4) Photolithograph the underlayer on the surface of the substrate to form cutting lines and the surface electrode underlayer; (5) Dicing and cutting into single test and positioning module bodies; (6) Make a positioning cavity in the central region of the surface of the single test and positioning module body; (7) Use a special sputtering fixture that can block non-sputtering areas. Place the single test positioning module body in the sputtering fixture in sequence, and sputter the composite metal layer primer on two opposite sides of the single test positioning module body. The two side composite metal layer primers and the surface composite metal layer primer are connected and conduct electricity; (8) Gold-plate the two side composite metal layer primers and the surface composite metal layer primer to complete the production of the test positioning module.

8. A manufacturing method of a micro planar chip inductor test positioning module as described in claim 1, characterized in that, it includes the following preparation processes: (1) Select an alumina or aluminum nitride ceramic insulating substrate with double-sided polished low dielectric constant material as the substrate; (2) Mark lines on the substrate according to the planar size of the test positioning module, dividing it into several cells; (3) Manufacture a silk screen stencil, and the silk screen pattern is the surface electrode pattern of the test positioning module; (3) Print the electrode pattern on the substrate with gold paste. The electrode pattern is a gold electrode line that penetrates through the left and right of the single test positioning module body and is symmetrical front and back; (4) Debind and sinter the gold paste to form a surface gold thick film layer; (5) Perform chipping along the substrate marking direction respectively to break it into single test positioning module bodies; (6) Manufacture a positioning cavity at the middle area position on the surface of the single test positioning module body; (7) Use a special sputtering fixture that can block non-sputtering areas. Place the single test positioning module body in the sputtering fixture in sequence, and sputter the composite metal layer primer on two opposite sides of the single test positioning module body. The two side composite metal layer primers and the surface gold paste printed layer are connected and conduct electricity; (8) Gold-plate the two side metal primers and the surface gold thick film layer to complete the production of the test positioning module.

9. A test method using the test positioning module as described in claim 1, characterized in that, it includes the following steps: (1) Select test parameters and a high-frequency test fixture including an Agilent fixture; (2) Perform open circuit calibration on the LCR meter or impedance analyzer; (3) Bond the end electrodes of the surface of the test positioning module with gold-plated electroplated layers at both ends with gold wires to make them conduct electricity, and connect the high-frequency test fixture of the LCR meter or impedance analyzer to perform short circuit calibration; (4) After calibration is completed, remove the test positioning module used for calibration; (5) Place the device under test in the positioning cavity of the test positioning module, and bond the two pads of the device under test with the corresponding gold electrodes of the test positioning module with gold wires respectively; (6) Connect the test positioning module with the high-frequency test fixture of the LCR meter or impedance analyzer to perform electrical performance testing on the device under test.

10. A test method using the test positioning module as described in claim 1 as described in claim 9, characterized in that, for the chip inductor, perform inductance or Q value testing respectively in the frequency ranges of DC - 500 MHz, DC - 2 GHz or DC - 3 GHz, and use the sweep frequency function of the impedance analyzer to read the resonance frequency points of the chip inductor within the test frequency range of the test component.

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