A parallel redundant system and method based on CAN bus level interface

Abstract

The present invention relates to the technical field of CAN bus transmission, and discloses a parallel redundancy system based on a CAN bus level interface, including a first endpoint and a second endpoint with a message redundancy backup function, the first endpoint and the second endpoint can both be used as a receiving end or a sending end, a plurality of buses are arranged in parallel between the first endpoint and the second endpoint, and the first endpoint and the second endpoint are arranged at the far end of the bus, and also includes a plurality of intermediate endpoints with message redundancy backup function, the plurality of intermediate endpoints can both be used as a receiving end or a sending end, each of the intermediate endpoints is connected to N buses, and is used to receive data from the N buses or send data to the N buses. The present invention also discloses a parallel redundancy method based on a CAN bus level interface. The present invention arranges a plurality of intermediate nodes in parallel on the bus, and each intermediate node is a device, thereby realizing parallel connection of devices.

Description

Technical Field

[0001] The present invention relates to the technical field of CAN bus transmission, and in particular to a parallel redundancy system and method based on a CAN bus level interface. Background Art

[0002] With the advancement of industrial technology, in order to further improve the reliability of industrial Ethernet, message redundancy backup technology has emerged. At the sending end, each message to be sent is copied to obtain two identical messages, and the two messages are sent through different ports.

[0003] However, the current parallel redundancy methods are all point-to-point transmission and reception, which cannot achieve parallel connection of devices. At the same time, there is no retransmission mechanism for data in the redundant system. Summary of the invention

[0004] The invention provides a parallel redundancy system and method based on a CAN bus level interface to realize parallel connection of equipment.

[0005] The present invention is achieved through the following technical solutions:

[0006] A parallel redundant system based on a CAN bus level interface includes a first endpoint and a second endpoint with a message redundancy backup function, the first endpoint and the second endpoint can both be used as a receiving end or a sending end, a plurality of buses are arranged in parallel between the first endpoint and the second endpoint, and the first endpoint and the second endpoint are arranged at the far end of the buses, and also includes a plurality of intermediate endpoints with a message redundancy backup function, the plurality of intermediate endpoints can both be used as a receiving end or a sending end, each of the intermediate endpoints is connected to N buses, and is used to receive data from the N buses or send data to the N buses, wherein N is a positive integer not less than 2.

[0007] In this technical solution, multiple intermediate nodes are set in parallel on the bus, each intermediate node is a device, thereby realizing parallel connection of devices, and each intermediate node has a message redundancy backup function, so that data transmission of the intermediate node can be realized reliably.

[0008] As an optimization, each of the N buses is composed of two cables, and the signals transmitted on the two cables are 2-wire differential signals.

[0009] As an optimization, the first endpoint, the second endpoint and the intermediate endpoint all include an FPGA and N CAN transceivers, the number of the CAN transceivers corresponds one-to-one to the number of the buses, the FPGA is provided with multiple redundant IP cores, the FPGA transmits data to the N buses respectively through several of the CAN transceivers, or the FPGA receives data from the N buses through the N CAN transceivers.

[0010] As an optimization, matching resistors are also provided on the buses of the CAN transceivers close to the first endpoint and the second endpoint, and both ends of the matching resistors are respectively connected to the two cables belonging to the same bus.

[0011] As an optimization, the number of the intermediate endpoints is no greater than 255.

[0012] The present invention also discloses a parallel redundancy method based on a CAN bus level interface, using the above-mentioned parallel redundancy system, comprising the following steps:

[0013] Step 1: The sending end receives data from the host computer and copies the data into N copies, and the N copies of the data are sent to N buses respectively;

[0014] Step 2: The non-sending endpoint receives data from N buses, and selects the data that first arrives at the non-sending endpoint as received data to be saved and parsed.

[0015] As an optimization, the first endpoint, the second endpoint and the intermediate endpoint all include an FPGA and N CAN transceivers, the FPGA is provided with multiple redundant IP cores, the FPGA transmits data to N buses respectively through several of the CAN transceivers, or the FPGA receives data from N buses through N CAN transceivers.

[0016] As an optimization, the specific implementation steps of step 1 are as follows:

[0017] Step 1.1, the host computer sends the data to the sending buffer of the sending end;

[0018] Step 1.2, the IP core of the transmitting end copies the data stored in the transmitting buffer into N copies, and at the same time, configures a sequential frame and a redundant frame on each copy of the data;

[0019] Step 1.3: Send the data configured in step 1.2 to N buses simultaneously through the N CAN transceivers.

[0020] As an optimization, the specific implementation steps of step 2 are as follows:

[0021] Step 2.1, the non-sending endpoint receives data from N buses and selects the first arriving data;

[0022] Step 2.2, after receiving the data, the non-sending endpoint stores the data in a receiving buffer, and then sends a response frame to the sending end through the N buses respectively;

[0023] Step 2.3, the IP core of the non-sending endpoint removes the redundant frames of the data that arrives first, and parses the IDs of the sequential frames;

[0024] Step 2.4: If the IP core of the sending end does not receive the response frame sent by the endpoint of the non-sending end, the sending end continues to send data repeatedly through N buses for several times. If the response frame is still not received, the IP core of the sending end sends a timeout information notification of the endpoint of the non-sending end that has not replied to the response frame to the host computer.

[0025] As an optimization, in step 2.1, when the non-sending endpoint receives data from N buses, the IP core of the non-sending endpoint compares all data from the N buses. If the data from the N buses is incorrect, an error frame is sent to the sending end, and the IP core of the sending end sends an error information notification to the host computer.

[0026] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0027] 1. The present invention sets a retransmission mechanism in a redundant system. When the IP core of the sending end does not receive a response frame sent by the endpoint of the non-sending end, the sending end continues to repeatedly send data through N buses for several times. If the response frame is still not received, the IP core of the sending end sends a timeout information notification of the endpoint of the non-sending end that has not replied to the response frame to the host computer, so that the host computer can know which endpoint is faulty in time.

[0028] 2. The present invention sets multiple intermediate nodes in parallel on the bus, each intermediate node is a device, thereby realizing parallel connection of devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without creative work. In the drawings:

[0030] Figure 1 The present invention is a schematic diagram of the system structure of a parallel redundant system based on a CAN bus level interface. DETAILED DESCRIPTION

[0031] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with embodiments and drawings. The exemplary embodiments of the present invention and their description are only used to explain the present invention and are not intended to limit the present invention.

[0032] Example 1

[0033] A parallel redundant system based on a CAN bus level interface includes a first endpoint and a second endpoint with a message redundancy backup function, the first endpoint and the second endpoint can both be used as a receiving end or a sending end, a plurality of buses are arranged in parallel between the first endpoint and the second endpoint, and the first endpoint and the second endpoint are arranged at the far end of the buses, and also includes a plurality of intermediate endpoints with a message redundancy backup function, the plurality of intermediate endpoints can both be used as a receiving end or a sending end, each of the intermediate endpoints is connected to N buses, and is used to receive data from the N buses or send data to the N buses, wherein N is a positive integer not less than 2.

[0034] In this embodiment, the first endpoint, the second endpoint and the intermediate endpoint all include an FPGA and N CAN transceivers, the number of the CAN transceivers corresponds to the number of the buses, and the FPGA is provided with multiple redundant IP cores. The FPGA transmits data to the N buses respectively through several of the CAN transceivers, or the FPGA receives data from the N buses through the N CAN transceivers. The buses of the CAN transceivers close to the first endpoint and the second endpoint are also provided with matching resistors, and the two ends of the matching resistors are respectively connected to the two cables belonging to the same bus. Adding matching resistors to the first endpoint and the second endpoint is determined by the driving characteristics of the CAN bus. This is a prior art and will not be described in detail.

[0035] like Figure 1As shown, N is 2, that is, there are dual redundant IP cores in the FPGA. The first endpoint is defined as endpoint A, and the second endpoint is defined as endpoint B. The parallel redundant system consists of endpoint A (FPGA (A00), CAN transceiver (A01), CAN transceiver (A02), matching resistor RA1, matching resistor RA2), endpoint B (FPGA (B00), CAN transceiver (B01), CAN transceiver (B02), matching resistor RB1, matching resistor RB2), endpoint N ((FPGA (N00), CAN transceiver (N1), CAN transceiver (N2)), bus A, bus B, where the FPGA end and CAN transceiver can be the same or different. Matching resistors RA1 and RB1 need to be hung on bus A (this Only the electrical characteristics of the CAN transceiver are used, that is, only the level of the CAN bus is used to make the redundant system of the present invention), RA2 and RB2 need to be hung on bus B, and all components used are domestic components. There can be a maximum of 255 intermediate endpoints, and the intermediate endpoints are not connected to matching resistors. Node A and node B need to be connected to the far end of the bus. Bus A is consistent with bus B, and the transmitted signals are all 2-wire differential signals. Here, the intermediate endpoint is set to 255, which is determined by the number of IDs of the CAN bus, and there can be a maximum of 255. Of course, the number of intermediate endpoints can be any number, by customizing the number of IDs to any number.

[0036] Differential transmission is a signal transmission technology. Different from the traditional method of one signal line and one ground line, differential transmission transmits signals on both lines. The two signals have the same amplitude and opposite phase. The signal transmitted on these two lines is a differential signal. The signal receiving end compares the difference between the two voltages to determine the logical state sent by the sending end.

[0037] Using differential signaling has the following benefits:

[0038] The first benefit is that because you are controlling the 'reference' voltage, small signals can be easily identified. In a ground referenced, single ended signal scheme, the exact value of the measured signal depends on the consistency of the 'ground' within the system. The farther the signal source and signal receiver are apart, the greater the chance that there will be a difference in the voltage values ​​of their local grounds. The signal value recovered from the differential signal is largely independent of the exact value of the 'ground', but within a certain range.

[0039] The second benefit is that it is highly immune to external electromagnetic interference (EMI Electromagnetic Interference). An interference source affects each end of the differential signal pair almost equally. Since the voltage difference determines the signal value, any identical interference that appears on the two conductors will be ignored. In addition to being less sensitive to interference, differential signals generate less EMI than single-ended signals.

[0040] The third benefit is that in a single-supply system, "bipolar" signals can be handled with ease and accuracy. In order to handle bipolar signals in a single-ended, single-supply system, we must establish a virtual ground at an arbitrary voltage between the ground and the power rail (usually the midpoint). Positive signals are represented by voltages above the virtual ground, and negative signals are represented by voltages below the virtual ground. Next, the virtual ground must be correctly distributed throughout the system. For differential signals, such a virtual ground is not required, which allows us to process and transmit bipolar signals with high fidelity without relying on the stability of the virtual ground.

[0041] A dual-redundant IP core is built inside the FPGA. The IP core complies with a custom parallel redundancy protocol, so that endpoint A, endpoint B, or endpoint N can achieve redundancy at the endpoint.

[0042] Take two copies of redundant data as an example: the processor prepares the data to be sent and sends it to the FPGA buffer. The FPGA adds the sequence frame and redundant frame to the end of the original data (the current sequence frame is 0 to 65535 (so many are used temporarily), and the redundant frame is defined as 0010 for the first channel and 0011 for the second channel (this definition has data jumps to avoid errors)). The whole process of adding data frames is the process of implementing the redundant information flow protocol. All device decoding and group coding at the endpoint follow this custom parallel redundant protocol.

[0043] Example 2

[0044] The present invention also discloses a parallel redundancy method based on a CAN bus level interface, using the parallel redundancy system of embodiment 1, comprising the following steps:

[0045] Step 1: The sending end receives data from the host computer and copies the data into N copies, and the N copies of the data are sent to N buses respectively.

[0046] The specific implementation steps are as follows:

[0047] Step 1.1, the host computer sends the data to the sending buffer of the sending end;

[0048] Step 1.2, the IP core of the sending end copies the data stored in the sending buffer into N copies, and at the same time, configures a sequential frame and a redundant frame on each copy of the data; the sequential frame is used to record the order of the data, and the sequential frame and the redundant frame are both at the very end of the data.

[0049] Step 1.3: Send the data configured in step 1.2 to N buses simultaneously through the N CAN transceivers.

[0050] Step 2: The non-sending endpoint receives data from N buses, and selects the data that first arrives at the non-sending endpoint as received data to be saved and parsed.

[0051] The specific implementation steps are as follows:

[0052] Step 2.1, the non-sending endpoint receives data from N buses and selects the first arriving data;

[0053] Step 2.2, after receiving the data, the non-sending endpoint stores the data in a receiving buffer, and then sends a response frame to the sending end through the N buses respectively;

[0054] Step 2.3, the IP core of the non-sending endpoint removes the redundant frames of the data that arrives first, and parses the IDs of the sequential frames;

[0055] Step 2.4: If the IP core of the sending end does not receive the response frame sent by the endpoint of the non-sending end, the sending end continues to send data repeatedly through N buses for several times. If the response frame is still not received, the IP core of the sending end sends a timeout information notification of the endpoint of the non-sending end that has not replied to the response frame to the host computer.

[0056] Take endpoint B as the sending end as an example.

[0057] The host computer sends the intended data to the send buffer of endpoint B. The IP core of endpoint B reads the data in the send buffer and copies the data into two copies. It then adds a sequential frame and a redundant frame and sends them to bus A and bus B respectively.

[0058] Endpoint A or endpoint N receives data on buses A and B, removes redundant frames in IP, assumes that data on bus A arrives first, discards data on bus B, selects data on bus A, parses frame ID, and replies to response frames on the bus when the destination is data to this endpoint (redundant A and B buses send at the same time). Because there are many endpoints on the bus, each endpoint parses bus data at all times, compares data, and sees if the destination is its own. If so, it responds.

[0059] In this embodiment, in step 2.1, when the endpoint of the non-sending end receives data from N buses, the IP core of the endpoint of the non-sending end compares all the data from the N buses. If the data from the N buses is incorrect (the data of the N buses are different), an error frame is sent to the sending end, and the IP core of the sending end sends an error information notification to the host computer.

[0060] By setting up a data verification mechanism in the IP core, after sending a redundant frame (because the redundant frame is at the end of the data, therefore, after sending the redundant frame, it means that the data of the frame has been sent), the other endpoint can compare the data received by bus A and bus B. If the data is wrong, a data error frame will be fed back (the data error frame can be configured). At present, the configuration method of the data error frame is to feed back an error code according to the errors of different sequence frames. The error code will add the sequence frame number. After the sender receives the error frame, it will resend the data of the corresponding sequence frame according to the sequence frame in the received error frame.

[0061] During the transmission of IP core data, when bus A or bus B fails, data transmission is not interrupted and has endpoint continuation capability, achieving zero data loss.

[0062] Each endpoint can be used as a master device to send and receive data. The high and low level status of the bus determines whether the endpoint can send data. The sending buffer and the receiving buffer are in different intervals. This is equivalent to an arbitration mechanism. Only when the bus is not occupied can the response be processed. The bus occupancy time and whether the bus has high and low jumps are regularly detected. If there is a problem with one of the buses, it will be sent from the other bus. If there are problems with both buses, a fault will be reported.

[0063] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A parallel redundancy method based on a CAN bus level interface, using a parallel redundancy system based on a CAN bus level interface, characterized in that: The parallel redundant system comprises a first endpoint and a second endpoint with a message redundancy backup function, the first endpoint and the second endpoint can both be used as a receiving end or a sending end, a plurality of buses are arranged in parallel between the first endpoint and the second endpoint, and the first endpoint and the second endpoint are arranged at the far end of the buses, and is characterized in that it also comprises a plurality of intermediate endpoints with a message redundancy backup function, the plurality of intermediate endpoints can both be used as a receiving end or a sending end, each of the intermediate endpoints is connected to N buses, and is used to receive data from the N buses or send data to the N buses, wherein N is a positive integer not less than 2; The parallel redundancy method comprises the following steps: Step 1: The sending end receives data from the host computer and copies the data into N copies, and the N copies of the data are sent to N buses respectively; Step 2: The non-sending endpoint receives data from N buses, and selects the data that first arrives at the non-sending endpoint as received data to be saved and parsed; The specific implementation steps of step 2 are as follows: Step 2.1, the non-sending endpoint receives data from N buses and selects the first arriving data; Step 2.2, after receiving the data, the non-sending endpoint stores the data in a receiving buffer, and then sends a response frame to the sending end through the N buses respectively; Step 2.3, the IP core of the non-sending endpoint removes the redundant frames of the data that arrives first, and parses the IDs of the sequential frames; Step 2.4, if the IP core of the transmitting end does not receive the response frame sent by the endpoint of the non-transmitting end, the transmitting end continues to repeatedly send data through N buses for several times. If the response frame is still not received, the IP core of the transmitting end sends a timeout information notification of the endpoint of the non-transmitting end that has not replied to the response frame to the host computer; In step 2.1, when the non-sending endpoint receives data from N buses, the IP core of the non-sending endpoint compares all the data from the N buses. If the data from the N buses is incorrect, an error frame is sent to the sending end, and the IP core of the sending end sends an error information notification to the host computer.

2. A parallel redundancy method based on CAN bus level interface according to claim 1, characterized in that: Each of the N buses is composed of two cables, and the signals transmitted on the two cables are 2-wire differential signals.

3. A parallel redundancy method based on CAN bus level interface according to claim 2, characterized in that: The first endpoint, the second endpoint and the intermediate endpoint all include an FPGA and N CAN transceivers, the number of the CAN transceivers corresponds one-to-one to the number of the buses, the FPGA is provided with multiple redundant IP cores, the FPGA transmits data to the N buses respectively through several of the CAN transceivers, or the FPGA receives data from the N buses through the N CAN transceivers.

4. A parallel redundancy method based on CAN bus level interface according to claim 3, characterized in that: Matching resistors are also provided on the buses of the CAN transceivers close to the first endpoint and the second endpoint, and both ends of the matching resistors are respectively connected to the two cables belonging to the same bus.

5. A parallel redundancy method based on CAN bus level interface according to claim 1, characterized in that: The number of the intermediate endpoints is no greater than 255.

6. A parallel redundancy method based on CAN bus level interface according to claim 1, characterized in that: The first endpoint, the second endpoint and the intermediate endpoint all include an FPGA and N CAN transceivers. The FPGA is provided with multiple redundant IP cores. The FPGA transmits data to N buses respectively through several of the CAN transceivers, or the FPGA receives data from N buses through N CAN transceivers.

7. A parallel redundancy method based on CAN bus level interface according to claim 6, characterized in that: The specific implementation steps of step 1 are as follows: Step 1.1, the host computer sends the data to the sending buffer of the sending end; Step 1.2, the IP core of the transmitting end copies the data stored in the transmitting buffer into N copies, and at the same time, configures a sequential frame and a redundant frame on each copy of the data; Step 1.3: Send the data configured in step 1.2 to N buses simultaneously through the N CAN transceivers.

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