Data recovery apparatus, method and wearable device

Abstract

The embodiment of the present application provides a data recovery device, method and wearable device, wherein the data recovery device comprises: a nonvolatile memory, address lines of the nonvolatile memory are respectively connected with corresponding address lines of a random access memory, and data lines of the nonvolatile memory are respectively connected with corresponding data lines of the random access memory; a watchdog circuit is used for detecting whether a system is normal, when the watchdog circuit detects that the system is abnormal, a backup control signal is sent to make data of selected storage units of the random access memory be written into selected storage units of the nonvolatile memory through the data lines until data of all storage units of the random access memory are written into the nonvolatile memory.

Description

Technical Field

[0001] This invention relates to the field of wearable device technology, and more specifically to a data recovery device, method, and wearable device. Background Technology

[0002] Wearable devices such as smart bracelets and smartwatches have gradually become commonplace in people's daily lives. Taking smart bracelets as an example, the data generated by a smart bracelet during operation, such as step count and heart rate, is temporarily stored in random access memory (RAM). However, during daily use, smart bracelets can be damaged by static electricity from the human body or have their own programs malfunction, leading to abnormal program crashes, memory overflows, and other faults, causing the smart bracelet to freeze. In this case, the watchdog circuit in the CPU or the user can reset and restart the hardware system by pressing a button. In this situation, the data stored in RAM, such as step count and heart rate, will be lost, and the data cannot be recovered after the hardware system restarts, resulting in a very poor user experience.

[0003] One existing method to prevent data loss is to periodically back up data temporarily stored in RAM to non-volatile memory such as FLASH memory (also known as flash memory). This allows the system to retrieve this data from the FLASH memory and restore it to the intended program when the wearable device restarts due to a malfunction. However, this approach has drawbacks. FLASH memory has a limited write / erase lifespan. Setting the backup cycle too short significantly increases the frequency of writing and erasing, which shortens the device's lifespan since FLASH memory is typically soldered onto the wearable device's motherboard. Conversely, setting the backup cycle too long leads to a larger discrepancy between the restored data and the actual data. Furthermore, regardless of the backup cycle length, there is always a time interval between the last backup and a device restart, which can still result in data loss. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a data recovery apparatus, method, and wearable device to solve the problem of data loss caused by abnormal system restarts in wearable devices in the prior art.

[0005] According to a first aspect, embodiments of the present invention provide a data recovery apparatus, comprising: a non-volatile memory, wherein the address lines of the non-volatile memory are respectively connected to the address lines of a random access memory, and the data lines of the non-volatile memory are respectively connected to the data lines of the random access memory; and a watchdog circuit for detecting whether the system is normal, wherein when the watchdog circuit detects a system abnormality, it issues a backup control signal to put the corresponding address lines of the non-volatile memory and the random access memory into a strobe state, so as to select the corresponding memory cells of the non-volatile memory and the random access memory, and to write the data of the selected memory cell of the random access memory to the selected memory cell of the non-volatile memory through the data lines, until the data of all memory cells of the random access memory is written to the non-volatile memory.

[0006] Optionally, the backup control signal is a counting signal used by the watchdog circuit to reset the counter and start counting again after detecting a system fault.

[0007] Optionally, the non-volatile memory and the random access memory have the same number of storage units, each having m*n storage units, where m is the number of rows of storage units and n is the number of columns of storage units.

[0008] Optionally, both the non-volatile memory and the random access memory include m data lines, each of the m data lines of the non-volatile memory and the random access memory is connected to the data terminal of each memory cell in its respective row, and the data lines of the non-volatile memory and the random access memory are correspondingly connected; both the non-volatile memory and the random access memory include n column address lines, and the column address lines of the non-volatile memory are correspondingly connected to the column address lines of the random access memory.

[0009] Optionally, when the watchdog circuit issues the counting signal, the row address lines of both the non-volatile memory and the random access memory are enabled, and the column address lines of both the non-volatile memory and the random access memory corresponding to the counting signal are enabled, so that the data of the selected column of memory cells in the random access memory is written to the selected column of memory cells in the non-volatile memory through the data lines, until the data of all memory cells in the random access memory is written to the non-volatile memory.

[0010] Optionally, both the non-volatile memory and the random access memory include n data lines, each of the n data lines of the non-volatile memory and the random access memory is connected to the data terminal of each memory cell in its respective column, and the data lines of the non-volatile memory and the random access memory are correspondingly connected; both the non-volatile memory and the random access memory include m row address lines, and the row address lines of the non-volatile memory are correspondingly connected to the row address lines of the random access memory.

[0011] Optionally, when the watchdog circuit issues the counting signal, the column address lines of both the non-volatile memory and the random access memory are enabled, and the row address lines of both the non-volatile memory and the random access memory corresponding to the counting signal are enabled, so that the data of the enabled row of the random access memory is written to the enabled row of the non-volatile memory through the data lines, until the data of all the random access memory cells are written to the non-volatile memory.

[0012] Optionally, the watchdog circuit is further configured to send a restart signal to the processor after all the data in all the memory cells of the random access memory has been written to the non-volatile memory, so as to cause the system to restart and reset.

[0013] Optionally, the watchdog circuit is further configured to, after the system completes a restart, issue a recovery control signal to enable the corresponding address lines of the non-volatile memory and the random access memory to be in a strobe state, so as to enable the corresponding memory cells of the non-volatile memory and the random access memory, and enable the data of the selected memory cells of the non-volatile memory to be written to the selected memory cells of the random access memory through the data lines, until the data of all memory cells of the non-volatile memory is written to the random access memory.

[0014] Optionally, the recovery control signal is the counting signal of the watchdog circuit.

[0015] According to a second aspect, embodiments of the present invention provide a wearable device including the data recovery apparatus described in any one of the first aspects above.

[0016] According to a third aspect, embodiments of the present invention provide a data recovery method, comprising: when a system anomaly is detected, sending a backup control signal to a random access memory (RAM) and a predetermined non-volatile memory (NDM), causing the corresponding address lines of the NDM and the RAM to be in a strobe state, thereby selecting the corresponding storage units of the NDM and the RAM, so as to write the data of each storage unit of the RAM into the NDM; and / or when the system restarts, sending a recovery control signal to the RAM and the predetermined NDM, causing the corresponding address lines of the NDM and the RAM to be in a strobe state, thereby selecting the corresponding storage units of the NDM and the RAM, so as to write the data of each storage unit of the NDM into the RAM; wherein the address lines of the NDM are respectively connected to the address lines of the RAM, and the data lines of the NDM are respectively connected to the data lines of the RAM.

[0017] According to a fourth aspect, embodiments of the present invention provide a data recovery method, comprising: when a system anomaly is detected, using the data recovery device described in any one of the first aspects to save data from a random access memory to a non-volatile memory; and / or when the system restarts, using the data recovery device described in any one of the first aspects to restore the data in the non-volatile memory to the random access memory.

[0018] According to the data recovery apparatus, method, and wearable device of the present invention, when a system anomaly is detected by a watchdog circuit, a backup control signal is issued to enable the corresponding address lines of the non-volatile memory and the random access memory to be in a strobe state, so as to select the corresponding memory cells of the non-volatile memory and the random access memory, and write the data of the selected memory cell of the random access memory to the selected memory cell of the non-volatile memory through the data line. This realizes the data backup of the random access memory to avoid data loss when the system is abnormal, and the data backup is only performed when the system is abnormal, without frequent erasing and writing of the non-volatile memory, thereby improving the service life of the wearable device. Attached Figure Description

[0019] The features and advantages of the invention will be more clearly understood by referring to the accompanying drawings, which are schematic and should not be construed as limiting the invention in any way. In the drawings:

[0020] Figure 1 A schematic diagram of a data recovery apparatus according to an embodiment of the present invention is shown;

[0021] Figure 2A schematic diagram of an optional embodiment of a data recovery apparatus according to an embodiment of the present invention is shown;

[0022] Figure 3 A schematic diagram of another alternative embodiment of the data recovery apparatus according to an embodiment of the present invention is shown. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] Figure 1 A data recovery apparatus according to an embodiment of the present invention is shown. This data recovery apparatus can be applied to various wearable devices and is used to save the random access memory 11 (RAM, also known as memory) of the wearable device when a system malfunction is detected, so that the saved data can be restored to the RAM 11 after the system restarts. The data recovery apparatus includes a non-volatile memory 12, which may be, for example, a FLASH memory (also known as flash memory). The non-volatile memory 12 may be a predetermined area partitioned from the wearable device's own FLASH memory, or it may be a memory separately disposed within the wearable device, other than the wearable device's own FLASH memory. In this embodiment, the address lines 13 of the non-volatile memory 12 and the RAM 11 are respectively connected, and the data lines 14 of the non-volatile memory and the RAM 11 are respectively connected.

[0025] The data recovery device also includes a watchdog circuit 15, which is a timer circuit that counts down or up in response to an external clock pulse. Taking the incrementing count as an example, the watchdog circuit's counter initially has a value of 0. Each clock pulse increments the counter by 1. If the processor is working normally, it periodically sends a signal to reset the counter (commonly known as "feeding the dog"), and the counter starts counting again from 0. If a system fault occurs and the processor does not reset the counter in time, the counter value will continuously increment by 1 until it exceeds a certain preset value. At this point, the watchdog circuit determines that the system is abnormal. For the decrementing count, similar to the incrementing count, the watchdog circuit's counter initially has a value greater than 0. Each clock pulse decrements the counter by 1. If a system fault occurs and the processor does not reset the counter in time, the counter value will decrease to 0. At this point, the watchdog circuit determines that the system is abnormal. Unlike existing watchdog circuits that immediately send a restart signal to the processor when a system anomaly is detected, the watchdog circuit in this embodiment sends a backup control signal to enable the corresponding address lines 13 of the non-volatile memory 12 and the random access memory 11 to be selected when a system anomaly is detected. This selects the corresponding memory cells of the non-volatile memory 12 and the random access memory 11, and writes the data of the selected memory cells of the random access memory 11 to the selected memory cells of the non-volatile memory 12 through the data line 14. Only after all the data of the memory cells of the random access memory 11 has been written to the non-volatile memory 12 does the watchdog circuit send a restart signal to the processor to restart and reset the system.

[0026] In this embodiment, similar to the data backup process described above, after the system restarts, the watchdog circuit 15 sends a recovery control signal to enable the corresponding address lines 13 of the non-volatile memory 12 and the random access memory 11 to be selected. This selects the corresponding memory cells of the non-volatile memory 12 and the random access memory 11, and writes the data of the selected memory cells in the non-volatile memory 12 to the selected memory cells in the random access memory 11 via the data line 14. This process continues until all the data in the memory cells of the non-volatile memory 12 has been written to the random access memory 11, thus completing the data recovery process. In an optional embodiment, the recovery control signal is the counting signal of the watchdog circuit 15.

[0027] The data recovery device of this invention, when a system anomaly is detected by a watchdog circuit, issues a backup control signal to enable the corresponding address lines of the non-volatile memory and random access memory to be in a strobe state, thereby enabling the corresponding memory cells of the non-volatile memory and random access memory to be selected. Data from the selected memory cell of the random access memory is then written to the selected memory cell of the non-volatile memory via a data line. This achieves data backup of the random access memory in the event of a system anomaly to avoid data loss. Furthermore, the data backup is only performed during system anomalies, avoiding frequent erasure and rewriting of the non-volatile memory, thus improving the lifespan of wearable devices.

[0028] The following text will refer to Figure 2 The data recovery apparatus of the present invention will be described in further detail below. For example... Figure 2 As shown, the random access memory 11 and the non-volatile memory 12 have the same number of storage cells, each having m*n storage cells, where m is the number of rows of storage cells and n is the number of columns of storage cells. The storage cells of the random access memory 11 are A11, A12, ..., Amn, and the storage cells of the non-volatile memory 12 are B11, B12, ..., Bmn. Both the random access memory (RAM) 11 and the non-volatile memory (NDRAM) 12 include m data lines. The data lines of the RAM 11 are Dr1, Dr2, ..., Drm, and the data lines of the NDRAM 12 are Df1, Df2, ..., Dfm. Each of the m data lines of the RAM 11 is connected to the data terminal of each memory cell in a row, and each of the m data lines of the NDRAM 12 is connected to the data terminal of each memory cell in a row. The data lines of the NDRAM 12 and RAM 11 are correspondingly connected; that is, the data line Dfi of the NDRAM 12 connecting to the i-th row of memory cells is connected to the data line Dri of the RAM 11 connecting to the i-th row of memory cells, where 1 ≤ i ≤ m. In an optional embodiment, the data lines of the NDRAM 12 and RAM 11 are correspondingly connected via a controllable switch.

[0029] exist Figure 2In the example, the data line Dr1 of the random access memory 11 is connected to the data terminals of the n memory cells in the first row, and the data line Df1 of the non-volatile memory 12 is connected to the data terminals of the n memory cells in the first row. The data lines Dr1 and Df1 are connected via a controllable switch. Similarly, the data line Dr2 of the random access memory 11 is connected to the data terminals of the n memory cells in the second row, and the data line Df2 of the non-volatile memory 12 is connected to the data terminals of the n memory cells in the second row. The data lines Dr2 and Df2 are connected via a controllable switch. Likewise, the data line Drm of the random access memory 11 is connected to the data terminals of the n memory cells in the m-th row, and the data line Dfm of the non-volatile memory 12 is connected to the data terminals of the n memory cells in the m-th row. The data lines Drm and Dfm are connected via a controllable switch.

[0030] In this embodiment, both the non-volatile memory 12 and the random access memory 11 include n column address lines, and the column address lines of the non-volatile memory 12 are respectively connected to the column address lines of the random access memory 11. Figure 2 In the example, the column address line Yf1 of the non-volatile memory 12 is connected to the column address line Yr1 of the random access memory 11, the column address line Yf2 of the non-volatile memory 12 is connected to the column address line Yr2 of the random access memory 11, and so on, the column address line Yfn of the non-volatile memory 12 is connected to the column address line Yrn of the random access memory 11. Optionally, the row address lines of the random access memory 11 and the non-volatile memory 12 are connected together.

[0031] In this embodiment, the backup control signal is a counting signal used by the watchdog circuit 15 to reset the counter and start counting again after detecting a system fault. When the watchdog circuit 15 issues a counting signal, it enables the row address lines of both the non-volatile memory 12 and the random access memory 11 to be in a strobe state, and enables the column address lines of both the non-volatile memory 12 and the random access memory 11 to be in a strobe state, so that the data of the selected column of memory cells in the random access memory 11 is written to the selected column of memory cells in the non-volatile memory 12 through the data lines, until the data of all memory cells in the random access memory 11 is written to the non-volatile memory 12.

[0032] The following will refer to Figure 2This will be explained in detail, taking the high-level selection state and the watchdog circuit 15's counting signal incrementing from 0 as an example. When the watchdog circuit 15 detects a system fault, it resets the counter to 0 and starts counting again. After the first clock pulse, the counter value is 1, and the watchdog circuit 15's counting signal value is 1. At this time, the row address lines of the non-volatile memory 12 and the random access memory 11 are both at a high level, for example, by controlling a controllable switch to connect the row address lines to the power supply; and the column address lines Yr1 and Yf1 of the non-volatile memory 12 and the random access memory 11 corresponding to the counting signal 1 are also at a high level, for example, by controlling a controllable switch to connect them to the power supply, while the other column address lines are grounded and in a deselected state. At this time, the first column of the random access memory 11... Storage cells A11, A21, ..., Am1 are selected, and the first column of storage cells B11, B21, ..., Bm1 of the non-volatile memory 12 is selected. Data in storage cell A11 is written to storage cell B11 through data lines Dr1 and Df1, data in storage cell A21 is written to storage cell B21 through data lines Dr2 and Df2, and so on. Data in storage cell Am1 is written to storage cell Bm1 through data lines Drm and Dfm, thus completing the data backup of the first column of storage cells of the random access memory 11 in one clock cycle. Similarly, after the second clock pulse, the watchdog circuit 15 sets the column address lines Yr2 and Yf2 corresponding to the counting signal 2 of the non-volatile memory 12 and the random access memory 11 to a high level, thereby completing the data backup of the second column memory cell of the random access memory 11. This process continues until the nth clock pulse, completing the data backup of the nth column memory cell of the random access memory 11, thus writing the data of all memory cells in the random access memory 11 into the non-volatile memory 12. Here, the reset value of the watchdog circuit 15 can be set to n+1. After the (n+1)th clock pulse, the watchdog circuit 15 sends a restart signal to the processor, causing the system to restart and reset. Optionally, while sending the restart signal to the processor, the watchdog circuit 15 disconnects all address lines of the random access memory 11 and the non-volatile memory 12, and also disconnects the data lines of the random access memory 11 and the non-volatile memory 12.

[0033] Those skilled in the art should understand that it is also feasible for the watchdog circuit 15 to count down. For example, the watchdog circuit can start counting down from n. When the count value of the watchdog circuit 15 is n, the backup of the nth column of memory cells in the random access memory 11 is completed; when the count value of the watchdog circuit 15 is n-1, the backup of the (n-1)th column of memory cells in the random access memory 11 is completed; and so on. When the count value of the watchdog circuit 15 is 1, the backup of the first column of memory cells in the random access memory 11 is completed, and thus the data of all memory cells in the random access memory 11 is written to the non-volatile memory 12. In the next clock cycle, the count value of the watchdog circuit 15 is 0, and a restart signal is sent to the processor to restart and reset the system. Of course, when the watchdog circuit starts counting down from n, the backup of the random access memory 11 can also be implemented starting from the first column of memory cells. In this case, a predetermined data n+1 can be used to subtract the count value of the watchdog circuit to select the memory cell of the corresponding column. In addition, those skilled in the art should understand that the strobe state may also be low.

[0034] Similar to the data backup process described above, after the system restarts, the watchdog circuit 15 sends a counting signal. This counting signal can increment from 0 or decrement from n, restoring the data of each memory cell in the non-volatile memory 12 to the random access memory 11 column by column. Optionally, after completing the data restoration, the watchdog circuit 15 disconnects all address lines of the random access memory 11 and the non-volatile memory 12, and also disconnects the data lines of the random access memory 11 and the non-volatile memory 12.

[0035] In the above implementation, when the system malfunctions, the data in the random access memory 11 is backed up to the non-volatile memory 12 column by column. When the system restarts, the data in the non-volatile memory 12 is restored to the random access memory 11 column by column. Those skilled in the art should understand that the present invention is not limited to this; backing up or restoring data one by one is also feasible. Another optional implementation of the present invention is as follows: Figure 3 As shown, with Figure 2 The difference in the implementation shown is that, Figure 3In the data recovery device shown, both the non-volatile memory 12 and the random access memory 11 include n data lines. Each of the n data lines of the non-volatile memory 12 and the random access memory 11 is connected to the data terminal of each memory cell in its respective column, and the data lines of the non-volatile memory 12 and the random access memory 11 are correspondingly connected. The m row address lines of the non-volatile memory 12 and the random access memory 11 are correspondingly connected. When the watchdog circuit 15 sends a counting signal, for example, counting from 0 to m, the column address lines of the non-volatile memory 12 and the random access memory 11 are both in a strobe state, and the row address lines of the non-volatile memory 12 and the random access memory 11 corresponding to the counting signal are also in a strobe state. This allows the data of the selected row of memory cells in the random access memory 11 to be written to the selected row of memory cells in the non-volatile memory 12 through the data lines, until the data of all memory cells in the random access memory 11 is written to the non-volatile memory 12. After the system restarts, the watchdog circuit 15 sends a counting signal again, restoring the data of each memory cell in the non-volatile memory 12 to the random access memory 11 row by row. In this embodiment, when the system malfunctions, the data in the random access memory 11 is backed up to the non-volatile memory 12 row by row, and when the system restarts, the data in the non-volatile memory 12 is restored to the random access memory 11 row by row.

[0036] Accordingly, this invention also provides a data recovery method. In this data recovery method, when a system anomaly is detected, a backup control signal is sent to a random access memory (RAM) and a predetermined non-volatile memory (NDM) to enable the corresponding address lines of the NDM and the RAM to be in a strobe state, thereby enabling the corresponding memory cells of the NDM and the RAM to be selected, so as to write the data of each memory cell of the RAM to the NDM. The address lines of the NDM are connected to the address lines of the RAM, and the data lines of the NDM are connected to the data lines of the RAM.

[0037] Furthermore, in this data recovery method, after the system restarts, a recovery control signal is sent to the random access memory and the predetermined non-volatile memory to enable the corresponding address lines of the non-volatile memory and the random access memory to be selected, so as to select the corresponding memory cells of the non-volatile memory and the random access memory, and write the data of each memory cell of the non-volatile memory into the random access memory.

[0038] The connection relationship between the aforementioned random access memory and non-volatile memory can be found in the corresponding references. Figures 1 to 3 The relevant descriptions in the illustrated embodiments are for reference only and will not be repeated here.

[0039] The data recovery method of this invention, when a system anomaly is detected, issues a backup control signal to enable the corresponding address lines of the non-volatile memory and the random access memory to be in a strobe state, thereby enabling the corresponding memory cells of the non-volatile memory and the random access memory to be selected. Data from the selected memory cell of the random access memory is then written to the selected memory cell of the non-volatile memory via a data line. This achieves data backup of the random access memory in the event of a system anomaly to avoid data loss. Furthermore, the data backup is only performed during system anomalies, avoiding frequent erasure and rewriting of the non-volatile memory, thus improving the lifespan of wearable devices.

[0040] Another embodiment of the present invention also provides a data recovery method, in which, when a system anomaly is detected, the above-mentioned... Figures 1 to 3 The data recovery device in the illustrated embodiment saves the data from the random access memory to non-volatile memory; and when the system restarts, it utilizes the above-described... Figures 1 to 3 The data recovery device in the illustrated embodiment recovers data from the non-volatile memory to the random access memory.

[0041] For details regarding the data recovery device in the data recovery method of this embodiment, please refer to the above text. Figures 1 to 3 The relevant descriptions and effects in the illustrated device embodiments are for understanding purposes only and will not be repeated here.

[0042] Finally, embodiments of the present invention also provide a wearable device, including the one described above. Figures 1 to 3 The data recovery device shown is designed to address the issue of wearable devices like smart bracelets crashing or experiencing memory overflows due to static electricity or program malfunctions during daily use. When a watchdog timer detects this anomaly, it sends a backup control signal to select the corresponding address lines of the non-volatile memory (NDRAM) and random access memory (RAM). This selects the corresponding memory cells in the NDRAM and RAM, allowing data from the selected RAM cell to be written to the selected NDRAM cell via a data line. This data backup prevents data loss, and since it only occurs during system anomalies, it avoids frequent erasures and rewriting of the NDRAM, thus extending the device's lifespan.

[0043] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A data recovery apparatus for a wearable device, the apparatus comprising: include: The address lines of the non-volatile memory are connected to the address lines of the random access memory, and the data lines of the non-volatile memory are connected to the data lines of the random access memory. A watchdog circuit is used to detect whether the system is normal. When the watchdog circuit detects a system abnormality, it sends a backup control signal to enable the corresponding address lines of the non-volatile memory and the random access memory to be in a strobe state, so as to enable the corresponding memory cells of the non-volatile memory and the random access memory, and write the data of the selected memory cell of the random access memory to the selected memory cell of the non-volatile memory through the data line, until the data of all memory cells of the random access memory is written to the non-volatile memory. The backup control signal is the counting signal that the watchdog circuit resets the counter and counts again after detecting a system fault; When the watchdog circuit issues the counting signal, it enables the row address lines of both the non-volatile memory and the random access memory to be in a strobe state, and also enables the column address lines of both the non-volatile memory and the random access memory corresponding to the counting signal to be in a strobe state. This allows the data of the strobe column of memory cells in the random access memory to be written to the strobe column of memory cells in the non-volatile memory through the data lines, until the data of all memory cells in the random access memory is written to the non-volatile memory.

2. The data recovery device of claim 1, wherein The non-volatile memory and the random access memory have the same number of storage units, each having m*n storage units, where m is the number of rows of storage units and n is the number of columns of storage units.

3. The data recovery device of claim 2, wherein, Both the non-volatile memory and the random access memory include m data lines. Each of the m data lines of the non-volatile memory and the random access memory is connected to the data terminal of each memory cell in its respective row, and the data lines of the non-volatile memory and the random access memory are connected accordingly. Both the non-volatile memory and the random access memory include n column address lines, and the column address lines of the non-volatile memory are respectively connected to the column address lines of the random access memory.

4. The data recovery device of claim 1, wherein The watchdog circuit is also used to send a restart signal to the processor after all the data in all the memory cells of the random access memory has been written to the non-volatile memory, so that the system restarts and resets.

5. The data recovery apparatus according to any one of claims 1 to 4, wherein The watchdog circuit is also used to send a recovery control signal after the system restarts to enable the corresponding address lines of the non-volatile memory and the random access memory to be in a strobe state, so as to enable the corresponding memory cells of the non-volatile memory and the random access memory, and to write the data of the selected memory cell of the non-volatile memory to the selected memory cell of the random access memory through the data line, until the data of all memory cells of the non-volatile memory is written to the random access memory.

6. A wearable device, comprising: The data recovery device of any one of claims 1-5. 7.A data recovery method for a wearable device, comprising: Comprising: When detecting system abnormality, sending a backup control signal to the random access memory and the predetermined non-volatile memory through the watchdog circuit, making the corresponding address lines of the non-volatile memory and the random access memory in a gating state, gating the corresponding memory cells of the non-volatile memory and the random access memory, and writing the data of each memory cell of the random access memory into the corresponding memory cell of the non-volatile memory; And / or When the system is restarted, sending a recovery control signal to the random access memory and the predetermined non-volatile memory through the watchdog circuit, making the corresponding address lines of the non-volatile memory and the random access memory in a gating state, gating the corresponding memory cells of the non-volatile memory and the random access memory, and writing the data of each memory cell of the non-volatile memory into the corresponding memory cell of the random access memory; Wherein, the address lines of the non-volatile memory are respectively connected with the address lines of the random access memory, and the data lines of the non-volatile memory are respectively connected with the data lines of the random access memory; The backup control signal or the recovery control signal is a counting signal in which the watchdog circuit resets the counter after detecting system failure and counts again; When the watchdog circuit sends the counting signal, the row address lines of the non-volatile memory and the random access memory are both in a gating state, and the column address lines of the non-volatile memory and the random access memory corresponding to the counting signal are in a gating state, so that the data of the gated column of memory cells of the random access memory is written into the gated column of memory cells of the non-volatile memory through the data lines, until the data of all memory cells of the random access memory is written into the non-volatile memory. 8.A data recovery method for a wearable device, comprising: Comprising: When detecting system abnormality, using the data recovery device of any one of claims 1-5 to save the data of the random access memory to the non-volatile memory; And / or When the system is restarted, using the data recovery device of any one of claims 1-5 to recover the data in the non-volatile memory to the random access memory.

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