Dual-chip backup switching circuit and switching method

Abstract

The application discloses a dual-chip backup switching circuit and a switching method, and belongs to the technical field of electronic engineering.The dual-chip backup switching circuit comprises two chips with the same function model, namely, a main chip and a backup chip; the main chip is responsible for completing control or operation functions in a current system, and the main chip and the backup chip monitor each other to check whether the other one is invalid; a RESET signal of the chip is connected with a weak pull-up port of a GPIO pin in an AND logic, so that the two chips have the ability to control hardware reset of the other one.When the backup chip detects that the main chip is invalid, the backup chip sends a reset signal to restart the invalid chip, switches the backup chip to the main chip, and continues to execute functions; after the invalid chip is restarted, the invalid chip is switched to the role of the backup chip, so that the dual-chip backup system is automatically switched without external intervention.

Description

Technical Field

[0001] This invention relates to the field of electronic engineering technology, and in particular to a dual-chip backup switching circuit and switching method. Background Technology

[0002] At critical nodes of critical systems, dual-backup designs are often employed to ensure the stability of system operation. When the current system fails, a series of measures are taken to switch to the backup system to ensure that the system is not affected. As chips are the key computing or control nodes of the entire electronic system, dual-chip backup circuits have many applications. However, existing dual-backup circuits often require the design of additional detection circuits or the writing of monitoring and switching logic on other chips, resulting in additional design burden and cost. Summary of the Invention

[0003] The purpose of this invention is to provide a dual-chip backup switching circuit and switching method to solve the problem that existing dual-chip backup systems require additional external detection logic, or the system cannot afford the time overhead of restarting a single-chip watchdog logic.

[0004] To solve the above-mentioned technical problems, the present invention provides a dual-chip backup switching circuit, comprising two chips with the same function and model: a main chip and a backup chip;

[0005] The main chip is responsible for performing control or computation functions in the current system, and the main chip and backup chip monitor each other for failure.

[0006] The chip's RESET signal is ANDed with the weak pull-up pin of the GPIO pin, giving the two chips the ability to control each other's hardware reset.

[0007] Optionally, when the main chip and the backup chip are monitoring each other for failure, the function-related circuits in the backup chip will temporarily turn off the clock to save power.

[0008] Optionally, both chips are equipped with a Timer module for timing the toggle of GPIO pins and timeout detection of external input level toggle signals.

[0009] The present invention also provides a switching method based on the aforementioned dual-chip backup switching circuit, comprising:

[0010] Both chips start up simultaneously to identify the main chip and the backup chip;

[0011] The main chip performs control or computation functions, and the main chip and backup chip monitor each other for failure.

[0012] If the backup chip fails, the main chip sends a reset signal to reset the backup chip, and the backup chip begins to monitor the recovery of the main chip.

[0013] If the main chip fails, the backup chip activates the relevant circuit clock to perform control or computation functions in place of the main chip.

[0014] Optionally, after both chips start up simultaneously, the method for determining the primary and backup chips is as follows:

[0015] The I2C bus of two chips is used to implement the competition arbitration of the master chip. After the two chips are powered on, they first send a level toggling signal to the monitoring port of the other chip to query the I2C bus status.

[0016] If it is BUSY, then the chip is a backup chip, and its I2C bus is set to slave state;

[0017] If in FREE state, the chip sends arbitrary data to the broadcast address via the I2C bus and checks for I2C bus arbitration failure. If arbitration fails, the chip is a backup chip; if no failure response is received, the chip is the master chip.

[0018] Optionally, when the backup chip detects whether the main chip has failed, the function-related circuits in the backup chip temporarily turn off the clock to save power.

[0019] Optionally, the main chip and backup chip can monitor each other's failure status using the following method:

[0020] After both chips are powered on, they both output level toggling signals from GPIO pins or other external pins at regular intervals.

[0021] The receiver performs two tasks: first, it sets up an internal timing module to generate an interrupt at a certain time interval and accumulates a count in the timer interrupt, which is used for timeout judgment; second, after receiving an external level flip signal, it executes an interrupt handling function, in which the timer count is cleared to zero, thus resetting the timer count and preventing the count from exceeding the timeout threshold.

[0022] If the timer count accumulates to a value greater than the timeout threshold, the other chip is considered to have failed, and further measures to switch between the primary and backup chips are required.

[0023] Optionally, if the backup chip fails, the main chip first maintains the occupation of the I2C bus, then sends a reset signal to the backup chip. After the backup chip is reset, it checks the I2C bus status according to the procedure to confirm its role as a backup chip and begins to monitor the recovery of the main chip.

[0024] If the main chip fails, the backup chip initiates a main chip reset, occupies the I2C bus, and assumes the responsibilities of the main chip, sending processed data or control signals to the outside. After the main chip is reset, it determines that its role has been switched through the I2C bus, enters the role of the backup chip, monitors the external level toggle signal, and stops sending processed data or control signals to the outside to avoid bus conflicts.

[0025] In the dual-chip backup switching circuit and switching method provided by this invention, when the backup chip detects a failure in the main chip's function, it sends a reset signal to restart the failed main chip and switches the backup chip to the main chip to continue performing its function. After restarting, the failed chip switches to the role of the backup chip, achieving automatic switching of the dual-chip backup system without external intervention. This invention enables the setting of the backup switching circuit's role, chip failure monitoring, and backup circuit switching processes to be implemented within the dual-chip circuit itself, eliminating the need for additional external monitoring and intervention, thus reducing development and production costs. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the dual-chip backup switching circuit framework provided by the present invention;

[0027] Figure 2 This is a schematic diagram of the dual-chip backup switching method provided by the present invention. Detailed Implementation

[0028] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the dual-chip backup switching circuit and switching method proposed in this invention. The advantages and features of this invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0029] Taking a dual-DSP chip backup system as an example, with chip 1 and chip 2 respectively, refer to... Figure 1 In common DSP applications, dual-chip hardware interconnection is implemented. External input data is typically processed and sent from the data source to both the main chip and the backup chip. However, only the main chip is responsible for processing the task and providing the processed data. The backup chip can perform the same processing task but does not send out data. It can also shut down circuits other than the Timer module (responsible for internal timing) and GPIO pins (responsible for sending hardware "heartbeats" and participating in reset) to reduce the overall circuit power consumption.

[0030] In board-level reset circuit design, the GPIO pins coupled to the reset circuit should generally be in input state by default upon power-up in the DSP chip. A weak pull-up resistor can be applied to avoid interference with the reset signal when the chip is not initialized upon power-up. After the chip powers on, the corresponding GPIO pin should be set to output and high. This GPIO pin is then logically ANDed with the board-level reset signal and input to the chip's reset pin, responsible for resetting the failed chip in case of a problem.

[0031] Both chips share the same I2C bus, specifically SCL and SDA. During power-up configuration, the local I2C bus is first configured to master-transmit mode. The external device address is set to the general broadcast address of the I2C bus: an all-zero address. Then, randomly generated data is sent. The I2C bus is designed for dual-chip role contention. The principle is that only one master chip can occupy the I2C bus at a time. Using this mechanism, the chip that first broadcasts and sends data is considered the master chip and undertakes data processing. Other chips, upon power-up, detect that the I2C bus is in a BUSY state, indicating that a chip is already assuming master responsibilities, and switch their I2C bus to slave-receiver mode. In extreme cases, both chips may start broadcasting data simultaneously. According to the I2C bus protocol's arbitration rules, arbitration will occur during subsequent random number transmissions. The successful arbitrator retains the master chip role.

[0032] The dual-chip system internally incorporates a Timer module for timing GPIO pin toggling and timeout detection of external input level toggling signals. These processes are handled within the Timer interrupt function. Each Timer interrupt increments the timeout count, and the count is reset upon receiving an external level toggling signal and triggering a GPIO pin toggling interrupt. This detection mechanism allows for adjustable Timer interrupt intervals, supporting values ​​from microseconds to seconds. Upon detecting a timeout, the same Timer interrupt function pulls the GPIO pin coupled to the reset signal low, resetting the faulty chip.

[0033] The chip uses a single GPIO pin to output high and low levels: a "heartbeat" signal. This signal is input to the GPIO pin of the other chip. A high level or rising and falling edges of the GPIO input pin will generate an interrupt signal, and the timeout count will be cleared in the interrupt handling function.

[0034] The present invention also provides a method based on, for example Figure 1 The switching method of the dual-chip backup switching circuit shown is as follows: Figure 2 As shown, it includes the following steps:

[0035] Step 1: Start both chips simultaneously to identify the main chip and the backup chip.

[0036] The I2C bus of two chips is used to implement the competition arbitration of the master chip. After the two chips are powered on, they first send a level toggling signal to the monitoring port of the other chip to query the I2C bus status.

[0037] If it is BUSY, then the chip is a backup chip, and its I2C bus is set to slave state;

[0038] If in FREE state, the chip sends arbitrary data to the broadcast address via the I2C bus and checks for I2C bus arbitration failure. If arbitration fails, the chip is a backup chip; if no failure response is received, the chip is the master chip.

[0039] Step 2: The main chip performs control or calculation functions, and the main chip and backup chip monitor each other for failure.

[0040] When the backup chip monitors whether the main chip has failed, the circuits related to the function in the backup chip temporarily turn off the clock to save power.

[0041] The main chip and backup chip monitor each other for failure by the following method: after both chips are powered on, they output level toggling signals from GPIO pins or other external pins at regular intervals.

[0042] The receiver performs two tasks: first, it sets up an internal timing module to generate an interrupt at a certain time interval and accumulates a count in the timer interrupt, which is used for timeout judgment; second, after receiving an external level flip signal, it executes an interrupt handling function, in which the timer count is cleared to zero, thus resetting the timer count and preventing the count from exceeding the timeout threshold.

[0043] If the timer count accumulates to a value greater than the timeout threshold, the other chip is considered to have failed, and further measures to switch between the primary and backup chips are required.

[0044] Step 3: If the backup chip fails, the main chip first maintains the occupation of the I2C bus, and then sends a reset signal to the backup chip. After the backup chip is reset, it checks the I2C bus status according to the process to confirm its role as a backup chip and begins to monitor the recovery of the main chip.

[0045] If the main chip fails, the backup chip initiates a main chip reset, occupies the I2C bus, and assumes the responsibilities of the main chip, sending processed data or control signals to the outside. After the main chip is reset, it determines that its role has been switched through the I2C bus, enters the role of the backup chip, monitors the external level toggle signal, and stops sending processed data or control signals to the outside to avoid bus conflicts.

[0046] In summary, this invention employs three GPIO pins and two I2C buses to achieve automatic dual-chip competition for the master chip, failure detection, and automatic switching without external host control. When a chip fails, it can automatically switch to backup chip after reset due to the I2C bus occupancy design, continuing to perform failure monitoring tasks. This invention can be used in scenarios with high reliability requirements, as well as in applications where the time consumption of resetting a single chip is unacceptable and rapid functional recovery is needed.

[0047] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A switching method based on a dual-chip backup switching circuit, the dual-chip backup switching circuit comprising two chips of the same functional type: a main chip and a backup chip; the main chip is responsible for completing the control or operation functions in the current system, and the main chip and the backup chip monitor each other for failure; the RESET signal of the chip and the weak pull-up port of the GPIO pin are logically ANDed, giving the two chips the ability to control the hardware reset of the other; when the main chip and the backup chip monitor each other for failure, the function-related circuits in the backup chip temporarily turn off the clock to save power consumption; both chips are internally configured with a Timer module for timing flip of the GPIO pin and timeout detection of the external input level flip signal; characterized in that the method comprises: both chips are started simultaneously to determine the main chip and the backup chip; the main chip performs control or operation functions, and the main chip and the backup chip monitor each other for failure; if the backup chip fails, the main chip sends a reset signal to reset the backup chip, and the backup chip starts to monitor the main chip; if the main chip fails, the backup chip turns on the clock of the function-related circuits to replace the main chip to perform control or operation functions; after both chips are started simultaneously, the method for determining the main chip and the backup chip is as follows: the I2C bus of the two chips is used to realize competition arbitration of the main chip, after both chips are powered on, the chip first sends a level flip signal to the monitoring port of the other chip to query the I2C bus state, if it is BUSY, the chip is the backup chip, and the I2C bus of the chip is set to slave state; if it is FREE state, the chip sends any data to the broadcast address through the I2C bus, and detects whether there is an I2C bus arbitration failure, if there is an arbitration failure, the chip is the backup chip, if no failure response is received, it means that the chip is the main chip.

2. The handover method of claim 1, wherein, When the backup chip monitors the main chip for failure, the function-related circuits in the backup chip temporarily turn off the clock to save power consumption.

3. The handover method of claim 1, wherein, The method for the main chip and the backup chip to monitor each other for failure is as follows: after both chips are powered on, they both output a level flip signal from the GPIO pin or other external pin output port at a certain time interval; the receiving side performs two tasks, one is to set an internal timing module to generate an interrupt at a certain time interval, and to count in the timing interrupt, the count is used for timeout judgment; the other is to receive the external level flip signal and perform an interrupt processing function, which resets the timing count in the interrupt processing function to prevent the count from exceeding the timeout threshold; if the timing count exceeds the timeout threshold, it is considered that the other chip has failed, and further main backup chip switching measures need to be taken.

4. The handover method of claim 1, wherein, If the backup chip fails, the main chip first maintains the occupation of the I2C bus, then sends a reset signal to the backup chip, after the backup chip is reset, it detects the I2C bus state according to the process to confirm its backup chip role and start to monitor the main chip. If the main chip fails, the backup chip initiates the main chip reset, occupies the I2C bus, and assumes the main chip responsibility to send processing data or control signals to the outside; after the main chip reset, the role of the main chip is switched through the I2C bus, enters the backup chip role, monitors the external level flip signal, and stops sending processing data or control signals to the outside to avoid bus conflict.

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