Implementation circuit, method and electronic device of sm3 algorithm

Abstract

The application provides an implementation circuit, method and electronic equipment of an SM3 algorithm, wherein a plurality of carry-save adders for performing three-parameter addition operation and three-parameter XOR operation are arranged in the implementation circuit of the SM3 algorithm, so that the multi-parameter operation in the compression operation is completed through the carry-save adders, and therefore, various multi-logic operations such as the calculation of the intermediate variable FF and the calculation of TT1 can be realized through the carry-save adders, the repeated logic structure in the existing implementation circuit of the SM3 algorithm is saved, the number of registers required by the implementation circuit of the SM3 algorithm is reduced, and the circuit area of the implementation circuit of the SM3 algorithm is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of data security, and in particular to an SM3 algorithm implementation circuit, method and electronic device. BACKGROUND

[0002] The SM3 algorithm, namely the SM3 cryptographic hash algorithm, the calculation of the SM3 algorithm needs to be completed through a corresponding calculation circuit, and in the SM3 calculation circuit, the loop iteration step in the algorithm is often set to a parallel operation mode, but the parallel implementation needs to use more data registers, thus leading to a large circuit area of the SM3 algorithm implementation circuit, which is difficult to meet the current circuit design needs. SUMMARY

[0003] Therefore, the present application provides an SM3 algorithm implementation circuit, method and electronic device to improve the large circuit area of the SM3 algorithm implementation circuit.

[0004] In a first aspect, an SM3 algorithm implementation circuit is provided, which comprises a message compression unit, and the message compression unit comprises a first preset number of carry-save adders.

[0005] The first preset number of carry-save adders are configured to perform three-parameter addition and three-parameter XOR operations in the SM3 algorithm.

[0006] Optionally, in an embodiment, the message compression unit further comprises a second preset number of registers.

[0007] The second preset number of registers are configured to cooperate with the first preset number of carry-save adders to calculate intermediate variables, and the intermediate variables at least include an intermediate variable SS1, an intermediate variable FF and an intermediate variable TT1.

[0008] Further, in an embodiment, the second preset number of registers comprises first to eighth registers, the first preset number of carry-save adders comprises first to third carry-save adders, and the message compression unit further comprises an XOR operator, an addition operator and first to sixth data selectors.

[0009] The first register and the fifth register are connected with the first carry-save adder, the first to third data selectors are connected with the second carry-save adder, the fourth to sixth data selectors are connected with the third carry-save adder, the first register and the second carry-save adder are connected with the first data selector, the first carry-save adder is connected with the first data selector through an exclusive-OR operator, the first register and the second register are connected with the second data selector, the third register and the fourth register are connected with the third data selector, the first carry-save adder is connected with the fourth to sixth data selectors through the exclusive-OR operator and an addition operator, one end of the eighth register is connected with the sixth data selector, and the other end is connected with the fourth to sixth data selectors through the addition operator, and the fifth to seventh registers are connected with the fifth data selector;

[0010] The first carry-save adder is configured to calculate an intermediate variable SS1 according to data in the first register and the fifth register.

[0011] The second carry-save adder is configured to calculate an intermediate variable FF and an intermediate variable TT1 according to data input by the first to third data selectors.

[0012] The third carry-save adder is configured to calculate an intermediate variable TT2 according to data input by the fourth to sixth data selectors.

[0013] Further, in an embodiment provided by the embodiment of the present application, the second carry-save adder is further configured to calculate a first sum value based on data in the fourth register and the intermediate variable FF, and send the first sum value to the fourth register, so that data in the fourth register is updated.

[0014] The third carry-save adder is further configured to calculate a second sum value based on data in the eighth register and the intermediate variable GG, and send the second sum value to the eighth register, so that data in the eighth register is updated.

[0015] Optionally, in an embodiment provided by the embodiment of the present application, the implementation circuit of the SM3 algorithm further comprises a message expansion unit, and the message expansion unit comprises an exclusive-OR operator, a ninth register, and ninth to thirteenth data selectors.

[0016] The message expansion unit is connected with the message compression unit.

[0017] The ninth register is connected with the ninth data selector, the tenth data selector, and the eleventh data selector.

[0018] The thirteenth data selector and the tenth data selector are both connected with the ninth data selector.

[0019] The eleventh data selector is connected with the twelfth data selector;

[0020] The tenth data selector, the twelfth data selector and the thirteenth data selector are connected with the exclusive or operator;

[0021] The exclusive or operator is connected with the ninth register;

[0022] The path of the intermediate variable P1 output by the message expansion unit comprises: the intermediate variable W j-16 The intermediate variable W j-3 is input to the exclusive or operator through the tenth data selector and then input to the exclusive or operator through the twelfth data selector after being left shifted by 15 bits; j-9 The intermediate variable W j-16 is input to the exclusive or operator through the thirteenth data selector; j-3 The intermediate variable W j-9 is left shifted by 15 bits; The intermediate variable P1, the intermediate variable W j-3 which is left shifted by 15 bits, and the intermediate variable W j-6 are input to the exclusive or operator through the ninth register and the tenth data selector, through the ninth register and then input to the exclusive or operator through the ninth data selector and the thirteenth data selector after being left shifted by 23 bits, and through the ninth register and the eleventh data selector and then input to the exclusive or operator through the twelfth data selector after being left shifted by 15 bits, and the intermediate variable P1, the intermediate variable W j-3 which is left shifted by 23 bits, and the intermediate variable W j-6 which is left shifted by 15 bits pass through the exclusive or operator to obtain an intermediate variable P1;

[0023] The path of the intermediate variable W j output by the message expansion unit comprises: the intermediate variable P1 is input to the exclusive or operator through the ninth register and the tenth data selector, the intermediate variable W j-3 which is stored in the ninth register is left shifted by 7 bits and then input to the exclusive or operator through the ninth data selector and the thirteenth data selector, the intermediate variable W j-6 is input to the exclusive or operator through the twelfth data selector, and the intermediate variable P1, the intermediate variable W j-3 which is left shifted by 7 bits, and the intermediate variable W j-6 pass through the exclusive or operator to obtain the corresponding intermediate variable W j .

[0024] In a second aspect, an implementation method of an SM3 algorithm is provided, and the implementation circuit comprises a message compression unit, and the message compression unit comprises a first preset number of carry-save adders;

[0025] The first preset number of carry-save adders are used to perform three-parameter addition and three-parameter XOR operations in the SM3 algorithm.

[0026] Optionally, in an embodiment provided by the present application, the message compression unit further comprises a second preset number of registers.

[0027] The second preset number of registers are controlled to cooperate with the first preset number of carry-save adders to calculate intermediate variables, wherein the intermediate variables at least include an intermediate variable SS1, an intermediate variable FF, and an intermediate variable TT1.

[0028] Further, in an embodiment provided by the present application, the second preset number of registers include first to eighth registers, the first preset number of carry-save adders include first to third carry-save adders, and the message compression unit further comprises first to sixth data selectors.

[0029] The control of the second preset number of registers to cooperate with the first preset number of carry-save adders to calculate intermediate variables, wherein the intermediate variables at least include an intermediate variable SS1, an intermediate variable FF, and an intermediate variable TT1, includes:

[0030] The first carry-save adder calculates the intermediate variable SS1 according to data in the first register and the fifth register.

[0031] The second carry-save adder calculates the intermediate variable FF and the intermediate variable TT1 according to data input by the first to third data selectors.

[0032] The third carry-save adder calculates the intermediate variable TT2 according to data input by the fourth to sixth data selectors.

[0033] Further, in an embodiment provided by the present application, the method further comprises:

[0034] The second carry-save adder calculates a first sum value based on data in the fourth register and the intermediate variable FF, and sends the first sum value to the fourth register to update the data in the fourth register.

[0035] The third carry-save adder calculates a second sum value based on data in the eighth register and the intermediate variable GG, and sends the second sum value to the eighth register to update the data in the eighth register.

[0036] In a third aspect, an embodiment of the present application further provides an electronic device comprising the implementation circuit of the SM3 algorithm according to any one of the first aspect.

[0037] In the implementation circuit of the SM3 algorithm, a plurality of reserved carry adders for performing three-parameter addition operation and three-parameter XOR operation are arranged, so that the three-parameter addition operation and the three-parameter XOR operation in the SM3 algorithm are completed through the reserved carry adders, and then a plurality of registers are not required to complete the multi-parameter operation, thereby reducing the number of registers required by the implementation circuit of the SM3 algorithm and reducing the circuit area of the implementation circuit of the SM3 algorithm. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the protection scope of the present application. In each drawing, similar components are denoted by similar reference numerals.

[0039] Figure 1 The circuit structure diagram of the implementation circuit of the SM3 algorithm provided by the embodiment of the present application is shown;

[0040] Figure 2 The circuit structure diagram of the message compression unit provided by the embodiment of the present application is shown;

[0041] Figure 3 The circuit structure diagram of the message expansion unit provided by the embodiment of the present application is shown;

[0042] Figure 4 The flowchart of the implementation method of the SM3 algorithm provided by the embodiment of the present application is shown. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be described in detail below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments.

[0044] The components of the embodiments of the present application generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0045] Hereinafter, the terms "include", "have", and their conjugates, used in various embodiments of the present application, merely indicate the presence of the features, numbers, steps, operations, elements, components, or combinations thereof, and do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0046] In addition, the terms "first", "second", "third", and the like are used only to distinguish the description, and are not to be understood as indicating or implying a relative importance.

[0047] Unless defined otherwise, all terms used herein (including technical terms and scientific terms) have the same meanings as those generally understood by those having ordinary knowledge in the art to which various embodiments of the present application belong. The terms, such as those defined in a generally used dictionary, are to be interpreted as having the same meanings as those in the context of relevant technology and will not be interpreted to have ideal or excessively formal meanings unless clearly defined in various embodiments of the present application.

[0048] To better illustrate the optimization method of the SM3 algorithm proposed in the embodiments of the present application, first, a brief description of the SM3 algorithm in the prior art and the implementation circuit of the SM3 algorithm is given.

[0049] SM3 is a one-way cryptographic hash function. One-way means that it is extremely difficult to backtrack the input data from the output result. The input data of the cryptographic hash function is usually referred to as a message, and the output result is often referred to as a message digest or digest, i.e. a hash value.

[0050] Further, in the process of converting the message into a hash value, the message needs to be padded first.

[0051] Specifically, a 1 and multiple 0s are added at the end of the message until the length of the padded message is the smallest non-negative integer of 448 mod 512, and then a 64-bit bit string is added at the end of the padded message, the bit string being the binary representation of the length of the unpadded message. Finally, the bit length of the padded message is a multiple of 512.

[0052] Next, after padding the message, the padded message is divided into multiple message groups with a group size of 512 bits.

[0053] Then, each message group is expanded; that is, for any given message group, the message group is divided into 16 strings of equal length, namely W0-W0. 15 Then, based on W0-W 15 Generate W 16 -W 67 That is, 52 strings, finally based on W0-W 64 Generate 64 strings, namely W'0–W' 63 .

[0054] Among them, according to W0-W 15 Generate W 16 -W 67 The process can be referenced using the following formula.

[0055]

[0056] In the formula, P1 represents the first permutation function, and the symbol "←" represents leftward assignment.

[0057] According to W0-W 64 Generate W'0–W' 63 The process can be referenced using the following formula.

[0058]

[0059] After obtaining 132 strings, 64 data compression operations are performed based on these 132 strings and 8 registers, i.e., using W0-W 63 and W'0–W' 63 Perform data compression.

[0060] Specifically, taking a single data compression process as an example, let the eight registers be numbered A, B, C...H. First, compressed data V is written to AH. i Then, the intermediate variables SS1, SS2, TT1, and TT2 are calculated using the data in the registers, and the data in each register is updated based on the four intermediate variables. Finally, the data in the eight registers is used as the parameters for the next compression, i.e., V. i+1 =V i .

[0061] The calculation of intermediate variables SS1, SS2, TT1, and TT2, the updating of data in each register, and V i+1 The following formulas can be used to obtain the values.

[0062] ABCDEFGH←V i

[0063] SS1←((A<<12)+E+(T j <<j))<<7

[0064]

[0065] TT1←FF j (A, B, C) + D + SS2 + W j ′

[0066] TT2←GG j (E, F, G) + H + SS1 + W j

[0067] D←C

[0068] C←B<<9

[0069] B←A

[0070] A←TT1

[0071] H←G

[0072] G←F<<19

[0073] F←E

[0074] E←P0(TT2)

[0075] V i+1 ←ABCDEFGH

[0076] In the formula, P0 represents the second permutation function, and T j Let FF represent a constant that varies with the magnitude of j. j and GG j These all represent different Boolean functions in the SM3 algorithm.

[0077] FF j and GG j The following formulas can be used as a reference for calculations.

[0078]

[0079]

[0080] Therefore, after 64 loop operations, the data in the 8 registers represent the hash values ​​corresponding to the messages.

[0081] It should be noted that the above content is only a brief introduction to the existing technology, and the present invention will not introduce more details of the SM3 calculation process and the SM3 implementation circuit.

[0082] Based on this, refer to Figure 1 , Figure 1A circuit structure diagram of an implementation circuit of an SM3 algorithm is shown, the implementation circuit comprising a message compression unit, the message compression unit comprising a first preset number of carry-save adders;

[0083] The first preset number of carry-save adders are used to perform three-parameter addition and three-parameter XOR operations in the SM3 algorithm.

[0084] It can be understood that the carry-save adder in the embodiment of the present application is used to perform operations according to the data sent by the data selector, and the output of the carry-save adder comprises a carry value (Carry) and a sum value (Sum).

[0085] It can also be understood that in the prior art SM3 algorithm implementation circuit, in addition to the eight registers numbered A, B, C, …, H, a plurality of additional registers are also needed to complete the corresponding operations. For example, the calculation process of the intermediate variable TT1 is as follows: the register A, the register B and the register C send data to the FF calculator; the FF calculator calculates the intermediate variable FF according to the data in the register A, the register B and the register C, and sends the intermediate variable FF to the first additional register; the first additional register receives the intermediate variable SS2 and the intermediate variable FF from the FF calculator output, calculates the sum of the intermediate variable SS2 and the intermediate variable FF, and sends the sum to the second additional register; the second additional register receives data from the register D and data in the first additional register, and calculates the sum again, and sends the sum to the third additional register; the third additional register receives W j and data from the second additional register, performs a sum operation to obtain the intermediate variable TT1.

[0086] In the above prior art SM3 algorithm implementation circuit, a plurality of additional registers are needed to complete the multi-parameter addition / XOR operation, resulting in a large circuit area of the SM3 algorithm implementation circuit, which is difficult to meet the current circuit design requirements.

[0087] Therefore, the implementation circuit of the SM3 algorithm provided by the embodiment of the present application makes the multi-parameter operation in the compression operation complete through the carry-save adder capable of performing three-parameter addition and three-parameter XOR operations, so that various multi-logic operations such as the calculation of the intermediate variable FF and the calculation of TT1 can be realized through the carry-save adder, the repeated logic structure in the prior art SM3 algorithm implementation circuit is saved, the number of registers required by the SM3 algorithm implementation circuit is reduced, and the circuit area of the SM3 algorithm implementation circuit is reduced.

[0088] In addition, the number of registers and carry-save adders in the implementation circuit of the SM3 algorithm provided by the embodiment of the present application can be set according to actual conditions,Figure 1 The implementation circuit of the SM3 algorithm provided by the embodiment of the present application is only used for illustration, and does not limit the circuit structure.

[0089] Further, in a feasible manner provided by the embodiment of the present application, the message compression unit further comprises a second preset number of registers.

[0090] The second preset number of registers are used to calculate intermediate variables in cooperation with the first preset number of carry-save adders, and the intermediate variables at least include an intermediate variable SS1, an intermediate variable FF and an intermediate variable TT1.

[0091] Specifically, the second preset number of registers are connected with the first preset number of carry-save adders, so that the second preset number of registers complete the calculation of the intermediate variables such as the intermediate variable SS1, the intermediate variable FF and the intermediate variable TT1 in cooperation with the first preset number of carry-save adders.

[0092] It can be understood that the number of registers and carry-save adders in the message compression unit and the connection relationship between the registers and the carry-save adders can be set according to actual conditions.

[0093] Preferably, in a feasible manner provided by the embodiment of the present application, the first preset number of carry-save adders can be specifically referred to Figure 2 , Figure 2 The circuit structure diagram of the message compression unit provided by the embodiment of the present application is shown, that is, in an embodiment provided by the embodiment of the present application, the second preset number of registers include first to eighth registers, the first preset number of carry-save adders include first to third carry-save adders, and the message compression unit further comprises an exclusive OR operator, an addition operator and first to sixth data selectors.

[0094] The first register and the fifth register are connected with the first carry-save adder, the first to third data selectors are connected with the second carry-save adder, the fourth to sixth data selectors are connected with the third carry-save adder, the first register and the second carry-save adder are connected with the first data selector, the first carry-save adder is connected with the first data selector through the exclusive OR operator, the first register and the second register are connected with the second data selector, the third register and the fourth register are connected with the third data selector, the first carry-save adder is connected with the fourth to sixth data selectors through the exclusive OR operator and the addition operator, one end of the eighth register is connected with the sixth data selector, and the other end is connected with the fourth to sixth data selectors through the addition operator, and the fifth to seventh registers are connected with the fifth data selector.

[0095] The first carry-save adder is configured to calculate an intermediate variable SS1 according to data in the first register and the fifth register;

[0096] The second carry-save adder is configured to calculate an intermediate variable FF and an intermediate variable TT1 according to data input by the first to third data selectors;

[0097] The third carry-save adder is configured to calculate an intermediate variable TT2 according to data input by the fourth to sixth data selectors.

[0098] It should be noted that, Figure 2 The hollow circle in the figure represents an exclusive OR operator, and the hollow trapezoid represents an addition operator.

[0099] It should also be noted that, Figure 2 The fifth to sixth registers can not be connected to the fifth data selector through the register GG in another feasible manner, i.e., the fifth to sixth registers are directly connected to the fifth data selector, and then the intermediate variable GG is calculated by the third carry-save adder.

[0100] In addition, it should be understood that, in order to better illustrate the connection relationship between the various registers, data selectors and carry-save adders in the embodiment of the present application, Figure 2 Some operators / registers are hidden in the figure.

[0101] Specifically, the first carry-save adder is further connected with a register for storing T j , and then the first carry-save adder is further configured to receive an input of the constant T j ; the first register is further connected with the first carry-save adder through a bit shift operator, so that the data in the first register is left shifted by 12 bits before being input into the first carry-save adder; the second data selector is further configured to receive W j '; the third data selector is further configured to receive an input of a register storing 32' b0, and then when the third data selector outputs the received 32' b0, the first data selector outputs the intermediate variable SS1, and the second data selector outputs the data in the first register which has been left shifted by 12 bits, the second carry-save adder outputs the intermediate variable SS2; the fourth data selector is further connected with a register for storing W j , and then the fourth data selector is further configured to receive W jThe XOR unit closest to the first carry-retaining adder is also connected to the adder via a shift operator, so that the data has been shifted left by 7 bits before being sent to the adder, thus completing the calculation of the intermediate variable SS1. The adder is connected to the fourth data selector via a shift operator for shifting the data left by 9 bits, and also to the sixth data selector via a shift operator for shifting the data left by 17 bits. It is understood that the location and function of the hidden arithmetic unit / register can be determined according to existing technology in the art, and therefore will not be elaborated further.

[0102] Based on this, embodiments of the present invention, through a carry-retaining adder and a data selector connected to the carry-retaining adder, enable the carry-retaining adder to perform operations on different intermediate variables according to different inputs to the data selector. Exemplarily, for example, the first carry-retaining adder uses the first register, the fifth register, and the constant T... j The intermediate variable SS1 is calculated. For example, the second carry-holding adder calculates the intermediate variable FF based on the data in the first register output by the first data selector, the data in the second register output by the second data selector, and the data in the third register output by the third data selector. Similarly, the third carry-holding adder calculates the intermediate variable FF based on the data output by the fourth data selector. j The intermediate variable TT2 is calculated by adding the intermediate variable GG output from the fifth data selector and the intermediate variable SS1 output from the sixth data selector with the data in the eighth register (SS1+H).

[0103] Understandably, the output results of the second and third carry-retaining adders can be set according to the actual situation. Figure 2 For example, the second carry-retaining adder will output at least one of the intermediate variables FF, TT1, SS1, and SS2, and the third carry-retaining adder will be used to output at least the intermediate variable TT2. It is also understood that the specific calculation process for each data point can be based on existing technology in the field. Figure 2 The connection relationships between the various components are implemented, so they will not be described in detail here.

[0104] In addition, regarding Figure 2 The seventh data selector in W j and W jWhen j is less than or equal to 15, the second carry-retaining adder outputs the sum (sum) based on the data in the first register, the second register, and the third register, as the intermediate variable FF. When j is not less than or equal to 15, the carry value (Carry) is the intermediate variable FF. Therefore, to ensure that the register used to store the intermediate variable FF, i.e., the register containing the rectangle with the letter "FF", receives the correct intermediate variable FF, the second carry-retaining adder is connected to the register containing the rectangle with the letter "FF" through the seventh data selector. This allows the seventh data selector to output the sum when j is less than or equal to 15 and to output the carry value when j is not less than or equal to 15.

[0105] It is easy to understand that if the second carry-retaining adder can output the sum when j is less than or equal to 15 and output the carry value when j is not less than or equal to 15 during the calculation of the intermediate variable FF, then the output of the second carry-retaining adder can be directly connected to the first data selector.

[0106] Furthermore, to further optimize the implementation circuit of the SM3 algorithm provided in the embodiments of the present invention, in one embodiment of the present invention, the second carry-retaining adder is further used to calculate a first sum based on the data in the fourth register and the intermediate variable FF, and send the first sum to the fourth register so that the data in the four registers is updated;

[0107] The third carry-retaining adder is also used to calculate a second sum based on the data in the eighth register and the intermediate variable GG, and send the second sum to the eighth register to update the data in the eighth register.

[0108] It is understood that the fourth register and the eighth register in the SM3 algorithm implementation circuit provided in this application embodiment need to participate in the calculation of intermediate variable TT1 and intermediate variable TT2, respectively, and both are updated after the calculation is completed.

[0109] However, it should be noted that, compared with the fourth and eighth registers in the SM3 algorithm implementation circuit in the prior art, the fourth and eighth registers in this embodiment of the invention are also used to store the first sum and the second sum, respectively. That is, the fourth and eighth registers are also used to store the process quantities in the calculation process.

[0110] Furthermore, with Figure 2 For example, when the output of the first data selector is the intermediate variable FF, the output of the second data selector is W. j When the output of the third data selector is the data in the fourth register, the second carry-holding adder calculates the intermediate variable FF, the data (D) in the fourth register, and W. jFF+D+W j ), and then sends (FF+D+W j ) to the fourth register to update the data of the fourth register, i.e., sends (FF+D+W j ) to the fourth register through the exclusive-OR operator closest to the third data selector. Further, when the fourth register sends (FF+D+W j ) to the third data selector to input to the second carry-save adder, the output of the first data selector is SS1, and the output of the second data selector is the data in the first register which has been left shifted by 12 bits, the second carry-save adder outputs an intermediate variable TT1.

[0111] Similarly, when the third carry-save adder calculates the sum of an intermediate variable GG, the data (H) in the eighth register, and W j , i.e., (GG+H+W j ), the third carry-save adder sends (GG+H+W j ) to the exclusive-OR operator closest to the seventh data selector, and the exclusive-OR operator sends (GG+H+W j ) to the eighth data selector, and the eighth data selector sends (GG+H+W j ) to the eighth register to update the data of the eighth register, and the eighth register sends the data to the adder operator above the third carry-save adder to calculate (SS1+H), i.e., (SS1+GG+H+W j ), thereby obtaining an intermediate variable TT2.

[0112] It can be understood that the eighth data selector is also used to output the data in the seventh register. Further, when the eighth data selector outputs the data in the seventh register, the eighth register updates the data according to the output of the eighth data selector, i.e., H←G.

[0113] Thus, the embodiment of the present application is based on the carry-save adder, so that the fourth register and the eighth register are multiplexed, thereby further reducing the number of registers in the circuit, avoiding the case that the process variable such as (GG+H+W j ) still needs to be stored through an additional register, and further optimizing the circuit area of the implementation circuit of the SM3 algorithm.

[0114] In addition, in specific applications, the SM3 algorithm implementation circuit of the embodiment of the present application further includes a message expansion unit, the message compression unit is connected with the message expansion unit, and the message expansion unit is used to generate to-be-compressed data, such as W0-W 67 and W'0-W' 63The message compression unit is configured to compress the received data to be compressed, and obtain a hash value corresponding to the data to be compressed.

[0115] In some specific embodiments, reference can be made to Figure 3 , Figure 3 The circuit structure of the message expansion unit is shown, that is, the message expansion unit comprises an XOR operator, a ninth register, and ninth to thirteenth data selectors.

[0116] The message expansion unit is connected with the message compression unit.

[0117] The ninth register is connected with the ninth, tenth, and eleventh data selectors.

[0118] The thirteenth data selector and the tenth data selector are both connected with the ninth data selector.

[0119] The eleventh data selector is connected with the twelfth data selector.

[0120] The tenth data selector, the twelfth data selector, and the thirteenth data selector are all connected with the XOR operator.

[0121] The XOR operator is connected with the ninth register.

[0122] The path of the intermediate variable P1 output by the message expansion unit comprises: the intermediate variable W j-16 The intermediate variable W j-3 The intermediate variable W j-9 The intermediate variable W j-16 , the intermediate variable W j-3 , and the intermediate variable W j-9 are input to the XOR operator through the tenth data selector, left shifted by 15 bits and then input to the XOR operator through the twelfth data selector, and input to the XOR operator through the thirteenth data selector, respectively.

[0123] The message extension unit outputs the intermediate variable W. j The path is as follows: the intermediate variable P1 is input to the XOR operator through the ninth register and the tenth data selector, and the intermediate variable W is stored in the ninth register. j-3 After shifting left by 7 bits, the data is input to the XOR operator through the ninth and thirteenth data selectors, with the intermediate variable W... j-6 The intermediate variable P1 and the intermediate variable W, shifted left by 7 bits, are input to the XOR operator through the twelfth data selector. j-3 and intermediate variable W j-6 The XOR operator yields the corresponding intermediate variable W. j .

[0124] It is understood that the message extension unit in this embodiment of the invention can be used to extend the message based on the received intermediate variables W0 to W0. 15 Calculate intermediate variable W 16 To W 67 .

[0125] In one feasible approach, the message extension unit first completes the intermediate variables W0 to W... 15 The calculation, and the intermediate variables W0 to W 15 Stored in a preset memory. The preset memory then calculates any intermediate variable W with j≥16 according to the message extension unit. j As required, the corresponding intermediate variables are sent to the message extension unit. The message extension unit also sends each W... j The intermediate variable W is stored in a pre-defined memory. 16 To W 67 The calculation.

[0126] It is also understood that the tenth data selector in this embodiment of the invention is also used to receive the intermediate variable W. j-16 The eleventh data selector is also used to receive the intermediate variable W. j-3 The twelfth data selector is also used to receive the intermediate variable W. j-6 The thirteenth data selector is also used to receive the intermediate variable W. j-9 The XOR operator is used to perform the operation on intermediate variable P1 and any intermediate variable W with j≥16 based on the inputs of each data selector. j The calculation is performed and the result is stored in the ninth register, which is used to receive and store the data.

[0127] Based on this, the embodiments of the present invention enable the XOR operator to perform multiple logical operations, such as the operation of intermediate variable P1, simultaneously through multiple data selectors connected to the XOR operator in the message extension unit. This improves the utilization rate of the XOR operator and avoids the need to set multiple operators / registers in the message extension unit, thereby further optimizing the circuit area of ​​the SM3 algorithm implementation circuit provided in the embodiments of the present invention.

[0128] Furthermore, it should be noted that, in order to clearly describe the connection relationships of the various devices in the message expansion unit, [the following information is hidden]. Figure 3 This refers to certain registers / arithmetic units within the system. Specifically, for example, the ninth register is connected to the ninth data selector via two bit shift operators, ensuring that data is shifted left by 7 bits or 23 bits before reaching the ninth data selector; similarly, the eleventh data selector is connected to the twelfth data selector via a bit shift operator, ensuring that data is shifted left by 15 bits before reaching the twelfth data selector. It is understandable that... Figure 3 The hidden registers / arithmetic units can be determined according to the technology in this field, so they will not be described in detail here.

[0129] Optionally, to optimize the circuit area of ​​the SM3 algorithm implementation circuit, in one embodiment of the present invention, the circuit further includes a data padding unit, and the message compression unit and the message expansion unit are both connected to the data padding unit;

[0130] The message expansion unit is used to send a second preset number of expanded messages to the message compression unit after expanding the message to obtain a first preset number of expanded messages, and to send a third preset number of expanded messages to the data filling unit, wherein the second preset number and the third preset number are both less than the first preset number;

[0131] The data filling unit is used to send the third preset number of extended messages to the message compression unit after the message compression unit completes the message compression of the second preset number of extended messages.

[0132] Specifically, in this embodiment of the invention, the message extension unit obtains the message group and generates the extended message corresponding to the message group, namely 68 W. j And 64 W j Then, a portion of the message is input to the message compression unit for message compression, and the other portion is input to the data filling unit for storage. Based on the configuration of the data filling unit, no additional registers are needed in the message compression unit to store all the extended messages.

[0133] In one feasible approach, the second preset number of extended messages includes multiple Ws. j and multiple W jthe value range of j of the third preset number of extension messages is [0, 15]; the third preset number of extension messages also includes a plurality of W j and a plurality of W j , but the value range of j of the third preset number of extension messages is [16, 64].

[0134] In another possible way, to further optimize the calculation efficiency of the message compression unit, the data padding unit sends 16 extension messages connected in sequence to the message compression unit after the message compression unit completes the compression of the second preset number of extension messages. For example, when the message compression unit completes the compression of the 0th to 15th W j and W j , the data padding unit sends the 16th to 31st W j and W j to the message compression unit, so that the message compression unit performs the next round of parallel operation.

[0135] Optionally, the data padding unit includes a static random access memory.

[0136] Corresponding to the implementation circuit of the SM3 algorithm provided in the embodiments of the present application, the embodiments of the present application also provide an implementation method of the SM3 algorithm, which can be specifically referred to Figure 4 , Figure 4 The flowchart of the implementation method of the SM3 algorithm provided in the embodiments of the present application is shown, and the implementation method of the SM3 algorithm provided in the embodiments of the present application is applied to the implementation circuit of the SM3 algorithm shown in Figure 1 , which includes a message compression unit, and the message compression unit includes a first preset number of carry-save adders, and the method includes:

[0137] S210, performing three-parameter addition operation and three-parameter XOR operation in the SM3 algorithm by using the first preset number of carry-save adders.

[0138] Optionally, in a possible way provided in the embodiments of the present application, the message compression unit further includes a second preset number of registers, and the method further includes:

[0139] controlling the second preset number of registers to cooperate with the first preset number of carry-save adders to calculate intermediate variables, wherein the intermediate variables at least include an intermediate variable SS1, an intermediate variable FF, and an intermediate variable TT1.

[0140] Further, in an implementation provided by the embodiment of the present application, the second preset number of registers includes first to eighth registers, the first preset number of carry-save adders includes first to third carry-save adders, and the message compression unit further includes first to sixth data selectors;

[0141] The control of the second preset number of registers cooperates with the first preset number of carry-save adders to calculate intermediate variables, wherein the intermediate variables at least include an intermediate variable SS1, an intermediate variable FF, and an intermediate variable TT1, and include:

[0142] The first carry-save adder calculates the intermediate variable SS1 according to data in the first register and the fifth register;

[0143] The second carry-save adder calculates the intermediate variable FF and the intermediate variable TT1 according to data input by the first to third data selectors;

[0144] The third carry-save adder calculates the intermediate variable TT2 according to data input by the fourth to sixth data selectors.

[0145] Further, in an implementation provided by the embodiment of the present application, the method further includes:

[0146] The second carry-save adder calculates a first sum value based on data in the fourth register and the intermediate variable FF, and sends the first sum value to the fourth register to update the data in the fourth register;

[0147] The third carry-save adder calculates a second sum value based on data in the eighth register and the intermediate variable GG, and sends the second sum value to the eighth register to update the data in the eighth register.

[0148] Optionally, in an implementation provided by the embodiment of the present application, the implementation circuit of the SM3 algorithm further includes a message expansion unit, and the message expansion unit includes an exclusive OR operator, a ninth register, and ninth to thirteenth data selectors;

[0149] The path of the intermediate variable P1 output by the message expansion unit includes: the intermediate variable W j-16 The intermediate variable W j-3 The intermediate variable W j-9 The intermediate variable W j-16 , the intermediate variable W j-3and the intermediate variable W j-9 The XOR operator obtains the corresponding intermediate XOR value. The intermediate XOR value is input to the XOR operator through the ninth register and the tenth data selector. It is then input to the XOR operator through the ninth register, shifted left by 23 bits, through the ninth data selector and the thirteenth data selector, and finally input to the XOR operator through the ninth register and the eleventh data selector, shifted left by 15 bits, and then input to the XOR operator through the twelfth data selector. The intermediate XOR value, the intermediate XOR value shifted left by 23 bits, and the intermediate XOR value shifted left by 15 bits are then processed by the XOR operator to obtain the intermediate variable P1.

[0150] The message extension unit outputs the intermediate variable W. j The path is as follows: the intermediate variable P1 is input to the XOR operator through the ninth register and the tenth data selector, and the intermediate variable W is stored in the ninth register. j-3 After shifting left by 7 bits, the data is input to the XOR operator through the ninth and thirteenth data selectors, with the intermediate variable W... j-6 The intermediate variable P1 and the intermediate variable W, shifted left by 7 bits, are input to the XOR operator through the twelfth data selector. j-3 and intermediate variable W j-6 The XOR operator yields the corresponding intermediate variable W. j .

[0151] It is understood that the implementation method of the SM3 algorithm disclosed in the embodiments of the present invention is used to... Figure 1 The circuit shown implements the SM3 algorithm and performs the following: Figure 4 The process steps shown, the implementation schemes involved in the SM3 algorithm implementation circuit, and the beneficial effects are also applicable to the implementation method of the SM3 algorithm, and will not be repeated here.

[0152] This application also discloses an electronic device, which includes, as described above... Figure 1 The corresponding circuit embodiment is the implementation circuit of the SM3 algorithm.

[0153] In several embodiments provided in the present application, it should be understood that the disclosed apparatus and method can also be implemented by other means. The apparatus embodiments described above are only illustrative, for example, the flowcharts and structural diagrams in the drawings show the possible implementation architecture, function and operation of the apparatus, method and computer program product according to the embodiments of the present application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment or a part of code, which contains one or more executable instructions for implementing the specified logic function. It should also be noted that in alternative implementation, the functions noted in the blocks can also occur in different order from that noted in the drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the structural diagram and / or flowchart, and the combination of blocks in the structural diagram and / or flowchart, can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0154] In addition, each functional module or unit in the embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0155] If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part of the prior art that contributes to the technical solutions or part of the technical solutions can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions for causing an electronic device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0156] The above description is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A circuit for implementing the SM3 algorithm, characterized in that, The implementation circuit includes a message compression unit, which includes a first preset number of carry-retaining adders. The first preset number of carry-retaining adders are used to perform the three-parameter addition and three-parameter XOR operations in the SM3 algorithm; The message compression unit further includes a second preset number of registers; The second preset number of registers are used in conjunction with the first preset number of carry-retaining adders to calculate intermediate variables, the intermediate variables including at least intermediate variable SS1, intermediate variable FF and intermediate variable TT1; The second preset number of registers includes the first to eighth registers, the first preset number of carry-holding adders includes the first to third carry-holding adders, and the message compression unit further includes an XOR operator, an adder, and the first to sixth data selectors; The first register and the fifth register are both connected to the first carry-holding adder; the first to third data selectors are all connected to the second carry-holding adder; the fourth to sixth data selectors are all connected to the third carry-holding adder; the first register and the second register are both connected to the second data selector; the third register and the fourth register are both connected to the third data selector; one end of the eighth register is connected to the sixth data selector; and the fifth to seventh registers are all connected to the fifth data selector. The first carry-retaining adder is used to calculate the intermediate variable SS1 based on the data in the first register and the fifth register; The second carry-retaining adder is used to calculate intermediate variables FF and TT1 based on the data input from the first to third data selectors; The third carry-retaining adder is used to calculate the intermediate variable TT2 based on the data input from the fourth to sixth data selectors.

2. The implementation circuit of the SM3 algorithm according to claim 1, characterized in that, The first register and the second carry-holding adder are both connected to the first data selector. The first carry-holding adder is connected to the first data selector through the XOR operator. The first carry-holding adder is connected to the fourth to sixth data selectors through the XOR operator and the adder. The other end of the eighth register is connected to the fourth to sixth data selectors through the adder.

3. The implementation circuit of the SM3 algorithm according to claim 2, characterized in that, The second carry-retaining adder is also used to calculate a first sum based on the data in the fourth register and the intermediate variable FF, and send the first sum to the fourth register so that the data in the fourth register is updated; The third carry-retaining adder is also used to calculate a second sum based on the data in the eighth register and the intermediate variable GG, and send the second sum to the eighth register to update the data in the eighth register.

4. The implementation circuit of the SM3 algorithm according to claim 1, characterized in that, The implementation circuit of the SM3 algorithm also includes a message extension unit, which includes an XOR operator, a ninth register, and ninth to thirteenth data selectors. The message expansion unit is connected to the message compression unit; The ninth register is connected to the ninth data selector, the tenth data selector, and the eleventh data selector. Both the thirteenth and tenth data selectors are connected to the ninth data selector. The eleventh data selector is connected to the twelfth data selector; The tenth data selector, the twelfth data selector, and the thirteenth data selector are all connected to the XOR operator; The XOR operator is connected to the ninth register; The message extension unit outputs intermediate variables. P1 The path includes: intermediate variables W j-16 The intermediate variable is input to the XOR operator via the tenth data selector. W j-3 The data is processed by the tenth data selector, shifted left by 15 bits, and then input to the XOR operator via the twelfth data selector. The intermediate variable... W j-9 The intermediate variable is input to the XOR operator via the thirteenth data selector. W j-16 An intermediate variable shifted 15 bits to the left W j-3 and the intermediate variables W j-9 The XOR operator obtains the corresponding intermediate XOR value. This intermediate XOR value is input to the XOR operator through the ninth register and the tenth data selector. It is then input to the XOR operator through the ninth register (shifted left by 23 bits), the ninth data selector, the thirteenth data selector, the eleventh data selector, and the eleventh data selector (shifted left by 15 bits), and the twelfth data selector. The intermediate XOR value, the intermediate XOR value shifted left by 23 bits, and the intermediate XOR value shifted left by 15 bits are then processed by the XOR operator to obtain an intermediate variable. P1 ; Message extension unit outputs intermediate variables W j The path is: the intermediate variable P1 The intermediate variable is input to the XOR operator through the ninth register and the tenth data selector, and stored in the ninth register. W j-3 After shifting left by 7 bits, the data is input to the XOR operator through the ninth and thirteenth data selectors, and the intermediate variable... W j-6 The intermediate variable is input to the XOR operator via the twelfth data selector. P1 , left-shifted 7 bits intermediate variable W j-3 and intermediate variables W j-6 The XOR operator obtains the corresponding intermediate variable. W j .

5. A method for implementing the SM3 algorithm, characterized in that, An implementation circuit for the SM3 algorithm as described in claim 1, the implementation circuit including a message compression unit, the message compression unit including a first preset number of carry-retaining adders, the method including; The three-parameter addition and three-parameter XOR operations in the SM3 algorithm are performed using the first preset number of carry-retaining adders.

6. The implementation method of the SM3 algorithm according to claim 5, characterized in that, The message compression unit further includes a second preset number of registers, and the method further includes: The second preset number of registers are controlled in conjunction with the first preset number of carry-retaining adders to calculate intermediate variables, wherein the intermediate variables include at least intermediate variable SS1, intermediate variable FF and intermediate variable TT1.

7. The implementation method of the SM3 algorithm according to claim 6, characterized in that, The second preset number of registers includes the first to eighth registers, the first preset number of carry-holding adders includes the first to third carry-holding adders, and the message compression unit further includes the first to sixth data selectors; The control of the second preset number of registers in conjunction with the first preset number of carry-retaining adders to calculate intermediate variables, wherein the intermediate variables include at least intermediate variable SS1, intermediate variable FF, and intermediate variable TT1, including: The first carry-retaining adder calculates the intermediate variable SS1 based on the data in the first and fifth registers; The second carry-retaining adder calculates intermediate variables FF and TT1 based on the data input from the first to third data selectors. The third carry-retaining adder calculates the intermediate variable TT2 based on the data input from the fourth to sixth data selectors.

8. The implementation method of the SM3 algorithm according to claim 7, characterized in that, The method further includes: The second carry-retaining adder calculates the first sum based on the data in the fourth register and the intermediate variable FF, and sends the first sum to the fourth register to update the data in the fourth register; The third carry-retaining adder calculates the second sum based on the data in the eighth register and the intermediate variable GG, and sends the second sum to the eighth register to update the data in the eighth register.

9. An electronic device, characterized in that, It includes the implementation circuit of the SM3 algorithm as described in any one of claims 1 to 4.

Images