A method and apparatus for determining a truth table of a logic circuit, and an electronic device

Abstract

The embodiment of the present application discloses a logic circuit truth table determination method, device and electronic equipment, relates to the technical field of electronic circuits, and can quickly extract the truth table of a logic circuit. The method comprises the following steps: based on a first group of input truth values in an input truth value list, input ports of a logic circuit described by a netlist are valued; the input truth value list is generated in advance according to the input ports of the logic circuit described by the netlist; based on the valuation of the input ports, the level value of the output ports of the logic circuit described by the netlist is calculated; it is judged whether the output ports have level values calculated; if the output ports have level values calculated, the calculated level value of the output ports is taken as the output truth value corresponding to the first group of input truth values. The present application is suitable for extracting the truth table of a logic circuit.

Description

Technical Field

[0001] This invention relates to the field of electronic circuit technology, and in particular to a method, apparatus, and electronic device for determining the truth table of a logic circuit. Background Technology

[0002] Electronic circuits are divided into two main categories: one is circuits that transmit and process analog signals, called analog circuits; the other is circuits that transmit and process digital signals, called logic circuits.

[0003] In electronic design, it is often necessary to extract the truth table of logic circuits. Current technology obtains the truth table by creating stimulus files using simulation tools. However, this method cannot automatically analyze input / output ports, and simulation tools generally have long runtimes and complex extraction methods, making it impossible to quickly extract the truth table of logic circuits. The higher the complexity of the logic circuit, the more significant this technical problem becomes. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a method, apparatus, electronic device, and storage medium for determining the truth table of a logic circuit, which can quickly extract the truth table of a logic circuit.

[0005] In a first aspect, embodiments of the present invention provide a method for determining a truth table of a logic circuit, the method comprising: assigning values ​​to input ports of a logic circuit described by a netlist based on a first set of input truth values ​​in an input truth value list; the input truth value list being pre-generated based on the input ports of the logic circuit described by the netlist; calculating the level value of the output port of the logic circuit described by the netlist based on the assigned values ​​to the input ports; determining whether a level value has been calculated for the output port; and if a level value has been calculated for the output port, using the calculated level value of the output port as the output truth value corresponding to the first set of input truth values.

[0006] Optionally, before assigning values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list, the method further includes: determining the input ports and output ports of the logic circuit, as well as the ground connection terminals and operating voltage connection terminals of the transistors in the logic circuit, based on the netlist; wherein the transistors are field-effect transistors or bipolar junction transistors; and assigning a low level to the ground connection terminal of the transistor and a high level to the operating voltage connection terminal.

[0007] Optionally, calculating the level value of the output port of the logic circuit described by the netlist based on the assignment of the input port includes: determining whether the first transistor is in a conducting state based on the assignment of the input port; if the first transistor is in a conducting state, and the source of the first transistor has been assigned a value but the drain has not, then assigning the level value of the source of the first transistor to the drain of the first transistor; calculating the level value of the output port of the logic circuit based on the level value of the drain of the first transistor; or, if the first transistor is in a conducting state, and the source of the first transistor has not been assigned a value but the drain has been assigned a value, then assigning the level value of the drain of the first transistor to the source of the first transistor; calculating the level value of the output port of the logic circuit based on the level value of the source of the first transistor.

[0008] Optionally, after determining whether a voltage level value has been calculated for the output port, the method further includes: if no voltage level value has been calculated for the output port, then based on the value assigned to the input port, determining whether the second transistor is in a conducting state; if the second transistor is in a conducting state, and the source of the second transistor has been assigned a value but the drain has not, then assigning the voltage level value of the source of the second transistor to the drain of the second transistor; calculating the voltage level value of the output port based on the voltage level value of the drain of the second transistor; or, if the second transistor is in a conducting state, and the source of the second transistor has not been assigned a value but the drain has been assigned a value, then assigning the voltage level value of the drain of the second transistor to the source of the second transistor; calculating the voltage level value of the output port based on the voltage level value of the source of the second transistor.

[0009] Optionally, determining whether the first transistor is in a conducting state based on the value assigned to the input port includes: determining the type of the first transistor based on the netlist; determining the gate level value of the first transistor based on the value assigned to the input port; and determining whether the first transistor is in a conducting state based on the type of the first transistor and the gate level value.

[0010] Optionally, the gate voltage level of the first transistor is the same as the voltage level level of the first input port of the logic circuit; determining whether the first transistor is in a conducting state based on the type of the first transistor and the gate voltage level includes: determining whether the first transistor is in a conducting state based on the type of the first transistor and the voltage level level of the first input port of the logic circuit.

[0011] Optionally, determining whether the second transistor is in a conducting state based on the value assigned to the input port includes: determining the type of the second transistor based on the netlist; determining the gate level value of the second transistor based on the value assigned to the input port; and determining whether the second transistor is in a conducting state based on the type of the second transistor and the gate level value.

[0012] Optionally, the gate voltage level of the second transistor is the same as the voltage level level of the second input port of the logic circuit; determining whether the second transistor is in a conducting state based on the type of the second transistor and the gate voltage level includes: determining whether the second transistor is in a conducting state based on the type of the second transistor and the voltage level level of the second input port of the logic circuit.

[0013] Optionally, after determining the output truth value corresponding to the first set of input truth values, the method further includes: in the netlist, initializing the ungrounded and unconnected operating voltage terminals of each transistor to an unassigned state; assigning values ​​to the input ports based on the second set of input truth values ​​in the input truth value list; calculating the level value of the output port based on the assigned values ​​of the input ports; determining whether a level value has been calculated for the output port; if a level value has been calculated for the output port, then using the calculated level value of the output port as the output truth value corresponding to the second set of input truth values.

[0014] Optionally, the method further includes: if no level value is calculated for the output port after an assignment operation has been performed on all transistors described in the netlist, then determining each pole of each transistor in the netlist that has changed from an unassigned state to an assigned state; and calculating the level value of the output port again based on the level values ​​of each pole of each transistor that has changed from an unassigned state to an assigned state, and the assignment to the input port.

[0015] Optionally, the logic circuit described by the netlist includes a first logic circuit and a second logic circuit, and the output terminal of the first logic circuit is connected to the input terminal of the second logic circuit; the truth table of the first logic circuit is predetermined; assigning values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list includes: assigning values ​​to the input ports of the first logic circuit based on the first set of input truth values ​​in the input truth value list; correspondingly, calculating the level value of the output port of the logic circuit described by the netlist based on the assigned values ​​to the input ports includes: obtaining the level value of the output port of the first logic circuit based on the assigned values ​​to the input ports of the first logic circuit and the predetermined truth table of the first logic circuit; assigning values ​​to the input ports of the second logic circuit based on the level values ​​of the output ports of the first logic circuit; and calculating the level value of the output port of the logic circuit based on the assigned values ​​to the input ports of the second logic circuit.

[0016] Secondly, embodiments of the present invention provide a device for determining a truth table of a logic circuit, comprising: a first assignment module, configured to assign values ​​to the input ports of a logic circuit described by a netlist based on a first set of input truth values ​​in an input truth value list; the input truth value list is pre-generated based on the input ports of the logic circuit described by the netlist; a first calculation module, configured to calculate the level value of the output port of the logic circuit described by the netlist based on the assigned values ​​to the input ports; a first judgment module, configured to determine whether a level value has been calculated for the output port; and a first output truth value acquisition module, configured to, if a level value has been calculated for the output port, use the calculated level value of the output port as the output truth value corresponding to the first set of input truth values.

[0017] Optionally, the device further includes: a first determining module, configured to determine, based on the netlist, the input ports and output ports of the logic circuit, and the ground connection terminal and operating voltage connection terminal of the transistor in the logic circuit, before assigning values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list; wherein the transistor is a field-effect transistor or a bipolar junction transistor; and a second assigning module, configured to assign a low level to the ground connection terminal of the transistor and a high level to the operating voltage connection terminal.

[0018] Optionally, the first calculation module includes: a first conduction state determination unit, configured to determine whether the first transistor is in a conduction state based on the value assigned to the input port; a first assignment unit, configured to, if the first transistor is in a conduction state and the source of the first transistor has been assigned a value but the drain has not been assigned a value, assign the level value of the source of the first transistor to the drain of the first transistor; and calculate the level value of the output port of the logic circuit based on the level value of the drain of the first transistor; or, a second assignment unit, configured to, if the first transistor is in a conduction state and the source of the first transistor has not been assigned a value but the drain has been assigned a value, assign the level value of the drain of the first transistor to the source of the first transistor; and calculate the level value of the output port of the logic circuit based on the level value of the source of the first transistor.

[0019] Optionally, the first calculation module further includes: a second conduction state judgment unit, used to determine whether the second transistor is in a conduction state based on the assignment of the input port if no level value is calculated after determining whether the output port has a calculated level value; a third assignment unit, used to assign the level value of the source of the second transistor to the drain of the second transistor if the second transistor is in a conduction state and the source of the second transistor has been assigned a value but the drain has not been assigned a value; and calculate the level value of the output port based on the level value of the drain of the second transistor; or, a fourth assignment unit, used to assign the level value of the drain of the second transistor to the source of the second transistor if the second transistor is in a conduction state and the source of the second transistor has not been assigned a value but the drain has been assigned a value; and calculate the level value of the output port based on the level value of the source of the second transistor.

[0020] Optionally, the first conduction state determination unit includes: a first type determination subunit, used to determine the type of the first transistor based on the netlist; a first gate level determination subunit, used to determine the gate level value of the first transistor based on the value assigned to the input port; and a first conduction state determination subunit, used to determine whether the first transistor is in a conduction state based on the type of the first transistor and the gate level value.

[0021] Optionally, the gate voltage level of the first transistor is the same as the voltage level level of the first input port of the logic circuit; the first conduction state determination subunit is specifically used to: determine whether the first transistor is in a conduction state based on the type of the first transistor and the voltage level level of the first input port of the logic circuit.

[0022] Optionally, the second conduction state determination unit includes: a second type determination subunit, used to determine the type of the second transistor based on the netlist; a second gate level determination subunit, used to determine the gate level value of the second transistor based on the value assigned to the input port; and a second conduction state determination subunit, used to determine whether the second transistor is in a conduction state based on the type of the second transistor and the gate level value.

[0023] Optionally, the gate voltage level of the second transistor is the same as the voltage level level of the second input port of the logic circuit; the second conduction state determination subunit is specifically used to: determine whether the second transistor is in a conduction state based on the type of the second transistor and the voltage level level of the second input port of the logic circuit.

[0024] Optionally, the device further includes: an initialization module, configured to, after determining the output truth value corresponding to the first set of input truth values, initialize the ungrounded and unconnected operating voltage terminals of each transistor to an unassigned state in the netlist; a third assignment module, configured to assign values ​​to the input ports based on the second set of input truth values ​​in the input truth value list; a second calculation module, configured to calculate the level value of the output port based on the assignment of values ​​to the input ports; a second judgment module, configured to determine whether a level value has been calculated for the output port; and a second output truth value acquisition module, configured to, if a level value has been calculated for the output port, use the calculated level value of the output port as the output truth value corresponding to the second set of input truth values.

[0025] Optionally, the apparatus further includes: a second determining module, configured to determine each pole of each transistor in the netlist that has transitioned from an unassigned state to an assigned state if no level value is calculated for the output port after an assignment operation has been performed on all transistors described in the netlist; and a recalculation module, configured to recalculate the level value of the output port based on the level values ​​of each pole of each transistor that has transitioned from an unassigned state to an assigned state, and the assignment to the input port.

[0026] Optionally, the logic circuit described by the netlist includes a first logic circuit and a second logic circuit, and the output terminal of the first logic circuit is connected to the input terminal of the second logic circuit; the truth table of the first logic circuit is predetermined; the first assignment module is specifically used to: assign values ​​to the input ports of the first logic circuit based on the first set of input truth values ​​in the input truth table; correspondingly, the first calculation module is specifically used to: obtain the level value of the output port of the first logic circuit based on the assigned values ​​to the input ports of the first logic circuit and the predetermined truth table of the first logic circuit; assign values ​​to the input ports of the second logic circuit based on the level values ​​of the output ports of the first logic circuit; and calculate the level value of the output port of the logic circuit based on the assigned values ​​to the input ports of the second logic circuit.

[0027] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising: a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within a space enclosed by a housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing any of the logic circuit truth table determination methods provided in the embodiments of the present invention.

[0028] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs that can be executed by one or more processors to implement any of the logic circuit truth table determination methods provided in the embodiments of the present invention.

[0029] The present invention provides a method, apparatus, electronic device, and storage medium for determining the truth table of a logic circuit. Based on a first set of input truth values ​​in an input truth value list, values ​​are assigned to the input ports of the logic circuit described by the netlist. The input truth value list is pre-generated based on the input ports of the logic circuit described by the netlist. Based on the assigned values ​​to the input ports, the level value of the output port of the logic circuit described by the netlist is calculated. It is determined whether a level value is calculated for the output port. If a level value is calculated for the output port, the calculated level value of the output port is used as the output truth value corresponding to the first set of input truth values. In this way, the level value of the output port of the logic circuit can be directly calculated based on the input truth values, thereby obtaining the output truth value corresponding to the input truth values. The extraction method is simple and can quickly extract the truth table of the logic circuit. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A flowchart illustrating a method for determining the truth table of a logic circuit, provided as an embodiment of the present invention;

[0032] Figure 2 A schematic diagram of a logic circuit structure provided for an embodiment of the present invention;

[0033] Figure 3 A truth representation of a logic circuit provided for embodiments of the present invention;

[0034] Figure 4 Another schematic diagram of a logic circuit structure provided for an embodiment of the present invention;

[0035] Figure 5 A schematic diagram of a device for determining the truth table of a logic circuit, provided for an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of the structure of an electronic device provided as an embodiment of the present invention. Detailed Implementation

[0037] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0038] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0039] In a first aspect, embodiments of the present invention provide a method for determining the truth table of a logic circuit, which can quickly extract the truth table of a logic circuit.

[0040] like Figure 1 As shown, the method for determining the truth table of a logic circuit provided in the embodiments of the present invention may include:

[0041] S11, based on the first set of input truth values ​​in the input truth value list, assign values ​​to the input ports of the logic circuit described by the netlist;

[0042] The input truth list is pre-generated based on the input ports of the logic circuit described by the netlist.

[0043] In this step, "logic circuit" refers to combinational logic circuits. Each logic circuit has a corresponding simulation program with integrated circuit emulation (SPICE) netlist. In electronic design automation, a netlist (or connection list) is a description method that uses basic logic gates to describe the connections of a logic circuit. Because the array of logic gates has an appearance similar to a connection list, it is called a "netlist."

[0044] For example, Figure 2 The logic circuit X shown has two input ports, namely input port A and input port B.

[0045] The SPICE netlist information corresponding to logic circuit X (hereinafter referred to as netlist) is as follows:

[0046] “SUBCKT NAND ABQ VDD VSS

[0047] M01 QA VDD VDD pmos

[0048] M02 QA net01 VSS nmos

[0049] M03 net01 B VSS VSS nmos

[0050] M04 QB VDD VDD pmos

[0051] .ENDS”

[0052] The first row of the netlist includes the input port A, output port B, operating voltage VDD, and ground VSS of logic circuit X. From the second to fifth rows, it can be seen that logic circuit X includes four field-effect transistors: M01, M02, M03, and M04.

[0053] Taking the information of field-effect transistor M01 in the first line as an example, the first digit from the left after M01 represents the drain (D), the second digit represents the gate (G), the third digit represents the source (S), the fourth digit represents the substrate, and the fifth digit represents the type of M01. If Q is written as the first digit from the left after M01, it indicates that the drain of M01 is connected to the output terminal Q. Similarly, if A is written as the second digit, VDD as the third digit, VDD as the fourth digit, and pmos as the fifth digit, it indicates that the gate of M01 is connected to the operating voltage VDD, the substrate of M01 is connected to the operating voltage VDD, and the substrate of M01 is connected to the operating voltage VDD, respectively.

[0054] The above example uses MOSFET M01 as an illustration to demonstrate the netlist corresponding to logic circuit X. For MOSFETs M02, M03, and M04, their types, and the connections between their source (S), drain (D), gate (G), substrate, and other ports can be read in the same way; these details will not be elaborated here. Therefore, the netlist corresponding to logic circuit X includes the type information of all MOSFETs in logic circuit X, the connections between each MOSFET, and the connections between each MOSFET and the operating voltage VDD and ground VSS.

[0055] For logic circuit X, it includes two input ports, input port A and input port B. In the netlist, A and B can be considered as two variables representing the two input ports. Before obtaining the truth table of logic circuit X, a list of input truth values ​​corresponding to logic circuit X can be pre-established, which includes four sets of input truth values: the first set of input truth values ​​is A=0, B=0; the second set of input truth values ​​is A=0, B=1; the third set of input truth values ​​is A=1, B=0; and the fourth set of input truth values ​​is A=1, B=1, representing all the level input conditions of the input ports, such as... Figure 3 As shown in the first and second columns. Here, 0 represents a logic low level, and 1 represents a logic high level.

[0056] When obtaining the truth table of logic circuit X, the output level values ​​under the four conditions mentioned above can be calculated respectively. Specifically, the output level values ​​corresponding to the first set of input truth values ​​A=0 and B=0 can be calculated first, according to the order. Before performing the calculation, the first set of input truth values ​​A=0 and B=0 can be obtained from the pre-established input truth value list and assigned to the corresponding input ports A and B, so that the level value of the output port Q corresponding to this input condition can be calculated in the subsequent process.

[0057] S12, based on the values ​​assigned to the input ports, calculate the level value of the output port of the logic circuit described by the netlist.

[0058] In this embodiment of the invention, after assigning values ​​to the input ports A and B of the logic circuit X, the level value of the output port Q of the logic circuit X can be directly calculated based on the above assignment. The extraction method is simple and can quickly extract the truth table of the logic circuit. By using different input values ​​from the truth table, the level value of the output port Q corresponding to the input value can be calculated.

[0059] S13, determine whether the output port has a voltage level and calculate it.

[0060] The embodiments of the present invention may have one or more output ports. This embodiment only illustrates the principle of the invention with a single output port. There is no substantial difference in implementation principle between this and the case where there are multiple output ports.

[0061] When there are multiple output ports, step S13 means that the level values ​​of all output ports of the logic circuit are calculated, rather than that the level values ​​of some of the output ports are calculated.

[0062] If the output port level value can be calculated through step S13, then step S14 is executed.

[0063] S14, the calculated level value of the output port is used as the output true value corresponding to the first set of input true values.

[0064] Based on the example above, if the input values ​​are A=0 and B=0, and the corresponding output port Q is calculated to be 1, then Q=1 can be taken as the output true value corresponding to the input true value "A=0, B=0".

[0065] Furthermore, it is understandable that based on the four input truth values ​​mentioned above, the corresponding output port Q level can be calculated, and a truth table corresponding to logic circuit X can be generated subsequently.

[0066] The method for determining the truth table of a logic circuit provided in the embodiments of the present invention can assign values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list. The input truth value list is pre-generated based on the input ports of the logic circuit described by the netlist. Based on the assigned values ​​to the input ports, the level value of the output port of the logic circuit described by the netlist is calculated. It is determined whether a level value is calculated for the output port. If a level value is calculated for the output port, the calculated level value of the output port is used as the output truth value corresponding to the first set of input truth values. In this way, the level value of the output port of the logic circuit can be directly calculated based on the input truth values ​​of the logic circuit, thereby obtaining the output truth value corresponding to the input truth values. The extraction method is simple and can quickly extract the truth table of the logic circuit.

[0067] Optionally, in one embodiment of the present invention, before assigning values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list in step S11, the method for determining the truth table of the logic circuit provided in this embodiment of the present invention may further include: determining the input ports and output ports of the logic circuit, as well as the ground connection terminal and the operating voltage connection terminal of the transistor in the logic circuit, based on the netlist; wherein the transistor is a field-effect transistor or a bipolar transistor; and assigning a low level to the ground connection terminal of the transistor and a high level to the operating voltage connection terminal.

[0068] Any logic circuit requires a working voltage and a ground connection to provide power for its operation. Specifically, the output port Q of logic circuit X depends not only on the true values ​​of the input ports A and B, but also on the connection between the field-effect transistors in logic circuit X and the working voltage VDD and ground VSS.

[0069] Therefore, before assigning values ​​to the ports of a logic circuit, in addition to determining which ports the logic circuit includes from the netlist, it is also necessary to determine from the netlist which ports of the field-effect transistors in the logic circuit are connected to the operating voltage VDD and ground VSS. Specifically, taking logic circuit X as an example, from the netlist, it can be determined that the source (S) terminals of M01 and M04 are connected to the operating voltage VDD, so the source terminals of M01 and M04 can be assigned a high level (1). Similarly, from the netlist, it can be determined that the source terminal of M03 is connected to ground VSS, so the source terminal of M03 can be assigned a low level (0).

[0070] After assigning values ​​to all ground and operating voltage connections in logic circuit X, the level value of output port Q can be calculated by combining the aforementioned assignments to input ports A and B.

[0071] It is understood that the transistor used in the above logic circuit X is an enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET), which is only used to illustrate the principle of the embodiment of the present invention. Other types of field-effect transistors or bipolar transistors can also be used in the logic circuit, which does not affect the substantive content of the embodiment of the present invention and all fall within the protection scope of the embodiment of the present invention.

[0072] Optionally, in one embodiment of the present invention, step S12, calculating the level value of the output port of the logic circuit described by the netlist based on the assignment of the input port, may include: determining whether the first transistor is in a conducting state based on the assignment of the input port; if the first transistor is in a conducting state, and the source of the first transistor has been assigned a value but the drain has not been assigned a value, then assigning the level value of the source of the first transistor to the drain of the first transistor; calculating the level value of the output port of the logic circuit based on the level value of the drain of the first transistor; or, if the first transistor is in a conducting state, and the source of the first transistor has not been assigned a value but the drain has been assigned a value, then assigning the level value of the drain of the first transistor to the source of the first transistor; calculating the level value of the output port of the logic circuit based on the level value of the source of the first transistor.

[0073] In this embodiment of the invention, the transistor is used as a switching device, which can be a field-effect transistor (FET) or a bipolar junction transistor (BJT). To calculate the level value of the output port Q of the logic circuit, a basic principle is used: when a FET is in the ON state, its source (S) level is equal to its drain (D) level; when a BJT is in the ON state, its collector level is equal to its emitter level.

[0074] The following example uses an enhancement-mode MOSFET (hereinafter referred to as MOSFET) as an example to illustrate the implementation principle of the present invention. When the transistor is of other types, the logic circuit can be implemented in the same or similar way. When implementing the present invention, the method used is the same or similar to the example below. Therefore, all transistors that can be used as switching transistors are within the scope of protection of the present invention.

[0075] To calculate the voltage level of the output port of a logic circuit, since the output port is connected to a specific terminal of a MOSFET in the logic circuit (for example, the output port Q of logic circuit X is connected to the drain (D) terminal of MOSFETs M01 and M04), the voltage level of the output port can be calculated by calculating the voltage level of each terminal (D or S) of each MOSFET.

[0076] When calculating the voltage levels of each terminal of each MOSFET in logic circuit X, the conduction state of each MOSFET can be determined sequentially (the order can be arbitrary). When the first MOSFET is in the conduction state, its source (S) and drain (D) voltage levels are equal. Therefore, if the source of the first MOSFET is in the assigned state and the drain is in the unassigned state, based on the characteristic that the source and drain voltage levels are equal, the source voltage level can be assigned to the drain, thus obtaining the drain voltage level of the first MOSFET. Conversely, when the drain of the first MOSFET is in the assigned state and the source is in the unassigned state, based on the characteristic that the source and drain voltage levels are equal, the drain voltage level can be assigned to the source, thus obtaining the source voltage level. Therefore, when the above conditions are met, the source or drain of the first MOSFET can be changed from the unassigned state to the assigned state.

[0077] Specifically, when the input port of logic circuit X is assigned the true input value of A=0 and B=0, taking the first MOSFET as M01 as an example, based on the above true input value, the conduction state of M01 is judged. It can be determined that M01 is in the conduction state at this time, and the value assigned to the source (S) of M01 is 1, while the drain (D) is not assigned a value. Therefore, the value of 1 assigned to the source (S) can be assigned to the drain (D), thereby obtaining the drain level value of M01 as 1.

[0078] In subsequent steps, it can be determined whether the value of the output port Q of logic circuit X has been calculated. Based on the previous example, it can be read from the netlist that the output port Q is connected to the drain of M01, thus indicating that the level value of the output port Q is also 1. It is understandable that after calculating the level value of the output port Q, there is no need to perform the above assignment operations on other MOSFETs; the level value of the output port Q can be directly used as the output true value corresponding to the input true value of A=0 and B=0 mentioned above.

[0079] Optionally, in one embodiment of the present invention, after determining whether a level value has been calculated for the output port, the method for determining the truth table of the logic circuit provided in this embodiment further includes: if no level value has been calculated for the output port, then determining whether the second transistor is in a conducting state based on the assignment of the input port; if the second transistor is in a conducting state, and the source of the second transistor has been assigned a value but the drain has not been assigned a value, then assigning the level value of the source of the second transistor to the drain of the second transistor; calculating the level value of the output port based on the level value of the drain of the second transistor; or, if the second transistor is in a conducting state, and the source of the second transistor has not been assigned a value but the drain has been assigned a value, then assigning the level value of the drain of the second transistor to the source of the second transistor; calculating the level value of the output port based on the level value of the source of the second transistor.

[0080] In this embodiment of the invention, based on the foregoing example, if the output port Q level cannot be calculated after the first MOSFET in logic circuit X is assigned a value, the same assignment operation method as for the first MOSFET can be used to further assign a value to the second MOSFET in logic circuit X. After completing the assignment operation of the second MOSFET, it is determined whether the output port Q level can be obtained. If it still cannot be obtained, the assignment operation is performed on the third MOSFET, and this process is repeated iteratively until the output port Q level is obtained.

[0081] It should be noted that in each assignment operation, even if the output port Q level value is not output, the level value of some MOSFETs' source (S) or drain (D) terminals can be changed from an unassigned state to an assigned state during the assignment operation. These results help calculate the values ​​of each terminal of other connected MOSFETs. Therefore, in the overall logic circuit, each assignment operation helps reduce the number of unassigned terminals (S, D, or G) of each MOSFET terminal, which in turn helps to obtain the level value of the logic circuit's output port Q in subsequent assignment operations.

[0082] Optionally, in one embodiment of the present invention, determining whether the first transistor is in a conducting state based on the value assigned to the input port includes: determining the type of the first transistor based on the netlist; determining the gate level value of the first transistor based on the value assigned to the input port; and determining whether the first transistor is in a conducting state based on the type of the first transistor and the gate level value.

[0083] In this embodiment of the invention, when determining whether the first MOSFET is in the on state, the type of the first MOSFET, whether it is a pMOS (p-channel MOSFET) or an nmos (n-channel MOSFET), can first be obtained from the netlist. The on conditions for the two are completely different. If the MOSFET type is pMOS, it is in the on state when the gate-source voltage Vgs is less than a specified threshold, that is, when the gate level is 0, the MOSFET is in the on state. When the MOSFET type is nmos, it is in the on state when Vgs is greater than the specified threshold, that is, when the gate level is 1, the MOSFET is in the on state. Then, based on the value assigned to the input port, the gate level of the first MOSFET can be determined, and thus, based on the type of the first MOSFET and the gate level, it can be determined whether the first MOSFET is in the on state.

[0084] Taking M01 as the first MOSFET in logic circuit X as an example, the netlist shows that M01 is of type PMOS. The netlist also shows that the gate (G) of M01 is connected to input port A. Therefore, based on the voltage level of input port A (0), the voltage level of the gate (G) of M01 is 0, indicating that M01 is in the ON state.

[0085] It should be noted that, since the embodiments of the present invention do not limit the order of MOSFETs in the logic circuit, the first MOSFET mentioned above can be M01, or any other MOSFET. The use of M01 as the first MOSFET is merely an example, reflecting that when input port A or B is directly connected to the gate (G) of the first MOSFET, the voltage level of the gate of the first MOSFET can be obtained based on the value assigned to the input port. Conversely, when input ports A and B are not connected to the gate of the first MOSFET, the voltage level of the gate of the first MOSFET cannot be directly obtained, thus making it impossible to directly determine the conduction state of the first MOSFET.

[0086] Additionally, it's understandable that when the first transistor is a bipolar junction transistor (BJT), its type is either PNP or NPN. Correspondingly, the conduction state of the BJT needs to be determined based on its type and base voltage level. The specific implementation process will not be detailed here. Specifically, an NPN transistor consists of two N-type semiconductors sandwiching a P-type semiconductor, while a PNP transistor consists of two P-type semiconductors sandwiching an N-type semiconductor.

[0087] Optionally, in one embodiment of the present invention, the voltage level of the gate (G) of the first transistor is the same as the voltage level of the first input port of the logic circuit; determining whether the first transistor is in a conducting state based on the type of the first transistor and the voltage level of its gate includes: determining whether the first transistor is in a conducting state based on the type of the first transistor and the voltage level of the first input port of the logic circuit.

[0088] As mentioned earlier, when the gate (G) of the first MOSFET is not connected to any input port, it is impossible to determine whether the first MOSFET is in a conducting state when performing assignment operations. To solve this technical problem, in this embodiment of the invention, when sorting and naming the MOSFETs, an association can be established between the input port and the MOSFET. The MOSFET connected to the first input port is designated as the first MOSFET. In this way, the gate voltage level of the first MOSFET is the voltage level of the first input port. Therefore, based on the voltage level of the first input port and the type of the first MOSFET, it is possible to directly determine whether the first MOSFET is conducting, thereby improving the efficiency of the assignment operation.

[0089] Optionally, in one embodiment of the present invention, determining whether the second transistor is in a conducting state based on the value assigned to the input port includes: determining the type of the second transistor based on the netlist; determining the gate level value of the second transistor based on the value assigned to the input port; and determining whether the second transistor is in a conducting state based on the type of the second transistor and the gate level value.

[0090] In this embodiment of the invention, the same method as for determining the conduction state of the first MOSFET can be used when determining the conduction state of the second MOSFET. Specifically, when determining whether the second MOSFET is in the conduction state, the type of the second MOSFET, whether it is PMOS or NMOS, can be determined based on the information in the netlist. If the type of the second MOSFET is PMOS and the gate voltage is 0, or if the type of the second MOSFET is NMOS and the gate voltage is 1, then the second MOSFET is in the conduction state.

[0091] Optionally, in one embodiment of the present invention, the voltage level of the gate (G) of the second transistor is the same as the voltage level of the second input port of the logic circuit; determining whether the second transistor is in a conducting state based on the type of the second transistor and the voltage level of its gate includes: determining whether the second transistor is in a conducting state based on the type of the second transistor and the voltage level of the second input port of the logic circuit.

[0092] Specifically, when the gate (G) of the second MOSFET is not connected to any input port, it may be impossible to determine whether the second MOSFET is in a conducting state when performing value assignment operations. To solve this technical problem, in this embodiment of the invention, when sorting and naming MOSFETs, an association can be established between input ports and MOSFETs. The MOSFET connected to the second input port is designated as the second MOSFET. In this way, the gate voltage level of the second MOSFET is the voltage level of the second input port. Therefore, based on the voltage level of the second input port and the type of the second MOSFET, it is possible to directly determine whether the second MOSFET is conducting, thereby improving the efficiency of the value assignment operation.

[0093] Optionally, in one embodiment of the present invention, after determining the output truth value corresponding to the first set of input truth values, the method further includes: initializing the ungrounded and unconnected operating voltage terminals of each transistor to an unassigned state in the netlist; assigning values ​​to the input ports based on the second set of input truth values ​​in the input truth value list; calculating the level value of the output port based on the assigned values ​​of the input ports; determining whether a level value has been calculated for the output port; and if a level value has been calculated for the output port, using the calculated level value of the output port as the output truth value corresponding to the second set of input truth values.

[0094] Specifically, after calculating the output truth value corresponding to the first set of input truth values, the output truth value corresponding to the second set of input truth values ​​can be calculated. Taking logic circuit X as an example, during the calculation of the output truth value for the first set of input truth values, each pole (G, S or D) of each MOSFET may be assigned a value, which will interfere with the calculation.

[0095] Therefore, the ungrounded and unconnected terminals of each MOSFET can be initialized to an unassigned state. Furthermore, since the terminals connected to the operating voltage VDD and VSS have already been assigned values ​​during the calculation of the output truth value from the first set of input truth values, and these values ​​do not change in this calculation, there is no need to reassign them. Simply use the second set of input truth values ​​from the input truth value list (e.g., A=0, B=1) to reassign the input ports A and B of the logic circuit X. After completing the above steps, the output truth value corresponding to the second set of input truth values ​​can be calculated using the aforementioned method, which will not be elaborated further here.

[0096] Optionally, in one embodiment of the present invention, the method for determining the truth table of the logic circuit provided by the present invention may further include: if no level value is calculated for the output port after an assignment operation has been performed on all transistors described in the netlist, then the terminals of each transistor in the netlist that have changed from an unassigned state to an assigned state are determined; based on the level values ​​of each terminal of each transistor that have changed from an unassigned state to an assigned state, and the assignment of the input port, the level value of the output port is calculated again.

[0097] In this embodiment of the invention, based on the foregoing example, when the input truth values ​​of logic circuit X are A=1 and B=1, an assignment operation is performed on M01. From the netlist, M01 is of type pmos, connected to input port A, and its input level is 1. Therefore, M01 is in a non-conducting state. The levels of the drain (D) and source (S) terminals are not necessarily equal, so no assignment can be performed. Then, an assignment operation is performed on M02. From the netlist, M02 is of type nmos, connected to input port A, and its input level is 1. Therefore, M02 is in a conducting state, and its levels of the drain (D) and source (S) terminals are equal. However, neither the drain nor the source terminal is assigned a value; therefore, the source terminal cannot be used to assign a value to the drain terminal, nor can the drain terminal be used to assign a value to the source terminal. Assigning a value to M03: From the netlist, M03 is identified as an NMOS type, connected to input port B, with an input level of 1. This indicates that M03 is in a conducting state. The drain (D) and source (S) levels are equal, and the source (S) is connected to ground VSS with a level of 0. Therefore, the level of 0 from the source (S) can be assigned to the drain (D), changing the drain of M03 from an unassigned state to an assigned state. However, the output port Q level is still not calculated, requiring further assignment to M04. From the netlist, M04 is identified as a PMOS type, connected to input port B, with an input level of 1. This indicates that M04 is in a non-conducting state. The drain (D) and source (S) levels are not necessarily equal, therefore, assignment cannot be performed.

[0098] Therefore, after sequentially performing the assignment operation on all MOSFETs in logic circuit X, the output port Q level still could not be obtained. In this case, we can determine the terminals of each MOSFET in logic circuit X that transitioned from an unassigned state to an assigned state, namely the drain (D) terminal of M03. Based on the D level of M03 (0), we retrieve the MOSFET associated with the D terminal of M03 from the netlist. The D terminal of M03 is connected to net01 in the netlist (therefore net01=0). By filtering all MOSFETs based on net01, we can find that the MOSFET connected to it is M02. Therefore, in the further assignment operation, only M02 and M03 need to be assigned a second time; the other MOSFETs do not need to participate in the assignment operation. Specifically, we perform the assignment operation on M02 again. Using the result of the first determination of the conduction state of M02, we can determine that M02 is in the conduction state, and the D and S levels are equal. At this point, the voltage level of net01, which is connected to the source (S) terminal of M02, is 0. Therefore, the source terminal is in a value-assigned state, and the drain (D) terminal is in an unvalued state. Assigning the voltage level of 0 from the source terminal to the drain terminal results in a voltage level of 0 at the drain terminal of M02. From the netlist, it can also be determined that the drain terminal of M02 is connected to the output port Q, thus confirming that the voltage level of the output port Q is 0.

[0099] Therefore, in the process of calculating the output true value based on the input true value, if the output port Q level cannot be calculated after assigning values ​​to all MOSFETs, the values ​​of each pole of each MOSFET that has changed from an unassigned state to an assigned state obtained in the first round of assignment operation can be used for the second round of assignment operation. If the output port Q level still cannot be calculated after this, the values ​​of each pole of each MOSFET that has changed from an unassigned state to an assigned state obtained in the first two rounds of assignment operation can be used for the third round of assignment operation. This process is repeated iteratively. In each round of assignment operation, some MOSFET poles change from an unassigned state to an assigned state. This is a process in which an unassigned quantity gradually changes to an assigned quantity. By continuously repeating the iterative operation, the output port Q level can eventually be calculated.

[0100] Optionally, in one embodiment of the present invention, the logic circuit described by the netlist includes a first logic circuit and a second logic circuit, and the output terminal of the first logic circuit is connected to the input terminal of the second logic circuit; the truth table of the first logic circuit is predetermined; in step S11, assigning values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list may include: assigning values ​​to the input ports of the first logic circuit based on the first set of input truth values ​​in the input truth value list; correspondingly, in step S12, calculating the level value of the output port of the logic circuit described by the netlist based on the assigned values ​​to the input ports may include: obtaining the level value of the output port of the first logic circuit based on the assigned values ​​to the input ports of the first logic circuit and the predetermined truth table of the first logic circuit; assigning values ​​to the input ports of the second logic circuit based on the level values ​​of the output ports of the first logic circuit; and calculating the level value of the output port of the logic circuit based on the assigned values ​​to the input ports of the second logic circuit.

[0101] In this embodiment of the invention, the first logic circuit can be either multiple logic circuits or a single logic circuit, without affecting the substantive content of the embodiment. For example, Figure 4 The logic circuit Z shown includes two logic circuits X and one circuit Y. When determining the truth table of logic circuit Z, the level value of the output port Q of logic circuit Z can be directly obtained by the aforementioned method. However, since logic circuit Z includes a large number of MOSFETs, the number of assignment operations is also correspondingly large.

[0102] If the truth table of logic circuit X is predetermined, it can be directly called without recalculating the two logic circuits X, thus improving computational efficiency. Specifically, based on the assignment of values ​​to the input ports A, B, C, and D of logic circuit X, such as "A=0, B=0, C=0, D=0", the truth table of logic circuit X can be called to obtain Q1=1 and Q2=1. Meanwhile, since Q1 and Q2 are the two input values ​​of logic circuit Y, the values ​​of M09 to M14 of logic circuit Y can be assigned using the aforementioned method to calculate the level value of the output port Q. In this embodiment of the invention, by directly calling the predetermined truth table corresponding to the sub-circuit, the amount of computation can be reduced and computational efficiency improved.

[0103] Secondly, embodiments of the present invention provide a device for determining the truth table of a logic circuit, which can quickly extract the truth table of a logic circuit.

[0104] like Figure 5As shown, the logic circuit truth table determination device 5 provided in the embodiment of the present invention includes: a first assignment module 51, used to assign values ​​to the input ports of the logic circuit described by the netlist based on a first set of input truth values ​​in the input truth value list; the input truth value list is pre-generated based on the input ports of the logic circuit described by the netlist; a first calculation module 52, used to calculate the level value of the output port of the logic circuit described by the netlist based on the assignment of values ​​to the input ports; a first judgment module 53, used to determine whether the output port has a calculated level value; and a first output truth value acquisition module 54, used to, if the output port has a calculated level value, use the calculated level value of the output port as the output truth value corresponding to the first set of input truth values.

[0105] The logic circuit truth table determination device provided in the embodiments of the present invention can assign values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list; the input truth value list is pre-generated based on the input ports of the logic circuit described by the netlist; based on the assignment of values ​​to the input ports, the level value of the output port of the logic circuit described by the netlist is calculated; it is determined whether the output port has a calculated level value; if the output port has a calculated level value, the calculated level value of the output port is used as the output truth value corresponding to the first set of input truth values. In this way, the level value of the output port of the logic circuit can be directly calculated based on the input truth values ​​of the logic circuit, thereby obtaining the output truth value corresponding to the input truth values. The extraction method is simple and can quickly extract the truth table of the logic circuit.

[0106] Optionally, the logic circuit truth table determination device 5 further includes: a first determination module, used to determine the input ports and output ports of the logic circuit, as well as the ground connection terminal and operating voltage connection terminal of the transistor in the logic circuit, based on the netlist, before assigning values ​​to the input ports of the logic circuit described by the netlist based on the first set of input truth values ​​in the input truth value list; wherein the transistor is a field-effect transistor or a bipolar junction transistor; and a second assignment module, used to assign a low level to the ground connection terminal of the transistor and a high level to the operating voltage connection terminal.

[0107] Optionally, the first calculation module 52 includes: a first conduction state judgment unit, used to determine whether the first transistor is in a conduction state based on the value assigned to the input port; a first assignment unit, used to assign the level value of the source of the first transistor to the drain of the first transistor if the first transistor is in a conduction state and the source of the first transistor has been assigned a value but the drain has not been assigned a value; and to calculate the level value of the output port of the logic circuit based on the level value of the drain of the first transistor; or, a second assignment unit, used to assign the level value of the drain of the first transistor to the source of the first transistor if the first transistor is in a conduction state and the source of the first transistor has not been assigned a value but the drain has been assigned a value; and to calculate the level value of the output port of the logic circuit based on the level value of the source of the first transistor.

[0108] Optionally, the first calculation module 52 further includes: a second conduction state judgment unit, used to determine whether the second transistor is in a conduction state based on the assignment of the input port if no level value is calculated after determining whether the output port has a calculated level value; a third assignment unit, used to assign the level value of the source of the second transistor to the drain of the second transistor if the second transistor is in a conduction state and the source of the second transistor has been assigned a value but the drain has not been assigned a value; and calculate the level value of the output port based on the level value of the drain of the second transistor; or, a fourth assignment unit, used to assign the level value of the drain of the second transistor to the source of the second transistor if the second transistor is in a conduction state and the source of the second transistor has not been assigned a value but the drain has been assigned a value; and calculate the level value of the output port based on the level value of the source of the second transistor.

[0109] Optionally, the first conduction state determination unit includes: a first type determination subunit, used to determine the type of the first transistor based on the netlist; a first gate level determination subunit, used to determine the gate level value of the first transistor based on the value assigned to the input port; and a first conduction state determination subunit, used to determine whether the first transistor is in a conduction state based on the type of the first transistor and the gate level value.

[0110] Optionally, the gate voltage level of the first transistor is the same as the voltage level level of the first input port of the logic circuit; the first conduction state determination subunit is specifically used to: determine whether the first transistor is in a conduction state based on the type of the first transistor and the voltage level level of the first input port of the logic circuit.

[0111] Optionally, the second conduction state determination unit includes: a second type determination subunit, used to determine the type of the second transistor based on the netlist; a second gate level determination subunit, used to determine the gate level value of the second transistor based on the value assigned to the input port; and a second conduction state determination subunit, used to determine whether the second transistor is in a conduction state based on the type of the second transistor and the gate level value.

[0112] Optionally, the gate voltage level of the second transistor is the same as the voltage level level of the second input port of the logic circuit; the second conduction state determination subunit is specifically used to: determine whether the second transistor is in a conduction state based on the type of the second transistor and the voltage level level of the second input port of the logic circuit.

[0113] Optionally, the logic circuit truth table determination device 5 further includes: an initialization module, used to initialize the ungrounded and unconnected operating voltage extremes of each transistor to an unassigned state in the netlist after determining the output truth value corresponding to the first set of input truth values; a third assignment module, used to assign values ​​to the input ports based on the second set of input truth values ​​in the input truth value list; a second calculation module, used to calculate the level value of the output port based on the assignment of the input ports; a second judgment module, used to determine whether the output port has a calculated level value; and a second output truth value acquisition module, used to, if the output port has a calculated level value, use the calculated level value of the output port as the output truth value corresponding to the second set of input truth values.

[0114] Optionally, the logic circuit truth table determination device 5 further includes: a second determination module, configured to determine each pole of each transistor in the netlist that has changed from an unassigned state to an assigned state if no level value is calculated for the output port after performing an assignment operation on all transistors described in the netlist; and a recalculation module, configured to recalculate the level value of the output port based on the level values ​​of each pole of each transistor that has changed from an unassigned state to an assigned state, and the assignment to the input port.

[0115] Optionally, the logic circuit described by the netlist includes a first logic circuit and a second logic circuit, and the output terminal of the first logic circuit is connected to the input terminal of the second logic circuit; the truth table of the first logic circuit is predetermined; the first assignment module 51 is specifically used to: assign values ​​to the input ports of the first logic circuit based on the first set of input truth values ​​in the input truth value list;

[0116] Correspondingly, the first calculation module 52 is specifically used to: obtain the level value of the output port of the first logic circuit based on the assignment of the input port of the first logic circuit and the predetermined truth table of the first logic circuit; assign the level value of the input port of the second logic circuit based on the level value of the output port of the first logic circuit; and calculate the level value of the output port of the logic circuit based on the assignment of the input port of the second logic circuit.

[0117] Thirdly, embodiments of the present invention provide an electronic device capable of quickly extracting the truth table of a logic circuit.

[0118] like Figure 6 As shown, an embodiment of the present invention provides an electronic device that may include: a housing 41, a processor 42, a memory 43, a circuit board 44, and a power supply circuit 45. The circuit board 44 is disposed inside the space enclosed by the housing 41, and the processor 42 and the memory 43 are disposed on the circuit board 44. The power supply circuit 45 is used to supply power to various circuits or devices of the above-mentioned electronic device. The memory 43 is used to store executable program code. The processor 42 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 43, for executing the method for determining the truth table of the logic circuit described in any of the foregoing embodiments.

[0119] The specific execution process of the above steps by the processor 42, as well as the steps further executed by the processor 42 by running executable program code, can be found in the description of the foregoing embodiments, and will not be repeated here.

[0120] This electronic device exists in various forms, including but not limited to:

[0121] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and are primarily designed to provide voice and data communication. These terminals include smartphones (such as iPhones), multimedia phones, feature phones, and low-end phones.

[0122] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0123] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes audio and video players (such as iPods), handheld game consoles, e-book readers, as well as smart toys and portable car navigation devices.

[0124] (4) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0125] (5) Other electronic devices with data interaction functions.

[0126] Fourthly, embodiments of the present invention also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the logic circuit truth table determination methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0127] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0128] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0129] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0130] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0131] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0132] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method of determining a truth table of a logic circuit, characterized by, The method comprises: valuing input ports of a logic circuit described by a netlist based on a first set of input truth values in an input truth value list; the input truth value list is generated in advance according to input ports of the logic circuit described by the netlist; the logic circuit described by the netlist comprises transistors; calculating a level value of an output port of the logic circuit described by the netlist based on the valuation of the input ports; judging whether the output port has a level value calculated; if the output port has a level value calculated, taking the calculated level value of the output port as an output truth value corresponding to the first set of input truth values; if the output port does not have a level value calculated, judging whether a second transistor is in a conducting state based on the valuation of the input ports; if the second transistor is in the conducting state and a source of the second transistor has been valued but a drain of the second transistor has not been valued, taking a level value of the source of the second transistor as the drain of the second transistor; calculating a level value of the output port based on the level value of the drain of the second transistor; or, if the second transistor is in the conducting state and the source of the second transistor has not been valued but the drain of the second transistor has been valued, taking a level value of the drain of the second transistor as the source of the second transistor; calculating a level value of the output port based on the level value of the source of the second transistor.

2. The method of determining a truth table of a logic circuit according to claim 1, wherein, Before the input ports of the logic circuit described by the netlist are valued based on the first set of input truth values in the input truth value list, the method further comprises: determining input ports and output ports of the logic circuit and ground connection ends and working voltage connection ends of transistors in the logic circuit based on the netlist; wherein the transistors are field effect transistors or triodes; valuing the ground connection ends of the transistors to low levels and the working voltage connection ends to high levels.

3. The method of claim 2, wherein the logic circuit truth table is determined by: The calculation of the level value of the output port of the logic circuit described by the netlist based on the valuation of the input ports comprises: judging whether a first transistor is in a conducting state based on the valuation of the input ports; if the first transistor is in the conducting state and a source of the first transistor has been valued but a drain of the first transistor has not been valued, taking a level value of the source of the first transistor as the drain of the first transistor; calculating a level value of the output port of the logic circuit based on the level value of the drain of the first transistor; or, if the first transistor is in the conducting state and the source of the first transistor has not been valued but the drain of the first transistor has been valued, taking a level value of the drain of the first transistor as the source of the first transistor; calculating a level value of the output port of the logic circuit based on the level value of the source of the first transistor.

4. The method of claim 3, wherein the logic circuit truth table is determined by: The judgment of whether the first transistor is in the conducting state based on the valuation of the input ports comprises: determining a type of the first transistor based on the netlist; determining a gate level value of the first transistor based on the valuation of the input ports; judging whether the first transistor is in the conducting state based on the type and the gate level value of the first transistor.

5. The method of claim 4, wherein The level of the gate of the first transistor is the same as the level of the first input port of the logic circuit; The judgment whether the first transistor is in the on state or not based on the type and the gate level of the first transistor comprises: The judgment whether the first transistor is in the on state or not based on the type of the first transistor and the level of the first input port of the logic circuit.

6. The method of determining a truth table of a logic circuit according to claim 1, wherein, The judgment whether the second transistor is in the on state or not based on the assignment to the input port comprises: The type of the second transistor is determined based on the netlist; The gate level of the second transistor is judged based on the assignment to the input port; The judgment whether the second transistor is in the on state or not based on the type and the gate level of the second transistor.

7. The method of determining a truth table of a logic circuit according to claim 6, wherein, The level of the gate of the second transistor is the same as the level of the second input port of the logic circuit; The judgment whether the second transistor is in the on state or not based on the type and the gate level of the second transistor comprises: The judgment whether the second transistor is in the on state or not based on the type of the second transistor and the level of the second input port of the logic circuit.

8. The method of claim 1, wherein: After the output truth value corresponding to the first group of input truth values is determined, the method further comprises: In the netlist, the ungrounded and unoperated poles of each transistor are initialized as unassigned states; The input port is assigned based on the second group of input truth values in the input truth value list; The level of the output port is calculated based on the assignment to the input port; It is judged whether the output port has a calculated level or not; If the output port has a calculated level, the calculated level of the output port is taken as the output truth value corresponding to the second group of input truth values.

9. The method of claim 1, wherein: The method further comprises: If no level of the output port is calculated after the assignment operation is performed once on all the transistors described in the netlist, the poles of each transistor in the netlist which are changed from unassigned states to assigned states are determined; The level of the output port is calculated again based on the levels of the poles of each transistor which are changed from unassigned states to assigned states and the assignment to the input port.

10. The method of claim 1, wherein The logic circuit described by the netlist comprises a first logic circuit and a second logic circuit, and the output of the first logic circuit is connected to the input of the second logic circuit; the truth table of the first logic circuit is predetermined; The assignment to the input port of the logic circuit described by the netlist based on the first group of input truth values in the input truth value list comprises: The input port of the first logic circuit is assigned based on the first group of input truth values in the input truth value list; Correspondingly, the calculation of the level of the output port of the logic circuit described by the netlist based on the assignment to the input port comprises: The level of the output port of the first logic circuit is obtained based on the assignment to the input port of the first logic circuit and the predetermined truth table of the first logic circuit; value of the output port of the first logic circuit, the input port of the second logic circuit is assigned a value; based on the assignment of the input port of the second logic circuit, the level value of the output port of the logic circuit is calculated.

11. An apparatus for determining a truth table of a logic circuit, characterized by comprising: a first assignment module, configured to assign a value to an input port of a logic circuit described by a netlist based on a first set of input truth values in an input truth value list; the input truth value list is generated in advance according to the input port of the logic circuit described by the netlist; the logic circuit described by the netlist comprises a transistor; a first calculation module, configured to calculate a level value of an output port of the logic circuit described by the netlist based on the assignment of the input port; a first judgment module, configured to judge whether the output port has a level value calculated; a first output truth value acquisition module, configured to, if the output port has a level value calculated, take the calculated level value of the output port as an output truth value corresponding to the first set of input truth values; wherein the first calculation module further comprises: a second conduction state judgment unit, configured to, after judging whether the output port has a level value calculated, if the output port does not have a level value calculated, judge whether a second transistor is in a conduction state based on the assignment of the input port; a third assignment unit, configured to, if the second transistor is in the conduction state and the source of the second transistor has been assigned a value but the drain has not, assign the level value of the source of the second transistor to the drain of the second transistor; and calculate the level value of the output port based on the level value of the drain of the second transistor; or, a fourth assignment unit, configured to, if the second transistor is in the conduction state and the source of the second transistor has not been assigned a value but the drain has, assign the level value of the drain of the second transistor to the source of the second transistor; and calculate the level value of the output port based on the level value of the source of the second transistor.

12. The apparatus of claim 11, wherein: The apparatus further comprises: a first determination module, configured to, before assigning a value to an input port of a logic circuit described by a netlist based on a first set of input truth values in an input truth value list, determine, based on the netlist, the input port and the output port of the logic circuit, and a ground connection end and a working voltage connection end of a transistor in the logic circuit; wherein the transistor is a field effect transistor or a triode; a second assignment module, configured to assign a low level to the ground connection end of the transistor and a high level to the working voltage connection end.

13. The apparatus of claim 12, wherein: The first calculation module comprises: a first conduction state judgment unit, configured to judge whether a first transistor is in a conduction state based on the assignment of the input port; a first assignment unit, configured to, if the first transistor is in the conduction state and the source of the first transistor has been assigned a value but the drain has not, assign the level value of the source of the first transistor to the drain of the first transistor; and calculate the level value of the output port of the logic circuit based on the level value of the drain of the first transistor; or, The second assignment unit is configured to, if the first transistor is in the on state and the source of the first transistor is not assigned but the drain of the first transistor is assigned, assign the level value of the drain of the first transistor to the source of the first transistor; and calculate the level value of the output port of the logic circuit based on the level value of the source of the first transistor.

14. The apparatus of claim 13, wherein: The first on state judgment unit comprises: A first type determination subunit is configured to determine the type of the first transistor based on the netlist; A first gate level determination subunit is configured to determine the gate level value of the first transistor based on the assignment of the input port; The first on state determination subunit is configured to determine whether the first transistor is in the on state based on the type and the gate level value of the first transistor.

15. The apparatus of claim 14, wherein: The level value of the gate of the first transistor is the same as the level value of the first input port of the logic circuit. The first on state determination subunit is specifically configured to: Determine whether the first transistor is in the on state based on the type of the first transistor and the level value of the first input port of the logic circuit.

16. The apparatus for determining a truth table of a logic circuit according to claim 11, wherein, The second on state judgment unit comprises: A second type determination subunit is configured to determine the type of the second transistor based on the netlist; A second gate level determination subunit is configured to determine the gate level value of the second transistor based on the assignment of the input port; The second on state determination subunit is configured to determine whether the second transistor is in the on state based on the type and the gate level value of the second transistor.

17. The apparatus for determining a truth table of a logic circuit according to claim 16, wherein, The level value of the gate of the second transistor is the same as the level value of the second input port of the logic circuit. The second on state determination subunit is specifically configured to: Determine whether the second transistor is in the on state based on the type of the second transistor and the level value of the second input port of the logic circuit.

18. The apparatus for determining a truth table of a logic circuit according to claim 11, wherein, The device further comprises: An initialization module is configured to, after determining the output truth value corresponding to the first group of input truth values, initialize the ungrounded and unoperated terminals of each transistor in the netlist to the unassigned state; A third assignment module is configured to assign the input port based on the second group of input truth values in the input truth value list; A second calculation module is configured to calculate the level value of the output port based on the assignment of the input port; A second judgment module is configured to determine whether the output port has a calculated level value; A second output truth value acquisition module is configured to, if the output port has a calculated level value, take the calculated level value of the output port as the output truth value corresponding to the second group of input truth values.

19. The apparatus for determining a truth table of a logic circuit according to claim 11, wherein, The device further comprises: A second determination module is configured to, if no level value of the output port is calculated after performing the assignment operation on all transistors described in the netlist, determine the terminals of each transistor in the netlist that are changed from the unassigned state to the assigned state; A re-computing module is configured to re-compute the level value of the output port based on the level value of each pole of each transistor that is changed from the unassigned state to the assigned state and the assignment of the input port.

20. The apparatus for determining a truth table of a logic circuit according to claim 11, wherein, The logic circuit described by the netlist comprises a first logic circuit and a second logic circuit, and an output of the first logic circuit is connected to an input of the second logic circuit; and a truth table of the first logic circuit is predetermined; The first assignment module is specifically configured to: assign the input port of the first logic circuit based on the first set of input truth values in the input truth table; Correspondingly, the first computing module is specifically configured to: obtain the level value of the output port of the first logic circuit based on the assignment of the input port of the first logic circuit and the predetermined truth table of the first logic circuit; assign the input port of the second logic circuit based on the level value of the output port of the first logic circuit; obtain the level value of the output port of the logic circuit based on the assignment of the input port of the second logic circuit.

21. An electronic device, comprising: The electronic device comprises a processor, a memory, a circuit board and a power supply circuit, wherein the circuit board is arranged inside a space enclosed by a shell, the processor and the memory are arranged on the circuit board; the power supply circuit is configured to supply power to each circuit or device of the electronic device; the memory is configured to store executable program codes; the processor is configured to run programs corresponding to the executable program codes by reading the executable program codes stored in the memory, and the programs are configured to execute the method for determining the truth table of the logic circuit according to any one of claims 1 to 10.

22. A computer-readable storage medium, characterized in that, The computer readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for determining the truth table of the logic circuit according to any one of claims 1 to 10.

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