A memory computing array and a data read-write computing method

Abstract

This application discloses a storage computing array, comprising: multiple storage computing units interconnected in an array structure; each storage computing unit includes a selection switch and N series-connected resistive memories connected in series or parallel with the selection switch; wherein one or more resistive memories are each connected to a bidirectional selector. It is evident that in this storage computing array, because N series-connected resistive memories are connected to a single selection switch within a storage computing unit, a greater number of storage computing units can be configured with the same area overhead. Furthermore, since N series-connected resistive memories are configured in each storage computing unit, this configuration significantly increases the data storage capacity of each storage computing unit, thereby improving the storage efficiency of the storage computing array.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a storage computing array and a data read / write computing method. Background Technology

[0002] In existing technologies, storage computing arrays are generally composed of storage computing units, which typically consist of a 1T1R storage structure and a logic computing module. The 1T1R storage structure includes a gating switch and a resistive memory connected in series with it. Since the data storage capacity of a storage computing array is determined by the number of resistive memories within the array, this architecture suffers from low storage efficiency. Currently, there is no effective solution to this problem.

[0003] Therefore, improving the storage efficiency of storage computing arrays is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a storage computing array and a data read / write computing method to improve the storage efficiency of the storage computing array. The specific solution is as follows:

[0005] A storage computing array, comprising:

[0006] Multiple storage computing units interconnected in an array structure, each storage computing unit including a gating switch and N series-connected resistive memories connected in series or parallel with the gating switch; wherein one or more resistive memories are each connected to a bidirectional selector, and N≥1.

[0007] Preferably, the N series-connected resistive memories have the same structure but different physical dimensions.

[0008] Preferred options also include:

[0009] A metal-film bidirectional selector or diode connected in parallel with the resistive memory; wherein the forward voltage of the metal-film bidirectional selector is greater than or equal to the write voltage of the resistive memory connected in parallel with the metal-film bidirectional selector, and less than the breakdown voltage of the resistive memory; or the forward voltage of the diode is greater than or equal to the write voltage of the resistive memory connected in parallel with the diode, and less than the breakdown voltage of the resistive memory.

[0010] Preferably, the selection switch is an NMOS transistor, a PMOS transistor, or a transmission gate.

[0011] Preferably, the resistive memory is a magnetoresistive memory, a ferroelectric memory, a phase-change memory, or a resistive switching memory.

[0012] Preferred options also include:

[0013] An enable switch used to jointly control the storage computing units connected in rows or columns in the array structure.

[0014] Accordingly, the present invention also discloses a data read / write computation method, applied to the storage computing array disclosed above, comprising:

[0015] When the first data stored in the storage computing array needs to be read, the resistive memory in the target storage computing unit is divided into multiple resistance intervals, and a corresponding target preset voltage is set for each resistance interval. A first current is applied to the target storage computing unit, and the target voltage corresponding to each resistance interval is read. The target voltage is compared with the target preset voltage in the order of the resistance intervals to obtain the target comparison result, so as to read the first data through the target comparison result.

[0016] When writing second data to the storage computing array, the target data to be written to the target storage computing unit is determined according to the second data, and the order of applying different currents to the target storage computing unit is determined according to the resistance value of the target storage computing unit to obtain a target current sequence, so as to write the target data in the target storage computing unit through the target current sequence;

[0017] When performing calculations on the storage computing array, a target electrical signal and target storage data corresponding to the target storage computing unit are determined, and the target electrical signal and the target storage data are multiplied to obtain the calculated value of the target storage computing unit. The calculated values ​​of all storage computing units in the storage computing array are added together to obtain the calculated value of the storage computing array.

[0018] Preferably, the process of dividing the resistive memory in the target storage computing unit into multiple resistance intervals, setting a corresponding target preset voltage for each resistance interval, applying a first current to the target storage computing unit, reading the target voltage corresponding to each resistance interval, comparing the target voltage with the target preset voltage in the order of the resistance intervals to obtain a target comparison result, and reading the first data through the target comparison result includes:

[0019] Obtain the total resistance of N series-connected resistive memories in the target storage computing unit within the storage computing array;

[0020] Based on the total resistance, the N series-connected resistive memory units are divided into 2... NA first preset voltage sequence is obtained by dividing the resistance range into three resistance ranges and setting a corresponding preset voltage for each resistance range.

[0021] The first current is applied to the target storage computing unit, and 2 are read respectively. N The voltage corresponding to each resistance interval is used to obtain the first voltage sequence;

[0022] According to 2 N The first preset voltage sequence and the first voltage sequence are compared sequentially according to the corresponding resistance intervals to obtain the first comparison sequence;

[0023] The first target sub-data stored in the target storage computing unit is read according to the first comparison sequence, and the first data stored in the storage computing array is read according to the first target sub-data.

[0024] Preferably, the process of dividing the resistive memory in the target storage computing unit into multiple resistance intervals, setting a corresponding target preset voltage for each resistance interval, applying a first current to the target storage computing unit, reading the target voltage corresponding to each resistance interval, comparing the target voltage with the target preset voltage in the order of the resistance intervals to obtain a target comparison result, and reading the first data through the target comparison result includes:

[0025] Obtain the total resistance of N series-connected resistive memories in the target storage computing unit within the storage computing array;

[0026] Based on the total resistance, the N series-connected resistive memory units are divided into 2... N-1 A second preset voltage sequence is obtained by dividing the resistance range into three resistance ranges and setting a corresponding preset voltage for each resistance range.

[0027] The first current is applied to the target storage computing unit, and 2 are read respectively. N-1 The voltage corresponding to each resistance interval is used to obtain the second voltage sequence;

[0028] According to 2 N-1 The second preset voltage sequence and the second voltage sequence are compared sequentially according to the corresponding resistance intervals to obtain the second comparison sequence;

[0029] The second target sub-data stored in the target storage computing unit is read according to the second comparison sequence, and the first data stored in the storage computing array is read according to the second target sub-data.

[0030] As can be seen, in the storage computing array provided by this invention, because N series-connected resistive memories are connected to a single selector switch within a storage computing unit, a greater number of storage computing units can be configured with the same area overhead compared to existing technologies. Furthermore, since N series-connected resistive memories are configured in each storage computing unit, this configuration significantly increases the data storage capacity of each storage computing unit, thereby improving the storage efficiency of the storage computing array. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of the storage computing unit provided in the embodiment of the present invention, in which the selection switch is connected in series with N series-connected resistive memories;

[0033] Figure 2 This is a schematic diagram of the structure of the storage computing unit provided in the embodiment of the present invention, in which the selection switch is connected in parallel with N series-connected resistive memories;

[0034] Figure 3 The embodiments of the present invention provide in Figure 1 A schematic diagram of the structure of the diodes connected in parallel on each resistive memory in the storage computing array shown.

[0035] Figure 4 The embodiments of the present invention provide in Figure 2 A schematic diagram of the structure of the diodes connected in parallel on each resistive memory in the storage computing array shown.

[0036] Figure 5 This is a schematic diagram showing the structure when the enable switch controls the storage computing units connected in columns in the storage computing array, and the selector switch in the target storage computing unit is connected in series with N series resistive memories.

[0037] Figure 6 This is a schematic diagram showing the structure when the enable switch controls the storage computing units connected in columns in the storage computing array, and the selection switch in the target storage computing unit is connected in parallel with N series resistive memories.

[0038] Figure 7 This is a flowchart of a data read / write calculation method provided in an embodiment of the present invention. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] This invention discloses a storage computing array, which includes: a plurality of storage computing units interconnected in an array structure, each storage computing unit including a selection switch, and N series-connected resistive memories connected in series or parallel with the selection switch; wherein one or more resistive memories are each connected to a bidirectional selector, and N≥1.

[0041] This embodiment provides a novel storage computing array that can significantly improve storage efficiency. Specifically, the main improvement lies in the storage computing units within the array. Each storage computing unit comprises a selector switch and N resistive memories, wherein the N resistive memories are connected in series, and these series-connected memories are then connected in series or parallel with the selector switch.

[0042] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the structure of the storage computing unit provided in an embodiment of the present invention, in which a selection switch is connected in series with N series-connected resistive memories. Figure 2 This is a schematic diagram illustrating the structure of a storage computing unit provided in an embodiment of the present invention, in which a selection switch is connected in parallel with N series-connected resistive memories. Figure 1 and Figure 2 In the middle, R a This represents a resistive memory, where 0 ≤ a ≤ N, 0 ≤ b ≤ i, and WL. <c>The signal indicates the selection switch, where 1 ≤ c ≤ N, and a, b, c, and i are all integers; BL and SL represent the two signal input terminals of the storage and computing unit.

[0043] It should be noted that when building a storage computing array using storage computing units, the array can be constructed using either a neatly aligned row and column arrangement or a staggered arrangement, meaning that the storage computing units in the later row are placed between two storage computing units in the previous row. Assuming the storage computing array has a size of M×K, meaning it has M rows and K columns of storage computing units, then in the actual construction process, you can first connect the SL terminals of each storage computing unit sequentially along the row direction, and then connect the BL terminals of each storage computing unit sequentially along the column direction. Next, connect the selector switches in each storage computing unit sequentially along the row direction to the same row control line, and then connect the row control lines connecting the same resistive memory to the same column control line along the column direction.

[0044] It is understandable that when N resistive memories are set in a storage computing unit, more data can be stored within that unit. Compared to existing technologies, the technical solution provided in this embodiment allows for the placement of more resistive memories in each storage computing unit, thus significantly improving the storage efficiency of the storage computing array. Furthermore, the storage computing array provided in this application not only achieves higher integration but also increases the data processing speed of the storage computing array.

[0045] Furthermore, as a preferred embodiment, the N series-connected resistive memories have the same structure but different physical dimensions. That is, this arrangement allows the memory computing array to have different write currents.

[0046] As can be seen, in the storage computing array provided in this embodiment, because N series-connected resistive memories are connected to a single selector switch within a storage computing unit, a greater number of storage computing units can be configured with the same area overhead compared to existing technologies. Furthermore, since N series-connected resistive memories are configured in each storage computing unit, this configuration significantly increases the data storage capacity of each storage computing unit, thereby improving the storage efficiency of the storage computing array.

[0047] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the storage computing array further includes:

[0048] A metal thin-film bidirectional selector or diode connected in parallel with a resistive memory;

[0049] Wherein, the forward voltage of the metal thin film bidirectional selector is greater than or equal to the write voltage of the resistive memory connected in parallel with the metal thin film bidirectional selector, and less than the breakdown voltage of the resistive memory; or the forward voltage of the diode is greater than or equal to the write voltage of the resistive memory connected in parallel with the diode, and less than the breakdown voltage of the resistive memory.

[0050] It is understandable that in practical applications, since the currents loaded on each resistive memory in the storage computing array differ greatly, the resistive memory may be damaged by the loaded current. Therefore, in this embodiment, in order to avoid the above situation, a metal thin film bidirectional selector or diode is connected in parallel on each resistive memory.

[0051] It should be noted that the materials of the metal thin-film bidirectional selectors or diodes are the same, but the thickness of each metal thin-film bidirectional selector or diode is different because the resistive memory connected in parallel with the metal thin-film bidirectional selector or diode has different write currents.

[0052] Please see Figure 3 and Figure 4 , Figure 3 The embodiments of the present invention provide in Figure 1 The diagram shows a parallel diode structure on each resistive memory within the storage computing array. Figure 4 The embodiments of the present invention provide in Figure 2 The diagram shows a parallel diode structure on each resistive memory within the storage computing array.

[0053] Obviously, the technical solution provided in this embodiment can further ensure the reliability of the storage computing array during use.

[0054] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the selection switch is specifically an NMOS transistor, a PMOS transistor, or a transmission gate.

[0055] Since NMOS transistors, PMOS transistors, or transmission gates can all control the on or off of storage computing units and meet the practical application requirements of storage computing arrays, in this embodiment, the selection switch is set as an NMOS transistor, PMOS transistor, or transmission gate, which makes the setting of the selection switch more flexible and diverse.

[0056] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the resistive memory is specifically a magnetoresistive memory, a ferroelectric memory, a phase-change memory, or a resistive switching memory.

[0057] It is understandable that, since magnetoresistive memory, ferroelectric memory, phase-change memory, or resistive switching memory are all common types of memory in practical operation, setting the resistive memory as a magnetoresistive memory, ferroelectric memory, phase-change memory, or resistive switching memory can relatively reduce the difficulty of building the storage computing array provided in this application in the actual construction process.

[0058] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, the storage computing array further includes:

[0059] An enable switch used to jointly control storage computing units connected in rows or columns in an array structure.

[0060] In this embodiment, an enable switch is also provided in the storage computing array for jointly controlling the storage computing units connected in rows or columns in the array structure. It is conceivable that by providing an enable switch in the storage computing array, the storage computing units connected in rows or columns can be controlled together, thereby further improving the convenience for users when using the storage computing array.

[0061] Please see Figure 5 and Figure 6 , Figure 5 This is a schematic diagram showing the structure when the enable switch controls the storage computing units connected in columns in the storage computing array, and the selector switch in the target storage computing unit is connected in series with N series resistive memories. Figure 6 This is a schematic diagram illustrating the structure when the enable switch in the target storage computing unit is connected in parallel with N series resistive memories, and the enable switch controls the storage computing units connected in columns in the storage computing array. It should be noted that... Figure 5 and Figure 6 In the middle, Ten0 and Ten M To enable the switch. Furthermore, in this embodiment, the target storage computing unit refers to any one of the storage computing units in the storage computing array.

[0062] Corresponding to the storage computing array disclosed in the above embodiments, this invention also provides a data read / write computing method corresponding to the above storage computing array. Please refer to [link to relevant documentation]. Figure 7 , Figure 7 The flowchart illustrates a data read / write calculation method provided in an embodiment of the present invention, wherein the data read / write calculation method includes:

[0063] Step S11: When it is necessary to read the first data stored in the storage computing array, the resistive memory in the target storage computing unit is divided into multiple resistance intervals, and a corresponding target preset voltage is set for each resistance interval. A first current is applied to the target storage computing unit, and the target voltage corresponding to each resistance interval is read respectively. The target voltage is compared with the target preset voltage in the order of the resistance intervals to obtain the target comparison result, so as to read the first data through the target comparison result.

[0064] It is understandable that when reading data stored in a storage computing array, it actually means reading the data stored in each storage computing unit within the array. Here, we will take reading the data stored in the target storage computing unit as an example. When reading data stored in the target storage computing unit, the resistive memory within the unit is first divided into multiple resistance intervals, and a corresponding target preset voltage is set for each interval. Then, a first current is applied to the target storage computing unit, and the target voltage corresponding to each resistance interval is read. Next, the read target voltages are compared sequentially with the target preset voltages according to the order of the resistance intervals to obtain the comparison result. The first data stored in the storage computing array is then read based on this comparison result.

[0065] It is conceivable that when the target comparison result is obtained, it is equivalent to obtaining the data stored in the target storage computing unit. At this point, by summing up the data stored in each storage computing unit, the first data stored in the storage computing array can be read.

[0066] Specifically, in Figure 1 In the storage computing array shown, when it is necessary to read the first data stored in the storage computing array, the first step is to select the target storage computing unit from the array. Then, the selection switch in the target storage computing unit and all resistive memories are turned on. At this point, a first current can be applied to the target storage computing unit through its signal input terminal. Figure 2 In the storage computing array shown, when it is necessary to read the first data stored in the storage computing array, the target storage computing array for which the data to be read is first selected from the storage computing array. Then, the selection switch in the target storage computing unit is turned off. At this time, the first current can be applied to the target storage computing unit through the signal input terminal of the target storage computing unit.

[0067] Step S12: When writing second data to the storage computing array, the target data to be written to the target storage computing unit is determined according to the second data, and the order of applying different currents to the target storage computing unit is determined according to the resistance value of the target storage computing unit to obtain the target current sequence, so as to write the target data in the target storage computing unit through the target current sequence.

[0068] It's understandable that writing second data into a storage computing array means writing data corresponding to the second data into each storage computing unit in the array. Here, we'll use writing data into a target storage computing unit as an example for further explanation.

[0069] First, the target data to be written to the target storage computing unit is determined based on the second data. Then, the order in which different currents are applied to the target storage computing unit is determined based on the resistance value of the target storage computing unit. Because the write current Ii of each layer of resistive memory is different, only resistive memory with Ii < Iwrite can be written under a certain write current Iwrite. Under this principle mechanism, the state of different combinations of resistive memory storage can be obtained through current control.

[0070] In other words, firstly, the order of applying the write current is established based on the states of the resistive memories corresponding to the states to be written, resulting in a target current sequence. Then, the resistive states of the resistive memories are changed by applying write currents of different magnitudes or directions once or multiple times to the target memory computing unit. Finally, the states of the multiple resistive memories are changed to the states corresponding to the write states. Obviously, this setup method allows target data to be written into the target memory computing unit.

[0071] Specifically, in Figure 1 In the illustrated storage computing array, when second data needs to be written into the array, a target storage computing unit to be written is first selected. Then, the target storage computing unit is controlled to be in a conducting state, while the selection switches in its adjacent storage computing units are in a de-energized state. A target current sequence is then applied across the signal terminals of the target storage computing unit based on the resistance value of the resistive memory within the target unit, so that the target data can be written into the target storage computing unit using this target current sequence. Figure 2 In the storage computing array shown, when it is necessary to write second data into the storage computing array, firstly, a target storage computing unit to be written is selected from the storage computing array. Then, all storage computing units in the storage computing array except the target storage computing unit are controlled to be in the conducting state, and the selection switch in the target storage computing unit is controlled to be in the off state. After that, a target current sequence is loaded onto the target storage computing unit, so as to change the resistance state of the resistive memory by the state of the current passing through the resistive memory, thereby achieving the purpose of writing data into the target storage computing unit.

[0072] Furthermore, in practical applications, if the selection switch in the target storage computing unit and its N interconnected resistive memories are in series, data reading and writing to all storage computing units in the storage computing array can be completed using an odd-even alternating method. Specifically, in actual operation, the storage computing units in the storage computing array can be assigned corresponding numerical labels first. Then, the storage computing units with odd numerical labels are divided into the first array, and the storage computing units with even numerical labels are divided into the second array. Next, data is read or written to the first array. When the data reading or writing to the first array is complete, the data reading or writing to the second array is then performed. When the data reading or writing to the second array is complete, the data reading or writing of the entire storage computing array is finished. Clearly, using this data read / write method, data reading or writing to all storage computing units in the storage computing array can be completed within 2N clock cycles, thus achieving faster data read / write performance.

[0073] Step S13: When performing calculations on the storage computing array, determine the target electrical signal and target storage data corresponding to the target storage computing unit, multiply the target electrical signal and target storage data to obtain the calculated value of the target storage computing unit, and add the calculated values ​​of all storage computing units in the storage computing array to obtain the calculated value of the storage computing array.

[0074] In practical applications, when performing calculations on a storage computing array, it is necessary to perform calculations on each storage computing unit within the array. Here, we will take the target storage computing unit as an example for specific explanation. When calculating the target storage computing unit, the first step is to obtain the target electrical signal applied to the target storage computing unit, as well as the target storage data stored within it. Then, the target electrical signal and the target storage data are multiplied to obtain the calculated value of the target storage computing unit. Finally, the same method is used to calculate the values ​​of the other storage computing units in the array excluding the target unit, and the calculated values ​​of all storage computing units in the array are summed to obtain the calculated value of the entire storage computing array.

[0075] Obviously, the technical solution provided in this embodiment realizes data reading, data writing and data calculation of the storage computing array. Furthermore, the storage computing array provided in this embodiment can perform calculations on the storage computing array without setting up an additional logical computing module in the storage computing array, thereby relatively reducing the design cost required for the storage computing array.

[0076] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, step S11 above: dividing the resistive memory in the target storage computing unit into multiple resistance intervals, setting a corresponding target preset voltage for each resistance interval, applying a first current to the target storage computing unit, reading the target voltage corresponding to each resistance interval, comparing the target voltage with the target preset voltage in the order of the resistance intervals to obtain the target comparison result, and reading the first data through the target comparison result, includes:

[0077] Obtain the total resistance of N series-connected resistive memories in the target storage computing unit within the storage computing array;

[0078] Divide the N series-connected resistive memory units into 2 based on the total resistance. N A first preset voltage sequence is obtained by dividing the resistance range into three resistance ranges and setting a corresponding preset voltage for each resistance range.

[0079] A first current is applied to the target storage computing unit, and 2 are read respectively. N The voltage corresponding to each resistance interval is used to obtain the first voltage sequence;

[0080] According to 2 N The first preset voltage sequence and the first voltage sequence are compared sequentially according to the corresponding resistance intervals to obtain the first comparison sequence;

[0081] The first target sub-data stored in the target storage computing unit is read according to the first comparison sequence, and the first data stored in the storage computing array is read according to the first target sub-data.

[0082] It is understandable that, since the storage computing unit contains a large number of resistive memories, different stored data in the storage computing unit can be read by combining the resistive memories in different ways.

[0083] In order to read the data stored in the target storage computing unit, the total resistance of the N series-connected resistive memories in the target storage computing unit can be obtained first, and the N series-connected resistive memories can be divided into 2... N If there are multiple resistance intervals, then each resistance interval will correspond to a data state, and the target storage computing unit will correspond to N bits of data.

[0084] Then, a corresponding preset voltage is set for each resistance interval; that is, the preset voltage corresponding to the first resistance interval is set as the first reference voltage, the preset voltage corresponding to the second resistance interval is set as the second reference voltage, and so on. N The preset voltage corresponding to each resistance range is set to the 2nd... N Given a reference voltage, the first preset voltage sequence is the first reference voltage, the second reference voltage, and so on, up to the second reference voltage. N A set of reference voltages.

[0085] A first current is applied to the target storage computing unit, and 2 are read respectively. N The voltage corresponding to each resistance interval is defined as follows: the voltage reading corresponding to the first resistance interval is the first reading voltage, the voltage reading corresponding to the second resistance interval is the second reading voltage, and so on... N The voltage reading corresponding to each resistance interval is the 2nd N Reading voltage, then the first voltage sequence is the first reading voltage, the second reading voltage, and so on, up to the 2nd reading voltage. N A set of voltage readings.

[0086] Then, according to 2 N The first preset voltage sequence is compared with the first voltage sequence in the order corresponding to each resistance interval. That is, the first reading voltage is compared with the first reference voltage, the second reading voltage is compared with the second reference voltage, and so on. N Read voltage and the 2nd N The comparison is performed against a reference voltage to obtain the first comparison result, the second comparison result, and so on, up to the 2nd comparison result. N Comparing the results, the first comparison sequence is the first comparison result, the second comparison result, and so on, up to the 2nd comparison result. N The set of comparison results. It should be noted that if the i-th reference voltage is greater than the i-th reading voltage, the i-th comparison result is 1; if the i-th reference voltage is less than the i-th reading voltage, the i-th comparison result is 0, where 1 ≤ i ≤ 2. N .

[0087] It's conceivable that obtaining the first comparison sequence is equivalent to obtaining the first target sub-data stored in the target storage computing unit. Finally, the data stored in the other storage computing units in the storage computing array, excluding the target storage computing unit, is read using the same method. Clearly, when the data stored in all storage computing units in the storage computing array is obtained, the first data stored in the storage computing array can be read.

[0088] Based on the above embodiments, this embodiment further explains and optimizes the technical solution. As a preferred implementation, step S11 above: dividing the resistive memory in the target storage computing unit into multiple resistance intervals, setting a corresponding target preset voltage for each resistance interval, applying a first current to the target storage computing unit, reading the target voltage corresponding to each resistance interval, comparing the target voltage with the target preset voltage in the order of the resistance intervals to obtain the target comparison result, and reading the first data through the target comparison result, includes:

[0089] Obtain the total resistance of N series-connected resistive memories in the target storage computing unit within the storage computing array;

[0090] Divide the N series-connected resistive memory units into 2 based on the total resistance. N-1 A second preset voltage sequence is obtained by dividing the resistance range into three resistance ranges and setting a corresponding preset voltage for each resistance range.

[0091] A first current is applied to the target storage computing unit, and 2 are read respectively. N-1 The voltage corresponding to each resistance interval is used to obtain the second voltage sequence;

[0092] According to 2 N-1 The second preset voltage sequence and the second voltage sequence are compared sequentially according to the corresponding resistance intervals to obtain the second comparison sequence;

[0093] The second target sub-data stored in the target storage computing unit is read according to the second comparison sequence, and the first data stored in the storage computing array is read according to the second target sub-data.

[0094] Alternatively, in practical applications, to read the data stored in the target storage computing unit, one can first obtain the total resistance of the N series-connected resistive memories in the target storage computing unit, and then divide the N series-connected resistive memories into 2... N-1 If there are multiple resistance intervals, then each resistance interval will correspond to a data state, and the target storage computing unit will correspond to N-1 bits of data.

[0095] Then, a corresponding preset voltage is set for each resistance interval; that is, the preset voltage corresponding to the first resistance interval is set to the first preset voltage, the preset voltage corresponding to the second resistance interval is set to the second preset voltage, and so on. N-1 The preset voltage corresponding to each resistance range is set to the 2nd... N-1 If the preset voltage is given, then the second preset voltage sequence is the first preset voltage, the second preset voltage, and so on, up to the 2nd preset voltage. N-1 A set of preset voltages.

[0096] A first current is applied to the target storage computing unit, and 2 are read respectively. N-1 The voltage corresponding to each resistance interval is defined as follows: the voltage reading corresponding to the first resistance interval is the first voltage, the voltage reading corresponding to the second resistance interval is the second voltage, and so on... N-1 The voltage reading corresponding to each resistance interval is the 2nd N-1 Voltage, then the second voltage sequence is the first voltage, the second voltage, and so on, up to the 2nd voltage. N-1 A collection of voltages.

[0097] Then, according to 2 N-1 The second preset voltage sequence and the second voltage sequence are compared sequentially according to the corresponding resistance intervals. That is, the first voltage is compared with the first preset voltage, the second voltage is compared with the second preset voltage, and so on, until the second... N-1 Voltage and the 2nd N-1 The preset voltages are compared to obtain the first comparison value, the second comparison value, and so on, up to the 2nd comparison value. N-1 If we compare the values, then the second comparison sequence is the first comparison value, the second comparison value, and so on, up to the 2nd comparison value. N-1 A set of comparison values. It should be noted that if the j-th preset voltage is greater than the j-th voltage, then the j-th comparison value is 1; if the j-th preset voltage is less than the j-th voltage, then the j-th comparison value is 0, where 1 ≤ j ≤ 2. N-1 .

[0098] It's conceivable that obtaining the second comparison sequence is equivalent to obtaining the second target sub-data stored in the target storage computing unit. Finally, the data stored in the other storage computing units in the storage computing array, excluding the target storage computing unit, is read using the same method. Clearly, when the data stored in all storage computing units in the storage computing array is obtained, the first data stored in the storage computing array can be read.

[0099] Clearly, the technical solution provided in this embodiment makes the data reading method of the storage computing array more flexible and diverse.

[0100] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0101] The foregoing has provided a detailed description of a storage computing array and a data read / write computing method provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.< / c>

Claims

1. A storage computing array, characterized in that, include: Multiple storage computing units interconnected in an array structure, each storage computing unit including a gating switch, and a series or parallel connection to the gating switch. A series of resistive memory modules; wherein one or more resistive memory modules are each connected to a bidirectional selector. ; The storage computing array is configured to, when reading the first data stored in the storage computing array, divide the resistive memory in the target storage computing unit into multiple resistance intervals, set a corresponding target preset voltage for each resistance interval, apply a first current to the target storage computing unit, read the target voltage corresponding to each resistance interval, compare the target voltage with the target preset voltage in the order of the resistance intervals, obtain a target comparison result, and read the first data through the target comparison result; When writing second data to the storage computing array, the target data to be written to the target storage computing unit is determined based on the second data, and the order in which different currents are applied to the target storage computing unit is determined based on the resistance value of the target storage computing unit to obtain a target current sequence, so as to write the target data to the target storage computing unit through the target current sequence.

2. The storage computing array according to claim 1, characterized in that, A series of resistive memory modules have the same structure but different physical dimensions.

3. The storage computing array according to claim 1, characterized in that, Also includes: A metal-film bidirectional selector or diode connected in parallel with the resistive memory; wherein the forward voltage of the metal-film bidirectional selector is greater than or equal to the write voltage of the resistive memory connected in parallel with the metal-film bidirectional selector, and less than the breakdown voltage of the resistive memory; or the forward voltage of the diode is greater than or equal to the write voltage of the resistive memory connected in parallel with the diode, and less than the breakdown voltage of the resistive memory.

4. The storage computing array according to claim 1, characterized in that, The selection switch is specifically an NMOS transistor, a PMOS transistor, or a transmission gate.

5. The storage computing array according to claim 1, characterized in that, The resistive memory is specifically a magnetoresistive memory, a ferroelectric memory, a phase-change memory, or a resistive switching memory.

6. The storage computing array according to claim 1, characterized in that, Also includes: An enable switch used to jointly control the storage computing units connected in rows or columns in the array structure.

7. A data reading and writing calculation method, characterized in that, Applied to the storage computing array as described in any one of claims 1 to 6, comprising: When the first data stored in the storage computing array needs to be read, the resistive memory in the target storage computing unit is divided into multiple resistance intervals, and a corresponding target preset voltage is set for each resistance interval. A first current is applied to the target storage computing unit, and the target voltage corresponding to each resistance interval is read. The target voltage is compared with the target preset voltage in the order of the resistance intervals to obtain the target comparison result, so as to read the first data through the target comparison result. When writing second data to the storage computing array, the target data to be written to the target storage computing unit is determined according to the second data, and the order of applying different currents to the target storage computing unit is determined according to the resistance value of the target storage computing unit to obtain a target current sequence, so as to write the target data in the target storage computing unit through the target current sequence; When performing calculations on the storage computing array, a target electrical signal and target storage data corresponding to the target storage computing unit are determined, and the target electrical signal and the target storage data are multiplied to obtain the calculated value of the target storage computing unit. The calculated values ​​of all storage computing units in the storage computing array are added together to obtain the calculated value of the storage computing array.

8. The data reading and writing calculation method according to claim 7, characterized in that, The process of dividing the resistive memory in the target storage computing unit into multiple resistance intervals, setting a corresponding target preset voltage for each resistance interval, applying a first current to the target storage computing unit, reading the target voltage corresponding to each resistance interval, comparing the target voltage with the target preset voltage in the order of the resistance intervals to obtain a target comparison result, and reading the first data through the target comparison result includes: Obtain the target storage computing unit within the storage computing array The total resistance of the series-connected resistive memory modules; Based on the total resistance The series-connected resistive memory is divided into A first preset voltage sequence is obtained by dividing the resistance range into three resistance ranges and setting a corresponding preset voltage for each resistance range. The first current is applied to the target storage computing unit, and the data is read respectively. The voltage corresponding to each resistance interval is used to obtain the first voltage sequence; According to The first preset voltage sequence and the first voltage sequence are compared sequentially according to the corresponding resistance intervals to obtain the first comparison sequence; The first target sub-data stored in the target storage computing unit is read according to the first comparison sequence, and the first data stored in the storage computing array is read according to the first target sub-data.

9. The data reading and writing calculation method according to claim 7, characterized in that, The process of dividing the resistive memory in the target storage computing unit into multiple resistance intervals, setting a corresponding target preset voltage for each resistance interval, applying a first current to the target storage computing unit, reading the target voltage corresponding to each resistance interval, comparing the target voltage with the target preset voltage in the order of the resistance intervals to obtain a target comparison result, and reading the first data through the target comparison result includes: Obtain the target storage computing unit within the storage computing array The total resistance of the series-connected resistive memory modules; Based on the total resistance The series-connected resistive memory is divided into A second preset voltage sequence is obtained by dividing the resistance range into three resistance ranges and setting a corresponding preset voltage for each resistance range. The first current is applied to the target storage computing unit, and the data is read respectively. The voltage corresponding to each resistance interval is used to obtain the second voltage sequence; According to The second preset voltage sequence and the second voltage sequence are compared sequentially according to the corresponding resistance intervals to obtain the second comparison sequence; The second target sub-data stored in the target storage computing unit is read according to the second comparison sequence, and the first data stored in the storage computing array is read according to the second target sub-data.

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