Semiconductor device with back gate isolation structure and method of forming the same

Abstract

The present disclosure relates to semiconductor devices having back gate isolation structures and methods of forming the same. A semiconductor device includes nanostructures vertically arranged along a first direction and spaced apart from each other. The semiconductor device also includes a dielectric fin structure having a dielectric material of uniform composition, and isolation structures on opposite sides of the nanostructures. Further, the semiconductor device includes a gate structure surrounding the nanostructures. The gate structure extends between the nanostructures and the dielectric fin structure, and between the nanostructures and the isolation structures. Further, the nanostructures are spaced apart from the dielectric fin structure by a first distance along a second direction perpendicular to the first direction, and spaced apart from the isolation structures by a second distance along the second direction, where the first distance is greater than the second distance. Further, the gate structure meets the dielectric fin structure on a surface extending perpendicular to the first direction.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices having a back-side gate isolation structure and methods for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has typically increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This miniaturization process generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of handling and manufacturing ICs.

[0003] In semiconductor manufacturing, diced metal gate (CMG) processes refer to the processes used to form isolation structures to divide a continuous gate electrode across multiple active regions into segments. These isolation structures may be called gate dicing features, dicing features, or CMG features. In some existing CMG processes, gate dicing features are formed on dielectric fins (or hybrid fins (HF)). Together, the top gate dicing feature and the bottom dielectric fins isolate the gate electrode into segments. In some example processes, gate dicing features are formed from the front side of a substrate (e.g., a wafer) using photolithography and etching processes. As semiconductor devices continue to shrink, the use of such dielectric fins increasingly limits the ability to further reduce cell height and / or maintain a reasonable processing window. Therefore, while existing CMG processes are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device is provided, comprising: a nanostructure arranged perpendicularly along a first direction and spaced apart from each other; a dielectric fin structure having a dielectric material of uniform composition; and an isolation structure located on the opposite side of the nanostructure; and a gate structure surrounding the nanostructure, extending between the nanostructure and the dielectric fin structure, and extending between the nanostructure and the isolation structure, wherein the nanostructure is spaced apart from the dielectric fin structure by a first distance along a second direction perpendicular to the first direction, and spaced apart from the isolation structure by a second distance along the second direction, wherein the first distance is greater than the second distance, and wherein the gate structure is in contact with the dielectric fin structure on a surface extending perpendicular to the first direction.

[0005] According to one aspect of this disclosure, a method of forming a semiconductor device is provided, comprising: receiving a workpiece having a front side and a back side, the workpiece comprising: a first plurality of semiconductor layers on the first base on the front side surface of a substrate, and a second plurality of semiconductor layers on the second base on the front side surface of the substrate; a first dielectric feature located on a first side of the first plurality of semiconductor layers and between the first plurality of semiconductor layers and the second plurality of semiconductor layers; and a second dielectric feature located on a second side of the first plurality of semiconductor layers, the second side being opposite to the first side, and the second dielectric feature having a feature surface facing the front side; forming a gate structure that engages the first plurality of semiconductor layers and the second plurality of semiconductor layers and is in contact with the first dielectric feature on the feature surface; replacing the first base and the second base respectively to form a first back side dielectric and a second back side dielectric; removing the first dielectric feature but not the second dielectric feature, thereby forming an opening between the first plurality of semiconductor layers and the second plurality of semiconductor layers; recessing the gate structure from the opening to form a gate dicing opening that extends from the front surface of the gate structure to the rear surface of the gate structure; and forming a third dielectric feature in the gate dicing opening.

[0006] According to one aspect of this disclosure, a method of forming a semiconductor device is provided, comprising: receiving a workpiece having a front side and a back side, the front side and the back side being opposite to each other in a vertical direction, the workpiece including a first semiconductor layer stack over a first base on a front surface of a substrate and a second semiconductor layer stack over a second base on a front surface of the substrate, wherein the first stack and the second stack each include a first semiconductor layer and a second semiconductor layer arranged in a vertically staggered manner, wherein the first stack and the second stack each extend longitudinally along a first direction, and wherein an isolation feature is located between the first base and the second base; forming a hybrid structure between the sidewall surfaces of the first stack and the second stack and on a first surface of the isolation feature, wherein the hybrid structure includes a first low-k dielectric layer surrounded by a first high-k dielectric layer, and a layer between the first low-k dielectric layer and the first high-k dielectric layer. A second high-k dielectric layer is formed on the first stack and the second stack along a second direction perpendicular to the first direction, the first gate stack covering a portion of the second high-k dielectric layer; source / drain features are formed on both sides of the first gate stack; the portion of the second high-k dielectric layer not covered by the first gate stack is recessed; the second semiconductor layer is selectively removed; the first high-k dielectric layer on the sidewall surface of the first low-k dielectric layer is recessed; a gate dielectric layer is formed around the first semiconductor layer and around the first low-k dielectric layer, a gate electrode layer is formed around the gate dielectric layer, and a gate cap is formed covering the gate electrode layer; the first base and the second base are replaced from the back side to form a back dielectric layer; and a gate dicing feature is formed, the gate dicing feature extending vertically through the back dielectric layer, through the gate electrode layer and through the gate cap. Attached Figure Description

[0007] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1A , Figure 1B and Figure 1C A flowchart of a method for forming a semiconductor device having gate dicing features formed from the back side of the semiconductor device, according to one or more aspects of this disclosure, is shown.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A Based on one or more aspects of this disclosure Figure 1A , Figure 1B and Figure 1C The method provides a three-dimensional (3D) view of the workpiece during the manufacturing process.

[0010] Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 25B-1 , Figure 25B-2 , Figure 25B-3 , Figure 25B-4 , Figure 26B and Figure 26B-1 Based on one or more aspects of this disclosure Figures 1A-1C During the manufacturing process of the method, along the corresponding Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A and Figure 26A A partial cross-sectional view of the workpiece along line B-B'.

[0011] Figure 24C , Figure 25C , Figure 25C-1 , Figure 25C-2 , Figure 25C-3 , Figure 26C and Figure 27 Based on one or more aspects of this disclosure Figures 1A-1C During the manufacturing process of the method, along the corresponding Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A and Figure 26A A partial cross-sectional view of the workpiece along the C-C' line. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Spatially related terms (e.g., “below,” “under,” “down,” “above,” “up,” etc.) are used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein will be interpreted accordingly.

[0014] Furthermore, when using terms such as "about," "approximately," etc., to describe numbers or ranges of numbers, the term is intended to cover a reasonable range of numbers that takes into account variations inherent during manufacturing, as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing features having numerical characteristics, the number or range of numbers covers a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Further, reference numerals and / or letters may be repeated in various examples of this disclosure. Such repetition is for the purposes of simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0015] This disclosure generally relates to integrated circuits (ICs) and semiconductor devices, and methods of forming them. More specifically, this disclosure relates to gate isolation structures for ICs and semiconductor devices. In semiconductor manufacturing, diced metal gate (CMG) processes refer to processes used to form dielectric features to divide a continuous gate structure across multiple active regions into two or more segments. Such dielectric features may be referred to as gate dicing features or dicing features. In some existing CMG processes, gate dicing features are formed on dielectric fins (or hybrid fins (HF)). The top gate dicing feature and the bottom dielectric fin work together to divide the gate structure into two segments. In some example processes, gate dicing features are formed from the front side (or front edge) of a substrate (e.g., a wafer) using photolithography and etching processes. As semiconductor devices continue to shrink, the use of such dielectric fins increasingly limits the ability to further reduce cell height and / or maintain a reasonable processing window. Therefore, while existing CMG processes are generally sufficient for their intended purpose, they are not satisfactory in all respects.

[0016] This disclosure provides a CMG process different from prior art, which forms dicing features from the back side (or back side) of the substrate. Furthermore, the dicing features according to this disclosure extend from the back side of the substrate through the gate structure. That is, the dicing features of this disclosure segment the gate structure individually without the aid of dielectric fins or hybrid fins. In some cases, the dicing features of this disclosure can even extend horizontally through multiple gate structures or vertically through one or more dielectric features or dielectric layers above the gate structures. The process of this disclosure is not only formed from the back side but is also self-aligned to avoid defects associated with mask misalignment. Embodiments of this disclosure can continuously reduce cell height while maintaining or increasing the process window.

[0017] In one example, this disclosure can be implemented in a nanosheet-based semiconductor device. In this regard, a nanosheet-based device (sometimes interchangeably referred to as a gate-all-around (GAA) device, a multi-bridge channel (MBC) device, a gate-around transistor (SGT), or other similar names) comprises multiple channel layers, one channel layer stacked on top of another. The channel layers of a nanosheet-based device can include any suitable shape and / or configuration. For example, the channel layer can be one of many different shapes, such as a wire (or nanowire), a sheet (or nanosheet), a rod (or nanorod), and / or other suitable shapes. In other words, the term nanosheet-based device broadly encompasses devices having channel layers with nanowires, nanorods, and any other suitable shapes. The channel layer connects a pair of source / drain features such that charge carriers can flow from the source region to the drain region through the channel layer during operation (e.g., when the transistor is turned on). Furthermore, an internal spacer is formed between the source / drain features and the gate electrode such that the source / drain features can be shielded from operation targeting the gate electrode.

[0018] Nanosheet-based devices may include multiple fin structures on top (or front) of a semiconductor substrate, each of which includes a channel layer, source / drain features, and internal spacers formed thereon. Dielectric fins of a low-k dielectric material are formed between adjacent fin structures. Gate electrodes are formed above and between the channel layers of the fin structures, and above the dielectric fins. In some approaches, these dielectric fins serve as a substrate for subsequently formed gate cleaving features, which, together with the dielectric fins, isolate each gate electrode into multiple segments. However, the mere presence of these dielectric fins may limit the material flow designed to reach the sacrificial layer between or around the channel layers, as they are very close to the sidewalls of the channel layers. For example, in a channel release process, etch chemicals are expected to flow around the top of the dielectric fins and reach the sacrificial layer between the channel layers; and byproducts of the etch process are expected to flow around the top of the dielectric fins and leave the system. Such limitations may cause certain regions of the sacrificial layer to remain even after the channel release process is complete. For example, in the gate layer deposition process, the gate layer precursor material is expected to flow around the top of the dielectric fins to reach the space between the channel layers and form the gate layer therebetween. Such constraints can similarly cause the space regions to be not fully filled, leaving gaps. Ultimately, these defects can lead to work function shifts and undesirable changes in the design threshold voltage.

[0019] One approach to addressing the aforementioned problems associated with gate isolation schemes is to configure the dielectric fins away from the sidewalls of the channel layer, which unfortunately hinders cell height reduction. Another approach is to trim the dielectric fins to reduce their width. However, in methods where the dielectric fins are used as part of the gate isolation structure, this reduced lateral width can lead to time-degraded dielectric breakdown (or TDDB) performance. Therefore, this disclosure provides an alternative method in which the gate cleaving feature is formed independently of the dielectric fins. More specifically, the dielectric fins are entirely replaced by a new gate cleaving feature on the back side of the substrate (or below the substrate). Thus, the dielectric fins can be trimmed to allow for further reduction without concern for TDDB failure or the aforementioned defects. Other advantages can also be achieved, including an increased processing window, improved performance, and easy integration with power rails on the back side of the cell.

[0020] The nanosheet-based devices described herein can be complementary metal-oxide-semiconductor (CMOS) devices, p-type metal-oxide-semiconductor (PMOS) devices, or n-type metal-oxide-semiconductor (NMOS) devices. Those skilled in the art will recognize other examples of semiconductor devices that can benefit from the aspects of this disclosure. Furthermore, while this disclosure uses nanosheet-based devices as examples, those skilled in the art will recognize other examples of semiconductor devices that can benefit from the aspects of this disclosure. For example, other types of metal-oxide-semiconductor field-effect transistors (MOSFETs) can benefit from this disclosure, such as planar MOSFETs, FinFETs, and other multi-gate FETs.

[0021] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figures 1A-1C A flowchart of a method 100 for forming a semiconductor device according to an embodiment of the present disclosure is shown. Method 100 is merely an example and is not intended to limit the present disclosure to what is expressly described in method 100. Additional steps may be provided before, during, or after method 100, and some described steps may be replaced, eliminated, or moved for other embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2-18 and Figures 19A-26A Description method 100, Figures 2-18 and Figures 19A-26A These are three-dimensional (3D) views of the workpiece 200 at different manufacturing stages according to an embodiment of method 100. Figures 19B-25B , Figure 25B-1 , Figure 25B-2 , Figure 25B-3 , Figure 25B-4 , Figure 26B and Figure 26B-1 Workpiece 200 is along respectively Figures 19A-26A A cross-sectional view of line B-B'; Figure 24C , Figure 25C , Figure 25C-1 , Figure 25C-2 , Figure 25C-3 , Figure 26C and Figure 27 Workpiece 200 is along respectively Figures 25A-26A A cross-sectional view along line C-C'. Since workpiece 200 will be manufactured into a semiconductor device at the end of the manufacturing process, workpiece 200 may be referred to as semiconductor device (or device) 200 depending on the context. Furthermore, throughout this application, the same reference numerals denote the same features unless otherwise specified.

[0022] The accompanying drawings summarize features of several embodiments to enable those skilled in the art to better understand the following detailed description. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of this disclosure.

[0023] refer to Figure 1A and Figure 2 Method 100 includes block 102, wherein a workpiece 200 is received. Figure 2 The workpiece 200 is shown with its front side facing upwards. That is to say, it has not yet been... Figure 2 The workpiece 200 shown performs a back-side process. Workpiece 200 includes a substrate 202. In one embodiment, substrate 202 includes silicon (Si). In other embodiments, substrate 202 may also include other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Workpiece 200 includes a first base 202-1 and a second base 202-2, each base being patterned from substrate 202 and sharing the same composition as substrate 202. In some embodiments, bases 202-1 and 202-2 are spaced apart by a distance t0. In some embodiments, distance t0 is from about 14 nm to about 50 nm. If distance t0 is too small, for example less than about 14 nm, the isolation between adjacent fins may be insufficient; while if distance t0 is too large, for example greater than about 50 nm, it may hinder the shrinkage process. In some embodiments, the distance between adjacent fins in different pairs may be different, such as... Figure 2 As shown. As described later, the distance t0 determines the width of the hybrid fin structure formed therein along the X direction. Although the substrate 202 is Figure 2 The figures are shown, but may be omitted from at least some other figures for simplicity. The first base 202-1 and the second base 202-2 are spaced apart from each other by an isolation feature 204. In some embodiments, the isolation feature 204 is deposited in a trench between and around the bases 202-1 and 202-2. The isolation feature 204 may also be referred to as a shallow trench isolation (STI) feature 204. The isolation feature 204 may comprise silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0024] Workpiece 200 includes a plurality of vertically stacked channel layers 208 over a first base 202-1 and another plurality of vertically stacked channel layers 208 over a second base 202-2. In the depicted embodiment, two (2) vertically stacked channel layers 208 are disposed over each of the first base 202-1 and the second base 202-2, which is for illustrative purposes only and is not intended to limit the scope beyond that specifically set forth in the claims. The channel layers 208 may be formed of a semiconductor material similar to that of the substrate 202. In one embodiment, the channel layer 208 may comprise silicon (Si). The channel layers 208 are perpendicularly spaced from each other and further spaced from the substrate 202 by sacrificial layers 206. The material composition of the sacrificial layer 206 allows for etch selectivity in a subsequent channel release process. For example, in such a channel release process, the sacrificial layer 206 can be completely removed without substantially affecting the channel layers 208. In some embodiments, the sacrificial layer 206 comprises silicon germanium (SiGe). In some embodiments, each of the channel layers 208 has a thickness of about 4 nm to about 12 nm. If the thickness of the channel layer is too small, the resistance may be too high; if the thickness is too large, the gate control in the middle portion of the channel layer may be weak. The channel layer 208, the sacrificial layer 206, and the base 202-1 or 202-2 together form a fin structure 211. The fin structures 211 are partially separated from each other by isolation features 204. Furthermore, in some embodiments, each of the fin structures 211 also includes a layer 209 on the top surface of the topmost sacrificial layer 206. Layer 209 can protect the topmost channel layer 208 in subsequent processing.

[0025] refer to Figure 1A and Figure 3 Method 100 includes block 104, wherein a cladding layer 216 is formed on the sidewall surfaces of channel layer 208 and sacrificial layer 206. In some embodiments, cladding layer 216 may have a composition similar to that of sacrificial layer 206. This common composition allows for efficient and selective removal of sacrificial layer 206 and cladding layer 216 in subsequent processes without adversely affecting channel layer 208 (e.g., formed of Si). In one example, cladding layer 216 may be formed of SiGe. In some embodiments, cladding layer 216 may be conformally and epitaxially grown using VPE or MBE, followed by etch-back to remove portions located on top of fin structure 211 and on top of isolation feature 204. In some alternative embodiments, cladding layer 216 may be deposited using CVD, ALD, other suitable deposition methods, or combinations thereof. Example etch-back processes may be dry etching processes that include plasma using hydrogen bromide (HBr), oxygen (O2), chlorine (Cl2), or mixtures thereof. In some cases, the coating layer 216 may have a thickness between about 5 nm and about 10 nm.

[0026] Furthermore, a dielectric layer 218 is formed on the sidewall surface of the overlay layer 216 and the top surface of the isolation feature 204. In some embodiments, the dielectric layer 218 may comprise a material with a k-value greater than that of silicon dioxide. In some embodiments, the dielectric layer 218 may comprise a material with a k-value greater than about 7. Therefore, the dielectric layer 218 may alternatively be referred to as a high-k dielectric layer 218. In some embodiments, the dielectric layer 218 may comprise hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), or hafnium silicon oxide (HfSiO2). x ), Hafnium aluminum oxide (HfAlO) x Zirconia (ZrO2), aluminum oxide (Al2O3), other suitable high-k materials, or combinations thereof. In some embodiments, the dielectric layer 218 is formed by conformally depositing a high-k dielectric material on the top surface of the workpiece 200. In some embodiments, the dielectric layer 218 may have a thickness of about 2 nm to about 6 nm.

[0027] Further, another dielectric layer 220 is formed on and between portions of dielectric layer 218. In some embodiments, dielectric layer 220 may comprise a material with a k value less than about 7, and is therefore interchangeably referred to as low-k dielectric layer 220. For example, in some embodiments, dielectric layer 220 may comprise silicon carbonitride (SiCN), silicon carbide (SiOC), or silicon carbonitride oxynitride (SiOCN). In some embodiments, a chemical mechanical polishing (CMP) operation is performed to remove material on and above the top surface of layer 209 and to planarize the top surface of workpiece 200. Thus, portions of dielectric layer 218 on the top surface of layer 209 are removed.

[0028] refer to Figure 1A and Figure 4 Method 100 includes block 106, wherein dielectric layers 218 and 220 are vertically recessed such that the top surfaces of dielectric layers 218 and 220 extend below the top surface of layer 209, thereby forming a trench between them. In some embodiments, the recessed surfaces of dielectric layers 218 and 220 extend below the bottom surface of layer 209 but above the bottom surface of the topmost sacrificial layer 206. For example, in the depicted embodiment, the recessed surfaces of dielectric layers 218 and 220 extend generally along the top surface of the topmost channel layer 208 and the bottom surface of the topmost sacrificial layer 206. As will be described, a dielectric material different from dielectric layer 220 is subsequently formed on the top surface, thereby forming a hybrid fin structure. In some cases, placing the material interface at this height level relative to the channel layer allows for the appropriate formation of gate cleavage features from this combination of dielectric materials without complex processing.

[0029] refer to Figure 1A and Figure 5Method 100 includes block 108, wherein another dielectric layer 222 is formed within a trench between adjacent layers 209 (e.g., between portions of overlay layer 216). In some embodiments, dielectric layer 222 may include hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), or hafnium silicon oxide (HfSiO). x ), Hafnium aluminum oxide (HfAlO) x Zirconia (ZrO2), alumina (Al2O3), other suitable high-k materials, or combinations thereof. In other words, dielectric layer 222 can also be a high-k dielectric layer. In some embodiments, the material of dielectric layer 222 may be the same as or similar to the material of dielectric layer 218, but different from the material of dielectric layer 220. In some embodiments, dielectric layer 222 protects the underlying dielectric layer 220 during subsequent etching operations (e.g., during source / drain trench formation processes) to prevent bridging between adjacent features (e.g., adjacent source / drain features). CMP operations can be performed to planarize the top surface of workpiece 200. During this processing stage, dielectric layers 218, 220, and 222 collectively form hybrid fins 224. Hybrid fins 224 are formed on the sidewall surfaces of overlay layer 216 and on the top surface of isolation feature 204. In some embodiments, the dimension of dielectric layer 220 along the X direction is thickness t1. As mentioned above, fin structures 211 may have different spacings from each other. Therefore, thickness t1 may vary in different regions. In some embodiments, the thickness t1 is from about 5 nm to about 40 nm. For example, the thickness t1 in the first region can be from about 5 nm to about 15 nm; while the thickness t1 in the second region can be from about 10 nm to about 40 nm.

[0030] refer to Figure 1A and Figure 6 Method 100 includes frame 110, in which layer 209 and topmost sacrificial layer 206 are removed, thereby exposing topmost channel layer 208. Thus, the top of dielectric layer 222 protrudes above the top surface of workpiece 200 (and the top surface of topmost channel layer 208).

[0031] refer to Figure 1A and Figure 7Method 100 includes block 112, wherein a dummy gate stack 230 is formed on fin structure 211. In some embodiments, the dummy gate stack 230 extends perpendicular to the longitudinal direction of fin structure 211. For example, in the depicted embodiment, fin structure 211 extends along the Y direction; and dummy gate stack 230 extends along the X direction. In some embodiments, a gate replacement process (or post-gate process) is performed later, wherein the dummy gate stack 230 serves as placeholders for subsequently formed functional gate structures. Other processes and configurations are possible. Each dummy gate stack 230 includes a dummy gate electrode layer 226 (e.g., including polycrystalline silicon) and a dummy gate dielectric layer 225. In some embodiments, the dummy gate stack 230 may also include other layers, such as interface layers, hard mask layers, other suitable layers, or combinations thereof. The layers of the dummy gate stack 230 can be formed by any suitable method, such as CVD.

[0032] refer to Figure 1A and Figure 8 Method 100 includes block 114, wherein a gate spacer 234 is formed around the top and sidewall surfaces of the dummy gate stack 230. The gate spacer 234 may include one or more gate spacer layers, each comprising a dielectric material, such as allowing selective removal of the dummy gate stack 230 without affecting the dielectric material of the gate spacer 234. Suitable dielectric materials may include SiON, SiCN, SiOC, SiOCN, SiN, other low-k dielectric materials, or combinations thereof. The gate spacer 234 may be conformally deposited on the workpiece 200 using CVD, subatmospheric CVD (SACVD), or ALD. In some embodiments, the gate spacer 234 is etched back. The gate spacer 234 and the dummy gate stack 230 together form a gate structure 250. Reference Figure 1B and Figure 9 Method 100 includes block 116, wherein source / drain trenches 236 are formed on both sides of a dummy gate stack 230 using anisotropic etching, wherein the dummy gate stack 230 and gate spacer 234 serve as an etching mask. Figure 9In some embodiments shown, the operation at block 116 can substantially completely remove the channel layer 208 and sacrificial layer 206 in the corresponding region and further recess them into bases 202-1 and 202-2. Thus, the source / drain trenches 236 each extend below the top surface of the isolation feature 204. Anisotropic etching can include a dry etching process or a suitable etching process. For example, a dry etching process can be implemented using oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. During anisotropic etching, the presence of dielectric layer 222 protects the low-k dielectric material of the underlying dielectric layer 220. In the depicted embodiments, dielectric layer 222 is substantially retained, but in some other embodiments (not depicted), dielectric layer 222 is partially or completely removed.

[0033] The source / drain trench 236 exposes the sidewall surfaces of the channel layer 208 and the sacrificial layer 206. (Reference) Figure 10 Method 100 includes forming an internal spacer feature 242. For example, a sacrificial layer 206 exposed in a source / drain trench 236 is first selectively and partially recessed to form an internal spacer recess, while the exposed channel layer 208 is substantially unetched due to etch selectivity. Additionally, a portion of a cladding layer 216 is also etched during this process, for example because the cladding layer 216 has the same or similar material as the sacrificial layer 206 (e.g., SiGe). An internal spacer material is then deposited on the workpiece 200 using CVD or ALD, including on and within the internal spacer recess 238. The internal spacer material may include SiON, SiCN, SiOC, SiOCN, SiN, other low-k dielectric materials, or combinations thereof. Subsequently, the internal spacer material located outside the internal spacer recess is etched back to form the internal spacer feature 242.

[0034] refer to Figure 1B and Figure 10Method 100 includes block 118, forming source / drain features 245 in the remaining portion (if any) of the source / drain trench 236 and the internal spacer recess. In some embodiments, the source / drain features 245 can be formed by epitaxial processes, such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The source / drain features 245 can be n-type or p-type. The n-type source / drain features 245 can include silicon (Si) and can be doped with an n-type dopant, such as phosphorus (P) or arsenic (As). The p-type source / drain features 245 can include silicon germanium (SiGe) or germanium (Ge) and can be doped with a p-type dopant, such as boron (B) or gallium (Ga). In some embodiments, overgrowth of the epitaxial material may cause the source / drain features 245 to merge over the internal spacer features 242. However, the source / drain features 245 may terminate before their side surfaces covering the dielectric layer 222. In some embodiments, the presence of dielectric layer 222 prevents adjacent source / drain features 245 from merging (or bridging) with each other. In some embodiments, dielectric layer 222 may be partially or completely removed. For example, the remaining height of dielectric layer 222 along the Z direction may be up to about 16 nm.

[0035] refer to Figure 1B and Figure 11Method 100 includes block 120, in which a contact etch stop layer (CESL) 243 and an interlayer dielectric (ILD) layer 244 are deposited. In the example process, CESL 243 is first conformally deposited on workpiece 200 (including, for example, on the surface of source / drain features 245, such as on the sidewall and top surfaces of dielectric layer 222), and then ILD layer 244 is blanket-deposited on CESL 243. CESL 243 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. CESL 243 may be deposited using ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 244 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxides (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)) and / or other suitable dielectric materials. The ILD layer 244 can be deposited by spin coating, FCVD processes, or other suitable deposition techniques. To remove excess material and expose the top surface of the dummy gate electrode 226 of the dummy gate stack 230, a planarization process (e.g., chemical mechanical polishing (CMP)) can be performed on the workpiece 200 to provide a flat top surface. Furthermore, in the depicted embodiments, the ILD layer 244 is recessed to reduce its height. In some embodiments, a hard mask layer 246 is formed on the top surface of the ILD layer 244, which serves to protect the ILD in subsequent processing. The ILD layer 244 and the hard mask layer 246 are formed on and between the side surfaces of the gate spacers 234 of the gate structure 250. In some embodiments, a gate definition step (e.g., using a diced polyoxide defined edge (CPODE) process) is performed to define the length of the subsequently formed gate structure 250'. During this processing stage, in some embodiments, the top surface of the dummy gate electrode 226 is exposed on a flat top surface.

[0036] refer to Figure 1B and Figure 12Method 100 includes block 122, in which a dummy gate stack 230 (e.g., a dummy gate electrode layer 226 and a dummy gate dielectric layer 225) is recessed but not completely removed. Thus, a gate trench is formed on top of the recessed dummy gate electrode 226 and between adjacent gate spacers 234. In some embodiments, the remaining portion of the dummy gate electrode 226 protects the channel layer 208 beneath the dummy gate electrode 226 during subsequent recessing of the dielectric layer 222. Without this protection, the channel layer 208 could be damaged. The recessing of the dummy gate electrode 226 can be performed by any suitable method without damaging the gate spacers 234. In some embodiments, the etch duration is adjusted to control the amount of the recessed dummy gate electrode 226 and the height of the remaining dummy gate electrode 226. In some embodiments, the remaining portion of the dummy gate electrode may have a height h. In some embodiments, the height h may be from about 3 nm to about 30 nm. In some embodiments, the ratio of height h to the thickness of the channel layer may be from about 1:1 to about 1:18. If the height h is too small or the proportion is too small, the protective function may be ineffective; if the height h is too large or the proportion is too large, it may hinder subsequent etching of the dielectric layer 222. In some embodiments, the dielectric layer 222 may be etched simultaneously. Alternatively, the dielectric layer 222 may be substantially retained in this process.

[0037] refer to Figure 1B and Figure 13Method 100 includes block 124, wherein the dielectric layer 222 is selectively recessed without substantially damaging the remaining portion of the dummy gate dielectric layer 225 or the dummy gate electrode layer 226. In some embodiments, the dielectric layer 222 is not completely removed. In other words, a portion of the dielectric layer 222 is retained to protect the remaining portion of the hybrid fin 224 in subsequent processing. Without protection, the dielectric layer 220 may be substantially damaged due to its reduced etch selectivity relative to the materials of the dummy gate stack 230, the overlay layer 216, and / or the sacrificial layer 206. This can pose challenges in subsequent processes where the dielectric layer 220 is replaced with a gate dicing feature. For example, the profile and / or dimensions of such a gate dicing feature may be more difficult to control. In some embodiments, the remaining portion of the dielectric layer 222 may have a thickness of about 0.5 nm to about 5 nm. If the thickness is too small, the protection of dielectric layer 220 described herein may not be satisfactory in all cases; while if the thickness is too large, it unnecessarily occupies space that could otherwise accommodate the gate electrode layer, resulting in an unnecessary increase in resistance. In some other methods not implemented in this disclosure, dielectric layer 222 is removed in a substantially later processing stage. Removing dielectric layer 222 at this processing stage can be more efficient and less technically challenging than such other methods because there are no other subsequently formed dielectric features (e.g., dielectric features 270 and / or 284 described later) that may need to be protected during removal. Reference Figure 1B and Figure 14 After etching the dielectric layer 222, the recessed dummy gate electrode 226 and the recessed dummy gate dielectric 225 are removed to expose the top surface of the channel layer 208 (box 126 in FIG1).

[0038] refer to Figure 1B and Figure 15A channel release process (or sometimes called a nanostructure formation process) is performed (box 128 of FIG. 1), in which the remaining portions of the cladding layer 216 and the sacrificial layer 206 are selectively removed without substantially damaging the channel layer 208 or the dielectric layer 222. As described above, in the depicted embodiment, the channel layer 208 may comprise Si, while both the cladding layer 216 and the sacrificial layer 206 are formed of SiGe. Therefore, etching parameters can be selected to achieve the desired selectivity. After the channel release process, the channel layers 208 are each exposed circumferentially in 360°. Furthermore, in the depicted embodiment, the channel layers 208 are spaced apart from the dielectric layer 218. For example, the distance between the sidewall surface of the channel layer 208 and an adjacent feature (e.g., the sidewall surface of the dielectric layer 218) is distance D1. Distance D1 can be from about 5 nm to about 20 nm. In some embodiments, distance D1 can be adjusted by adjusting the thickness of the cladding layer 216. In this processing stage, distance D1 is sometimes referred to as the endcap distance. The end cap distance at least partially controls the area between the material entering and flowing into the channel layer.

[0039] refer to Figure 1B and Figure 16Method 100 includes block 130, in which the remaining uncovered portion of dielectric layer 222 and dielectric layer 218 on the sidewall surfaces of dielectric layer 220 are selectively removed without substantially damaging dielectric layer 220 or channel layer 208. Any suitable method capable of achieving this selectivity (e.g., wet etching, dry chemical etching, or a combination thereof) can be used. As a result, the spacing between the sidewall surfaces of channel layer 208 and adjacent features (e.g., dielectric layer 220) is increased. For example, in this processing stage, the distance between the sidewall surfaces of channel layer 208 and dielectric layer 220 is distance D2. Furthermore, the distance between the sidewall surfaces of the base (e.g., base 202-1 or 202-2) and dielectric layer 218 is distance D2. In some embodiments, distance D2 is determined by the sum of the thickness of dielectric layer 218 and the thickness of overlay layer 216. Therefore, distance D2 can be adjusted by adjusting the thickness of dielectric layer 218 and / or overlay layer 216. In some embodiments, the distance D2 can be from about 7 nm to about 22 nm. In other words, the end cap distance decreases from D1 to D2. In some embodiments, the difference between distances D1 and D2 can be from about 2 nm to about 10 nm. If the difference is too small, for example less than about 2 nm, any improvement in material flow or ingress in the region between adjacent channel layers may be negligible. If the difference is too large, for example greater than about 10 nm, the benefit may not justify the increased chip space footprint. In some embodiments, the etching operation may be configured to further retain the portion of dielectric layer 218 below dielectric layer 220 (e.g., the portion between dielectric layer 220 and isolation feature 204) substantially. Furthermore, in some alternative embodiments, the etching operation may also be configured to retain the portion of dielectric layer 222 directly above dielectric layer 220 (e.g., at the opposite end of dielectric layer 220) as the remainder of dielectric layer 218.

[0040] refer to Figure 1B and Figure 17 The method includes block 132, wherein a replacement gate stack (e.g., a high-k metal gate stack) is formed within a gate trench to replace the removed dummy gate stack 230. Note that, for clarity of depiction, the substrate 202 of workpiece 200... Figure 17 Workpiece 200 is shown in an alternative view (e.g., defined by an axis) (described in detail below). Figure 17As shown, a gate dielectric layer 254 is formed on and around each channel layer 208. In the depicted embodiment, the gate dielectric layer 254 includes an interface layer 254A on and around the channel layer 208, and a high-k gate dielectric layer 254B on and around the interface layer 254A. In some embodiments, the interface layer 254A includes silicon oxide. The gate dielectric layer 254B may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer 254B may comprise other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate dielectric layer 254 may be formed by any suitable method, such as CVD, ALD, PVD, other suitable techniques, or combinations thereof. During this processing stage, the dielectric layer 220 is surrounded on three sides by the gate dielectric layer 254 and on the other side by the dielectric layer 222. The gate dielectric layer 254 may have a thickness of about 1.5 nm to about 3 nm.

[0041] Furthermore, a gate electrode layer 255 is formed on and around the gate dielectric layer 254. The gate electrode layer 255 may comprise a single-layer or alternatively a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to improve device performance, a pad layer, a wetting layer, a first adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer 255 may comprise titanium nitride (TiN), aluminum titanium (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof.

[0042] In some embodiments, the gate electrode layer 255 may be recessed. In some embodiments, the height dimension H3 of the gate electrode 255 between the top surface of the gate dielectric layer 254 of the topmost channel layer 208 and the bottom surface of the gate electrode capping layer 253 may be from about 8 nm to about 30 nm. If the height dimension H3 is too small, the resistance within the gate electrode layer 255 may be high; while if the height dimension is too large, the benefits may not justify the material cost. For example, the gate electrode capping layer 253 may be formed therein by depositing one or more conductive materials on the recessed gate electrode layer 255, and then performing a CMP process on the one or more conductive materials. The gate electrode capping layer 253 may reduce the gate resistance, protect the gate electrode layer 255, and in some cases serve as an etch stop layer during subsequent via trench formation. In one embodiment, the gate electrode capping layer 253 comprises tungsten.

[0043] The gate dielectric layer 254 and the gate electrode 255 together form a high-k metal gate stack. The high-k metal gate stack and the gate spacer 234 together form a replacement gate structure 250', which replaces the above-mentioned... Figure 8 The original gate structure 250 is described. In some embodiments, one or more gate self-aligned contact (SAC) dielectric layers, such as SAC dielectric layers 256A and 256B, are formed to cover the gate structure 250' and the gate spacer 234. In some embodiments, the gate SAC dielectric layers 256A and / or 256B may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, and / or combinations thereof.

[0044] Furthermore, source / drain contacts 260 are formed on the source / drain feature 230. The source / drain contacts 260 may include titanium nitride (TiN), tantalum (Ta), titanium (TiN), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), aluminum (Al), molybdenum (Mo), titanium silicide (TiSi), tungsten silicide (WSi), platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi), or combinations thereof. In some embodiments, a silicide is formed between the source / drain contacts 260 and the source / drain feature 230. Additionally, further ILD layers, via features, intermetallic dielectric (IMD) layers, and / or passivation layers may be formed on the workpiece 200, for example, electrically connected to the source / drain contacts 260. These layers or features are collectively referred to as MEOL / BEOL features 258.

[0045] refer to Figure 17 and Figure 18 Method 100 includes flipping the workpiece 200 up and down to process it from its back side, such as with 2- Figure 16 compared to Figure 18The changes on the upper coordinate axis are shown. To flip the workpiece 200 upside down, a carrier wafer 301 can be bonded to the front side of the workpiece 200 away from the substrate 202. In some embodiments, the carrier wafer 301 can be bonded to the workpiece 200 by fusion bonding, by using an adhesive layer, or a combination thereof. In some cases, the carrier wafer 301 can be formed of a semiconductor material (e.g., silicon), sapphire, glass, a polymeric material, or other suitable material. In embodiments using fusion bonding, the carrier wafer 301 includes a bottom oxide layer and the workpiece 200 includes a top oxide layer. After both the bottom and top oxide layers have been processed, they are placed in fuzzy contact with each other for direct bonding at room temperature or elevated temperatures. Once the carrier wafer 301 is bonded to the workpiece 200, the workpiece 200 is flipped upside down, as... Figure 18 As shown in the accompanying figures. For simplicity, the figures already shown in the following figures are omitted. Figure 18 Some features are shown, such as carrier wafer 301.

[0046] After workpiece 200 is flipped, refer to Figure 1C and Figure 18 Method 100 includes block 134, where a chemical mechanical polishing (CMP) is used to planarize the back side of workpiece 200 until the isolation feature 204 is exposed on the back side of workpiece 200, with the back side of workpiece 200 now facing upwards. A first base 202-1 and a second base 202-2 (not shown) are also exposed on the back side of workpiece 200, and they are then selectively etched to form trenches exposing the back side of gate structure 250' (e.g., gate dielectric layer 254). The trenches also expose the surface of source / drain feature 230 and the sidewalls of isolation feature 204. In some embodiments, the operation at block 134 applies an etching process tailored to be selective for the semiconductor material (e.g., silicon) in the bases 202-1 / 202-2, without (or minimally) etching the gate structure 250' (e.g., gate dielectric layer 254), isolation feature 204, CESL 243, and internal spacer feature 242. In the illustrated embodiment, the etching process terminates upon reaching the gate dielectric layer 254. Therefore, the source / drain feature 230 is essentially not recessed. For example, the current top surface (i.e., the original bottom surface) of the source / drain feature 230 is aligned with the surface of the inner spacer feature 242. In some other alternative embodiments, the source / drain feature 230 may be further recessed such that the current top surface of the source / drain feature 230 extends below the current top surface of the inner spacer feature 242. The operation of block 134 may employ one or more etching processes, such as dry etching, wet etching, reactive ion etching, other etching methods, or combinations thereof.

[0047] Still referencing Figure 1C and Figure 18Method 100 includes block 136, wherein a back dielectric layer 270 having one or more dielectric materials is deposited to fill trenches and cover the exposed bottom surfaces of gate structure 250' and source / drain features 230. In some embodiments, the back dielectric layer 270 may include one or more of the following: SiO2, SiN, SiCN, SiOC, SiOCN, SiO x N y C z (One or more) other suitable materials or combinations thereof. In some embodiments, the back dielectric layer 270 may be formed by PE-CVD, F-CVD or other suitable methods. Subsequently, the back dielectric layer 270 is planarized by a CMP process to expose the isolation feature 204. In some embodiments, the back dielectric layer 270 and the isolation feature 204 may comprise different materials, such that the isolation feature 204 can be used as a CMP stop. During this processing stage, the source / drain feature 245 is vertically sandwiched between the source / drain contact 260 and the back dielectric layer 270.

[0048] refer to Figure 1C and Figures 19A-19B Method 100 includes block 138, wherein a patterned hard mask 280 is formed covering the back side of workpiece 200 while simultaneously exposing the region forming the dicing feature. In an example process, a hard mask layer is blanket-deposited over the back side of workpiece 200 using CVD. The hard mask layer can be a single layer or multiple layers. When the hard mask layer is multilayer, it may include a titanium nitride (TiN) layer bonded to the back dielectric layer 270 and the isolation feature 204, and a silicon nitride (SiN) layer bonded to the TiN layer. Subsequently, photolithography and etching processes can be performed to pattern the hard mask layer to form the patterned hard mask 280. In some cases, a photoresist layer is deposited over the hard mask layer. To pattern the photoresist layer, the photoresist layer is exposed to radiation reflected from or transmitted through the photomask, baked in a post-exposure bake process, and developed in a developer. A patterned photoresist layer is then used as an etching mask to etch a hard mask layer, thereby forming a patterned hard mask 280. As shown, the patterned hard mask 280 includes a mask opening 281 that is substantially aligned with a guide opening 282 to be formed. In some embodiments, the patterned hard mask 280 is used to mask un-etched portions of the isolation feature 204. In some embodiments, the etching process is configured to be selective on the isolation feature 204 and substantially not etch the back dielectric layer 270. Therefore, the mask opening 281 may or may not expose a portion of the back dielectric layer 270. In other words, the guide opening 282 can still be successfully formed even when the mask opening 281 is larger than the width of the isolation feature 204 or is misaligned.

[0049] In some embodiments, the mask opening 281 may have a dimension D3 along the Y direction and a dimension D4 along the X direction. In the depicted embodiment, dimension D3 is configured to extend along the Y direction across the entire width of the gate structure (in other words, dimension D3 is greater than the width of the gate structure 250' along the Y direction) and extend into the region above the source / drain feature 245. In the depicted embodiment, the mask opening 281 extends above the p-type source / drain feature 245A and the n-type source / drain feature 245B (collectively referred to as source / drain feature 245). Note that... Figure 19A A portion of the gate structure 250' and a portion of the mask opening 281 are illustrated. Therefore, the illustrated dimension D3' is smaller than dimension D3. Furthermore, in the depicted embodiment, dimension D4 is configured to extend along the X direction across the entire width of the isolation feature 204 (denoted as width D6) (in other words, dimension D4 is larger than the width of the isolation feature 204 along the X direction) and extend into the region vertically above the channel layer 208. During this processing stage, the endcap distances on both sides of the dielectric layer 220 are each distance D5. Distance D5 can be determined by distance D2 and the thickness of the gate dielectric layer 254. On the other hand, the hybrid fin structure 224 (e.g., including dielectric layers 220, 222, and 218) can have a width D9 along the X direction. Width D9 is determined by the sum of twice the thickness of dielectric layer 218 and the thickness t1 of dielectric layer 220 (see [reference]). Figure 4 ).

[0050] refer to Figure 1C and Figures 20A-20B Method 100 includes a block 140 in which a guide opening 282 is formed. In some embodiments, the isolation feature 204 is selectively and anisotropically etched to form the guide opening 282. In some embodiments, the isolation feature 204 can be etched using a dry etching process (e.g., reactive ion etching (RIE)) that uses chlorine (Cl2), oxygen (O2), boron trifluoride (BCl3), carbon tetrafluoride (CF4), or a combination thereof. Figures 20A-20B As shown, the guide opening 282 may terminate on the top-facing (or back-facing) surface of the gate dielectric layer 254, gate spacer 234, and CESL 243, without extending into the gate electrode layer 255 of the gate structure 250'. As described above, the width of the guide opening 282 in the X direction is substantially determined by the width D6 of the isolation feature 204 and is smaller than the width D4 of the mask opening 281; and the width in the Y direction is substantially determined by the width D3 of the mask opening 281. In some embodiments, the guide opening 282 exposes the back-facing surface of the dielectric layer 218 above the dielectric layer 220, as well as a portion of the source / drain feature 245. Figure 20BAs shown, in the depicted embodiment, the guide opening 282 exposes portions of the source / drain features 245A and 245B.

[0051] refer to Figure 1C and Figures 21A-21B Method 100 includes a frame 142 in which a pad 284 is deposited along the sidewall of a guide opening 282 and the size of the guide opening 282 is reduced, for example, from D4 to D8 along the X direction. The pad 284 defines the distance between the formed gate dicing feature and the channel layer 208. The pad 284 may be referred to as a dicing metal gate capping layer. The pad 284 also serves to protect the source / drain feature 245 from subsequent etching processes. The pad 284 may be a single layer or multiple layers. In an example process, at least one dielectric material is deposited on the back side of workpiece 200, and then the deposited dielectric material is anisotropically etched back to expose the gate dielectric layer 254. In some cases, the at least one dielectric material used for the pad 284 may include silicon, oxygen, nitrogen, or carbon. For example, at least one dielectric material may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonoxide, or silicon oxynitride. After the etch-back process, the pad 284 may have a thickness D7 between about 2 nm and about 12 nm. If the thickness D7 is too small, unintentional excessive etching of the gate electrode material may occur in some cases; while if D7 is too large, subsequent formation and extension of the gate dicing opening may be difficult. In some embodiments, the thickness D7 may be equal to half the difference between D4 and D8. In the depicted embodiment, the pad 284 covers the otherwise exposed portions of the source / drain features 245A and 245B (compare to...). Figure 20B Furthermore, the pad 284 is not formed on the back-facing surface of the dielectric layer 218, but is instead formed specifically on the top surface of the gate dielectric layer 254. In some embodiments, the pad 284 further assists in defining and adjusting the end cap distance, as described in detail later.

[0052] Still referencing Figure 1C and Figures 21A-21B Method 100 includes frame 144, wherein, upon completion of pad 284, dielectric layer 218 still exposed in guide opening 282 is removed (see [link to documentation]). Figure 20A The gate dicing opening 286 is formed by removing the dielectric layer 220 below the gate dielectric layer 254 and the dielectric layer 220. In some embodiments, this may be a multi-step etching operation. In some embodiments, the removal of the dielectric layer 220 may be performed by selectively removing material from the dielectric layer 220 without substantially damaging the parameters of the gate dielectric layer 254. Therefore, after removal, the gap width of the gate dicing opening 286 is substantially determined by the width t1 of the dielectric layer 220 (see...). Figure 4The gap width t1 is determined and therefore also referred to as the gap width t1. In some embodiments, the gap width t1 is less than the distance D8. In some embodiments, the gate cutout 286 extends into the source / drain region, such as Figure 21B As shown. Therefore, dielectric layer 222 is exposed in gate dicing opening 286.

[0053] The method continues to extend the gate cleavage opening 286 through the gate structure 250'. In the depicted embodiment, this extension is a multi-step process. (See reference...) Figure 1C and Figures 22A-22B Method 100 includes block 146, in which the gate dielectric layer 254 is removed, thereby exposing the surface of the underlying gate electrode layer 255. For example, anisotropic etching (e.g., dry plasma etching) can be performed to remove the gate dielectric layer 254. Alternatively, isotropic etching (e.g., wet etching or dry chemical etching) can be performed to remove the gate dielectric layer 254. Meanwhile, the gate dielectric layer 254 surrounding the channel layer 208 is not exposed at this processing stage, so that they are unaffected by the removal process. At this processing stage, the endcap distance (referred to as distance D11) can be similar to distance D5.

[0054] During this processing stage, the surface of the gate electrode layer 255 is exposed in the gate dicing opening 286. (Reference) Figure 1C and Figures 23A-23B Method 100 includes block 148, in which the gate electrode layer 255 can be recessed. For example, as Figure 23A As shown, the gate electrode layer 255 is laterally recessed and the gate dicing opening 286 is laterally widened. Therefore, the width of the gate opening 286 along the X direction increases to a distance t2, and the endcap distance between the sidewall surface of the gate dielectric layer 254 and the sidewall surface of the gate electrode layer 255 (or the sidewall surface of the gate dicing opening 286) decreases from D11 to D12. In some embodiments, the reduced endcap distance results in a decrease in capacitance between the gate electrodes and a decrease in capacitance between the gate electrode and the source / drain feature 245, thereby improving device performance (e.g., speed). Furthermore, the gate electrode layer 255 is vertically recessed and the gate dicing opening 286 is vertically deepened to reach the back-facing surface of the gate electrode capping layer 253. In some embodiments, the gate electrode capping layer 253 can be used as an etch stop layer during the vertical recessing process. In the depicted embodiment, the newly formed bottom of the gate dicing opening 286 can have a width t3 smaller than the width t2. Meanwhile, the endcap distance located in the source / drain region (see...) Figure 23B The dielectric layer 222 at the bottom of the gate cutout 286 protects the source / drain contact 260 below the dielectric layer 222, thereby minimizing damage to the source / drain contact 260, if any.

[0055] refer to Figure 1C and Figures 24A-24B Method 100 includes block 150, wherein a gate dicing opening 286 is further extended to penetrate the gate electrode capping layer 253, in other words, to reach the surface of the gate SAC dielectric layer 256. In some embodiments, the gate electrode capping layer 253 is etched using the gate SAC dielectric layer 256A as an etch stop layer. In some embodiments, the etch parameters implemented may be the same as those described above regarding... Figure 23A The etching parameters of the previous vertical recess operation are different. Simultaneously, the gate electrode layer 255 can be further laterally recessed during this process, causing the gate dicing opening 286 to be further widened (e.g., to width t4) and the end cap distance to be further reduced (e.g., to distance D13). In some embodiments, the width t4 can be from about 6 nm to about 42 nm. In some embodiments, the distance D13 can be from about 4 nm to about 15 nm. In some embodiments, the width t4 can be significantly larger and the distance D13 can be significantly smaller compared to structures obtained by methods not implementing this disclosure. Compared to those methods, this structure provides improved gate isolation without impairing material flow into the channel release or gate replacement phases. In this processing phase, the gate dicing opening 286 is completed, which separates the otherwise continuous gate structure 250' (and otherwise continuous gate electrode layer 255) into electrically isolated portions, for example, separating them into gate structures 250'-1 and 250'-2.

[0056] The region that forms the gate dicing opening 286 is called the gate dicing region; while the region along the gate structure 250' other than the region that forms the gate dicing opening 286 is called the non-gate dicing region. Figure 24C This is a cross-sectional view of the workpiece 200 along the XZ plane in the gate electrode region. As shown, the end cap distance in the gate dicing region is distance D13; while the end cap distance in the non-gate dicing region is distance D5. Distance D13 is substantially smaller than distance D5. In some embodiments, the ratio of distance D5 to distance D13 is from about 1:0.2 to about 1:0.9. Compared to methods in which all dielectric layers 220 are replaced by gate dicing features with a larger width, the gate resistance is reduced. Furthermore, compared to some other methods where dielectric layer 222 is not removed (remaining between the top surface of dielectric layer 220 and gate electrode cap layer 253), the gate resistance is also reduced due to the continuity of the conductive path and the larger volume.

[0057] In the illustrated embodiment, the operation at block 150 exposes the gate spacer 234 in the lower portion of the gate dicing opening 286. Alternatively, the gate spacer 234 can be further removed in a selective etching process, exposing the CESL 243 in the gate dicing opening 286. In yet another embodiment, the CESL 243 can be further removed in a selective etching process, exposing the ILD layer 244 in the gate dicing opening 286. One benefit of removing the gate spacer 234 and / or the CESL 243 is that the lower portion of the gate dicing opening 286 can extend along the X direction, allowing for the formation of one or more larger volume air gaps(s) in the gate dicing features subsequently formed in the gate dicing opening 286. As described below, the air gaps(s) further improve the isolation between the gate segments.

[0058] refer to Figure 1C and Figures 25A-25C Method 100 includes block 152, wherein a dielectric material is deposited in a gate dicing opening 286 to form a gate dicing feature 288. In some embodiments, the gate dicing feature 288 is formed of a low-k dielectric material to reduce parasitic capacitance. The dielectric material for the gate dicing feature 288 can be deposited using plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), or CVD. In some cases, the dielectric material for the gate dicing feature 288 may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbon oxynitride, or silicon oxynitride. The gate dicing feature 288 may be single-layer or multi-layer. When the gate dicing feature 288 is multi-layered, the gate dicing feature 288 may include a dielectric pad 288A in contact with a gate segment, and a dielectric filler 288B spaced apart from the gate segment by the dielectric pad (see [link to documentation]). Figure 25B-1 and Figure 25C-1 The dielectric pad and dielectric filler can be formed from different materials. For example, the dielectric pad may be oxygen-free, while the dielectric filler may include oxygen. As another example, the dielectric constant of the dielectric pad may be greater than that of the dielectric filler. When the gate dicing feature 288 is multilayered, the thickness of the dielectric pad may be between approximately 1 nm and approximately 6 nm. The operation at block 152 may include performing a planarization process, such as a CMP process, on the gate dicing feature 288 to remove excess dielectric material from the back side of workpiece 200 and expose the back dielectric layer 270, the isolation feature 204, and the pad 284.

[0059] In this processing stage, the workpiece includes a hybrid fin structure 224 (with a width D6 in the upper region and a width D9 in the lower region) separating adjacent source / drain features 245 in the source / drain region; and a gate cleaving feature 288 (with a width t4 in the upper region and a width t5 in the lower region) separating adjacent gate portions 250'-1 and 250'-2 in the gate region. Width t4 is greater than D9. Furthermore, width D9 is approximately equal to twice the thickness of dielectric layer 218 and the sum of D10. Although not explicitly depicted, the gate cleaving feature 288 of this disclosure can span multiple bonded gate structures.

[0060] In some alternative embodiments, the gate dicing opening 286 may have been present. Figure 1C The box 152 extends further. For example, see reference... Figure 25C-2 and Figure 25C-3 The gate cleaving opening 286 may have been extended such that, after the deposition of dielectric material, the gate cleaving feature 288 extends through the gate SAC layer 256A to reach the front-facing surface of the gate SAC layer 256A. Figure 25C-2 ) or further extended into the gate SAC layer 256B ( Figure 25C-3 These solutions further ensure electrical isolation between adjacent gate portions 250'-1 and 250'-2 to guarantee proper device operation. In some embodiments, forming a gate cleavage opening 286 in the source / drain region includes extending through the dielectric layer 222 to expose the back-side surface of the contact feature 260. Therefore, the gate cleavage feature 288 extends through to reach the contact feature 260. In some alternative embodiments, the dielectric layer 222 in the source / drain region has been completely removed (see [link to documentation]). Figure 25B-3 and Figure 25B-4 For example, in relation to Figure 10 The associated processing stage. Therefore, the gate dicing feature 288 similarly extends to reach the back-facing surface of the contact feature 260. Figure 25B-3 ) or further extended to contact feature 260 ( Figure 25B-4 ).

[0061] In some embodiments, reference Figures 26A-26CThe dielectric material of the gate dicing feature 288 covers the air gap (or void) 290 within the gate dicing feature 288. The deposition of the dielectric material of the gate dicing feature 288 can also be referred to as a capping process. In an embodiment, the dielectric material of the gate dicing feature 288 is deposited using a PECVD process, which facilitates the merging of the deposited dielectric material at the top of the narrow opening. Parameters in the PECVD process (e.g., pressure, temperature, and gas viscosity) are adjusted such that the gap-filling behavior of the deposited dielectric material maintains the air gap 290 without completely filling the gate dicing opening 286. In this embodiment, the PECVD process uses a setting of pressure less than about 0.75 Torr and temperature above about 75°C. Therefore, the dielectric material of the gate dicing feature 288 can surround the gate dicing opening 286 without completely filling the lower portion of the gate dicing opening 286, thereby forming the air gap 290. In some embodiments, the air gap 290 may have a width D14. For example, the width D14 may be from about 0.1 nm to about 5 nm. In some embodiments, the ratio of the width D14 of the air gap 290 to the width t4 of the gate dicing feature 288 can be from about 1:50 to about 1:1.2. The air gap 290 can extend continuously from the channel region to the adjacent source / drain region, providing isolation between adjacent gate segments 250-1 / 250-2 and between adjacent source / drain features. A gas (e.g., one or more gases used during the deposition of the dielectric material of the gate dicing feature 288) or any other substance that can diffuse into the air gap 290 can be present in the air gap 290. Alternatively, in some embodiments, the air gap 290 can be omitted, for example, to provide stronger structural support.

[0062] In some embodiments, the air gap 290 extends vertically across a large portion of the height of the gate electrode layer 255. For example, as described above, the gate electrode layer 255 may have a height H1 (measured as a vertical distance between the bottom surface of the gate dielectric layer 254 and the bottom surface of the gate electrode cap layer 253). In some embodiments, the height H1 may be from about 28 nm to about 60 nm. The air gap may have a height H2. In some embodiments, the height H2 may be from about 15 nm to about 60 nm. The ratio of height H2 to height H1 may be from about 50% to about 95%. In some embodiments, the air gap 290 extends across the height dimension of all suspended channel layers. For example, the bottommost channel layer 208 may have a bottom surface 310, and the topmost channel layer 208 may have a top surface 312. Both surfaces 310 and 312 lie between the bottom surface 320 and the top surface 322 of the air gap 290. Compared to other methods in which the air gap 290 has a smaller height, Figure 26A The described configuration further reduces capacitance and improves device performance. In some embodiments, reference... Figure 26B The air gap 290 is confined within the gate region. Alternatively, refer to Figure 26B-1 The air gap 290 extends further into the source / drain region. In some embodiments, this configuration reduces capacitance in the source / drain region and also improves device characteristics.

[0063] refer to Figure 1C and Figure 27 Method 100 includes block 154, wherein a gate via 295 is formed from the front side of the device. For example, the gate via 295 extends through gate SAC layers 256B, 256A to reach gate electrode cap layer 253. (See reference...) Figure 1C Method 100 includes block 156, in which additional device features can be formed. For example, source vias, drain vias, metal lines, and passivation layers can be formed to complete the fabrication of device 200.

[0064] As can be seen from the above disclosure, a semiconductor device is provided, comprising a gate cleaving feature 288 that isolates adjacent gate structure portions 250'-1 and 250'-2. Compared to the hybrid fin structure 224, the gate cleaving feature 288 has an increased width and, in some embodiments, may cover the air gap. These characteristics allow for a reduction in parasitic capacitance. The gate cleaving feature may extend into or beyond the gate SAC layer and may have different profiles. The hybrid fin structure between adjacent channel layers is laterally recessed, thereby increasing the endcap distance between the recessed hybrid fin structure and the channel layer. This improves material flow and reduces defects. Furthermore, in some embodiments, the recessed hybrid fin structure has a front-facing surface directly in contact with the gate structure. Therefore, the height of the gate portion at the location of the hybrid fin structure is increased compared to some other methods. This maximizes the conductive path and reduces the gate resistance. Furthermore, the method of this disclosure forms the gate cleaving feature from the back side of the workpiece. Utilizing the structure of the back side of the workpiece, the formation of the gate cleaving opening of this disclosure is self-aligned and does not depend on the high resolution or high coverage accuracy of the photolithography process. Other advantages may include an increased processing window and easy integration with the power rails on the back of the cell. This results in performance gains by implementing the methods described herein. For example, in some embodiments, the power efficiency (Peff) gain is greater than 5%.

[0065] In one exemplary aspect, this disclosure relates to a semiconductor device. The semiconductor device includes nanostructures arranged perpendicularly to and spaced apart from each other along a first direction. The semiconductor device also includes dielectric fin structures of a dielectric material having a uniform composition, and an isolation structure located on the opposite side of the nanostructures. Furthermore, the semiconductor device includes a gate structure surrounding the nanostructures. The gate structure extends between the nanostructures and the dielectric fin structures, and between the nanostructures and the isolation structure. Additionally, the nanostructures are spaced apart from the dielectric fin structures by a first distance along a second direction perpendicular to the first direction, and spaced apart from the isolation structure by a second distance along the second direction, wherein the first distance is greater than the second distance. Furthermore, the gate structure is in contact with the dielectric fin structures on a surface extending perpendicular to the first direction.

[0066] In some embodiments, the isolation structure extends along a first direction from above the top surface of the gate structure to below the bottom surface of the gate structure. In some embodiments, the dielectric material has a k constant of less than about 7, and the surface is the surface of the dielectric material. In some embodiments, the semiconductor device further includes a dielectric layer in contact with the isolation structure and on the first surface of the gate structure. In some embodiments, the isolation structure includes an air gap. In some embodiments, the air gap extends a first vertical height along the first direction, the gate structure extends a second vertical height along the first direction, and the ratio of the first vertical height to the second vertical height is about 50% to about 95%. In some embodiments, the gate structure includes a gate dielectric layer and a gate electrode layer, wherein the gate electrode layer is in contact with the isolation structure but not with the dielectric fin structure. In some embodiments, the semiconductor device further includes source / drain features connected to the nanostructure. The source / drain features are vertically located between the conductive material and the dielectric substrate, wherein the dielectric substrate is aligned with the nanostructure along the first direction.

[0067] In one exemplary aspect, this disclosure relates to a method. The method includes receiving a workpiece having a front side and a back side. The workpiece includes a first plurality of semiconductor layers over a first base on a front surface of a substrate, and a second plurality of semiconductor layers over a second base on a front surface of the substrate. The workpiece also includes a first dielectric feature and a second dielectric feature. The first dielectric feature is located on a first side of the first plurality of semiconductor layers and between the first plurality of semiconductor layers and the second plurality of semiconductor layers. The second dielectric feature is located on a second side of the first plurality of semiconductor layers, opposite to the first side, and has a feature surface facing the front side. The method further includes forming a gate structure that bonds the first plurality of semiconductor layers and the second plurality of semiconductor layers and is in contact with the first dielectric feature on the feature surface. The method further includes replacing the first base and the second base, respectively, to form a first back side dielectric and a second back side dielectric. Furthermore, the method includes removing the first dielectric feature but not the second dielectric feature, thereby forming an opening between the first plurality of semiconductor layers and the second plurality of semiconductor layers. Furthermore, the method includes recessing the gate structure from the opening to form a gate dicing opening, wherein the gate dicing opening extends from a front surface of the gate structure to a rear surface of the gate structure. Furthermore, the method includes forming a third dielectric feature in the gate dicing opening.

[0068] In some embodiments, the workpiece includes a sacrificial layer between vertically adjacent layers of a first plurality of semiconductor layers and between vertically adjacent layers of a second plurality of semiconductor layers. The workpiece also includes a fourth dielectric feature located on a first dielectric feature. Furthermore, the method includes forming a sacrificial gate structure covering a portion of the first plurality of semiconductor layers, the second plurality of semiconductor layers, and the fourth dielectric feature. The method also includes forming source / drain features on both sides of the sacrificial gate structure, recessing the sacrificial gate structure to expose the top and side surfaces of the fourth dielectric feature, recessing the exposed portion of the fourth dielectric feature to expose the top surface of the first dielectric feature, removing the sacrificial layer to form gaps between adjacent layers of the first plurality of semiconductor layers and between adjacent layers of the second plurality of semiconductor layers, and forming a gate structure in the gaps. In some embodiments, receiving the workpiece includes receiving a workpiece having: a fifth dielectric feature located on a first sidewall of the first dielectric feature and a sixth dielectric feature located on a second sidewall of the second dielectric feature. Furthermore, the method includes removing the fifth and sixth dielectric features, wherein forming the gate structure includes forming a gate structure on the first and second sidewalls. In some embodiments, the first and second dielectric features comprise a first dielectric material, and the fourth dielectric feature comprises a second dielectric material. The first dielectric material has a k value less than about 7, and the second dielectric material has a k value greater than about 7. In some embodiments, forming a sacrificial gate structure comprises forming a sacrificial dielectric layer on the front-facing surface of a first plurality of semiconductor layers. Furthermore, recessing the sacrificial gate structure comprises removing a first portion of the sacrificial gate structure without exposing the front-facing surface. Furthermore, the method comprises removing the remaining portion of the sacrificial gate structure after recessing the fourth dielectric feature. In some embodiments, forming a third dielectric feature comprises configuring the third dielectric feature to include an air gap. In some embodiments, forming a gate structure comprises forming a gate dielectric layer surrounding the semiconductor layers and surrounding the first and second dielectric features, and forming a gate electrode surrounding the gate dielectric layer. Furthermore, recessing the gate structure comprises recessing a portion of the gate dielectric layer surrounding the first dielectric feature to expose a side surface of the gate electrode, and recessing the gate electrode from the exposed side surface. In some embodiments, removing the first dielectric feature includes forming a patterned mask element having an opening aligned with the first dielectric feature on a back-side surface of the workpiece, removing an isolation feature between a first back-side dielectric and a second back-side dielectric to form a back-side trench, forming a pad layer on the sidewall surface of the back-side trench, and using the pad layer as a mask to etch the first dielectric feature. In some embodiments, receiving the workpiece includes receiving a workpiece having a contact feature in contact with one of the source / drain features. The method further includes recessing a fourth dielectric feature to expose a back-side surface of the contact feature. Forming a third dielectric feature includes forming a third dielectric feature on the exposed back-side surface of the contact feature.

[0069] In one exemplary aspect, this disclosure relates to a method. The method includes receiving a workpiece having a front side and a back side, the front side and the back side being opposite to each other in a vertical direction. The workpiece includes a first semiconductor layer stack over a first base on a front surface of a substrate and a second semiconductor layer stack over a second base on a front surface of the substrate, wherein the first stack and the second stack each include a first semiconductor layer and a second semiconductor layer arranged in a vertically staggered manner. The first stack and the second stack each extend longitudinally along a first direction. An isolation feature is interposed between the first base and the second base. The method further includes forming a hybrid structure between the sidewall surfaces of the first stack and the second stack and on a first surface of the isolation feature, wherein the hybrid structure includes a first low-k dielectric layer surrounded by a first high-k dielectric layer, and a second high-k dielectric layer on the first low-k dielectric layer and the first high-k dielectric layer. The method further includes forming a first gate stack on the first stack and the second stack along a second direction perpendicular to the first direction, wherein the first gate stack covers a portion of the second high-k dielectric layer. Furthermore, the method includes forming source / drain features on both sides of the first gate stack, recessing portions of the second high-k dielectric layer not covered by the first gate stack, selectively removing the second semiconductor layer, and recessing the first high-k dielectric layer on the sidewall surface of the first low-k dielectric layer. Additionally, the method includes forming a gate dielectric layer surrounding the first semiconductor layer and the first low-k dielectric layer, a gate electrode layer surrounding the gate dielectric layer, and a gate cap covering the gate electrode layer. Furthermore, the method includes replacing the first and second bases from the back side to form a back dielectric layer, and forming a gate dicing feature that extends vertically through the back dielectric layer, through the gate electrode layer, and through the gate cap.

[0070] In some embodiments, the method further includes removing a recessed portion of the second high-k dielectric layer after selectively removing the second semiconductor layer. Furthermore, forming the gate dicing feature includes removing an isolation feature to expose the sidewalls of the back dielectric layer, removing a first low-k dielectric layer to form a gate dicing opening, wherein the gate dicing opening exposes a portion of the gate dielectric layer, recessing the exposed portion of the gate dielectric layer to expose a portion of the gate electrode layer, laterally and vertically recessing the gate electrode layer to enlarge and extend the gate dicing opening, wherein the gate dicing opening extends through a gate cap, and forming a second low-k dielectric layer in the extended gate dicing opening. In some embodiments, the method further includes bonding the front side of the workpiece to a carrier wafer after forming the gate dielectric layer, the gate electrode layer, and the gate cap, and flipping the workpiece upside down before recessing the back side of the workpiece.

[0071] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0072] Example 1. A semiconductor device, comprising:

[0073] Nanostructures, wherein the nanostructures are arranged perpendicularly along a first direction and spaced apart from each other;

[0074] A dielectric fin structure of a dielectric material with uniform composition, and an isolation structure located on the opposite side of the nanostructure; and

[0075] A gate structure that surrounds the nanostructure, extends between the nanostructure and the dielectric fin structure, and extends between the nanostructure and the isolation structure.

[0076] The nanostructure is spaced apart from the dielectric fin structure by a first distance along a second direction perpendicular to the first direction, and is also spaced apart from the isolation structure by a second distance along the second direction, wherein the first distance is greater than the second distance.

[0077] The gate structure is connected to the dielectric fin structure on a surface extending perpendicular to the first direction.

[0078] Example 2. The semiconductor device according to Example 1, wherein the isolation structure extends along the first direction from above the top surface of the gate structure to below the bottom surface of the gate structure.

[0079] Example 3. The semiconductor device according to Example 1, wherein the dielectric material has a k constant of less than about 7, and the surface is the surface of the dielectric material.

[0080] Example 4. The semiconductor device according to Example 1 further includes: a dielectric layer in contact with the isolation structure and on a first surface of the gate structure.

[0081] Example 5. The semiconductor device according to Example 1, wherein the isolation structure includes an air gap.

[0082] Example 6. The semiconductor device according to Example 5, wherein the air gap extends a first vertical height along the first direction, the gate structure extends a second vertical height along the first direction, and the ratio of the first vertical height to the second vertical height is about 50% to about 95%.

[0083] Example 7. The semiconductor device according to Example 1, wherein the gate structure includes a gate dielectric layer and a gate electrode layer, wherein the gate electrode layer is connected to the isolation structure but not to the dielectric fin structure.

[0084] Example 8. The semiconductor device according to Example 1 further includes: a source / drain feature connected to the nanostructure, the source / drain feature being vertically located between a conductive material and a dielectric substrate, the dielectric substrate being aligned with the nanostructure along the first direction.

[0085] Example 9. A method of forming a semiconductor device, comprising:

[0086] Receive a workpiece having a front and a back side, the workpiece comprising:

[0087] A first plurality of semiconductor layers located on a first base on the front surface of the substrate, and a second plurality of semiconductor layers located on a second base on the front surface of the substrate;

[0088] A first dielectric feature is located on a first side of the plurality of semiconductor layers and between the plurality of semiconductor layers; and

[0089] A second dielectric feature is located on a second side of the first plurality of semiconductor layers, the second side being opposite to the first side, and the second dielectric feature having a feature surface facing the front side;

[0090] A gate structure is formed, which is bonded to the first plurality of semiconductor layers and the second plurality of semiconductor layers and is connected to the first dielectric feature on the feature surface;

[0091] The first base and the second base are replaced respectively to form a first back dielectric and a second back dielectric;

[0092] The first dielectric feature is removed but the second dielectric feature is not removed, thereby forming an opening between the first plurality of semiconductor layers and the second plurality of semiconductor layers;

[0093] The gate structure is recessed from the opening to form a gate cleaving opening, the gate cleaving opening extending from the front surface of the gate structure to the rear surface of the gate structure; and

[0094] A third dielectric feature is formed in the gate dicing opening.

[0095] Example 10. The method according to Example 9, wherein receiving the workpiece includes receiving a workpiece having the following:

[0096] A sacrificial layer is located between vertically adjacent layers of the first plurality of semiconductor layers and between vertically adjacent layers of the second plurality of semiconductor layers.

[0097] The fourth dielectric feature is located on the first dielectric feature;

[0098] The method also includes:

[0099] A sacrificial gate structure is formed, which covers the first plurality of semiconductor layers and the second plurality of semiconductor layers and a portion of the fourth dielectric feature;

[0100] Source / drain features are formed on both sides of the sacrificial gate structure;

[0101] The sacrificial gate structure is recessed to expose the top and side surfaces of the fourth dielectric feature;

[0102] The exposed portion of the fourth dielectric feature is recessed to expose the top surface of the first dielectric feature;

[0103] Remove the sacrificial layer to form gaps between adjacent layers of the first plurality of semiconductor layers and between adjacent layers of the second plurality of semiconductor layers; and

[0104] The gate structure is formed in the gap.

[0105] Example 11. The method according to Example 10, wherein receiving the workpiece includes receiving a workpiece having: a fifth dielectric feature located on a first sidewall of the first dielectric feature and a sixth dielectric feature located on a second sidewall of the second dielectric feature;

[0106] The method further includes: removing the fifth dielectric feature and the sixth dielectric feature.

[0107] The formation of the gate structure includes forming the gate structure on the first sidewall and the second sidewall.

[0108] Example 12. The method according to Example 10, wherein the first dielectric feature and the second dielectric feature comprise a first dielectric material, and the fourth dielectric feature comprises a second dielectric material, and

[0109] The first dielectric material has a k value of less than about 7, and the second dielectric material has a k value of greater than about 7.

[0110] Example 13. The method according to Example 10, wherein forming the sacrificial gate structure includes forming a sacrificial dielectric layer on the front-facing surface of the first plurality of semiconductor layers.

[0111] Specifically, recessing the sacrificial gate structure includes removing a first portion of the sacrificial gate structure without exposing the front-facing surface, and

[0112] The method also includes removing the remainder of the sacrificial gate structure after the fourth dielectric feature is recessed.

[0113] Example 14. The method according to Example 9, wherein forming the third dielectric feature includes configuring the third dielectric feature to include an air gap.

[0114] Example 15. The method according to Example 9, wherein forming the gate structure comprises: forming a gate dielectric layer surrounding the semiconductor layer and surrounding the first dielectric feature and the second dielectric feature, and forming a gate electrode surrounding the gate dielectric layer, and

[0115] The recessing of the gate structure includes:

[0116] The gate dielectric layer is recessed around a portion of the first dielectric feature to expose the side surface of the gate electrode; and

[0117] The gate electrode is recessed from the exposed side surface.

[0118] Example 16. The method according to Example 9, wherein removing the first dielectric feature includes:

[0119] A patterned mask element is formed on the back-facing surface of the workpiece, the patterned mask element having an opening aligned with the first dielectric feature;

[0120] Remove the isolation features between the first back dielectric and the second back dielectric to form a back trench;

[0121] A liner layer is formed on the sidewall surface of the back groove; and

[0122] The first dielectric feature is etched using the pad layer as a mask.

[0123] Example 17. The method according to Example 10, wherein receiving the workpiece includes receiving a workpiece having: a contact feature in contact with one of the source / drain features,

[0124] The method further includes recessing the fourth dielectric feature to expose the back-facing surface of the contact feature; and

[0125] The formation of the third dielectric feature includes forming the third dielectric feature on the exposed back-facing surface of the contact feature.

[0126] Example 18. A method of forming a semiconductor device, comprising:

[0127] The workpiece is received having a front and a back side, which are perpendicular to each other in a vertical direction. The workpiece includes a first semiconductor layer stack on a first base on the front surface of a substrate and a second semiconductor layer stack on a second base on the front surface of the substrate. The first stack and the second stack each include a first semiconductor layer and a second semiconductor layer arranged in a vertically staggered manner. The first stack and the second stack each extend longitudinally in a first direction. An isolation feature is located between the first base and the second base.

[0128] A hybrid structure is formed between the sidewall surfaces of the first stack and the second stack and on the first surface of the isolation feature, wherein the hybrid structure includes a first low-k dielectric layer surrounded by a first high-k dielectric layer, and a second high-k dielectric layer on the first low-k dielectric layer and the first high-k dielectric layer.

[0129] A first gate stack is formed on the first stack and the second stack along a second direction perpendicular to the first direction, the first gate stack covering a portion of the second high-k dielectric layer;

[0130] Source / drain features are formed on both sides of the first gate stack;

[0131] This causes the portion of the second high-k dielectric layer not covered by the first gate stack to be recessed;

[0132] The second semiconductor layer is selectively removed;

[0133] The first high-k dielectric layer on the sidewall surface of the first low-k dielectric layer is recessed.

[0134] A gate dielectric layer is formed around the first semiconductor layer and around the first low-k dielectric layer, a gate electrode layer is formed around the gate dielectric layer, and a gate cap is formed covering the gate electrode layer;

[0135] The first base and the second base are replaced from the back side to form a back dielectric layer; and

[0136] A gate dicing feature is formed, which extends vertically through the back dielectric layer, through the gate electrode layer and through the gate cap.

[0137] Example 19. The method according to Example 18 further includes: after selectively removing the second semiconductor layer, removing the recessed portion of the second high-k dielectric layer, and

[0138] The formation of the gate cleavage feature includes:

[0139] Remove the isolation features to expose the sidewalls of the back dielectric layer;

[0140] The first low-k dielectric layer is removed to form a gate cleaving opening that exposes a portion of the gate dielectric layer.

[0141] The exposed portion of the gate dielectric layer is recessed to expose a portion of the gate electrode layer;

[0142] The gate electrode layer is recessed laterally and vertically to enlarge and extend the gate dicing opening, the gate dicing opening extending through the gate cap; and

[0143] A second low-k dielectric layer is formed in the extended gate dicing opening.

[0144] Example 20. The method according to Example 18 further includes:

[0145] After forming the gate dielectric layer, the gate electrode layer, and the gate cap, the front side of the workpiece is bonded to the carrier wafer; and

[0146] Before concave the back of the workpiece, flip the workpiece over.

Claims

1. A semiconductor device, comprising: Nanostructures, wherein the nanostructures are arranged perpendicularly along a first direction and spaced apart from each other; The dielectric fin structure of the dielectric material having uniform composition, and the isolation structure located on the opposite side of the nanostructure; as well as A gate structure that surrounds the nanostructure, extends between the nanostructure and the dielectric fin structure, and extends between the nanostructure and the isolation structure. The nanostructure is spaced apart from the dielectric fin structure by a first distance along a second direction perpendicular to the first direction, and spaced apart from the isolation structure by a second distance along the second direction, wherein the first distance is greater than the second distance, and The gate structure is connected to the dielectric fin structure on a surface extending perpendicular to the first direction. The gate structure includes a gate dielectric layer and a gate electrode layer, wherein the gate electrode layer is connected to the isolation structure but not to the dielectric fin structure.

2. The semiconductor device according to claim 1, wherein, The isolation structure extends along the first direction from above the top surface of the gate structure to below the bottom surface of the gate structure.

3. The semiconductor device according to claim 1, wherein, The dielectric material has a k constant less than 7, and the surface is the surface of the dielectric material.

4. The semiconductor device according to claim 1, further comprising: A dielectric layer, in contact with the isolation structure and on the first surface of the gate structure.

5. The semiconductor device according to claim 1, wherein, The isolation structure includes an air gap.

6. The semiconductor device according to claim 5, wherein, The air gap extends a first vertical height along the first direction, the gate structure extends a second vertical height along the first direction, and the ratio of the first vertical height to the second vertical height is 50% to 95%.

7. The semiconductor device according to claim 1, further comprising: The source / drain features are connected to the nanostructure and are located vertically between the conductive material and the dielectric substrate, which is aligned with the nanostructure along the first direction.

8. A method of forming a semiconductor device, comprising: Receive a workpiece having a front and a back side, the workpiece comprising: A first plurality of semiconductor layers located on a first base on the front surface of the substrate, and a second plurality of semiconductor layers located on a second base on the front surface of the substrate; A first dielectric feature is located on a first side of the plurality of semiconductor layers and between the plurality of semiconductor layers; and A second dielectric feature is located on a second side of the first plurality of semiconductor layers, the second side being opposite to the first side, and the second dielectric feature having a feature surface facing the front side; A gate structure is formed, which is bonded to the first plurality of semiconductor layers and the second plurality of semiconductor layers and is connected to the first dielectric feature on the feature surface; The first base and the second base are replaced respectively to form a first back dielectric and a second back dielectric; The first dielectric feature is removed but the second dielectric feature is not removed, thereby forming an opening between the first plurality of semiconductor layers and the second plurality of semiconductor layers; The gate structure is recessed from the opening to form a gate cleaving opening, the gate cleaving opening extending from the front surface of the gate structure to the rear surface of the gate structure; and A third dielectric feature is formed in the gate dicing opening.

9. The method according to claim 8, wherein, Receiving the workpiece includes receiving a workpiece having the following: A sacrificial layer is located between vertically adjacent layers of the first plurality of semiconductor layers and between vertically adjacent layers of the second plurality of semiconductor layers. The fourth dielectric feature is located on the first dielectric feature; The method also includes: A sacrificial gate structure is formed, which covers the first plurality of semiconductor layers and the second plurality of semiconductor layers and a portion of the fourth dielectric feature; Source / drain features are formed on both sides of the sacrificial gate structure; The sacrificial gate structure is recessed to expose the top and side surfaces of the fourth dielectric feature; The exposed portion of the fourth dielectric feature is recessed to expose the top surface of the first dielectric feature; Remove the sacrificial layer to form gaps between adjacent layers of the first plurality of semiconductor layers and between adjacent layers of the second plurality of semiconductor layers; and The gate structure is formed in the gap.

10. The method according to claim 9, wherein, Receiving the workpiece includes receiving a workpiece having the following: a fifth dielectric feature located on a first sidewall of the first dielectric feature and a sixth dielectric feature located on a second sidewall of the second dielectric feature; The method further includes: removing the fifth dielectric feature and the sixth dielectric feature. The formation of the gate structure includes forming the gate structure on the first sidewall and the second sidewall.

11. The method according to claim 9, wherein, The first dielectric feature and the second dielectric feature include a first dielectric material, and the fourth dielectric feature includes a second dielectric material. Wherein, the first dielectric material has a k value less than 7, and the second dielectric material has a k value greater than 7.

12. The method according to claim 9, wherein, Forming the sacrificial gate structure includes forming a sacrificial dielectric layer on the front-facing surface of the first plurality of semiconductor layers. Specifically, recessing the sacrificial gate structure includes removing a first portion of the sacrificial gate structure without exposing the front-facing surface, and The method also includes removing the remainder of the sacrificial gate structure after the fourth dielectric feature is recessed.

13. The method according to claim 8, wherein, Forming the third dielectric feature includes configuring the third dielectric feature to include an air gap.

14. The method according to claim 8, wherein, Forming the gate structure includes: forming a gate dielectric layer surrounding the semiconductor layer and surrounding the first dielectric feature and the second dielectric feature; and forming a gate electrode surrounding the gate dielectric layer. The recessing of the gate structure includes: The gate dielectric layer is recessed around a portion of the first dielectric feature to expose the side surface of the gate electrode; and The gate electrode is recessed from the exposed side surface.

15. The method according to claim 8, wherein, Removing the first dielectric feature includes: A patterned mask element is formed on the back-facing surface of the workpiece, the patterned mask element having an opening aligned with the first dielectric feature; Remove the isolation features between the first back dielectric and the second back dielectric to form a back trench; A liner layer is formed on the sidewall surface of the back groove; and The first dielectric feature is etched using the pad layer as a mask.

16. The method according to claim 9, wherein, Receiving the workpiece includes receiving a workpiece having the following: a contact feature that is in contact with one of the source / drain features. The method further includes recessing the fourth dielectric feature to expose the back-facing surface of the contact feature; and The formation of the third dielectric feature includes forming the third dielectric feature on the exposed back-facing surface of the contact feature.

17. A method of forming a semiconductor device, comprising: A workpiece having a front and a back side is received, the front and back sides being opposite to each other in a vertical direction. The workpiece includes a first stack of semiconductor layers on a first base on the front surface of a substrate and a second stack of semiconductor layers on a second base on the front surface of the substrate. The first stack and the second stack each include a first semiconductor layer and a second semiconductor layer arranged in a vertically staggered manner. The first stack and the second stack each extend longitudinally in a first direction. An isolation feature is located between the first base and the second base. A hybrid structure is formed between the sidewall surfaces of the first stack and the second stack and on the first surface of the isolation feature, wherein the hybrid structure includes a first low-k dielectric layer surrounded by a first high-k dielectric layer, and a second high-k dielectric layer on the first low-k dielectric layer and the first high-k dielectric layer. A first gate stack is formed on the first stack and the second stack along a second direction perpendicular to the first direction, the first gate stack covering a portion of the second high-k dielectric layer; Source / drain features are formed on both sides of the first gate stack; This causes the portion of the second high-k dielectric layer not covered by the first gate stack to be recessed; The second semiconductor layer is selectively removed; The first high-k dielectric layer on the sidewall surface of the first low-k dielectric layer is recessed. A gate dielectric layer is formed around the first semiconductor layer and around the first low-k dielectric layer, a gate electrode layer is formed around the gate dielectric layer, and a gate cap is formed covering the gate electrode layer; The first base and the second base are replaced from the back side to form a back dielectric layer; and A gate dicing feature is formed, which extends vertically through the back dielectric layer, through the gate electrode layer and through the gate cap.

18. The method of claim 17, further comprising: After selectively removing the second semiconductor layer, the recessed portion of the second high-k dielectric layer is removed, and The formation of the gate cleavage feature includes: Remove the isolation features to expose the sidewalls of the back dielectric layer; The first low-k dielectric layer is removed to form a gate cleaving opening that exposes a portion of the gate dielectric layer. The exposed portion of the gate dielectric layer is recessed to expose a portion of the gate electrode layer; The gate electrode layer is recessed laterally and vertically to enlarge and extend the gate dicing opening, the gate dicing opening extending through the gate cap; and A second low-k dielectric layer is formed in the extended gate dicing opening.

19. The method of claim 17, further comprising: After forming the gate dielectric layer, the gate electrode layer and the gate cap, the front side of the workpiece is bonded to the carrier wafer; as well as Before concave the back of the workpiece, flip the workpiece over.

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