A method of interconnecting semiconductor devices

Abstract

The application relates to the field of semiconductor technology, in particular to a method for interconnecting semiconductor devices, which comprises the following steps: providing a substrate, the substrate being provided with a memory cell, a peripheral circuit, and an isolation medium area between the memory cell and the peripheral circuit, the memory cell being provided with a plurality of contact plugs, and the isolation medium area being provided with a plurality of residues of the contact plugs; forming a SiGeO composite oxide sacrificial layer on the substrate; performing photoetching on the SiGeO composite oxide sacrificial layer to form an etching window, the etching window corresponding to the isolation medium area, and the residues being removed through the etching window; removing the remaining SiGeO composite oxide sacrificial layer; forming a metal wiring on the substrate to realize the interconnection of the memory cell and the peripheral circuit; and using the SiGeO composite oxide sacrificial layer as a mask layer, when the mask layer is removed, the etching rate is relatively fast, the structure under the mask layer is not affected, over-etching is not caused, and the stability of the semiconductor device is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a method for interconnecting semiconductor devices. BACKGROUND

[0002] In forming an interconnection structure between a memory cell and a peripheral circuit, a contact plug is formed in the original semiconductor device, and there is a residue of the contact plug between the memory cell and the peripheral circuit, and the residue needs to be removed. In the prior art, a hard mask of SiO2 is used, and then a photoresist and a dry etching process are used to remove the residue of the contact plug. In this way, when the hard mask of SiO2 is removed, the structure below the hard mask of SiO2 is also removed, resulting in over-etching and causing reliability problems.

[0003] Therefore, how to avoid this over-etching phenomenon is a technical problem to be solved at present. SUMMARY

[0004] In view of the above problems, the present application is proposed to provide a method for interconnecting semiconductor devices to overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, an embodiment of the present application provides a method for interconnecting semiconductor devices, comprising:

[0006] providing a substrate, the substrate being formed with a memory cell, a peripheral circuit, and an isolation medium region between the memory cell and the peripheral circuit, the memory cell being formed with a plurality of contact plugs, and the isolation medium region being formed with a residue of the plurality of contact plugs;

[0007] forming a SiGeO composite oxide sacrificial layer on the substrate;

[0008] lithographing the SiGeO composite oxide sacrificial layer to form an etching window, the etching window corresponding to the isolation medium region;

[0009] removing the residue through the etching window;

[0010] removing the remaining SiGeO composite oxide sacrificial layer;

[0011] forming a metal wiring on the substrate to realize interconnection of the memory cell and the peripheral circuit.

[0012] Further, forming a SiGeO composite oxide sacrificial layer on the substrate comprises:

[0013] depositing the SiGeO composite oxide sacrificial layer on the substrate by using a plasma-enhanced atomic layer deposition method.

[0014] Further, the photoetching the SiGeO composite oxide sacrificial layer forms an etching window, and the etching window corresponds to the isolation medium region, including:

[0015] Forming a photoresist on the SiGeO composite oxide sacrificial layer, and forming an etching window, and the etching window corresponds to the isolation medium region.

[0016] Further, the removing the residue through the etching window, including:

[0017] The residue is removed through the etching window by using a dry etching method.

[0018] Further, the removing the remaining SiGeO composite oxide sacrificial layer, including:

[0019] The remaining SiGeO composite oxide sacrificial layer is removed by using a wet etching method.

[0020] Further, the SiGeO composite oxide sacrificial layer, including:

[0021] The SiO2 layer and the GeO layer, and the thickness ratio of the SiO2 layer to the GeO layer satisfies 1:1-1:5.

[0022] Further, the thickness ratio of the SiO2 layer to the GeO layer is 1:1, 1:3 or 1:5.

[0023] Further, the semiconductor device is a dynamic random access memory.

[0024] Further, the residue of the contact plug is specifically: doped polysilicon or SiGe.

[0025] Further, before forming the metal wiring on the substrate, the method further includes:

[0026] Forming an isolation layer on the substrate;

[0027] Etching the isolation layer to expose the plurality of contact plugs.

[0028] One or more technical solutions in the embodiments of the present application have at least the following technical effects or advantages:

[0029] The application provides a semiconductor device interconnection method, comprising the following steps: providing a substrate, wherein a memory cell, a peripheral circuit and an isolation medium area between the memory cell and the peripheral circuit are formed on the substrate, a plurality of contact plugs are formed on the memory cell, and a residue of the contact plug is formed on the isolation medium area; forming a SiGeO composite oxide sacrificial layer on the substrate; performing photoetching on the SiGeO composite oxide sacrificial layer to form an etching window, wherein the etching window corresponds to the isolation medium area, and the residue is removed through the etching window; removing the SiGeO composite oxide sacrificial layer; and forming a metal wiring on the substrate to realize the interconnection between the memory cell and the peripheral circuit, and then using the SiGeO composite oxide sacrificial layer as a mask layer, when the mask layer is removed, because the etching rate is relatively fast, the structure under the mask layer is not affected, over-etching is not caused, and the reliability of the semiconductor device is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0030] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The detailed description is made with reference to the accompanying drawings.

[0031] Figure 1 A step flow diagram of the semiconductor device interconnection method in the embodiment of the application is shown in the figure;

[0032] Figures 2-4 、 Figure 7 A schematic diagram of forming the semiconductor interconnection structure in the embodiment of the application is shown in the figure;

[0033] Figure 5 A schematic diagram of the relationship between the etching rate of the SiGeO composite oxide sacrificial layer removed by the wet etching method and the ratio of the thickness of the SiO2 layer to the thickness of the GeO layer in the SiGeO composite oxide sacrificial layer in the embodiment of the application is shown in the figure;

[0034] Figure 6 A schematic diagram of the over-etching phenomenon formed when the SiO2 layer is used as a mask layer in the prior art is shown in the figure. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure will be described herein below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be accurately conveyed to those skilled in the art.

[0036] Various structural diagrams according to embodiments of the present disclosure are shown in the drawings. These diagrams are not drawn to scale in which certain details are exaggerated for clarity and others omitted. The shapes of various regions, layers, and the relative sizes and positional relationships among them shown in the drawings are merely exemplary and can deviate in actuality due to manufacturing tolerances or technical limitations, and regions / layers with different shapes, sizes, and relative positions can be additionally designed according to actual needs by those skilled in the art.

[0037] In the context of the present disclosure, when a layer / element is referred to as being located "on" another layer / element, the layer / element can be directly on the other layer / element, or there can be an intervening layer / element between them. In addition, if a layer / element is located "on" another layer / element in one orientation, it can be located "under" the other layer / element when the orientation is reversed.

[0038] Embodiments of the present application provide a method for interconnecting semiconductor devices, as shown in Figure 1 as shown in Figure 2 First, as shown in FIG. 1, a substrate is provided, which is formed with a memory cell, a peripheral circuit (PERI), and an isolation medium region 201 between the memory cell and the peripheral circuit. The semiconductor device is specifically a dynamic random access memory (DRAM).

[0039] A plurality of contact plugs 202 are formed on the memory cell to realize interconnection of the upper and lower structures. The plurality of contact plugs 202 are specifically doped polysilicon contact plugs or SiGe contact plugs. When the plurality of contact plugs 202 are formed, the isolation medium region 201 is also formed with residues 203 of the contact plugs, so the residues 203 of the contact plugs 202 are specifically doped polysilicon or SiGe.

[0040] To remove the residues 203 of the contact plugs 202, a mask is formed, etching is performed on the residues to be removed, and then the mask is removed.

[0041] Therefore, according to the above steps, as shown in FIG. 2, a SiGeO composite oxide sacrificial layer 204, i.e., a mask, is formed on the substrate.

[0042] Specifically, the SiGeO composite oxide sacrificial layer 204 is deposited on the substrate by plasma enhanced atomic layer deposition (PE ALD).

[0043] The SiGeO composite oxide sacrificial layer 204 includes a SiO2 layer and a GeO layer, and the ratio of the thickness of the SiO2 layer to the thickness of the GeO layer satisfies 1:1-1:5.

[0044] Specifically, the ratio of the thickness of the SiO2 layer and the thickness of the GeO layer can be 1:1, or 1:3, or 1:5. Of course, the ratio of the SiO2 layer and the GeO layer can also be other ratios, which are not limited herein.

[0045] Next, S103 is performed, and the SiGeO composite oxide sacrificial layer is photoetched to form an etching window corresponding to the isolation medium region, so as to remove the residue 203 under the etching window.

[0046] Specifically, S103 includes forming a photoresist on the SiGeO composite oxide sacrificial layer and forming an etching window corresponding to the isolation medium region.

[0047] By spin-coating the photoresist and reserving the etching window, the removal of the residue 203 can be prepared.

[0048] Then, S104 is performed, and the residue 203 is removed through the etching window, as shown in Figure 3

[0049] Specifically, the residue 203 is removed by dry etching in the etching window.

[0050] First, the SiGeO composite oxide sacrificial layer 204 above the residue 203 is removed, and then the residue 203 is removed.

[0051] For the area other than the etching window, the photoresist 205 is removed first, and then, as shown in Figure 4 the SiGeO composite oxide sacrificial layer 204 under the photoresist 205 is removed. That is, S105 is performed to remove the SiGeO composite oxide sacrificial layer.

[0052] Specifically, the SiGeO composite oxide sacrificial layer 204 is removed by wet etching.

[0053] Here, the rate of removing the SiGeO composite oxide sacrificial layer 204 by wet etching is related to the ratio of the thickness of the SiO2 layer and the thickness of the GeO layer in the SiGeO composite oxide sacrificial layer, as shown in Figure 5 the thicker the thickness of the GeO layer, the faster the rate of removing the SiGeO composite oxide sacrificial layer 204 by wet etching. The GeO layer has strong water absorption and cannot be used alone, but should be used as a composite film of the SiO2 layer.

[0054] By using the SiGeO composite oxide sacrificial layer as a mask layer, when the mask layer is removed, since the etching rate is relatively fast, the structure under the mask layer will not be affected, and over-etching will not occur, thereby ensuring the reliability of the semiconductor device.​

[0055] The over-etched structure diagram is as follows: Figure 6 As shown, in the prior art, when using a SiO2 layer as a mask layer, over-etching is easily caused during the final removal of the SiO2 layer, specifically lateral over-etching and longitudinal over-etching. However, in this invention, using the SiGeO composite oxide sacrificial layer as a mask layer can effectively avoid this over-etching phenomenon.

[0056] Next, as Figure 7 As shown, in step S106, metal wiring 206 is formed on the substrate to realize the interconnection between the memory cell and the peripheral circuit.

[0057] Before forming the metal wiring 206, an isolation layer 207 needs to be formed on the substrate. Since the metal wiring 206 is only formed in a part of the substrate, the isolation layer 207 is used to isolate the metal wiring 206 from other areas.

[0058] The specific insulating material used for the isolation layer 207 will not be specified here.

[0059] After the isolation layer 207 is formed, the isolation layer 207 is etched to expose a plurality of contact plugs 202 so that the metal wiring 206 can contact the plurality of contact plugs 202, thereby realizing the interconnection of the plurality of contact plugs 202 with the peripheral circuit through the metal wiring 206.

[0060] First, a metal layer is formed on the isolation layer 207, and then the metal layer is patterned to form the metal wiring 206. Therefore, a portion of the metal layer needs to be etched. Since the SiGeO composite oxide sacrificial layer 204 is used as a mask, over-etching will not occur when the mask is removed. Therefore, there will be no over-etched areas. When etching a portion of the metal layer, such as etching excess metal layer in the isolation dielectric area, it will be easy to etch, thereby improving the efficiency of the etching process.

[0061] After forming the metal wiring 206 on the isolation layer 207, the method further includes forming a protective layer 208 on the metal wiring 206 to protect the metal wiring 206. The protective layer 208 covers the metal wiring, thereby protecting the entire semiconductor device.

[0062] In the above description, the technical details of the patterning, etching, etc. of each layer are not described in detail. However, those skilled in the art should understand that the layers, regions, etc. of desired shapes can be formed by various technical means. In addition, those skilled in the art can also design methods that are not exactly the same as the above-described methods in order to form the same structure. In addition, although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0063] The one or more technical solutions in the embodiments of the present application have at least the following technical effects or advantages:

[0064] The present application provides a method for interconnecting semiconductor devices, comprising: providing a substrate, the substrate having a memory cell, a peripheral circuit, and an isolation medium region between the memory cell and the peripheral circuit, the memory cell having a plurality of contact plugs formed thereon, and the isolation medium region having a residue of the contact plugs formed thereon; forming a SiGeO composite oxide sacrificial layer on the substrate; patterning the SiGeO composite oxide sacrificial layer to form an etching window, the etching window corresponding to the isolation medium region, and removing the residue through the etching window; removing the remaining SiGeO composite oxide sacrificial layer; forming a metal wiring on the substrate to realize interconnection between the memory cell and the peripheral circuit, and further using the SiGeO composite oxide sacrificial layer as a mask layer, when the mask layer is removed, since the etching rate is relatively fast, the structure below the mask layer is not affected, over-etching is not caused, and the reliability of the semiconductor device is ensured.

[0065] Although preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to cover all changes and modifications falling within the scope of the present application.

[0066] Obviously, various modifications and changes can be made to the present application by those skilled in the art without departing from the spirit and scope of the present application. Thus, it is intended that the present application cover the modifications and changes as long as they come within the scope of the claims and their equivalents.

Claims

1. A method for interconnecting semiconductor devices, characterized in that, include: A substrate is provided on which a memory cell, peripheral circuitry, and an isolation medium region between the memory cell and the peripheral circuitry are formed. A plurality of contact plugs are formed on the memory cell, and residues of the plurality of contact plugs are formed on the isolation medium region. A SiGeO composite oxide sacrificial layer is formed on the substrate; The SiGeO composite oxide sacrificial layer is photolithographically etched to form an etching window, which corresponds to the isolation dielectric region; The residue is removed through the etching window; Remove the SiGeO composite oxide sacrificial layer; Metal wiring is formed on the substrate to interconnect the memory cell and the peripheral circuit.

2. The method as described in claim 1, characterized in that, A SiGeO composite oxide sacrificial layer is formed on the substrate, comprising: The SiGeO composite oxide sacrificial layer was deposited on the substrate using plasma-enhanced atomic layer deposition.

3. The method as described in claim 1, characterized in that, The photolithography of the SiGeO composite oxide sacrificial layer forms an etching window, which corresponds to the isolation dielectric region and includes: Photoresist is formed on the SiGeO composite oxide sacrificial layer, and an etching window is formed, the etching window corresponding to the isolation medium region.

4. The method as described in claim 1, characterized in that, The removal of the residue through the etching window includes: The residue is removed by dry etching through the etching window.

5. The method as described in claim 1, characterized in that, The removal of the SiGeO composite oxide sacrificial layer includes: The SiGeO composite oxide sacrificial layer was removed using a wet etching method.

6. The method as described in claim 1, characterized in that, The SiGeO composite oxide sacrificial layer includes: The SiO2 layer and the GeO layer are provided, and the thickness ratio of the SiO2 layer to the GeO layer is 1:1 to 1:

5.

7. The method as described in claim 6, characterized in that, The ratio of the thickness of the SiO2 layer to the thickness of the GeO layer is 1:1, 1:3, or 1:

5.

8. The method as described in claim 1, characterized in that, The semiconductor device is a dynamic random access memory.

9. The method as described in claim 1, characterized in that, The residue of the contact plug is specifically: doped polycrystalline silicon or SiGe.

10. The method as described in claim 1, characterized in that, Before forming the metal wiring on the substrate, the method further includes: An isolation layer is formed on the substrate; The isolation layer is etched to expose the plurality of contact plugs.

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