Multi-chip three-dimensional stacking structure with electromagnetic shielding function and preparation method thereof

Abstract

The application discloses a multi-chip three-dimensional stacking structure with an electromagnetic shielding function, comprising N wiring layers and N-1 encapsulation layers which are alternately stacked, wherein each wiring layer is provided with a metal plane, each encapsulation layer is provided with a chip and a metal sidewall surrounding the chip, and the metal sidewall in each encapsulation layer is in closed connection with the metal planes in two adjacent wiring layers to enclose the chip in the encapsulation layer. The application further discloses a preparation method of the multi-chip three-dimensional stacking structure with the electromagnetic shielding function. The application solves the problems of electromagnetic interference and signal crosstalk of the chip in the three-dimensional stacking structure, and improves the heat dissipation effect of the three-dimensional stacking structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a multi-chip three-dimensional stacked structure with electromagnetic shielding function and its preparation method. Background Technology

[0002] Three-dimensional stacked chip packaging structures can integrate multiple chips into a small package space. By using the vertical interconnect structure between chips in the vertical direction, the channels for electrical signal connection between chips are shortened. Therefore, this packaging structure has many advantages, such as lower signal transmission loss, lower power consumption, lower signal delay, and smaller package size. It can also realize wafer-level three-dimensional packaging and three-dimensional heterogeneous integration, which is the future development direction of high-end chip packaging technology.

[0003] However, there are still two main problems to be solved in the three-dimensional stacked chip packaging structure: (1) Since the chips adopt a vertical interconnect structure, the distance between the chips is shorter. Especially when the signal of the high-speed chip is transmitted on such a short transmission line, the electromagnetic interference and signal crosstalk between the chips will inevitably increase; (2) After the integration density of multiple chips increases, the power consumption will increase. The heat effect caused by the impedance of the transmission line will also increase. Therefore, the three-dimensional stacked structure needs to solve the heat dissipation problem.

[0004] Regarding the first problem mentioned above, in order to solve the problems of electromagnetic interference and signal crosstalk between chips, a metal shielding layer is usually added around the chip. However, the metal shielding layer used in the existing technology still cannot provide comprehensive electromagnetic shielding protection for a single chip, so electromagnetic interference and signal interference problems still exist in the signal transmission between chips.

[0005] Regarding the second problem mentioned above, in order to solve the thermal effect caused by the three-dimensional stacked structure, the heat dissipation effect is usually improved by increasing the thermal conductivity of the metal material and increasing the heat dissipation area of ​​the metal material. However, additional processes and heat dissipation structures are required to solve the heat dissipation problem. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a multi-chip three-dimensional stacked structure with electromagnetic shielding function and its fabrication method, which can solve the problems of electromagnetic interference and signal crosstalk of single chips in existing technologies and improve thermal conductivity.

[0007] A multi-chip three-dimensional stacked structure with electromagnetic shielding function includes N wiring layers and N-1 encapsulation layers stacked alternately. Each wiring layer has a metal plane, and each encapsulation layer has a chip and a metal sidewall surrounding the chip. The metal sidewall in each encapsulation layer is closedly connected to the metal plane in two adjacent wiring layers to encapsulate the chip in the encapsulation layer.

[0008] As a preferred embodiment, the chip includes interconnect pillars located at its bottom, which are electrically connected to a metal plane in a wiring layer on one side of the bottom of the chip.

[0009] Furthermore, at least one of the chips includes a conductive pillar located on its top, and the chip also includes a communication structure connecting the interconnect pillar and the conductive pillar, the conductive pillar being electrically connected to a metal plane in a wiring layer on one side of the top of the chip.

[0010] Furthermore, in the wiring layers other than the highest and lowest layers, there are metal layers for electrical connection with conductive pillars of the underlying chip.

[0011] As a preferred embodiment, the bottom of the chip is provided with a bottom fill layer covering the interconnect pillars and pads.

[0012] A method for fabricating a multi-chip three-dimensional stacked structure with electromagnetic shielding function includes the following steps:

[0013] Prepare a carrier plate with a release layer;

[0014] Cyclic step 1: Create a wiring layer with a metal plane, and create pads on the metal plane;

[0015] Cyclic step 2: Solder the chip onto the pads;

[0016] Cyclic step 3: Encapsulate the chip and planarize it to form an encapsulation layer;

[0017] Cyclic step 4: Create a through-groove through the encapsulation layer, and fill the through-groove with metal material to obtain a metal sidewall;

[0018] Repeat the cycle steps 1 to 4 until the chips are stacked to a preset number;

[0019] A wiring layer with a metal plane is fabricated on the topmost encapsulation layer;

[0020] The prepared multi-layer stacked chip package is divided and the carrier board is removed to obtain a multi-chip three-dimensional stacked structure with electromagnetic shielding function.

[0021] Each of the metal sidewalls is closedly connected to the adjacent metal plane.

[0022] As a preferred embodiment, the following steps may be included before the cyclic step 3:

[0023] The chip is underfilled to form an underfill layer.

[0024] As a preferred embodiment, in the cyclic step 3, if the chip includes conductive pillars located on its top, the conductive pillars are exposed after the planarization process.

[0025] As a preferred option, the chip is an HBM chip.

[0026] As a preferred embodiment, the metal plane and metal sidewall are made of metal materials with high thermal conductivity.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] 1. By deploying four metal sidewalls in the Z-direction for a single chip, and preparing a metal base and / or metal top and / or metal plane for the single chip, a completely enclosed metal electromagnetic shielding cavity is provided for the single chip, constructing an equipotential Faraday electromagnetic shielding cage. This solves the electromagnetic interference problem of the single chip in the prior art, and also solves the signal crosstalk problem between adjacent chips in the Z-direction during signal transmission. It is more suitable for radio frequency signal transmission of high-speed chips.

[0029] 2. By constructing a heat-conducting network between multiple chips through the interconnection of metal planes and metal sidewalls, the heat generated by each chip can be exchanged with the external environment through the heat-conducting network, thereby increasing the heat dissipation effect of the three-dimensional stacked structure. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the multi-chip three-dimensional stacked structure with electromagnetic shielding function in this invention;

[0032] Figure 2 For the Figure 1 A magnified structural diagram of part A1 in the middle;

[0033] Figure 3 This is a schematic diagram of the fabrication process of the multi-chip three-dimensional stacked structure with electromagnetic shielding function in this invention;

[0034] Figure 4 This is a schematic diagram of steps S1 to S3 of the method for preparing the multi-chip three-dimensional stacked structure with electromagnetic shielding function in this invention;

[0035] Figure 5This is a schematic diagram of steps S4 to S5 of the method for preparing the multi-chip three-dimensional stacked structure with electromagnetic shielding function in this invention;

[0036] Figure 6 This is a schematic diagram of step S6 in the method for preparing a multi-chip three-dimensional stacked structure with electromagnetic shielding function in this invention.

[0037] One of them is a carrier board;

[0038] 2. Peel-off layer;

[0039] 31 First wiring layer; 31a First metal layer; 31b First dielectric layer; M31 First metal plane;

[0040] 32 Second wiring layer; 32a Second metal layer; 32b Second dielectric layer; M32 Second metal plane;

[0041] 33 Third wiring layer; 33a Third metal layer; 33b Third dielectric layer; M33 Third metal plane;

[0042] 34 Fourth wiring layer; 34a Fourth metal layer; 34b Fourth dielectric layer; M34 Fourth metal plane;

[0043] 35 Fifth wiring layer; 35a Fifth metal layer; 35b Fifth dielectric layer; M35 Fifth metal plane;

[0044] 41 First pad; 42 Second pad; 43 Third pad; 44 Fourth pad;

[0045] 51 First bottom fill layer; 52 Second bottom fill layer; 53 Third bottom fill layer; 54 Fourth bottom fill layer;

[0046] 61 First pack seal; 62 Second pack seal; 63 Third pack seal; 64 Fourth pack seal;

[0047] 10 First chip package; 100 First chip; 101-1 First interconnect post; 102-1 First TSV conductive post; 103-1 First conductive post; Z1 First metal sidewall;

[0048] 20 Second chip package; 200 Second chip; 101-2 Second interconnect post; 102-2 Second TSV conductive post; 103-2 Second conductive post; Z2 Second metal sidewall;

[0049] 30 Third chip package; 300 Third chip; 101-3 Third interconnect pillar; 102-3 Third TSV conductive pillar; 103-3 Third conductive pillar; Z3 Third metal sidewall;

[0050] 40 Fourth chip package; 400 Fourth chip; 101-4 Fourth interconnect post; 102-4 Fourth TSV conductive post; Z4 Fourth metal sidewall. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0053] In the first aspect, a multi-chip three-dimensional stacked structure with electromagnetic shielding function includes N wiring layers and N-1 encapsulation layers stacked alternately. Each wiring layer has a metal plane, and each encapsulation layer has a chip and a metal sidewall surrounding the chip. The metal sidewall in each encapsulation layer is closedly connected to the metal plane in two adjacent wiring layers to encapsulate the chip in the encapsulation layer.

[0054] The multi-chip three-dimensional stacked structure includes multiple alternately stacked wiring layers and encapsulation layers. The chips can be various types of functional chips, such as HBM chips. Figure 1 , Figure 2 As shown, the first chip package 10, the second chip package 20, the third chip package 30, and the fourth chip package 40 are interconnected by a vertical interconnection structure. Figure 2 As shown, the wiring layers can be divided into a first wiring layer 31, a second wiring layer 32, a third wiring layer 33, a fourth wiring layer 34, and a fifth wiring layer 35; the encapsulation layers can be divided into a first encapsulation layer 61, a second encapsulation layer 62, a third encapsulation layer 63, and a fourth encapsulation layer 64; the metal planes can be divided into a first metal plane M31, a second metal plane M32, a third metal plane M33, a fourth metal plane M34, and a fifth metal plane M35; the chips can be divided into a first chip 100, a second chip 200, a third chip 300, and a fourth chip 400; and the metal sidewalls can be divided into a first metal sidewall Z1, a second metal sidewall Z2, a third metal sidewall Z3, and a fourth metal sidewall Z4.

[0055] Taking the first chip package 10 as an example, the first wiring layer 31 has a first metal plane M31 flush with the upper surface, and the first metal sidewall Z1 in the first encapsulation layer 61 surrounds the first chip 100 in the middle; the lower end of the first metal sidewall Z1 is closedly connected to the first metal surface M31, and the upper end is closedly connected to the second metal surface M32, thereby forming a fully enclosed structure surrounding the first chip 100. The second chip package 20, the third chip package 30, and the fourth chip package 40 are similar.

[0056] This solution provides a completely enclosed electromagnetic shielding cavity for a single chip by arranging four metal sidewalls along the Z-axis and preparing metal planes as the top and bottom surfaces of the encapsulation layer containing the chip, which are then sealed and connected to the metal sidewalls. This constructs an equipotential Faraday electromagnetic shielding cage, effectively solving the electromagnetic interference and signal crosstalk problems present in existing technologies for single chips. The electromagnetic shielding cavity formed in this solution creates a heat-conducting network between multiple chips through the interconnection of the metal planes and sidewalls. This allows the heat generated by each chip to exchange with the external environment through this heat-conducting network, thereby increasing the heat dissipation effect of the three-dimensional stacked structure. Preferably, the material of the electromagnetic shielding cavity can be a metal with high thermal conductivity, such as copper.

[0057] In one embodiment, the chip includes interconnect pillars located at its bottom, the interconnect pillars being electrically connected to a metal plane in a wiring layer on one side of the bottom of the chip.

[0058] The interconnect pillars can be connected to the metal plane via pads disposed on the wiring layer. For example... Figure 2 As shown, the interconnect pillars can be divided into first interconnect pillar 101-1, second interconnect pillar 101-2, third interconnect pillar 101-3, and fourth interconnect pillar 101-4; the pads can be divided into first pad 41, second pad 42, third pad 43, and fourth pad 44.

[0059] Taking the first chip package 10 as an example, the first interconnect post 101-1 at the bottom of the first chip 100 is connected to the first metal plane M31 through the first pad 41 disposed on the first wiring layer 31. The second chip package 20, the third chip package 30 and the fourth chip package 40 are similar.

[0060] In a further optimization of the foregoing embodiments, at least one of the chips includes a conductive pillar located on its top, and the chip also includes a communication structure connecting the interconnect pillar and the conductive pillar, wherein the conductive pillar is electrically connected to a metal plane in a wiring layer on one side of the top of the chip.

[0061] The connecting structure can be a TSV conductive pillar. For example... Figure 2 As shown, the conductive pillars can be divided into a first conductive pillar 103-1, a second conductive pillar 103-2, and a third conductive pillar 103-3, and the connecting structure can be divided into a first TSV conductive pillar 102-1, a second TSV conductive pillar 102-2, a third TSV conductive pillar 102-3, and a fourth TSV conductive pillar 102-4.

[0062] Taking the first chip package 10 as an example, the first interconnect post 101-1 of the first chip 100 is connected to the first conductive post 103-1 through the first TSV conductive post 102-1. The first conductive post 103-1 is electrically connected to the second metal layer 32a in the second wiring layer 32. The second chip package 20 and the third chip package 30 are similar.

[0063] In a further optimization of the aforementioned embodiments, in addition to the highest and lowest wiring layers, there are metal layers for electrical connection with conductive pillars of the underlying chip.

[0064] In this configuration, of the N wiring layers, except for the first and Nth layers, the second to (N-1)th wiring layers may each have a metal layer for connecting to the conductive pillars of the chip in the encapsulation layer below. The metal layer is also connected to a metal plane within the same wiring layer. The wiring layer includes a dielectric layer and a metal layer, such as... Figure 1 , Figure 2 As shown, the dielectric layer can be divided into a first dielectric layer 31b, a second dielectric layer 32b, a third dielectric layer 33b, a fourth dielectric layer 34b, and a fifth dielectric layer 35b; the metal layer can be divided into a second metal layer 32a, a third metal layer 33a, a fourth metal layer 34a, and a fifth metal layer 35a.

[0065] Taking the first chip package 10 as an example, the first conductive post 103-1 on the top of the first chip 100 is connected to the second metal plane M32 through the second metal layer 32a in the second wiring layer 32. The second chip package 20 and the third chip package 30 are similar. For the fourth chip package 40, as... Figure 1 As shown, the fifth metal layer 35a can be used only to connect the fifth metal plane M35 and the fourth metal sidewall Z4.

[0066] In one embodiment, the bottom of the chip is provided with a bottom fill layer covering the interconnect pillars and pads.

[0067] Among them, such as Figure 2As shown, the bottom fill layer can be divided into a first bottom fill layer 51, a second bottom fill layer 52, a third bottom fill layer 53, and a fourth bottom fill layer 54; the interconnect pillars 101 can be divided into a first interconnect pillar 101-1, a second interconnect pillar 101-2, a third interconnect pillar 101-3, and a fourth interconnect pillar 101-4; and the pads 4 can be divided into a first pad 41, a second pad 42, a third pad 43, and a fourth pad 44.

[0068] Taking the first chip package 10 as an example, the first bottom filler layer 51 is used to fill the bottom space of the first chip 100 and cover the first interconnect pillar 101-1 and the first pad 41. Its function is to redistribute the thermal stress caused by material CTE mismatch between the first interconnect pillar 101-1, the first pad 41, the first wiring layer 31 and the package substrate or PCB board, which can effectively alleviate the warping phenomenon of the chip package. The second chip package 20, the third chip package 30 and the fourth chip package 40 are similar.

[0069] Secondly, the fabrication method of a multi-chip three-dimensional stacked structure with electromagnetic shielding function, such as... Figure 3 As shown, it includes the following steps:

[0070] S1: Prepare a carrier plate 1 with a release layer 2.

[0071] In this step, such as Figure 4 As shown, the carrier 1 provides mechanical support for the chip package through the release layer 2, and the release layer 2 is adhered to the carrier 1 by thermo-press bonding.

[0072] S2: Fabricate a first wiring layer 31 with a first metal plane M31, and fabricate a first pad 41 on the first metal plane M31.

[0073] In this step, such as Figure 4 As shown, a first wiring layer 31 and a first pad 4-1 are fabricated on the release layer 2 of the carrier 1 using photolithography and electroplating processes. The first wiring layer 31 includes a first metal layer 31a and a first dielectric layer 31b. A first metal plane M31, completely covering the base surface of the first metal layer 31a, is fabricated on the base surface of the first metal layer 31a. The first metal plane M31 is flush with the upper surface of the first wiring layer 31.

[0074] S3: Solder the first chip 100 onto the first pad 41.

[0075] In this step, such as Figure 4 As shown, the interconnect between the first chip 100 and the first pad 41 can be formed by hot-press bonding or high-temperature reflow soldering of tin-based alloy solder balls; the first interconnect post 101-1 on the first chip 100 is electrically interconnected with the first pad 41.

[0076] S4: Encapsulate the first chip 100 and perform planarization to form the first encapsulation layer 61.

[0077] In this step, the encapsulation can be achieved using a plastic sealing process. For example... Figure 5 As shown, the first chip 100 is encapsulated to form a first encapsulation layer 61, which covers the external interconnect component on the top of the first chip 100—the first conductive post 103-1; then the first encapsulation layer 6-1 is CMP polished until the first conductive post 103-1 is exposed.

[0078] S5: A through-groove is formed on the first encapsulation layer 61, and metal material is filled into the through-groove to obtain a first metal sidewall Z1, thereby obtaining a first chip package 10.

[0079] In this step, such as Figure 5 As shown, the through-slot surrounds the first chip 100 and exposes a portion of the first metal plane M31. After filling it with metal material, a first metal sidewall Z1 communicating with the first metal plane M31 is obtained. The through-slot can be formed using physical or chemical processes.

[0080] S6: Repeat the process steps S2 to S5 above to fabricate the second chip package 20, the third chip package 30 and the fourth chip package 40.

[0081] In this step, such as Figure 1 As shown, the following were prepared: a second metal sidewall Z2, a third metal sidewall Z3, and a fourth metal sidewall Z4, as well as a third metal plane M33 and a fourth metal plane M34.

[0082] The third metal layer 33a forms a closed connection with the second metal sidewall Z2 and the third metal base surface M33, and the fourth metal layer 34a forms a closed connection with the third metal sidewall Z3 and the fourth metal base surface M34.

[0083] Specifically, after step S5: a second wiring layer 32 and a second pad 42 are fabricated on the first encapsulation layer 61. Wherein... Figure 6 As shown, the second wiring layer 32 includes a second metal layer 32a and a second dielectric layer 32b. The second wiring layer 32 and the second pad 42 are fabricated on the first encapsulation layer 61 using photolithography and electroplating processes. A second metal base surface M32, completely covering the base surface of the second metal layer 32a, is fabricated on the base surface using an electroplating process. The second metal plane M32 is flush with the upper surface of the second wiring layer 32. This forms a closed connection between the second metal layer 32a, the first metal sidewall Z1, and the second metal base surface M32, thereby constructing a closed electromagnetic shielding cavity. The remaining repeated steps are similar and will not be described in detail.

[0084] S7: A fifth wiring layer 35 having a fifth metal plane M35 is formed on the fourth chip package 40.

[0085] In this step, such as Figure 1 , Figure 2 As shown, the fifth wiring layer 35 includes a fifth metal layer 35a and a fifth dielectric layer 35b. The fifth metal layer 35a forms a closed connection with the fourth metal sidewall Z4 and the fifth metal plane M35.

[0086] S8: For the prepared product, such as Figure 1 The multi-layered stacked chip package shown is divided and the carrier board is removed to obtain a three-dimensional stacked structure that provides complete electromagnetic shielding for individual chips.

[0087] The chip can be any type of functional chip, such as an HBM chip. This fabrication method enables the vertical three-dimensional stacking of multiple enclosed electromagnetic shielding cavities containing embedded chips. These cavities construct an equipotential Faraday electromagnetic shielding cage, solving the electromagnetic interference problem inherent in single chips in existing technologies, as well as the signal crosstalk problem during signal transmission.

[0088] In one embodiment, the following steps may be included before step S4:

[0089] The first chip 100 is bottom-filled to form a first bottom-fill layer 51.

[0090] In this step, the first bottom filler layer 51 is used to fill the first interconnect pillar 101-1 and the first pad 4-1. Its function is to redistribute the thermal stress caused by material CTE mismatch between the first interconnect pillar 101-1, the first pad 4-1, the first wiring layer 31 and the packaging substrate or PCB board, which can effectively alleviate the warping phenomenon of the chip package.

[0091] In one embodiment, in step S4, if the chip includes conductive pillars located on its top, the conductive pillars are exposed after the planarization process.

[0092] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A multi-chip three-dimensional stacked structure with electromagnetic shielding function, characterized in that, It includes N wiring layers and N-1 encapsulation layers stacked alternately. Each wiring layer has a metal plane, and each encapsulation layer has a chip and a metal sidewall surrounding the chip. The metal sidewall in each encapsulation layer is closedly connected to the metal plane in two adjacent wiring layers to encapsulate the chip in the encapsulation layer. The chip includes interconnect pillars located at its bottom, which are electrically connected to a metal plane in a wiring layer on one side of the bottom of the chip; the interconnect pillars can be connected to the metal plane via pads disposed on the wiring layer. At least one of the chips includes a conductive pillar located on its top, and the chip further includes a communication structure connecting the interconnect pillar and the conductive pillar, the conductive pillar being electrically connected to a metal plane in a wiring layer on one side of the top of the chip; the communication structure is a TSV conductive pillar.

2. The multi-chip three-dimensional stacked structure with electromagnetic shielding function as described in claim 1, characterized in that: In addition to the top and bottom layers, the other wiring layers have metal layers for electrical connection with conductive pillars of the underlying chip.

3. The multi-chip three-dimensional stacked structure with electromagnetic shielding function as described in claim 1, characterized in that: The bottom of the chip is provided with a bottom fill layer that covers the interconnect pillars and pads.

4. A method for fabricating a multi-chip three-dimensional stacked structure with electromagnetic shielding function, characterized in that, Includes the following steps: Prepare a carrier plate with a release layer; Cyclic step 1: Create a wiring layer with a metal plane, and create pads on the metal plane; Cyclic step 2: Solder the chip onto the pads; Cyclic step 3: Encapsulate the chip and planarize it to form an encapsulation layer; Cyclic step 4: Create a through-groove through the encapsulation layer, and fill the through-groove with metal material to obtain a metal sidewall; Repeat the cycle steps 1 to 4 until the chips are stacked to a preset number; A wiring layer with a metal plane is fabricated on the topmost encapsulation layer; The prepared multi-layer stacked chip package is divided and the carrier board is removed to obtain a multi-chip three-dimensional stacked structure with electromagnetic shielding function. Each of the metal sidewalls is closedly connected to the adjacent metal plane.

5. The method for fabricating a multi-chip three-dimensional stacked structure with electromagnetic shielding function as described in claim 4, characterized in that, Before the cyclic step 3, the following steps may also be included: The chip is underfilled to form an underfill layer.

6. The method for fabricating a multi-chip three-dimensional stacked structure with electromagnetic shielding function as described in claim 4, characterized in that: In the cyclic step 3, if the chip includes conductive pillars located on its top, the conductive pillars are exposed after the planarization process.

7. A method for fabricating a multi-chip three-dimensional stacked structure with electromagnetic shielding function as described in any one of claims 4 to 6, characterized in that: The chip is an HBM chip.

8. A method for fabricating a multi-chip three-dimensional stacked structure with electromagnetic shielding function as described in any one of claims 4 to 6, characterized in that: The metal plane and metal sidewalls are made of copper.

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