Substrate for flat panel detector testing and its testing method

Abstract

An embodiment of the present invention discloses a substrate for testing a flat panel detector and a testing method thereof. In the embodiment of the present invention, the characteristics of the TFTs in the entire testing area are tested. Compared with the prior art in which TFT test keys (Tegs) are used to test the characteristics of TFTs in the peripheral area outside the detection area, the present invention can obtain true and effective I-V data of the TFTs in the AA area. Therefore, the IV characteristics of the TFTs in the AA area can be truly and accurately reflected, effectively avoiding the problem of inaccurate test data in the Teg area in the prior art; moreover, in the detection area of the embodiment of the present invention, only TFTs and voltage lines for testing are fabricated, and the test response speed is faster.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic detection, and particularly relates to a substrate for testing a flat panel detector and a testing method thereof. Background Art

[0002] X-ray detection technology is widely used in industrial non-destructive testing, container scanning, circuit board inspection, medical, security, industry and other fields, and has broad application prospects. Traditional X-Ray imaging technology belongs to analog signal imaging, with low resolution and poor image quality. X-ray digital imaging technology uses an X-ray flat panel detector to directly convert an X-ray image into a digital image. Because the converted digital image is clear, has high resolution, and is easy to save and transmit, it has been widely developed and applied.

[0003] An X-ray flat panel detector generally includes a thin film transistor (TFT) and a photodiode. Under X-ray irradiation, the scintillator layer or phosphor layer of an indirect conversion type X-ray flat panel detector converts X-ray photons into visible light, and then under the action of the photodiode, the visible light is converted into an electrical signal. Finally, the electrical signal is read by the TFT and output, and after A / D conversion, the electrical signal forms a digital signal, and a computer then performs image processing on the digital signal to form an X-ray digital image.

[0004] During the design and manufacture of a flat panel detector, we usually design a TFT Teg test key (Testkey) outside the AA area around the Panel to monitor the relevant characteristics of the pixels TFT in the AA area. However, in the actual production process, due to differences in the position, pattern density, etc. between the test Teg area and the AA area, and affected by processes such as etching, there are differences in the TFT characteristics between the test Teg area and the AA area. Summary of the Invention

[0005] A substrate for testing a flat panel detector and a testing method thereof provided by an embodiment of the present invention are used to solve the problem that there are differences in the TFT characteristics between the test Teg area and the AA area when testing the TFT characteristics of a flat panel detector.

[0006] An embodiment of the present invention provides a substrate for testing a flat panel detector, including a substrate, the substrate having a test area and a peripheral area disposed around the test area, the test area including a plurality of gate lines and a plurality of data lines located on the substrate; the plurality of gate lines and the plurality of data lines intersect to define a plurality of detection areas, and each of the detection areas includes a thin film transistor;

[0007] It further includes a test metal layer on the side of the thin film transistor away from the substrate, and the test metal layer includes a plurality of test voltage lines which are electrically connected to the source electrodes of the thin film transistors.

[0008] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, the test metal layer further includes a light-shielding portion electrically connected to the test voltage lines, and the orthographic projection of the light-shielding portion on the substrate covers the orthographic projection of the active layer of the thin film transistor on the substrate.

[0009] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, the orthographic projection of the light-shielding portion on the substrate further covers the orthographic projection of the source electrode of the thin film transistor on the substrate, and the test voltage line is electrically connected to the source electrode through the light-shielding portion.

[0010] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, it further includes an insulating layer between the thin film transistor and the test metal layer, and the light-shielding portion is electrically connected to the source electrode through a via hole penetrating the insulating layer.

[0011] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, the test voltage line and the light-shielding portion are of an integral structure.

[0012] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, the test voltage line extends in the same direction as the data line.

[0013] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, the source electrodes of the thin film transistors in the same column are electrically connected to the same test voltage line, and the source electrodes of the thin film transistors in different columns are electrically connected to different test voltage lines.

[0014] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, the light-shielding portions correspond to the thin film transistors one by one.

[0015] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, it further includes a test signal input terminal in the peripheral area, and all the test voltage lines are electrically connected to the same test signal input terminal.

[0016] Optionally, in the above-mentioned substrate for testing a flat panel detector provided by an embodiment of the present invention, it further includes a gate signal input terminal in the peripheral area, and all the gate lines are electrically connected to the same gate signal input terminal.

[0017] Optionally, in the substrate for testing a flat panel detector provided in the embodiments of the present invention, a data signal input terminal is further included in the peripheral region, and all the data lines are electrically connected to the same data signal input terminal.

[0018] Correspondingly, the embodiments of the present invention further provide a method for testing a substrate for testing a flat panel detector, where the substrate for testing a flat panel detector is the substrate for testing a flat panel detector as described in any one of the above, and the testing method includes:

[0019] Simultaneously apply a gate signal to all the gate lines, simultaneously apply a test voltage signal to all the test voltage lines, and read the electrical signal output by the thin film transistor through the data line to determine the electrical characteristics of the thin film transistor.

[0020] The beneficial effects of the embodiments of the present invention are as follows:

[0021] A substrate for testing a flat panel detector and a testing method thereof provided by the embodiments of the present invention fabricate a thin film transistor (TFT) in each detection region within the test region (AA) of the substrate, and fabricate a test voltage line electrically connected to the source electrode of the thin film transistor. In this way, when testing the characteristics of the TFT, a gate signal can be applied to all the gate lines, a test signal can be applied to all the test voltage lines, and then the electrical signal (current) output by the TFT can be read through the data line. Whether the characteristics of the TFT are normal (whether they conform to the I-V curve of the TFT) can be determined through this electrical signal. If the characteristics of the TFT are normal, then when fabricating the flat panel detector subsequently, the thin film transistor process in the substrate for testing can be used to fabricate the flat panel detector. If the characteristics of the TFT are not normal, it can be determined which step has a problem when fabricating the TFT. In this way, when fabricating the flat panel detector subsequently, the problematic step can be optimized to make the fabricated TFT have good characteristics. Since the embodiments of the present invention test the characteristics of the TFTs in the entire test region, compared with the prior art where TFT Teg is used to test the TFT characteristics in the peripheral region outside the detection region, the present invention can obtain the real and effective I-V data of the TFTs in the AA region. Therefore, the IV characteristics of the TFTs in the AA region can be truly and accurately reflected, effectively avoiding the problem of inaccurate test data in the Teg region in the prior art; moreover, only the TFT and the test voltage line are fabricated in the detection region in the embodiments of the present invention, and the test response speed is faster. Description of the Drawings

[0022] Figure 1 A schematic plan view of a substrate for testing a flat panel detector provided by an embodiment of the present invention;

[0023] Figure 2 is Figure 1 a schematic structural view of four detection regions in

[0024] Figure 3 is Figure 2 a schematic cross-sectional view along the CC’ direction in

[0025] Figure 4 a schematic structural view of a thin-film transistor in a substrate for testing a flat panel detector provided by an embodiment of the present invention;

[0026] Figure 5 is Figure 2 a schematic structural view of a detection area in Detailed implementation manners

[0027] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. And, without conflict, the embodiments and features in the embodiments of the present invention may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0028] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the ordinary meanings understood by those of ordinary skill in the art to which the present invention pertains. The terms "including" or "comprising" and the like used in the present invention mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms "connected" or "coupled" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "inner", "outer", "upper", "lower", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0029] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of the present invention. And the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0030] An embodiment of the present invention provides a substrate for testing a flat panel detector, as Figures 1 - 3 shown, Figure 1 is a schematic plan view of the substrate for testing a flat panel detector, Figure 2 schematically showing Figure 1 the specific structural schematic views of four detection areas P in Figure 3 is Figure 2Schematic cross-sectional view along the CC' direction. The substrate for testing the flat panel detector includes a substrate 1, which has a test area AA and a peripheral area BB arranged around the test area AA. The test area AA includes a plurality of gate lines G and a plurality of data lines D located on the substrate 1; the plurality of gate lines G and the plurality of data lines D intersect to define a plurality of detection areas P, and each detection area P includes a thin film transistor 2;

[0031] It also includes a test metal layer 3 on the side of the thin film transistor 2 away from the substrate 1. The test metal layer 3 includes a plurality of test voltage lines T, and the test voltage lines T are electrically connected to the source electrode 21 of the thin film transistor 2.

[0032] In the substrate for testing the flat panel detector provided by the embodiment of the present invention, a thin film transistor (TFT) is fabricated in each detection area within the test area (AA) of the substrate, and a test voltage line electrically connected to the source electrode of the thin film transistor is fabricated. In this way, when testing the characteristics of the TFT, a gate signal can be loaded to all gate lines, a test signal can be loaded to all test voltage lines, and then the electrical signal (current) output by the TFT can be read through the data line. Whether the characteristics of the TFT are normal (whether they conform to the I-V curve of the TFT) can be judged through this electrical signal. If the TFT characteristics are normal, then in the subsequent fabrication of the flat panel detector, the thin film transistor process in the test substrate can be used to fabricate the flat panel detector. If the TFT characteristics are abnormal, it can be judged which step has problems during the fabrication of the TFT. In this way, in the subsequent fabrication of the flat panel detector, the problematic steps are optimized to make the fabricated TFT have good characteristics. Since the embodiment of the present invention tests the characteristics of the TFTs in the entire test area, compared with the prior art in which TFT test keys (Teg) are used to test the TFT characteristics in the peripheral area outside the detection area, the present invention can obtain real and effective I-V data of the TFTs in the AA area. Therefore, the IV characteristics of the TFTs in the AA area can be truly and accurately reflected, effectively avoiding the problem of inaccurate test data in the Teg area in the prior art; moreover, in the detection area of the embodiment of the present invention, only the TFT and the test voltage line are fabricated, and the test response speed is faster.

[0033] Specifically, in the substrate for testing the flat panel detector provided by the embodiment of the present invention, the fabrication process of the thin film transistor is the same as the mass production process flow in the prior art, and the present invention only adds 1 mask design for the test metal layer, with a relatively low cost.

[0034] Specifically, in the substrate for testing the flat panel detector provided by the embodiment of the present invention, large-size samples can be tested, which is convenient for subsequent test operations.

[0035] Specifically, to clearly show the structure of the thin film transistor 2 and the test voltage line T in each detection area P, as Figure 4 andFigure 5 As shown Figure 4 is the structure of the thin film transistor 2 in a detection region P Figure 5 is the structure of the thin film transistor 2 in a detection region P and the test voltage line T

[0036] In specific implementation, in the above-mentioned flat panel detector test substrate provided by the embodiments of the present invention, as Figures 3 - 5 shown, the test metal layer 3 further includes a light-shielding portion 31 electrically connected to the test voltage line T, and the orthographic projection of the light-shielding portion 31 on the substrate 1 covers the orthographic projection of the active layer 22 of the thin film transistor 2 on the substrate 1. In this way, the light-shielding portion 31 can block the active layer 22 to reduce the influence of light on the active layer 22 and improve the stability of the thin film transistor 2

[0037] In specific implementation, in the above-mentioned flat panel detector test substrate provided by the embodiments of the present invention, as Figure 3 and Figure 5 shown, the orthographic projection of the light-shielding portion 31 on the substrate 1 also covers the orthographic projection of the source electrode 21 of the thin film transistor 2 on the substrate 1, and the test voltage line T is electrically connected to the source electrode 21 through the light-shielding portion 31; it further includes an insulating layer 4 located between the thin film transistor 2 and the test metal layer 3, and the light-shielding portion 31 is electrically connected to the source electrode 21 through a via hole penetrating the insulating layer 4. In this way, the test voltage line T can provide a test signal to the source electrode 21 through the light-shielding portion 31

[0038] In specific implementation, in the above-mentioned flat panel detector test substrate provided by the embodiments of the present invention, as Figure 3 and Figure 5 shown, the test voltage line T and the light-shielding portion 31 are of an integral structure. In this way, only by changing the original layout pattern when forming the test voltage line T, the patterns of the light-shielding portion 31 and the test voltage line T can be formed through one lithography process, without adding a process for separately preparing the light-shielding portion 31, which can simplify the manufacturing process flow, save production costs, and improve production efficiency

[0039] Specifically, as Figure 5 shown, in order to simplify the manufacturing process, the light-shielding portion 31 can be directly designed as a square to completely block the thin film transistor 2

[0040] In specific implementation, in the above-mentioned flat panel detector test substrate provided by the embodiments of the present invention, as Figure 2 and Figure 5 shown, the test voltage line T can be in the same extending direction as the data line D

[0041] In specific implementation, in the above-mentioned flat panel detector test substrate provided by the embodiments of the present invention, as Figure 1 and Figure 2As shown, the source electrodes 21 of the thin film transistors 2 in the same column are electrically connected to the same test voltage line T, and the source electrodes of the thin film transistors 2 in different columns are electrically connected to different test voltage lines T. This can reduce the number of test voltage lines T and simplify the manufacturing process.

[0042] In specific implementation, in the above-mentioned test substrate for a flat panel detector provided by the embodiment of the present invention, as Figure 2 and Figure 5 shown, the light-shielding portions 31 correspond to the thin film transistors 2 one by one, so that all the thin film transistors 2 can be prevented from being irradiated by light and the stability of all the thin film transistors 2 can be ensured.

[0043] Specifically, as Figures 2 - 5 shown, the thin film transistor 2 further includes a gate electrode 23 and a drain electrode 24, and further includes a gate insulating layer 5 located between the gate electrode 23 and the active layer 22. The gate line G is electrically connected to the gate electrode 23, and the data line D is electrically connected to the drain electrode 24.

[0044] In specific implementation, in the above-mentioned test substrate for a flat panel detector provided by the embodiment of the present invention, as Figure 1 shown, it further includes a test signal input terminal INPUT1 located in the peripheral region BB. All the test voltage lines T are electrically connected to the same test signal input terminal INPUT1. In this way, a test signal can be input to all the test voltage lines T through the test signal input terminal INPUT1 and transmitted to the source electrode 21 of the thin film transistor 2.

[0045] Specifically, as Figure 1 shown, all the test voltage lines T can be led out from below the substrate 1 and electrically connected to the same metal wire 6, and then the metal wire 6 is electrically connected to the test signal input terminal INPUT1, that is, all the test voltage lines T are electrically connected to each other. When the gate electrode of the thin film transistor 2 is turned on, a test voltage signal is simultaneously input to all the test voltage lines T through the test signal input terminal INPUT1 so that a voltage difference is generated between the source electrode 21 and the drain electrode 24 of the thin film transistor 2.

[0046] In specific implementation, in the above-mentioned test substrate for a flat panel detector provided by the embodiment of the present invention, as Figure 1As shown, it further includes a gate signal input terminal INPUT2 located in the peripheral region BB, and all gate lines G are electrically connected to the same gate signal input terminal INPUT2. Specifically, all gate lines G can be led out to the bonding area on the left side of the substrate 1. Since the present invention is mainly used for testing large-size products, for example, the size of the substrate 1 is 43 cm × 43 cm, the number of gate lines G is relatively large (only some gate lines G are schematically shown in the present invention). All gate lines G can be divided into several regions, for example, 6 regions. Each region includes a certain number of gate lines G. The gate lines G in each region are led out to the bonding area and electrically connected to the same bonding pad. The gate lines G in different regions are led out to the bonding area and electrically connected to different bonding pads. For example, in the embodiment of the present invention Figure 1 only shows two regions. The gate lines G in one region are electrically connected to the first pad pad1, and the gate lines G in the other region are electrically connected to the second pad pad2. The first pad pad1 and the second pad pad2 are electrically connected through the first conductive connection portion 7. In this way, all gate lines G can be electrically connected to the same gate signal input terminal INPUT2, that is, all gate lines G are electrically connected to each other. In this way, a gate signal is input to all gate lines G simultaneously through the gate signal input terminal INPUT2 to turn on or off all TFTs in the test area AA simultaneously.

[0047] In specific implementation, in the above-mentioned substrate for flat panel detector testing provided by the embodiment of the present invention, as Figure 1 shown, it further includes a data signal input terminal INPUT3 located in the peripheral region BB, and all data lines D are electrically connected to the same data signal input terminal INPUT3. Specifically, all data lines D can be led out to the bonding area on the lower side of the substrate 1. Since the present invention is mainly used for testing large-size products, for example, the size of the substrate 1 is 43 cm × 43 cm, the number of data lines D is relatively large (only some data lines D are schematically shown in the present invention). All data lines D can be divided into several regions, for example, 6 regions. Each region includes a certain number of data lines D. The data lines D in each region are led out to the bonding area and electrically connected to the same bonding pad. The data lines D in different regions are led out to the bonding area and electrically connected to different bonding pads. For example, in the embodiment of the present invention Figure 1 only shows two regions. The data lines D in one region are electrically connected to the third pad pad3, and the data lines D in the other region are electrically connected to the fourth pad pad4. The third pad pad3 and the fourth pad pad4 are electrically connected through the second conductive connection portion 8. In this way, all data lines D can be electrically connected to the same data signal input terminal INPUT3, that is, all data lines D are electrically connected to each other, and are used to read the electrical signals output by all TFTs in the test area AA to judge the I-V characteristics of the TFTs.

[0048] It should be noted that the materials of the first conductive connection part 7 and the second conductive connection part 8 in the embodiments of the present invention can be metals, and the first conductive connection part 7, the second conductive connection part 8 and the test voltage line T can be of the same layer of metal. In this way, only by changing the original layout pattern when forming the test voltage line T, the patterns of the first conductive connection part 7, the second conductive connection part 8 and the test voltage line T can be formed through one lithography process, without adding a process for separately preparing the first conductive connection part 7 and the second conductive connection part 8, which can simplify the preparation process flow, save production costs and improve production efficiency.

[0049] Specifically, as Figure 1 shown, in order to improve the wiring uniformity of the bonding area, a floating electrode 9 is generally provided in the blank area (dummy area).

[0050] The following describes the test method for testing the characteristics of thin film transistors on the flat panel detector test substrate provided by the embodiments of the present invention.

[0051] As Figure 1 and Figure 2 shown, a gate signal is simultaneously input to all gate lines G through the gate signal input terminal INPUT2 to simultaneously turn on all TFTs in the test area AA; a test voltage signal is simultaneously input to all test voltage lines T through the test signal input terminal INPUT1 to generate a voltage difference between the source 21 and the drain 24 of the thin film transistor 2, and the electrical signals output by all TFTs in the test area AA are read through the data line D to determine the electrical characteristics (I-V) of the TFT.

[0052] Based on the same general inventive concept, the embodiments of the present invention also provide a test method for a flat panel detector test substrate. The flat panel detector test substrate is the above-mentioned flat panel detector test substrate provided by the embodiments of the present invention. The test method includes:

[0053] A gate signal is simultaneously loaded to all gate lines, a test voltage signal is simultaneously loaded to all test voltage lines, and the electrical signals output by the thin film transistors are read through the data line to determine the electrical characteristics of the thin film transistors.

[0054] Specifically, the test method for the above-mentioned flat panel detector test substrate can refer to the test method in the foregoing flat panel detector test substrate, and the repeated parts will not be described herein again.

[0055] A substrate for testing a flat panel detector and a testing method thereof provided by an embodiment of the present invention fabricate thin film transistors (TFTs) in each detection area within a testing area (AA) of a substrate, and fabricate test voltage lines electrically connected to the source electrodes of the thin film transistors. In this way, when testing the characteristics of the TFTs, gate signals can be loaded onto all gate lines, test signals can be loaded onto all test voltage lines, and then the electrical signals (currents) output by the TFTs can be read through data lines. Whether the characteristics of the TFTs are normal (whether they conform to the I-V curve of the TFTs) can be determined based on these electrical signals. If the characteristics of the TFTs are normal, then when fabricating the flat panel detector subsequently, the thin film transistor process in the test substrate can be used to fabricate the flat panel detector. If the characteristics of the TFTs are abnormal, it can be determined which step has problems during the fabrication of the TFTs. Then, when fabricating the flat panel detector subsequently, the problematic steps can be optimized to make the fabricated TFTs have good characteristics. Since the embodiment of the present invention tests the characteristics of the TFTs in the entire testing area, compared with the prior art where TFT test keys (Tegs) are used to test the characteristics of the TFTs in the peripheral area outside the detection area, the present invention can obtain true and effective I-V data of the TFTs in the AA area. Therefore, it can truly and accurately reflect the IV characteristics of the TFTs in the AA area, effectively avoiding the problem of inaccurate test data in the Teg area in the prior art; moreover, only TFTs and test voltage lines are fabricated in the detection area in the embodiment of the present invention, and the test response speed is faster.

[0056] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0057] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.

Claims

1. A substrate for testing a flat panel detector, characterized in that It includes a substrate, the substrate having a test area and a peripheral area disposed around the test area, the test area including a plurality of gate lines and a plurality of data lines located on the substrate; the plurality of gate lines and the plurality of data lines intersect to define a plurality of detection areas, each detection area including a thin film transistor; It further includes a test metal layer located on a side of the thin film transistor away from the substrate, the test metal layer including a plurality of test voltage lines, the test voltage lines being electrically connected to the source electrodes of the thin film transistors; the test metal layer further includes a light-shielding portion electrically connected to the test voltage lines, a positive projection of the light-shielding portion on the substrate covering a positive projection of the active layer of the thin film transistor on the substrate, the test voltage lines and the light-shielding portion being an integral structure.

2. The substrate for testing a flat panel detector according to claim 1, wherein The positive projection of the light-shielding portion on the substrate further covers a positive projection of the source electrode of the thin film transistor on the substrate, the test voltage lines being electrically connected to the source electrode through the light-shielding portion.

3. The substrate for testing a flat panel detector according to claim 2, characterized in that, It further includes an insulating layer located between the thin film transistor and the test metal layer, the light-shielding portion being electrically connected to the source electrode through a via hole penetrating the insulating layer.

4. The substrate for testing a flat panel detector according to any one of claims 1-3, characterized in that The test voltage lines have the same extending direction as the data lines.

5. The substrate for testing a flat panel detector according to any one of claims 1-3, characterized in that, The source electrodes of the thin film transistors in the same column are electrically connected to the same test voltage line, and the source electrodes of the thin film transistors in different columns are electrically connected to different test voltage lines.

6. The substrate for testing a flat panel detector according to claim 5, wherein, The light-shielding portions correspond to the thin film transistors one by one.

7. The substrate for flat panel detector testing according to any one of claims 1-3, characterized in that It further includes a test signal input terminal located in the peripheral area, all the test voltage lines being electrically connected to the same test signal input terminal.

8. The substrate for testing a flat panel detector according to any one of claims 1-3, characterized in that, It further includes a gate signal input terminal located in the peripheral area, all the gate lines being electrically connected to the same gate signal input terminal.

9. The substrate for testing a flat panel detector according to any one of claims 1-3, characterized in that, It further includes a data signal input terminal located in the peripheral area, all the data lines being electrically connected to the same data signal input terminal.

10. A test method for a substrate used in testing a flat panel detector, characterized in that, The test substrate for the flat panel detector is the test substrate for the flat panel detector according to any one of claims 1-9, and the test method includes: Simultaneously applying a gate signal to all the gate lines, simultaneously applying a test voltage signal to all the test voltage lines, and reading the electrical signals output by the thin film transistors through the data lines to determine the electrical characteristics of the thin film transistors.

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