Epitaxial structure of semiconductor device, device and method for preparing epitaxial structure

Abstract

The application relates to an epitaxial structure of a semiconductor device, a device and a preparation method of the epitaxial structure. The epitaxial structure comprises a substrate, a first semiconductor layer located on the substrate, and the first semiconductor layer comprises a buffer layer, the buffer layer at least comprising a first buffer layer, a second buffer layer and a third buffer layer which are arranged in a stack, and the second buffer layer is located between the first buffer layer and the third buffer layer. In the buffer layer, iron impurities are doped, and the iron impurities are concentratedly distributed in the second buffer layer. The epitaxial structure can realize a high-resistance buffer layer, and meanwhile, the crystal quality and the subthreshold characteristics of the device are considered.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to an epitaxial structure of a semiconductor device, the device and a preparation method of the epitaxial structure. BACKGROUND

[0002] Gallium nitride (GaN) has a large band gap, high electron mobility, high breakdown field strength, good heat conduction performance and other characteristics, and has strong spontaneous and piezoelectric polarization effects. Compared with the first generation of semiconductor materials and the second generation of semiconductor materials, it is more suitable for manufacturing high-frequency, high-voltage and high-temperature-resistant high-power electronic devices, especially in the fields of radio frequency and power supply.

[0003] In a gallium nitride high electron mobility transistor (GaN HEMT) structure, in order to obtain better device leakage characteristics and pinch-off characteristics, the buffer layer is usually set to be high resistance. It is extremely difficult to make intrinsic GaN material achieve high resistance in the process, but the high resistance of the buffer layer can be achieved by introducing acceptor impurities during the growth of the buffer layer. Common acceptor impurities include carbon (C) atoms or iron (Fe) atoms.

[0004] Deep level traps formed by doping can capture buffer layer electrons to achieve high resistance, but will also affect the crystal quality of the buffer layer and the subthreshold characteristics of the device. Therefore, it is necessary to find an epitaxial structure that can ensure the high resistance characteristics of the buffer layer while also considering the subthreshold characteristics of the device. SUMMARY

[0005] Therefore, it is necessary to provide an improved epitaxial structure of a semiconductor device to solve the problem that it is difficult to consider the crystal quality and the subthreshold characteristics of the device when preparing a high-resistance buffer layer in a traditional semiconductor material.

[0006] An epitaxial structure of a semiconductor device, comprising:

[0007] a substrate;

[0008] a first semiconductor layer located on the substrate, the first semiconductor layer comprising a buffer layer, the buffer layer comprising at least a first buffer layer, a second buffer layer and a third buffer layer stacked;

[0009] wherein the buffer layer is doped with iron impurities, and the iron impurities are concentrated in the second buffer layer.

[0010] The epitaxial structure of the semiconductor device, the buffer layer includes at least a first buffer layer, a second buffer layer and a third buffer layer, the buffer layer is doped with iron impurities and the iron impurities are concentrated in the second buffer layer, thereby on the one hand, the high resistance of the buffer layer is achieved, and the better leakage and pinch-off characteristics of the device are obtained; on the other hand, in the epitaxial structure, the iron impurities can be concentrated in the middle buffer layer in a suitable concentration range, and the buffer layers close to the substrate and the second semiconductor layer have almost no or only a small amount of iron impurities, thereby the crystal quality of the buffer layer is improved, and the DIBL effect and the tailing effect of the iron impurities of the device are improved, and the sub-threshold characteristics of the device are improved, and the reliability of the device is ensured.

[0011] In one of the embodiments, the second buffer layer is also doped with carbon impurities, and the carbon impurity concentration of the second buffer layer is less than the iron impurity concentration of the second buffer layer.

[0012] In one of the embodiments, the iron impurity concentration of the second buffer layer satisfies a first preset range, the first preset range includes , and the carbon impurity concentration of the second buffer layer satisfies a second preset range, the second preset range includes .

[0013] In one of the embodiments, the thickness of the second buffer layer is , wherein 200nm≤ ≤800nm.

[0014] In one of the embodiments, the first buffer layer is located on the side of the second buffer layer close to the substrate, and the third buffer layer is located on the side of the second buffer layer close to the second semiconductor layer; wherein the first buffer layer has carbon impurities, the carbon impurity concentration of the first buffer layer is less than or equal to the carbon impurity concentration of the second buffer layer; and the third buffer layer has carbon impurities, the carbon impurity concentration of the third buffer layer is less than the carbon impurity concentration of the first buffer layer.

[0015] In one of the embodiments, the carbon impurity concentration of the first buffer layer is less than or equal to , the carbon impurity concentration of the second buffer layer is greater than or equal to and less than or equal to , and the carbon impurity concentration of the third buffer layer is less than or equal to .

[0016] In one of the embodiments, the thickness of the third buffer layer is , wherein 200nm≤ ≤500nm.

[0017] In one of the embodiments, the first buffer layer has a thickness of wherein 200 nm ≤ ≤ 800 nm.

[0018] In one of the embodiments, the first semiconductor layer further comprises a nucleation layer, the nucleation layer is located on the substrate, and the buffer layer is located on a side of the nucleation layer away from the substrate.

[0019] The application further provides a semiconductor device.

[0020] The semiconductor device comprises the epitaxial structure as described above.

[0021] The semiconductor device can be prepared by the epitaxial structure as described above, thereby helping to obtain better device leakage and pinch-off characteristics and improve the sub-threshold characteristics of the device and ensure the reliability of the device.

[0022] The application further provides a preparation method of an epitaxial structure of a semiconductor device.

[0023] The preparation method of the epitaxial structure of the semiconductor device comprises:

[0024] providing a substrate;

[0025] preparing a first semiconductor layer on the substrate; the first semiconductor layer comprises a buffer layer, the buffer layer comprises at least a first buffer layer, a second buffer layer and a third buffer layer which are stacked, the second buffer layer is located between the first buffer layer and the third buffer layer, the buffer layer is doped with iron impurities, and the iron impurities are concentratedly doped in the second buffer layer, and the iron impurity concentration of the second buffer layer satisfies a first preset range; and

[0026] preparing a second semiconductor layer on a side of the first semiconductor layer away from the substrate, and forming a conductive channel in the second semiconductor layer.

[0027] In the preparation method, when the buffer layer is prepared, the first buffer layer, the second buffer layer and the third buffer layer can be formed respectively through three stages, and the iron impurities are concentratedly doped in the second buffer layer, and the iron impurity concentration of the second buffer layer satisfies the first preset range, which helps to realize high resistance of the buffer layer, makes the device obtain better leakage and pinch-off characteristics, and on the other hand, makes the iron impurities concentrated in the middle buffer layer in a suitable concentration range, and makes the buffer layers close to the substrate and the second semiconductor layer have almost no or only a small amount of iron impurities, which helps to improve the crystal quality of the buffer layer, and also helps to improve the drain-induced barrier lowering (DIBL) effect of the device and the trailing effect of the iron impurities, thereby improving the sub-threshold characteristics of the device and ensuring the reliability of the device.

[0028] In one of the embodiments, the preparing the first semiconductor layer on the substrate comprises: epitaxially growing a nucleation layer on the substrate; epitaxially growing the first buffer layer on a side of the nucleation layer away from the substrate; epitaxially growing the second buffer layer on a side of the first buffer layer away from the nucleation layer, while jointly doping iron impurities and carbon impurities into the second buffer layer; the carbon impurity concentration of the second buffer layer satisfies a second preset range, and the carbon impurity concentration of the second buffer layer is less than the iron impurity concentration of the second buffer layer; and epitaxially growing the third buffer layer on a side of the second buffer layer away from the first buffer layer.

[0029] In one of the embodiments, the first buffer layer has carbon impurities, the epitaxially growing the second buffer layer on a side of the first buffer layer away from the nucleation layer comprises: while forming the second buffer layer by the epitaxy process, controlling the carbon impurity concentration of the second buffer layer to be greater than or equal to the carbon impurity concentration of the first buffer layer; and the third buffer layer has carbon impurities, the epitaxially growing the third buffer layer on a side of the second buffer layer away from the first buffer layer comprises: while forming the third buffer layer by the epitaxy process, controlling the carbon impurity concentration of the third buffer layer to be less than the carbon impurity concentration of the first buffer layer. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 A structural schematic diagram of one embodiment of the present application;

[0031] Figure 2 A concentration distribution diagram of carbon impurities and iron impurities in an epitaxial structure of the present application;

[0032] Figure 3 A structural schematic diagram of a buffer layer of another embodiment of the present application.

[0033] The reference signs of the elements in the figures represent the following:

[0034] 100, epitaxial structure, 10, substrate, 20, first semiconductor layer, 30, second semiconductor layer;

[0035] 21, nucleation layer, 22, buffer layer, 221, first buffer layer, 222, second buffer layer, 223, third buffer layer, 224, fourth buffer layer, 225, fifth buffer layer, 31, channel layer, 32, barrier layer. DETAILED DESCRIPTION

[0036] For the purpose of promoting an understanding of the application, the application will now be described in detail with reference to the drawings. In the following drawings, the preferred embodiments of the application are depicted. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0037] It is to be noted that when an element as a preamble is "fixed" to another element, it can be directly on the other element or there can be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there can be an intervening element. The terms "vertical", "horizontal", "left", "right", "upper", "lower", "front", "back", "circumferential", and similar expressions as used herein are based on the orientation or position as shown in the drawings, and are used only for the purpose of describing and simplifying the present application, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the present application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0039] In order to obtain better device leakage and pinch-off characteristics, the buffer layer in the semiconductor device needs to be high resistance. In the conventional process, it can be realized by introducing acceptor impurities during the growth of the buffer layer. However, the higher acceptor impurity concentration in the buffer layer will affect the crystal quality of the buffer layer and the sub-threshold characteristics of the device, thereby causing the reliability of the device to be poor, limiting the application range of the device.

[0040] Therefore, in order to solve the problems existing in the prior art and realize the satisfaction of the high resistance of the buffer layer while reducing the influence of the doping on the crystal quality of the buffer layer and the sub-threshold characteristics of the device, the present application provides a novel epitaxial structure of a semiconductor device. The technical solutions of the present application will be described in detail below through specific embodiments.

[0041] Referring to Figure 1 The present application provides an epitaxial structure of a semiconductor device 100, comprising a substrate 10 and a first semiconductor layer 20, wherein the first semiconductor layer 20 is located on the substrate 10. The substrate 110 can be one or a combination of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, silicon, or any other material capable of growing III-nitride.

[0042] Specifically, the first semiconductor layer 20 includes a buffer layer 22, the buffer layer 22 at least includes a first buffer layer 221, a second buffer layer 222 and a third buffer layer 223 which are stacked, and the second buffer layer 222 is located between the first buffer layer 221 and the third buffer layer 223. It can be understood that the first buffer layer 221 can be located between the substrate 10 and the second buffer layer 222, or located on the side of the second buffer layer 222 away from the substrate 10, so as to Figure 1 For example, the first buffer layer 221 is located between the substrate 10 and the second buffer layer 222, and the third buffer layer 223 is located on the side of the second buffer layer 222 away from the substrate 10. The buffer layer 22 can play a role of bonding the semiconductor material layer which needs to be grown next, and at the same time can protect the substrate 10 from being invaded by some metal ions. The buffer layer 22 can be AlGaN, GaN or AlGaInN, etc. III-nitride material.

[0043] Further, the buffer layer 22 is doped with iron impurities, and the iron impurities are concentratedly distributed in the second buffer layer 222. Wherein, the iron impurities concentratedly distributed in the second buffer layer 222 at least means that when the buffer layer 22 is doped with a certain amount of iron impurities to achieve high resistance, the iron impurity concentration of the second buffer layer 222 is much larger than that of the first buffer layer 221, and the iron impurity concentration of the second buffer layer 222 is also much larger than that of the third buffer layer 223. Preferably, the iron impurities concentratedly distributed in the second buffer layer 222 are at least 1x1018cm-3, and the iron impurities in the first buffer layer 221 are 0, and the iron impurities in the third buffer layer 223 are a small part of the iron impurities due to the tailing effect of the iron impurities, but the content is extremely small, close to 0. Figure 1 For example, the iron impurities of the buffer layer 22 are concentratedly distributed in the second buffer layer 222, the content of the iron impurities in the first buffer layer 221 is 0, and the iron impurities in the third buffer layer 223 will have a small part of the iron impurities due to the tailing effect of the iron impurities, but the content is extremely small, close to 0. The iron impurities of the buffer layer 22 are concentratedly distributed in the second buffer layer 222 which is the middle layer, and the adjacent layer main material in contact with the second buffer layer 222 in which the iron impurities are concentratedly distributed is the same as the second buffer layer 222 main material. That is, the iron impurities of the buffer layer 22 are not in direct contact with the semiconductor layer whose main material is different from the substrate, the nucleation layer or the channel layer, etc.

[0044] Optionally, the semiconductor epitaxial structure can further include a second semiconductor layer 30 located on the side of the first semiconductor layer 20 away from the substrate, and a conductive channel is formed in the second semiconductor layer 30, such as Figure 1As shown, the conductive channel is shown by thick dashed line. Specifically, the second semiconductor layer 30 can include a channel layer 31 and a barrier layer 32. The channel layer 31 can be formed between the buffer layer 22 and the barrier layer 32, can form a heterojunction structure together with the barrier layer 32 above it, and form a two-dimensional electron gas channel (i.e. conductive channel) at the interface. The channel layer 31 provides a channel for the movement of two-dimensional electron gas, and the barrier layer 32 acts as a barrier. The barrier layer 32 can be an AlGaN material, and the Al content thereof can be controlled to be between 0-1%.

[0045] Specifically, the first buffer layer 221, the second buffer layer 222 and the third buffer layer 223 can be sequentially formed by an epitaxial growth process in stages. In the process of forming the first buffer layer 221, the growth conditions are controlled and the iron source is turned off, so that the iron impurity content in the first buffer layer 221 can be 0; in the process of forming the second buffer layer 222, the growth conditions are adjusted and the iron source is turned on, and the flow rate is controlled to make the iron impurity concentrated in the second buffer layer 222; in the process of forming the third buffer layer 223, the growth conditions are continuously adjusted and the iron source is turned off, so as to reduce the iron impurity concentration decaying to the conductive channel, and the iron impurity concentration of the third buffer layer 223 is maintained in a relatively low range. By the above-mentioned manner, the concentrated distribution of iron impurities in the second buffer layer 222 can be achieved. It should be understood that the first buffer layer 221, the second buffer layer 222 and the third buffer layer 223 can also be formed by other growth processes, and the application does not limit the specific preparation process of the buffer layer 22.

[0046] The epitaxial structure 100 of the semiconductor device described above, the buffer layer 22 includes at least the first buffer layer 221, the second buffer layer 222 and the third buffer layer 223, the buffer layer 22 is doped with iron impurities and the iron impurities are concentrated in the second buffer layer 222, and the iron impurity concentration of the second buffer layer 222 satisfies the first preset range, thereby on the one hand, it helps to achieve high resistance of the buffer layer 22, so that the device obtains better leakage and pinch-off characteristics; on the other hand, in the epitaxial structure 100 described above, the iron impurities are concentrated in the middle buffer layer in a suitable concentration range, and the buffer layers close to the substrate and the second semiconductor layer have almost no or only a small amount of iron impurities, thereby helping to improve the crystal quality of the buffer layer 22, and at the same time, it also helps to improve the drain-induced barrier lowering (DIBL) effect and the tailing effect of iron impurities, thereby the subthreshold characteristics of the device can be improved, and the reliability of the device can be ensured. Figure 1The epitaxial structure is shown as an example. The first buffer layer 221 has almost no iron impurities, so that the effect of reducing the leakage induced barrier of the device can be effectively improved while improving the crystal quality of the buffer layer 22. The third buffer layer 223 is further arranged between the second buffer layer 222 and the second semiconductor layer 30. The third buffer layer 223 has a very low concentration of iron impurities, so as to help reduce the content of iron in the channel, avoid the iron impurities entering the channel to cause impurity scattering and reduce the two-dimensional electron gas density and electron mobility, and affect the saturation current and output power of the device.

[0047] In the example embodiment, the second buffer layer 222 is further doped with carbon impurities. The concentration of the carbon impurities in the second buffer layer 222 satisfies a second preset range, and the concentration of the carbon impurities in the second buffer layer 222 is less than the concentration of the iron impurities in the second buffer layer 222.

[0048] Specifically, in order to obtain better crystal quality, a high-temperature and high-pressure epitaxial growth process can be used for crystal growth. Under this growth condition, the concentration of the carbon impurities in the second buffer layer 222 is not very high, and the concentration of the iron impurities is less affected by the temperature and pressure because the iron impurities are doped by flow control. Therefore, the iron impurities can be used as the main acceptor impurities for realizing the high resistance of the buffer layer 22. On the other hand, considering that the concentration of the carbon impurities is easily affected by the temperature and pressure, a suitable concentration of carbon impurities can be further doped in the second buffer layer 222 to compensate for the high resistance effect of the iron impurities, so as to obtain the required high resistance of the buffer layer.

[0049] Further, the first preset range of the concentration of the iron impurities in the second buffer layer 222 includes The second preset range of the concentration of the carbon impurities in the second buffer layer 222 includes The iron impurities and the carbon impurities are deep level acceptors. When the two impurities are doped in the second buffer layer 222 at a suitable concentration, the high resistance and the effect of reducing the leakage of the entire buffer layer 22 can be achieved. If the concentration of the iron impurities is too low, the required high resistance of the buffer layer cannot be achieved. If the concentration of the iron impurities is too high and the concentration of the carbon impurities is too low, the crystal quality and the surface morphology of the buffer layer 22 will be affected. If the concentration of the carbon impurities is too high, the crystal quality of the buffer layer will be deteriorated.

[0050] In the example embodiment, as shown in Figure 1 The first buffer layer 221 is arranged on the side of the second buffer layer 222 close to the substrate 10, and the third buffer layer 223 is arranged on the side of the second buffer layer 222 close to the second semiconductor layer 30. Further, as shown in Figure 2As shown, the first buffer layer 221 has carbon impurities, the carbon impurity concentration of the first buffer layer 221 is less than or equal to the carbon impurity concentration of the second buffer layer 222; and the third buffer layer 223 has carbon impurities, the carbon impurity concentration of the third buffer layer 223 is less than the carbon impurity concentration of the first buffer layer 221. By controlling the carbon impurity concentration of the first buffer layer 221 and the third buffer layer 223 to be less than the carbon impurity concentration of the second buffer layer 222, the crystal quality of the buffer layer 22 can be effectively improved while achieving high resistance; on the other hand, since the carbon impurity concentration of the third buffer layer 223 is easier to adjust, the crystal quality of the buffer layer 22 can be further improved by controlling the carbon impurity concentration of the third buffer layer 223 to be less than the carbon impurity concentration of the first buffer layer 221.

[0051] Further, the carbon impurity concentration of the first buffer layer 221 is less than or equal to , the carbon impurity concentration of the second buffer layer 222 is greater than or equal to and less than or equal to , and the carbon impurity concentration of the third buffer layer 223 is less than or equal to By controlling the carbon impurity concentration of the first buffer layer 221, the second buffer layer 222 and the third buffer layer 223 to meet the above ranges respectively, it is beneficial to achieve high resistance of the buffer layer 22 and improve the crystal quality of the buffer layer 22. When the carbon impurity concentration of each buffer layer is too high, the crystal quality of the buffer layer 22 will be significantly reduced, and when the carbon impurity concentration of the second buffer layer 222 is too low, the high resistance effect of the iron impurity cannot be compensated well.

[0052] In an exemplary embodiment, please continue to refer to Figure 1 , the thickness of the third buffer layer 223 is , wherein 200nm≤ ≤500nm. By controlling the thickness of the third buffer layer 223 to meet the above relationship, the iron impurities in the second buffer layer 222 have a proper distance from the conductive channel, so that the influence of the doped iron impurities on the two-dimensional electron gas in the conductive channel can be reduced. When the third buffer layer 223 is too thin, the distance between the iron impurities in the second buffer layer 222 and the conductive channel is too small, which easily leads to excessive iron impurities decaying to the conductive channel, thereby affecting the saturation current and output power of the device, and the reliability of the device is difficult to guarantee; when the thickness of the third buffer layer 223 is too thick, the growth efficiency of the buffer layer 22 will be affected.

[0053] In an exemplary embodiment, the thickness of the second buffer layer 222 is , wherein 200nm≤ ≤800nm. By controlling the thickness of the second buffer layer 222 to satisfy the above relationship, the high resistance of the buffer layer 22 can be better achieved, and the crystal quality of the buffer layer 22 can be improved. When the second buffer layer 222 is too thin, the high resistance of the entire buffer layer 22 can be affected. When the thickness of the second buffer layer 222 is too thick, the growth efficiency of the buffer layer 22 can be affected. In addition, the second buffer layer 222 is doped with a high concentration of iron impurities. If the thickness of the second buffer layer 222 is too thick, the crystal quality and surface morphology of the second buffer layer 222 can also be affected.

[0054] In an example embodiment, the thickness of the first buffer layer is , where 200nm≤ ≤800nm. By controlling the thickness of the first buffer layer 221 to satisfy the above relationship, the crystal of the first buffer layer 221 can be converted from three-dimensional growth to two-dimensional growth in time, so as to ensure the crystal growth quality of the subsequent buffer layer, and the growth efficiency of the buffer layer 22 will not be affected. When the first buffer layer 221 is too thin, it is very likely that the three-dimensional growth of the first buffer layer 221 will not be converted to two-dimensional growth in time, which will result in poor growth quality of the subsequent buffer layer. When the thickness of the first buffer layer 221 is too thick, the growth efficiency of the buffer layer 22 can be affected.

[0055] In an example embodiment, please refer to Figure 3 The buffer layer 22 can further include a fourth buffer layer 224 and a fifth buffer layer 225. Specifically, the fourth buffer layer 224 is located between the first buffer layer 221 and the second buffer layer 222, and the fifth buffer layer 225 is located between the second buffer layer 222 and the third buffer layer 223. When the first buffer layer 221 is too thin, the fourth buffer layer 224 can be used to compensate for the thickness of the first buffer layer 221. When the third buffer layer 223 is too thin, the fifth buffer layer 225 can be used to compensate for the thickness of the third buffer layer 223. When the second buffer layer 222 is too thin, the fourth buffer layer 224 and / or the fifth buffer layer 225 can be used to compensate for the thickness of the second buffer layer 222. Since the more layers in the buffer layer 22, the more likely it is to affect the growth efficiency of the buffer layer 22, the number of layers of the buffer layer 22 is preferably 3, 4 or 5.

[0056] In an example embodiment, please continue to refer to Figure 1The first semiconductor layer 20 can further include a nucleation layer 21 located on the substrate 10, and the buffer layer 22 located on a side of the nucleation layer 21 away from the substrate 10. The nucleation layer 21 can affect parameters such as the crystal quality, surface morphology and electrical properties of the heterojunction material thereon. The nucleation layer 21 varies with the material of the substrate 10, and mainly serves to match the substrate 10 and the semiconductor material layer in the heterojunction structure. In the present application, the nucleation layer 21 can be formed of high-temperature AlN or low-temperature GaN, and is mainly used to convert the initial three-dimensional growth mode of the buffer layer 22 into a two-dimensional growth mode.

[0057] The present application further provides a semiconductor device including the epitaxial structure 100 as described above. The semiconductor device can be prepared by the epitaxial structure 100 as described above, thereby helping to obtain better device leakage and pinch-off characteristics, and improving the subthreshold characteristics of the device to ensure the reliability of the device. For example, a source, a gate and a drain can be further prepared on the epitaxial structure 100 as described above, thereby obtaining a field effect transistor with better performance.

[0058] The present application further provides a preparation method of an epitaxial structure 100 of a semiconductor device, wherein the structure of the epitaxial structure 100 is shown in the following. Figure 1 The preparation method includes the following steps:

[0059] S1, providing a substrate 10.

[0060] S2, preparing a first semiconductor layer 20 on the substrate 10; the first semiconductor layer 20 includes a buffer layer 22, the buffer layer 22 at least includes a first buffer layer 221, a second buffer layer 222 and a third buffer layer 223 which are stacked, the second buffer layer 222 is located between the first buffer layer 221 and the third buffer layer 223, the buffer layer 22 is doped with iron impurities, and the iron impurities are concentratedly doped in the second buffer layer 222, and the iron impurity concentration of the second buffer layer 222 satisfies a first preset range.

[0061] The preparation method as described above, when preparing the buffer layer 22, can form the first buffer layer 221, the second buffer layer 222 and the third buffer layer 223 through three stages respectively, and concentrate the iron impurities in the second buffer layer 222, and make the iron impurity concentration of the second buffer layer 222 satisfy the first preset range. On the one hand, it helps to realize the high resistance of the buffer layer 22, so that the device obtains better leakage and pinch-off characteristics. On the other hand, the iron impurities are concentrated in the middle buffer layer with a suitable concentration range, and the buffer layers close to the substrate 10 and the second semiconductor layer 30 have almost no or only a small amount of iron impurities, which helps to improve the crystal quality of the buffer layer 22, and at the same time, helps to improve the drain-induced barrier lowering (DIBL) effect and the trailing effect of the iron impurities, thereby improving the subthreshold characteristics of the device and ensuring the reliability of the device.

[0062] In the example embodiment, step S2 specifically comprises:

[0063] S210, epitaxially growing a nucleation layer 21 on the substrate 10;

[0064] The nucleation layer 21 can be formed of high-temperature AlN or low-temperature GaN, and is mainly used to convert the initial three-dimensional growth mode of the buffer layer 22 into a two-dimensional growth mode.

[0065] S220, epitaxially growing a first buffer layer 221 on a side of the nucleation layer 21 away from the substrate 10;

[0066] Specifically, the carbon impurity concentration in the first buffer layer 221 can be controlled to be within a lower range by an epitaxial growth process, thereby helping to improve the subsequent crystal growth quality of the buffer layer.

[0067] S230, epitaxially growing a second buffer layer 222 on a side of the first buffer layer 221 away from the nucleation layer 21, while jointly doping the second buffer layer 222 with iron impurities and carbon impurities; the carbon impurity concentration of the second buffer layer 222 satisfies a second preset range, and the carbon impurity concentration of the second buffer layer 222 is less than the iron impurity concentration of the second buffer layer 222;

[0068] Specifically, the combined use of iron impurities and carbon impurities helps to achieve the high resistance required by the buffer layer 22.

[0069] S240, epitaxially growing a third buffer layer 223 on a side of the second buffer layer 222 away from the first buffer layer 221.

[0070] Specifically, the carbon impurity concentration in the third buffer layer 223 can be controlled to be within a lower range by an epitaxial growth process, thereby helping to improve the crystal quality of the buffer layer 22.

[0071] Further, step S230 further comprises: while forming the second buffer layer 222 by an epitaxial process, controlling the carbon impurity concentration of the second buffer layer 222 to be greater than or equal to the carbon impurity concentration of the first buffer layer 221. Step S240 further comprises: while forming the third buffer layer 223 by an epitaxial process, controlling the carbon impurity concentration of the third buffer layer 223 to be less than the carbon impurity concentration of the first buffer layer 221. By making the carbon impurity concentrations of the first buffer layer 221, the second buffer layer 222, and the third buffer layer 223 satisfy the above relationship, it helps to effectively improve the crystal quality of the buffer layer 22 while achieving the high resistance of the buffer layer 22, thereby ensuring the performance reliability of the device.

[0072] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered within the scope of the present disclosure.

[0073] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the present application patent shall be subject to the appended claims.

Claims

1. An epitaxial structure for a semiconductor device, characterized in that, include: Substrate; A first semiconductor layer is located on the substrate. The first semiconductor layer includes a buffer layer. The buffer layer includes at least a first buffer layer, a second buffer layer and a third buffer layer stacked together. The second buffer layer is located between the first buffer layer and the third buffer layer. The buffer layer is doped with iron impurities, which are concentrated in the second buffer layer. The first buffer layer contains carbon impurities, and the second buffer layer is also doped with carbon impurities. The carbon impurity concentration in the first buffer layer is less than that in the second buffer layer. The third buffer layer contains carbon impurities, which are less than that in the first buffer layer. The carbon impurity concentration in the second buffer layer is less than that in the iron impurity concentration in the second buffer layer.

2. The epitaxial structure according to claim 1, characterized in that, The iron impurity concentration of the second buffer layer meets a first preset range, the first preset range including The carbon impurity concentration of the second buffer layer meets a second preset range, which includes... .

3. The epitaxial structure according to claim 1, characterized in that, The thickness of the second buffer layer is , where 200nm≤ ≤800nm.

4. The epitaxial structure according to claim 1, characterized in that, The first buffer layer is located on the side of the second buffer layer closer to the substrate, the third buffer layer is located on the side of the second buffer layer closer to the second semiconductor layer, and the second semiconductor layer is located on the side of the first semiconductor layer away from the substrate.

5. The epitaxial structure according to claim 4, characterized in that, The carbon impurity concentration of the first buffer layer is less than or equal to The carbon impurity concentration of the second buffer layer is greater than or equal to and less than or equal to The carbon impurity concentration of the third buffer layer is less than or equal to .

6. The epitaxial structure according to claim 4, characterized in that, The thickness of the third buffer layer is , where 200nm≤ ≤500nm; the thickness of the first buffer layer is , where 200nm≤ ≤800nm.

7. A semiconductor device, characterized in that, Includes the epitaxial structure as described in any one of claims 1-6.

8. A method for fabricating an epitaxial structure of a semiconductor device, characterized in that, include: Provide substrate; A first semiconductor layer is fabricated on the substrate; the first semiconductor layer includes a buffer layer, the buffer layer comprising at least a first buffer layer, a second buffer layer, and a third buffer layer stacked thereon, a second buffer layer located between the first buffer layer and the third buffer layer, the buffer layer being doped with iron impurities, and the iron impurities being concentrated in the second buffer layer, the iron impurity concentration of the second buffer layer satisfying a first preset range, the first buffer layer having carbon impurities, the second buffer layer being doped with carbon impurities, the carbon impurity concentration of the first buffer layer being less than the carbon impurity concentration of the second buffer layer; and the third buffer layer having carbon impurities, the carbon impurity concentration of the third buffer layer being less than the carbon impurity concentration of the first buffer layer, and the carbon impurity concentration of the second buffer layer being less than the iron impurity concentration of the second buffer layer; and... A second semiconductor layer is formed on the side of the first semiconductor layer away from the substrate, and a conductive channel is formed in the second semiconductor layer.

9. The preparation method according to claim 8, characterized in that, The step of fabricating the first semiconductor layer on the substrate includes: A nucleation layer is epitaxially grown on the substrate; The first buffer layer is epitaxially grown on the side of the nucleation layer away from the substrate; A second buffer layer is epitaxially grown on the side of the first buffer layer away from the nucleation layer, while iron impurities and carbon impurities are co-incorporated into the second buffer layer; and... The third buffer layer is grown epitaxially on the side of the second buffer layer away from the first buffer layer.

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