Decoding device, driving equipment and parameter determination method of sine and cosine encoder

Abstract

This invention discloses a decoding device, driving device, and parameter determination method for a sine / cosine encoder. The device includes: a sine / cosine encoder for detecting the rotor position information of a motor and outputting sine / cosine differential signals; a differential operational amplifier unit for differentially processing the sine / cosine differential signals to obtain sine / cosine analog signals; the sine / cosine analog signals are divided into two paths; an interleaved triggering unit for interleaved triggering of the sine and cosine signals in the first path of the sine / cosine analog signals to obtain sine / cosine square wave signals; an ADC unit for analog-to-digital conversion of the second path of the sine / cosine analog signals to obtain sine / cosine digital signals; and a control unit for determining the rotor position information of the motor based on the sine / cosine square wave signals and the sine / cosine digital signals. This scheme improves the accuracy of the angular position information of the motor obtained by the servo driver by utilizing the interleaved triggering unit to eliminate the influence of interference on pulse counting, thereby improving the control precision of the servo driver.

Description

Technical Field

[0001] This invention belongs to the field of motor control technology, specifically relating to a decoding device for a sine and cosine encoder, a driving device and a method for determining its parameters, and particularly to an interference-resistant sine and cosine encoder decoding circuit, a driving device (such as a frequency converter, servo driver, motor controller, etc.) having the sine and cosine encoder decoding circuit, and a method for determining the parameters of the driving device. Background Technology

[0002] In servo systems requiring high precision and dynamic performance, it is essential to measure the position and speed of the rotor in the motor in real time and with high accuracy. Sine and cosine encoders, with their advantages of high resolution and high precision, are widely used in precision measurement and real-time control technologies.

[0003] In the relevant solutions, the acquisition of motor angular position information (such as motor angular position and angular velocity) using sine and cosine encoders mainly employs a combination of quadruple frequency counting and fine interpolation subdivision. Specifically, the signal from the sine and cosine encoder is filtered and amplified, then split into two signals: one signal is used to generate a TTL (transistor-to-transistor logic level) pulse signal for frequency multiplication counting to obtain the encoder coarse code information; the other signal is transmitted to the AD conversion unit (i.e., analog-to-digital conversion unit), and after obtaining the digital signal, a subdivision algorithm is used to obtain the sine and cosine encoder fine code signal, which serves as the fine interpolation information; finally, the coarse code information and fine interpolation information obtained from the two signals are integrated to obtain accurate motor angular position, angular velocity, and other information.

[0004] However, in servo drive devices, especially high-power servo drives, the switching power supply and power module in the servo driver operate in a high-frequency switching state, generating strong conducted interference and radiation. Furthermore, the alternating current in the power transmission lines and the motor also generates strong radiated interference in space. These interferences will affect the signal quality of the sine and cosine encoders, leading to pulse counting errors. When pulse counting is incorrect, the servo driver will obtain significant deviations in the motor's angular position information (such as angular position and angular velocity), resulting in poor control accuracy.

[0005] The above content is only used to help understand the technical solution of the present invention and does not represent an admission that the above content is prior art. Summary of the Invention

[0006] The purpose of this invention is to provide a decoding device, driving device, and parameter determination method for a sine and cosine encoder. This addresses the problem that interference generated by the switching power supply, power module, power transmission line, and alternating current of the motor in the servo driver of a servo drive device can lead to pulse counting errors in the sine and cosine encoder, resulting in significant deviations in the angular position information of the motor acquired by the servo driver and affecting the control accuracy of the servo driver. The invention aims to improve the anti-interference performance of the sine and cosine encoder decoding circuit to eliminate the influence of interference on pulse counting, thereby improving the accuracy of the angular position information of the motor acquired by the servo driver and enhancing the control accuracy of the servo driver.

[0007] This invention provides a decoding device for a sine / cosine encoder, comprising: a differential operational amplifier unit, an interleaved triggering unit, an ADC unit, and a control unit; wherein, the sine / cosine encoder is configured to detect the rotor position information of a motor and output sine / cosine differential signals; the sine / cosine differential signals include: a sine differential signal and a cosine differential signal; the differential operational amplifier unit is configured to perform differential operational amplifier processing on the sine / cosine differential signals output by the sine / cosine encoder to obtain sine / cosine analog signals; the sine / cosine analog signals are divided into two paths, namely a first sine / cosine analog signal and a second sine / cosine analog signal; the interleaved triggering unit is configured to interleave the sine and cosine signals in the first sine / cosine analog signal to obtain sine / cosine square wave signals; the ADC unit is configured to perform analog-to-digital conversion processing on the second sine / cosine analog signal to obtain sine / cosine digital signals; and the control unit is configured to determine the rotor position information of the motor based on the sine / cosine square wave signals and the sine / cosine digital signals.

[0008] In some embodiments, the interleaved triggering unit includes: a first signal generation module and a second signal generation module, a first signal transformation module, a second signal transformation module, a first signal triggering module, and a second signal triggering module; wherein, the interleaved triggering unit interleaved the sine and cosine signals in the first channel of sine and cosine analog signals to obtain sine and cosine square wave signals, including: the first signal generation module being configured to generate a first square wave signal based on the sine signal in the first channel of sine and cosine analog signals; the first signal transformation module being configured to perform signal transformation based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at the transition edge, denoted as the first pulse signal; the second signal generation module being configured to perform signal transformation based on the first channel of sine and cosine analog signals to obtain a pulse signal generated by the first square wave signal at the transition edge, denoted as the first pulse signal; and the second signal generation module being configured to perform signal transformation based on the first channel of sine and cosine analog signals at the transition edge. The cosine signal is used to generate a second square wave signal; the second signal conversion module is configured to perform signal conversion based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal; the first signal triggering module is configured to perform D triggering at the rising edge of the second pulse signal, output the first square wave signal, and obtain a first TTL signal, denoted as the first trigger square wave signal; the first trigger square wave signal serves as the sine square wave signal in the sine-cosine square wave signal; the second signal triggering module is configured to perform D triggering at the rising edge of the first pulse signal, output the second square wave signal, and obtain a second TTL signal, denoted as the second trigger square wave signal; the second trigger square wave signal serves as the cosine square wave signal in the sine-cosine square wave signal.

[0009] In some embodiments, the first signal generation module includes: a first comparator; the first signal generation module generates a first square wave signal based on the sine signal in the first channel of sine-cosine analog signals, including: the first comparator being configured to compare the sine signal in the first channel of sine-cosine analog signals with a preset first reference signal to obtain a first comparison result, and recording the first comparison result as the first square wave signal; the second signal generation module includes: a second comparator; the second signal generation module generates a second square wave signal based on the cosine signal in the first channel of sine-cosine analog signals, including: the second comparator being configured to compare the cosine signal in the first channel of sine-cosine analog signals with a preset second reference signal to obtain a second comparison result, and recording the second comparison result as the second square wave signal.

[0010] In some embodiments, the first signal conversion module includes: a first RC module, a first XOR module, and a first inverting module; the first signal conversion module performs signal conversion based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at a transition edge, denoted as a first pulse signal, and includes: the first RC module is configured to generate a pulse signal with a set width based on the first square wave signal; the first XOR module is configured to perform XOR processing on the first square wave signal and the pulse signal generated by the first RC module to obtain a first XOR processing result; the first inverting module is configured to invert the first XOR processing result to obtain a pulse signal generated by the first square wave signal at a transition edge, denoted as the first pulse signal. A pulse signal; the second signal conversion module includes: a second RC module, a second XOR module, and a second inverting module; the second signal conversion module performs signal conversion based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal, and includes: the second RC module, configured to generate a pulse signal with a set width based on the second square wave signal; the second XOR module, configured to perform XOR processing based on the second square wave signal and the pulse signal generated by the second RC module to obtain a second XOR processing result; the second inverting module, configured to invert the second XOR processing result to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal.

[0011] In some embodiments, the first signal conversion module further includes: a third inverting module; the first signal conversion module performs signal conversion based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at a transition edge, denoted as a first pulse signal, and further includes: the third inverting module is configured to invert the first square wave signal to obtain a first inverted square wave signal; the first RC module is further configured to generate a pulse signal with a set width based on the first inverted square wave signal; the first XOR module is further configured to perform XOR processing based on the first inverted square wave signal and the pulse signal generated by the first RC module to obtain a first XOR processing result; the first inverting module is further configured to invert the first XOR processing result to obtain a pulse signal generated by the first square wave signal at a transition edge, denoted as the first pulse signal. The second signal conversion module further includes: a fourth inverting module; the second signal conversion module performs signal conversion based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal, and further includes: the fourth inverting module, configured to invert the second square wave signal to obtain a second inverted square wave signal; the second RC module, further configured to generate a pulse signal with a set width based on the second inverted square wave signal; the second XOR module, further configured to perform XOR processing based on the second inverted square wave signal and the pulse signal generated by the second RC module to obtain a second XOR processing result; the second inverting module, further configured to invert the second XOR processing result to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal.

[0012] In some embodiments, the first signal triggering module includes a first D flip-flop; the second signal triggering module includes a second D flip-flop.

[0013] In some embodiments, the control unit includes: a QEP module, a subdivision algorithm module, and a parameter determination module; the control unit determines the rotor position information of the motor based on the sine and cosine square wave signals and the sine and cosine digital signals, including: the QEP module is configured to count the edges of the sine and cosine square wave signals to obtain coarse code information of the sine and cosine encoder; the subdivision algorithm module is configured to perform subdivision calculations on the sine and cosine digital signals to obtain fine code information of the sine and cosine encoder; the parameter determination module is configured to combine the coarse code information of the sine and cosine encoder and the fine code information of the sine and cosine encoder, and calculate using the subdivision algorithm to obtain the rotor position information of the motor; the rotor position information of the motor includes at least one of the angular velocity of the motor and the angular position of the motor.

[0014] In some embodiments, the QEP module counts the edges of the sine and cosine square wave signals to obtain coarse code information of the sine and cosine encoder, including: when the first signal generation module in the interleaved trigger unit is composed of a first RC module, a first XOR module, and a first inverting module, and the second signal generation module in the interleaved trigger unit is composed of a second RC module, a second XOR module, and a second inverting module, counting the edges of the sine and cosine square wave signals and compensating for a set number of pulses to obtain coarse code information of the sine and cosine encoder; the parameter determination module combines the coarse code information of the sine and cosine encoder with the fine code information of the sine and cosine encoder, and calculates the rotor position information of the motor through a subdivision algorithm, including: combining the coarse code information of the sine and cosine encoder with the fine code information of the sine and cosine encoder, correcting the subdivision algorithm, and calculating the rotor position information of the motor through the corrected subdivision algorithm.

[0015] In conjunction with the above-described device, the present invention further provides a driving device, comprising: a decoding device for the sine and cosine encoder described above.

[0016] In conjunction with the aforementioned motor, this invention further provides a method for determining the parameters of a drive device, comprising: detecting the rotor position information of the motor using a sine / cosine encoder and outputting a sine / cosine differential signal; the sine / cosine differential signal comprising a sine differential signal and a cosine differential signal; performing differential operational amplifier processing on the sine / cosine differential signal output by the sine / cosine encoder using a differential operational amplifier unit to obtain a sine / cosine analog signal; the sine / cosine analog signal being divided into two paths, namely a first sine / cosine analog signal and a second sine / cosine analog signal; interleaving the sine and cosine signals in the first sine / cosine analog signal using an interleaved triggering unit to obtain a sine / cosine square wave signal; performing analog-to-digital conversion processing on the second sine / cosine analog signal using an ADC unit to obtain a sine / cosine digital signal; and determining the rotor position information of the motor based on the sine / cosine square wave signal and the sine / cosine digital signal using a control unit.

[0017] In some implementations, the rotor position information of the motor is determined by the control unit based on the sine and cosine square wave signals and the sine and cosine digital signals. This includes: counting the edges of the sine and cosine square wave signals using a QEP module to obtain coarse code information of the sine and cosine encoder; performing subdivision calculations on the sine and cosine digital signals using a subdivision algorithm module to obtain fine code information of the sine and cosine encoder; and combining the coarse code information and the fine code information of the sine and cosine encoder using a parameter determination module, and performing calculations using a subdivision algorithm to obtain the rotor position information of the motor. The rotor position information of the motor includes at least one of the motor's angular velocity and the motor's angular position.

[0018] In some implementations, the coarse code information of the sine and cosine square wave signal is obtained by counting the edges of the sine and cosine square wave signal through the QEP module. This includes: when the first signal generation module in the interleaved trigger unit is composed of a first RC module, a first XOR module, and a first inverting module, and the second signal generation module in the interleaved trigger unit is composed of a second RC module, a second XOR module, and a second inverting module, the edges of the sine and cosine square wave signal are counted, and a set number of pulses is compensated to obtain the coarse code information of the sine and cosine encoder; the coarse code information of the sine and cosine encoder and the fine code information of the sine and cosine encoder are combined through the parameter determination module, and the rotor position information of the motor is calculated by a subdivision algorithm. This includes: combining the coarse code information of the sine and cosine encoder and the fine code information of the sine and cosine encoder, correcting the subdivision algorithm, and calculating the rotor position information of the motor by the corrected subdivision algorithm.

[0019] Therefore, the solution of the present invention, by adding an interleaved trigger circuit to the sine and cosine encoder decoding circuit, after differentially amplifying the differential signal output by the sine and cosine encoder using a differential operational amplifier circuit, uses the interleaved trigger circuit to generate a square wave signal by interleaving the differentially amplified signal with sine and cosine signals. This ensures that the square wave signal is output at the most stable moment, thereby eliminating the influence of interference on the square wave signal. Thus, by improving the anti-interference performance of the sine and cosine encoder decoding circuit, the influence of interference on pulse counting is eliminated, thereby improving the accuracy of the angular position information of the motor obtained by the servo driver and improving the control precision of the servo driver.

[0020] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention.

[0021] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of an embodiment of the sine / cosine encoder decoding circuit in a related scheme;

[0023] Figure 2 This is a schematic diagram of the structure of a decoding device for a sine / cosine encoder according to an embodiment of the present invention;

[0024] Figure 3 This is a schematic diagram of the structure of an embodiment of the sine and cosine encoder decoding circuit of the present invention;

[0025] Figure 4 This is a schematic diagram of an embodiment of the interleaved trigger circuit in the sine and cosine encoder decoding circuit of the present invention;

[0026] Figure 5 This is a schematic diagram of a specific waveform of an embodiment of the sine and cosine encoder decoding circuit of the present invention;

[0027] Figure 6 This is a flowchart illustrating an embodiment of the parameter determination method of the present invention;

[0028] Figure 7 This is a flowchart illustrating an embodiment of the parameter determination method of the present invention for determining the rotor position information of a motor. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0030] Figure 1 This is a schematic diagram of one embodiment of the sine / cosine encoder decoding circuit in a related scheme. For example... Figure 1As shown, the sine / cosine encoder decoding circuit includes: a differential operational amplifier circuit, a hysteresis comparator, an ADC chip (analog-to-digital converter chip), and an MCU. The MCU includes: a QEP circuit (quadrature encoder pulse circuit), a motor angular velocity or angular position determination module, and a microstepping algorithm module. The output of the sine / cosine encoder is connected to the input of the differential operational amplifier circuit. The first output of the differential operational amplifier circuit is connected to the input of the hysteresis comparator, and the second output of the differential operational amplifier circuit is connected to the input of the ADC chip. The output of the hysteresis comparator is input to the first input of the MCU. The output of the ADC chip is input to the second input of the MCU. In the MCU, the QEP circuit processes the output signal of the hysteresis comparator and outputs it to the first input of the motor angular velocity or angular position determination module. In the MCU, the microstepping algorithm module processes the output signal of the ADC chip and outputs it to the second input of the motor angular velocity or angular position determination module. The output of the motor angular velocity or angular position determination module can output the motor angular velocity or angular position.

[0031] like Figure 1 The sine / cosine encoder decoding circuit shown first processes the differential signals output by the sine / cosine encoder (sin+, sin-, cos+, and cos-) through a differential operational amplifier circuit for differential filtering and amplification, resulting in sin1 and cos1 signals. These sin1 and cos1 signals are then split into two paths. One path, sin1 and cos1, is directly connected to the ADC chip and converted to digital signals (ADC_sin and ADC_cos) after analog-to-digital conversion. The ADC_sin and ADC_cos signals are then processed by a subdivision algorithm module to obtain the encoder's fine code signal. The other path, sin1 and cos1, is converted to TTL pulse signals (sin_TTL and cos_TTL) by a hysteresis comparator. The edges of the sin_TTL and cos_TTL signals are then counted using the MCU's QEP circuit to obtain the encoder's coarse code information. Finally, by adding the encoder coarse code information and the encoder fine interpolation information (i.e., the encoder fine code signal), accurate information such as motor angular velocity and angular position is obtained. This involves subdivision algorithms, such as the arctangent method, closed-loop tracking method, and table lookup method.

[0032] but, Figure 1The sine and cosine encoder decoding circuit shown uses a hysteresis comparator to generate a square wave. The hysteresis comparator has a hysteresis voltage, but this voltage cannot be set too high, otherwise it will cause significant delays between the sin1 and cos1 signals, and between the sin_TTL and cos_TTL signals. Therefore, the hysteresis voltage setting of the hysteresis comparator is generally small, meaning that using a hysteresis comparator to generate a square wave can only eliminate the influence of small fluctuations near the comparison point. It is evident that... Figure 1 The sine and cosine encoder decoding circuit shown has poor anti-interference capability, which results in low control accuracy of the servo driver.

[0033] In other solutions, the count value of the quadrature square wave signal is corrected based on the analog quadrant of the original sine and cosine signals. This not only involves a large amount of software computation, but also fails to guarantee the accuracy of the square wave when there is interference in the analog signal obtained by the AD conversion chip.

[0034] According to an embodiment of the present invention, a decoding device for a sine / cosine encoder is provided. See also Figure 2 The diagram shows a schematic representation of an embodiment of the device of the present invention. The decoding device of the sine / cosine encoder may include: a differential operational amplifier unit, an interleaved trigger unit, an ADC unit, and a control unit. The differential operational amplifier unit may be a differential operational amplifier circuit, the interleaved trigger unit may be an interleaved trigger circuit, the ADC unit may be an ADC chip, and the control unit may be an MCU. The differential operational amplifier circuit may be a differential operational amplifier.

[0035] The sine and cosine encoder is configured to detect the rotor position information of the motor and output sine and cosine differential signals. These sine and cosine differential signals include a sine differential signal and a cosine differential signal. Specifically, the sine and cosine differential signals output by the encoder are sin+, sin-, cos+, and cos- signals.

[0036] The differential operational amplifier unit is configured to perform differential operational amplifier processing on the sine and cosine differential signals output by the sine and cosine encoder to obtain sine and cosine analog signals. The sine and cosine analog signals are divided into two paths, namely a first sine and cosine analog signal and a second sine and cosine analog signal. Specifically, the sine and cosine analog signals are sin1 and cos1 signals.

[0037] The interleaved triggering unit is configured to interleave the sine and cosine signals in the first channel of sine and cosine analog signals to obtain sine and cosine square wave signals. Specifically, the sine and cosine square wave signals are TTL pulse signals, namely sin_TTL and cos_TTL signals.

[0038] The ADC unit is configured to perform analog-to-digital conversion on the second sine and cosine analog signals to obtain sine and cosine digital signals. Specifically, the sine and cosine digital signals are the ADC_sin signal and the ADC_cos signal.

[0039] The control unit is configured to determine the rotor position information of the motor based on the sine and cosine square wave signals and the sine and cosine digital signals.

[0040] This invention proposes a novel sine / cosine encoder decoding circuit, relating to motor control fields such as servo drives and frequency converters. Specifically, it provides an anti-interference design scheme for a sine / cosine encoder decoding circuit. By adding an interleaved trigger circuit to the circuit, the formation of the square wave signal is achieved through an interleaved triggering method using sine and cosine signals. Specifically, the square wave signal is generated by alternating between sin and cosine signals. Hardware processing ensures the square wave signal is output at its most stable moment, thereby eliminating the impact of signal jitter and spike interference on pulse counting and improving the anti-interference capability of the decoding circuit. Thus, by adding an interleaved trigger circuit to the sine / cosine encoder decoding circuit, the square wave signal is guaranteed to be output at its most stable moment, eliminating the influence of signal jitter and spike interference on the square wave signal, improving the anti-interference capability of the sine / cosine encoder decoding circuit, ensuring the accuracy of the encoder's coarse code counting, and improving the control precision of the servo drive. Here, signal jitter refers to the error in the square wave signal caused by jitter in the input signal.

[0041] Figure 3 This is a schematic diagram of an embodiment of the sine / cosine encoder decoding circuit of the present invention. Figure 3 As shown, in order to enhance the anti-interference capability of the sine and cosine encoder decoding circuit, an interleaved trigger circuit is added to the square wave generation circuit of the sine and cosine encoder decoding circuit.

[0042] Specifically, in Figure 3 In the example shown, the sine / cosine encoder decoding circuit includes: a differential operational amplifier circuit, an interleaved trigger circuit, an ADC chip (i.e., an analog-to-digital converter chip), and an MCU. The output of the sine / cosine encoder is connected to the input of the differential operational amplifier circuit. The first output of the differential operational amplifier circuit is connected to the input of the interleaved trigger circuit, and the second output of the differential operational amplifier circuit is connected to the input of the ADC chip. The output of the interleaved trigger circuit is input to the first input of the MCU. The output of the ADC chip is input to the second input of the MCU.

[0043] like Figure 3The sine / cosine encoder decoding circuit shown first processes the differential signals output by the sine / cosine encoder (sin+, sin-, cos+, and cos-) through a differential operational amplifier circuit for differential filtering and amplification, resulting in sin1 and cos1 signals. These sin1 and cos1 signals are then split into two paths. One path, sin1 and cos1, is directly input to the ADC chip and converted to digital signals (ADC_sin and ADC_cos) after analog-to-digital conversion. The other path, sin1 and cos1, is converted to TTL pulse signals (sin_TTL and cos_TTL) through an interleaved trigger circuit. Finally, the MCU uses the ADC_sin and ADC_cos signals, as well as the sin_TTL and cos_TTL signals, to determine accurate motor angular velocity and angular position information.

[0044] In some embodiments, the interleaved triggering unit includes: a first signal generation module and a second signal generation module, a first signal transformation module, a second signal transformation module, a first signal triggering module, and a second signal triggering module.

[0045] The interleaved triggering unit interleaved the sine and cosine signals in the first channel of sine and cosine analog signals to obtain sine and cosine square wave signals, including:

[0046] The first signal generation module is configured to generate a first square wave signal based on the sine signal in the first channel of sine and cosine analog signals. The first signal generation module is, for example, comparator U1, and the first square wave signal is, for example, the square wave signal sin2.

[0047] The first signal conversion module is configured to perform signal conversion based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at the transition edge, denoted as the first pulse signal. The first pulse signal is, for example, a sin3 signal.

[0048] The second signal generation module is configured to generate a second square wave signal based on the cosine signal in the first sine-cosine analog signal. The second signal generation module is, for example, comparator U5, and the second square wave signal is, for example, the square wave signal cos2.

[0049] The second signal conversion module is configured to perform signal conversion based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal. The second pulse signal is, for example, a cos 3 signal.

[0050] The first signal triggering module is configured to perform D-triggering on the rising edge of the second pulse signal, outputting the first square wave signal to obtain a first TTL signal, denoted as the first trigger square wave signal. The first trigger square wave signal serves as the sine square wave signal in the sine and cosine square wave signals.

[0051] The second signal triggering module is configured to perform D-triggering on the rising edge of the first pulse signal, outputting the second square wave signal to obtain a second TTL signal, denoted as the second trigger square wave signal. The second trigger square wave signal serves as the cosine square wave signal in the sine-cosine square wave signal. In other words, the first trigger square wave signal and the second trigger square wave signal together form the sine-cosine square wave signal obtained by the interleaved triggering unit.

[0052] In related solutions, the main software measure to eliminate the influence of interference on square wave signals is generally to increase signal filtering. This method has some drawbacks, such as increasing signal delay. Since the peak interference frequency is within the input signal frequency range, filtering can eliminate the interference. The solution of this invention, by adding an interleaved triggering method based on D flip-flops to the sine and cosine encoder decoding circuit, suppresses the influence of signal jitter and peak interference on pulse counting, thereby improving the accuracy of the encoder's position information and enhancing the control precision of the servo driver. Thus, the solution of this invention mainly eliminates interference through pure hardware circuitry, reducing the computational load of software and solving the problem of pulse counting errors caused by interference in sine and cosine encoder signals.

[0053] In some implementations, the first signal generation module includes: a first comparator, such as comparator U1.

[0054] The first signal generation module generates a first square wave signal based on the sinusoidal signal in the first channel of sine and cosine analog signals, including:

[0055] The first comparator is configured to compare a sinusoidal signal in the first channel of sine and cosine analog signals with a preset first reference signal to obtain a first comparison result, and the first comparison result is recorded as a first square wave signal.

[0056] The second signal generation module includes: a second comparator, such as comparator U5.

[0057] The second signal generation module generates a second square wave signal based on the cosine signal in the first sine-cosine analog signal, including:

[0058] The second comparator is configured to compare the cosine signal in the first sine-cosine analog signal with a preset second reference signal to obtain a second comparison result, and the second comparison result is recorded as a second square wave signal.

[0059] Figure 4 This is a schematic diagram of an embodiment of the interleaved trigger circuit in the sine / cosine encoder decoding circuit of the present invention. Figure 4 As shown, the interleaved trigger circuit includes: comparator U1 and comparator U5. In Figure 4 In the example shown, the function of comparators U1 and U5 is to compare the input signal with a reference voltage. When the voltage value of the input signal is higher than the reference voltage, a high level is output; when the voltage value of the input signal is lower than the reference voltage, a low level is output. The sin1 and cos1 signals are input to comparators U1 and U5 to generate square wave signals sin2 and cos2, respectively.

[0060] In some implementations, the first signal conversion module includes: a first RC module, a first XOR module, and a first inverting module. The first RC module specifically includes a resistor R1 and a capacitor C1, the first XOR module is such as an XOR gate U2, and the first inverting module is such as an inverter U3.

[0061] The first signal conversion module performs signal conversion based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at the transition edge, denoted as the first pulse signal, including:

[0062] The first RC module is configured to generate a pulse signal with a set width based on the first square wave signal.

[0063] The first XOR module is configured to perform XOR processing based on the first square wave signal and the pulse signal generated by the first RC module to obtain the first XOR processing result.

[0064] The first inverting module is configured to invert the first XOR processing result to obtain the pulse signal generated by the first square wave signal at the transition edge, which is denoted as the first pulse signal.

[0065] The second signal conversion module includes: a second RC module, a second XOR module, and a second inverting module. The second RC module specifically includes a resistor R2 and a capacitor C2; the second XOR module is such as an XOR gate U6; and the second inverting module is such as an inverter U7.

[0066] The second signal conversion module performs signal conversion based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal, including:

[0067] The second RC module is configured to generate a pulse signal with a set width based on the second square wave signal.

[0068] The second XOR module is configured to perform XOR processing based on the second square wave signal and the pulse signal generated by the second RC module to obtain the second XOR processing result.

[0069] The second inverting module is configured to invert the second XOR processing result to obtain the pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal.

[0070] like Figure 4 As shown, the interleaved trigger circuit also includes: XOR gates U2 and U6, inverters U3 and U7, resistors R1 and R2, and capacitors C1 and C2. At the non-tipping edges of the square wave signals sin2 and cos2, XOR gates U2 and U6 remain at a low level, and the output after passing through inverters U3 and U7 is a high level. When the square wave signal sin2 undergoes a transition, the input level of XOR gate U2 does not change abruptly due to the presence of capacitor C1, so XOR gate U2 outputs a high level, which is then converted to a low level by inverter U3. The same applies to the square wave signal cos2.

[0071] exist Figure 4 In the example shown, the function of resistor R1 and capacitor C1, and resistor R2 and capacitor C2, is to generate a narrow pulse signal by charging and discharging the capacitors. Generating a narrow pulse signal by charging and discharging the capacitors ensures that the edges of both the sin_TTL and cos_TTL square wave bars occur in the most stable regions of the sin1 and cos1 signals, i.e., at the peaks or troughs of the sin1 and cos1 signals. Therefore, this method can improve the circuit's anti-interference capability, eliminate the influence of signal jitter and spike interference on pulse counting, thereby improving the accuracy of the encoder's position information and enhancing the control precision of the servo driver.

[0072] In the RC circuits formed by resistor R1 and capacitor C1, and resistor R2 and capacitor C2, the design must ensure that the time constant is much smaller than the period of the sinusoidal signal at the highest operating frequency. For example, the time constant of the RC circuit should be less than 1 / 15 of the period of the sinusoidal signal at the highest operating frequency. Specifically, in the RC circuit formed by resistor R1 and capacitor C1, due to the short discharge time of capacitor C1, the XOR gate U2 and inverter U3 are equivalent to generating a falling-edge pulse signal. In the RC circuit formed by resistor R2 and capacitor C2, due to the short discharge time of capacitor C2, the XOR gate U6 and inverter U7 are equivalent to generating a falling-edge pulse signal. The square wave signals sin2 and cos2 output corresponding phase square wave signals when the pulse is formed.

[0073] In some embodiments, the first signal conversion module further includes a third inverting module. The third inverting module is, for example, another inverter U3. The third inverting module is located at the output of the first signal generation module, specifically between the first signal generation module and the first XOR module. By adding another inverter (such as another inverter U3) between the comparator U1 and the XOR gate U2, pulse compensation can be avoided in the program.

[0074] The first signal conversion module performs signal conversion based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at the transition edge, denoted as the first pulse signal, and further includes:

[0075] The third inverting module is configured to invert the first square wave signal to obtain a first inverted square wave signal.

[0076] The first RC module is also configured to generate a pulse signal with a set width based on the first inverted square wave signal.

[0077] The first XOR module is further configured to perform XOR processing based on the first inverted square wave signal and the pulse signal generated by the first RC module to obtain a first XOR processing result.

[0078] The first inverting module is further configured to invert the first XOR processing result to obtain a pulse signal generated by the first square wave signal at the transition edge, denoted as the first pulse signal.

[0079] The second signal conversion module further includes a fourth inverting module. The fourth inverting module is another inverter U7. The fourth inverting module is located at the output of the second signal generation module, specifically between the second signal generation module and the second XOR module.

[0080] The second signal conversion module performs signal conversion based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal, and further includes:

[0081] The fourth inverting module is configured to invert the second square wave signal to obtain a second inverted square wave signal.

[0082] The second RC module is also configured to generate a pulse signal with a set width based on the second inverted square wave signal.

[0083] The second XOR module is further configured to perform XOR processing based on the second inverted square wave signal and the pulse signal generated by the second RC module to obtain a second XOR processing result.

[0084] The second inverting module is further configured to invert the second XOR processing result to obtain the pulse signal generated by the second square wave signal at the transition edge, denoted as the second pulse signal.

[0085] In some alternative implementations, see Figure 4 The example shown can also be used to add another inverter between the comparator (such as comparator U1, comparator U5) and the XOR gate (such as XOR gate U2, XOR gate U4), such as adding another inverter between comparator U1 and XOR gate U2, and adding another inverter U4 between comparator U5 and XOR gate U4.

[0086] In some embodiments, the first signal triggering module includes a first D flip-flop, such as D flip-flop U4. The second signal triggering module includes a second D flip-flop, such as D flip-flop U8.

[0087] like Figure 4 As shown, the interleaved trigger circuit also includes: D flip-flop U4 and D flip-flop U8.

[0088] See Figure 3 and Figure 4 In the example shown, the differential signals output by the sine and cosine encoders—sin+, sin-, cos+, and cos-—are differentially filtered and amplified by a differential operational amplifier circuit to obtain sin1 and cos1 signals. These sin1 and cos1 signals are then split into two paths. One path, consisting of sin1 and cos1 signals, is directly connected to the ADC chip and converted from analog to digital to obtain the digital signals ADC_sin and ADC_cos. ADC_sin and ADC_cos are then processed by a subdivision algorithm module to obtain the encoder's fine code signal. The other path, consisting of sin1 and cos1 signals, is processed by an interleaved trigger circuit and a QEP module to obtain the encoder's coarse code signal. The terms "fine code signal" and "coarse code signal" are relative to each other in terms of signal precision.

[0089] Specifically, the other two signals, sin1 and cos1, are input to comparators U1 and U5 to generate square wave signals sin2 and cos2. At the non-tipping edges of sin2 and cos2, XOR gates U2 and U6 remain low, and after passing through inverters U3 and U7, their outputs are high. D flip-flops U4 and U8 retain their previous outputs. When sin2 transitions, the input level of XOR gate U2 does not change abruptly due to the presence of capacitor C1, so XOR gate U2 outputs a high level. After passing through inverter U3, it becomes low, and the transition-triggered D flip-flop U8 outputs the current level state of port D. The situation is the same for cos2.

[0090] In some embodiments, the control unit includes: a QEP module, a subdivision algorithm module, and a parameter determination module, wherein the parameter determination module is, for example, a motor angular velocity or angular position determination module.

[0091] The control unit determines the rotor position information of the motor based on the sine and cosine square wave signals and the sine and cosine digital signals, including:

[0092] The QEP module is configured to count the edges of the sine and cosine square wave signals to obtain the coarse code information of the sine and cosine encoder, i.e., the encoder coarse code information.

[0093] The subdivision algorithm module is configured to perform subdivision calculations on the sine and cosine digital signals to obtain the fine code information of the sine and cosine encoder, i.e., the encoder fine code signal.

[0094] The parameter determination module is configured to combine the coarse code information and the fine code information of the sine and cosine encoders, and calculate the rotor position information of the motor using a subdivision algorithm. The rotor position information of the motor includes at least one of the motor's angular velocity and angular position.

[0095] See Figure 3 The example shown, an MCU, includes: a QEP (Quadrature Encoded Pulse) circuit, a motor angular velocity or angular position determination module, and a microstepping algorithm module. In the MCU, the QEP circuit processes the output signal from the interleaved trigger circuit and outputs it to the first input of the motor angular velocity or angular position determination module. In the MCU, the microstepping algorithm module processes the output signal from the ADC chip and outputs it to the second input of the motor angular velocity or angular position determination module. The output of the motor angular velocity or angular position determination module can output the motor angular velocity or angular position.

[0096] like Figure 3 The sine and cosine encoder decoding circuit shown uses a subdivision algorithm on ADC_sin and ADC_cos to obtain the encoder precision signal. The edges of the sin_TTL and cos_TTL signals are counted using the MCU's QEP circuit to obtain the encoder coarse signal information. Finally, the encoder coarse signal information and the encoder precision interpolation information (i.e., the encoder precision signal) are added together to obtain accurate motor angular velocity, angular position, and other information.

[0097] In some implementations, the QEP module counts the edges of the sine and cosine square wave signals to obtain the coarse code information of the sine and cosine encoder, including: when the first signal generation module in the interleaved trigger unit is composed of a first RC module, a first XOR module, and a first inverting module, and the second signal generation module in the interleaved trigger unit is composed of a second RC module, a second XOR module, and a second inverting module, counting the edges of the sine and cosine square wave signals and compensating for a set number of pulses, such as incrementing the count value by 1 to obtain the coarse code information of the sine and cosine encoder.

[0098] Specifically, see Figure 4 In the example shown, due to the interleaved triggering of D flip-flops U4 and U8, the outputs of the square wave signals sin_TTL and cos_TTL lag behind the sine and cosine signals sin1 and cos1. Therefore, it is necessary to compensate for the pulse count by adding a fixed number of pulses, such as incrementing the count by 1.

[0099] When the first signal generation module in the interleaved trigger unit is composed of a third inverting module, a first RC module, a first XOR module, and a first inverting module, and the second signal generation module in the interleaved trigger unit is composed of a fourth inverting module, a second RC module, a second XOR module, and a second inverting module, there is no need to compensate for the setting pulse. Instead, the edges of the sine and cosine square wave signals are counted directly to obtain the coarse code information of the sine and cosine encoder.

[0100] See Figure 4 In the example shown, when the first signal conversion module also includes a third inverting module and the second signal conversion module also includes a fourth inverting module, the output signal of the inverter (such as inverter U3, inverter U4) is used as the input signal of the D port of the D flip-flop (such as D flip-flop U4, D flip-flop U8). The output of the square wave signal sin_TTL and the square wave signal cos_TTL does not lag relative to the sine and cosine signals sin1 and cos1, so no further software pulse compensation is required.

[0101] In some implementations, the parameter determination module combines the coarse code information of the sine and cosine encoders with the fine code information of the sine and cosine encoders and calculates the rotor position information of the motor using a subdivision algorithm. This includes: combining the coarse code information of the sine and cosine encoders with the fine code information of the sine and cosine encoders, modifying the subdivision algorithm, and calculating the rotor position information of the motor using the modified subdivision algorithm.

[0102] See Figure 4In the example shown, the hysteresis correction method caused by RC is such as adding a fixed angular velocity or angular position, compared with... Figure 1 The correction method for the hysteresis comparator is consistent in the example shown.

[0103] Since RC or hysteresis comparators can cause phase inconsistencies between sin1 and sin_TTL, and between cos1 and cos_TTL, the increment counter will not be updated immediately. This results in a phase inconsistency between the subdivision algorithm and the interval obtained by counting. To eliminate the impact of this interval judgment deviation, corresponding correction processing will be performed in the software algorithm.

[0104] Figure 5 This is a schematic diagram of a specific waveform of an embodiment of the sine / cosine encoder decoding circuit of the present invention. Figure 5 As shown, the differential signals output by the sine and cosine encoders, after differential filtering and amplification by a differential operational amplifier circuit, yield sin1 and cos1 signals that differ by 90 degrees, representing signals conditioned by the differential operational amplifier. The sin2 signal is a square wave output from comparator U1 of the sin1 signal, and the sin3 signal is a pulse signal generated at the rising edge of the sin2 signal. The sin_TTL signal is the sin2 signal triggered by the rising edge of the cos3 signal. Similarly, the cos2 signal is a square wave output from comparator U5 of the cos1 signal, and the cos3 signal is a pulse signal generated at the rising edge of the cos2 signal. The cos_TTL signal is the cos2 signal triggered by the rising edge of the sin3 signal.

[0105] from Figure 5 As shown in the waveform diagram, the edges of the square wave bars of the sin_TTL and cos_TTL signals are generated in the most stable regions of the sin1 and cos1 signals, i.e., at the peaks or troughs of the sin1 and cos1 signals. Therefore, this method can improve the anti-interference capability of the sine and cosine encoder decoding circuit, eliminate the influence of signal jitter and spike interference on pulse counting, thereby improving the accuracy of the encoder's position information and enhancing the control precision of the servo driver. In this way, by eliminating the influence of interference signals through hardware circuitry, the accuracy of the encoder's coarse code counting is ensured, enhancing the reliability of the servo driver and improving its control precision.

[0106] By employing the technical solution of this invention, an interleaved trigger circuit is added to the sine / cosine encoder decoding circuit. After differentially amplifying the differential signal output by the sine / cosine encoder using a differential operational amplifier circuit, the interleaved trigger circuit generates a square wave signal by interleaving one channel of the differentially amplified signal with sine / cosine signals. This ensures that the square wave signal is output at its most stable moment, thus eliminating the influence of interference on the square wave signal. Therefore, by improving the anti-interference performance of the sine / cosine encoder decoding circuit, the influence of interference on pulse counting is eliminated, thereby improving the accuracy of the angular position information of the motor acquired by the servo driver and enhancing the control precision of the servo driver.

[0107] According to an embodiment of the present invention, a driving device corresponding to a decoding device for a sine / cosine encoder is also provided. This driving device may include the decoding device for the sine / cosine encoder described above.

[0108] Since the processing and functions implemented by the motor in this embodiment are basically the same as those in the embodiments, principles and examples of the device, any details not covered in this embodiment can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0109] By employing the technical solution of this invention, an interleaved trigger circuit is added to the decoding circuit of the sine and cosine encoder. After differential amplification of the differential signal output by the sine and cosine encoder using a differential operational amplifier circuit, the interleaved trigger circuit generates a square wave signal by interleaving the differential amplified signal with sine and cosine signals. This ensures that the square wave signal is output at the most stable moment, thereby eliminating the influence of interference on the square wave signal, improving the anti-interference capability of the sine and cosine encoder decoding circuit, ensuring the accuracy of the encoder coarse code counting, and improving the control precision of the servo driver.

[0110] According to an embodiment of the present invention, a method for determining parameters of a drive device corresponding to a motor is also provided, such as... Figure 6 The diagram shows a flowchart of an embodiment of the method of the present invention. The parameter determination method for the drive device may include steps S110 to S150.

[0111] In step S110, the rotor position information of the motor is detected by a sine / cosine encoder, and a sine / cosine differential signal is output. The sine / cosine differential signal includes a sine differential signal and a cosine differential signal. Specifically, the sine / cosine differential signal output by the sine / cosine encoder is a sin+ signal, a sin- signal, a cos+ signal, and a cos- signal.

[0112] In step S120, the sine and cosine differential signals output by the sine and cosine encoder are processed by a differential operational amplifier unit to obtain sine and cosine analog signals. These analog signals are divided into two paths: a first sine and cosine analog signal and a second sine and cosine analog signal. Specifically, the sine and cosine analog signals are sin1 and cos1 signals.

[0113] In step S130, the sine and cosine signals in the first channel of sine and cosine analog signals are interleaved and triggered by the interleaved triggering unit to obtain sine and cosine square wave signals. Specifically, the sine and cosine square wave signals are TTL pulse signals, namely sin_TTL and cos_TTL signals.

[0114] In step S140, the second sine and cosine analog signals are converted from analog to digital using an ADC unit to obtain sine and cosine digital signals. Specifically, the sine and cosine digital signals are the ADC_sin signal and the ADC_cos signal.

[0115] In step S150, the control unit determines the rotor position information of the motor based on the sine and cosine square wave signals and the sine and cosine digital signals.

[0116] This invention proposes a novel sine / cosine encoder decoding circuit, relating to motor control fields such as servo drives and frequency converters. Specifically, it provides an anti-interference design scheme for a sine / cosine encoder decoding circuit. By adding an interleaved trigger circuit to the circuit, the formation of the square wave signal is achieved through an interleaved triggering method using sine and cosine signals. Specifically, the square wave signal is generated by alternating between sin and cosine signals. Hardware processing ensures the square wave signal is output at its most stable moment, thereby eliminating the impact of signal jitter and spike interference on pulse counting and improving the anti-interference capability of the decoding circuit. Thus, by adding an interleaved trigger circuit to the sine / cosine encoder decoding circuit, the square wave signal is guaranteed to be output at its most stable moment, eliminating the influence of signal jitter and spike interference on the square wave signal, improving the anti-interference capability of the sine / cosine encoder decoding circuit, ensuring the accuracy of the encoder's coarse code counting, and improving the control precision of the servo drive. Here, signal jitter refers to the error in the square wave signal caused by jitter in the input signal.

[0117] In some implementations, the specific process of determining the rotor position information of the motor by the control unit based on the sine and cosine square wave signals and the sine and cosine digital signals in step S150 is described in the following exemplary description.

[0118] The following is combined Figure 7The flowchart of an embodiment of the method of the present invention for determining the rotor position information of a motor is shown below. The specific process of determining the rotor position information of the motor in step S150 is further explained, including steps S210 to S230.

[0119] Step S210: The edges of the sine and cosine square wave signals are counted by the QEP module to obtain the coarse code information of the sine and cosine encoder, i.e., the encoder coarse code information.

[0120] Step S220: The sine and cosine digital signals are subdivided and calculated using the subdivision algorithm module to obtain the fine code information of the sine and cosine encoder, i.e., the encoder fine code signal.

[0121] Step S230: The parameter determination module combines the coarse code information and the fine code information of the sine and cosine encoders, and calculates the rotor position information of the motor using a subdivision algorithm. The rotor position information of the motor includes at least one of the motor's angular velocity and angular position.

[0122] See Figure 3 The example shown, an MCU, includes: a QEP (Quadrature Encoded Pulse) circuit, a motor angular velocity or angular position determination module, and a microstepping algorithm module. In the MCU, the QEP circuit processes the output signal from the interleaved trigger circuit and outputs it to the first input of the motor angular velocity or angular position determination module. In the MCU, the microstepping algorithm module processes the output signal from the ADC chip and outputs it to the second input of the motor angular velocity or angular position determination module. The output of the motor angular velocity or angular position determination module can output the motor angular velocity or angular position.

[0123] like Figure 3 The sine and cosine encoder decoding circuit shown uses a subdivision algorithm on ADC_sin and ADC_cos to obtain the encoder precision signal. The edges of the sin_TTL and cos_TTL signals are counted using the MCU's QEP circuit to obtain the encoder coarse signal information. Finally, the encoder coarse signal information and the encoder precision interpolation information (i.e., the encoder precision signal) are added together to obtain accurate motor angular velocity, angular position, and other information.

[0124] In some implementations, step S210 involves counting the edges of the sine and cosine square wave signals using the QEP module to obtain coarse code information of the sine and cosine encoder. This includes: when the first signal generation module in the interleaved trigger unit is composed of a first RC module, a first XOR module, and a first inverting module, and the second signal generation module in the interleaved trigger unit is composed of a second RC module, a second XOR module, and a second inverting module, counting the edges of the sine and cosine square wave signals and compensating for the set number of pulses to obtain coarse code information of the sine and cosine encoder.

[0125] Specifically, see Figure 4 In the example shown, due to the interleaved triggering of D flip-flops U4 and U8, the outputs of the square wave signals sin_TTL and cos_TTL lag behind the sine and cosine signals sin1 and cos1. Therefore, it is necessary to compensate for the pulse count by adding a fixed number of pulses, such as incrementing the count by 1.

[0126] When the first signal generation module in the interleaved trigger unit is composed of a third inverting module, a first RC module, a first XOR module, and a first inverting module, and the second signal generation module in the interleaved trigger unit is composed of a fourth inverting module, a second RC module, a second XOR module, and a second inverting module, there is no need to compensate for the setting pulse. Instead, the edges of the sine and cosine square wave signals are counted directly to obtain the coarse code information of the sine and cosine encoder.

[0127] See Figure 4 In the example shown, when the first signal conversion module also includes a third inverting module and the second signal conversion module also includes a fourth inverting module, the output signal of the inverter (such as inverter U3, inverter U4) is used as the input signal of the D port of the D flip-flop (such as D flip-flop U4, D flip-flop U8). The output of the square wave signal sin_TTL and the square wave signal cos_TTL does not lag relative to the sine and cosine signals sin1 and cos1, so no further software pulse compensation is required.

[0128] In some implementations, step S230 involves a parameter determination module combining the coarse code information of the sine and cosine encoders with the fine code information of the sine and cosine encoders, and calculating the rotor position information of the motor using a subdivision algorithm. This includes combining the coarse code information of the sine and cosine encoders with the fine code information of the sine and cosine encoders, modifying the subdivision algorithm, and calculating the rotor position information of the motor using the modified subdivision algorithm.

[0129] See Figure 4In the example shown, the hysteresis correction method caused by RC is such as adding a fixed angular velocity or angular position, compared with... Figure 1 The correction method for the hysteresis comparator is consistent in the example shown.

[0130] Figure 5 This is a schematic diagram of a specific waveform of an embodiment of the sine / cosine encoder decoding circuit of the present invention. Figure 5 As shown, the differential signals output by the sine and cosine encoders, after differential filtering and amplification by a differential operational amplifier circuit, yield sin1 and cos1 signals that differ by 90 degrees, representing signals conditioned by the differential operational amplifier. The sin2 signal is a square wave output from comparator U1 of the sin1 signal, and the sin3 signal is a pulse signal generated at the rising edge of the sin2 signal. The sin_TTL signal is the sin2 signal triggered by the rising edge of the cos3 signal. Similarly, the cos2 signal is a square wave output from comparator U5 of the cos1 signal, and the cos3 signal is a pulse signal generated at the rising edge of the cos2 signal. The cos_TTL signal is the cos2 signal triggered by the rising edge of the sin3 signal.

[0131] from Figure 5 As shown in the waveform diagram, the edges of the square wave bars of the sin_TTL and cos_TTL signals are generated in the most stable regions of the sin1 and cos1 signals, i.e., at the peaks or troughs of the sin1 and cos1 signals. Therefore, this method can improve the anti-interference capability of the sine and cosine encoder decoding circuit, eliminate the influence of signal jitter and spike interference on pulse counting, thereby improving the accuracy of the encoder's position information and enhancing the control precision of the servo driver. In this way, by eliminating the influence of interference signals through hardware circuitry, the accuracy of the encoder's coarse code counting is ensured, enhancing the reliability of the servo driver and improving its control precision.

[0132] Since the processing and functions implemented by the method in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned motor, any details not covered in the description of this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0133] The technical solution of this embodiment adds an interleaved trigger circuit to the decoding circuit of the sine and cosine encoder. After the differential signal output by the sine and cosine encoder is differentially amplified by the differential operational amplifier circuit, the interleaved trigger circuit generates a square wave signal by interleaving the sine and cosine signals of one of the differentially amplified signals. This ensures that the square wave signal is output at the most stable moment, thereby eliminating the influence of interference on the square wave signal, eliminating the influence of signal jitter and spike interference on pulse counting, and improving the anti-interference capability of the decoding circuit.

[0134] In summary, it is readily understood by those skilled in the art that, without conflict, the aforementioned advantageous methods can be freely combined and superimposed.

[0135] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A decoding device of a sine-cosine encoder, characterized in that, The method comprises the following steps: The differential operational amplifier unit, the staggered trigger unit, the ADC unit and the control unit; wherein The sine-cosine encoder is configured to detect rotor position information of the motor and output a sine-cosine differential signal; the sine-cosine differential signal comprises a sine differential signal and a cosine differential signal; The differential operational amplifier unit is configured to perform differential operational amplifier processing on the sine-cosine differential signal output by the sine-cosine encoder to obtain a sine-cosine analog signal; the sine-cosine analog signal is divided into two paths, i.e. a first path sine-cosine analog signal and a second path sine-cosine analog signal; The staggered trigger unit is configured to perform staggered triggering on the sine signal and the cosine signal in the first path sine-cosine analog signal to obtain a sine-cosine square wave signal; The ADC unit is configured to perform analog-to-digital conversion processing on the second path sine-cosine analog signal to obtain a sine-cosine digital signal; The control unit is configured to determine the rotor position information of the motor according to the sine-cosine square wave signal and the sine-cosine digital signal; the control unit comprises a QEP module, a subdivision algorithm module and a parameter determination module; The control unit determines the rotor position information of the motor according to the sine-cosine square wave signal and the sine-cosine digital signal, which comprises: The QEP module is configured to count the edges of the sine-cosine square wave signal to obtain coarse code information of the sine-cosine encoder; The subdivision algorithm module is configured to perform subdivision calculation on the sine-cosine digital signal to obtain fine code information of the sine-cosine encoder; The parameter determination module is configured to combine the coarse code information of the sine-cosine encoder and the fine code information of the sine-cosine encoder, and calculate the rotor position information of the motor through the subdivision algorithm; the rotor position information of the motor comprises at least one of the angular velocity of the motor and the angular position of the motor.

2. The decoding apparatus of a sine-cosine encoder according to claim 1, characterized in that, The staggered trigger unit comprises a first signal generation module and a second signal generation module, a first signal transformation module, a second signal transformation module, and a first signal trigger module and a second signal trigger module; wherein The staggered trigger unit performs staggered triggering on the sine signal and the cosine signal in the first path sine-cosine analog signal to obtain a sine-cosine square wave signal, which comprises: The first signal generation module is configured to generate a first square wave signal based on the sine signal in the first path sine-cosine analog signal; The first signal transformation module is configured to perform signal transformation based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at a jump edge, denoted as a first pulse signal; The second signal generation module is configured to generate a second square wave signal based on the cosine signal in the first path sine-cosine analog signal; The second signal transformation module is configured to perform signal transformation based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at a jump edge, denoted as a second pulse signal; The first signal trigger module is configured to trigger D at a rising edge of the second pulse signal, output the first square wave signal, and obtain a first TTL signal, denoted as a first triggered square wave signal; the first triggered square wave signal is a sine square wave signal in the positive and sine square wave signal; The second signal trigger module is configured to trigger D at a rising edge of the first pulse signal, output the second square wave signal, and obtain a second TTL signal, denoted as a second triggered square wave signal; the second triggered square wave signal is a cosine square wave signal in the positive and sine square wave signal.

3. The decoding apparatus of a sine-cosine encoder according to claim 2, characterized in that, The first signal generation module comprises a first comparator. The first signal generation module generates a first square wave signal based on a sine signal in the first positive and sine analog signal, and comprises the following steps: The first comparator is configured to compare the sine signal in the first positive and sine analog signal and a preset first reference signal, obtain a first comparison result, and record the first comparison result as the first square wave signal. The second signal generation module comprises a second comparator. The second signal generation module generates a second square wave signal based on a cosine signal in the first positive and sine analog signal, and comprises the following steps: The second comparator is configured to compare the cosine signal in the first positive and sine analog signal and a preset second reference signal, obtain a second comparison result, and record the second comparison result as the second square wave signal. The first signal transform module comprises a first RC module, a first XOR module, and a first inverter module.

4. The decoding apparatus of a sine-cosine encoder according to claim 2, characterized in that, The first signal transform module performs signal transformation based on the first square wave signal, obtains a pulse signal generated by the first square wave signal at a jump edge, and records the pulse signal as a first pulse signal, and comprises the following steps: The first RC module is configured to generate a pulse signal with a set width based on the first square wave signal. The first XOR module is configured to perform XOR processing on the first square wave signal and the pulse signal generated by the first RC module, obtain a first XOR processing result, and record the first XOR processing result as the first pulse signal. The first inverter module is configured to perform inverting processing on the first XOR processing result, obtain the pulse signal generated by the first square wave signal at the jump edge, and record the pulse signal as the first pulse signal. The second signal transform module comprises a second RC module, a second XOR module, and a second inverter module. The second signal transform module performs signal transformation based on the second square wave signal, obtains a pulse signal generated by the second square wave signal at a jump edge, and records the pulse signal as a second pulse signal, and comprises the following steps: The second RC module is configured to generate a pulse signal with a set width based on the second square wave signal. The second XOR module is configured to perform XOR processing on the second square wave signal and the pulse signal generated by the second RC module, obtain a second XOR processing result, and record the second XOR processing result as the second pulse signal. The second inverter module is configured to perform inverting processing on the second XOR processing result, obtain the pulse signal generated by the second square wave signal at the jump edge, and record the pulse signal as the second pulse signal. The first signal transform module comprises a first RC module, a first XOR module, and a first inverter module. ​ 5. The decoding apparatus of a sine-cosine encoder according to claim 4, characterized in that, ​ The first signal conversion module further comprises a third inverting module. The first signal conversion module performs signal conversion based on the first square wave signal to obtain a pulse signal generated by the first square wave signal at a jump edge, denoted as a first pulse signal, and further comprises: The third inverting module is configured to perform inverting processing on the first square wave signal to obtain a first inverting square wave signal. The first RC module is further configured to generate a pulse signal with a set width based on the first inverting square wave signal. The first XOR module is further configured to perform XOR processing based on the first inverting square wave signal and the pulse signal generated by the first RC module to obtain a first XOR processing result. The first inverting module is further configured to perform inverting processing on the first XOR processing result to obtain the pulse signal generated by the first square wave signal at the jump edge, denoted as the first pulse signal. The second signal conversion module further comprises a fourth inverting module. The second signal conversion module performs signal conversion based on the second square wave signal to obtain a pulse signal generated by the second square wave signal at a jump edge, denoted as a second pulse signal, and further comprises: The fourth inverting module is configured to perform inverting processing on the second square wave signal to obtain a second inverting square wave signal. The second RC module is further configured to generate a pulse signal with a set width based on the second inverting square wave signal. The second XOR module is further configured to perform XOR processing based on the second inverting square wave signal and the pulse signal generated by the second RC module to obtain a second XOR processing result. The second inverting module is further configured to perform inverting processing on the second XOR processing result to obtain the pulse signal generated by the second square wave signal at the jump edge, denoted as the second pulse signal.

6. The decoding apparatus of a sine-cosine encoder according to claim 2, characterized in that, Wherein, The first signal trigger module comprises a first D flip-flop. The second signal trigger module comprises a second D flip-flop.

7. The decoding apparatus of a sine-cosine encoder according to claim 6, characterized in that, Wherein, The QEP module counts the edges of the sine-cosine square wave signal to obtain coarse code information of the sine-cosine encoder, including: In the case where the first signal generation module in the interleaved trigger unit is composed of a first RC module, a first XOR module, and a first inverting module, and the second signal generation module in the interleaved trigger unit is composed of a second RC module, a second XOR module, and a second inverting module, the edges of the sine-cosine square wave signal are counted, and a set number of pulses is compensated to obtain coarse code information of the sine-cosine encoder; The parameter determination module combines the coarse code information of the sine-cosine encoder and the fine code information of the sine-cosine encoder, calculates through a subdivision algorithm to obtain rotor position information of the motor, including: The coarse code information of the sine-cosine encoder and the fine code information of the sine-cosine encoder are combined to modify the subdivision algorithm, and the modified subdivision algorithm is calculated to obtain the rotor position information of the motor.

8. A drive apparatus characterized by comprising: Including: The decoding device of the sine-cosine encoder according to any one of claims 1 to 7.

9. A parameter determination method of a driving apparatus as claimed in claim 8, characterized by, Including: The rotor position information of the motor is detected by a sine-cosine encoder, and a sine-cosine differential signal is output. The sine-cosine differential signal includes a sine differential signal and a cosine differential signal. The sine-cosine differential signal output by the sine-cosine encoder is processed by a differential operational amplifier unit to obtain a sine-cosine analog signal. The sine signal and the cosine signal in the first sine-cosine analog signal are staggered and triggered by a staggered trigger unit to obtain a sine-cosine square wave signal. The second sine-cosine analog signal is processed by an ADC unit to obtain a sine-cosine digital signal. The rotor position information of the motor is determined by a control unit according to the sine-cosine square wave signal and the sine-cosine digital signal.

10. The parameter determination method of a drive apparatus according to claim 9, characterized by, The rotor position information of the motor is determined by a control unit according to the sine-cosine square wave signal and the sine-cosine digital signal, including: The edges of the sine-cosine square wave signal are counted by a QEP module to obtain coarse code information of the sine-cosine encoder. The sine-cosine digital signal is calculated by a subdivision algorithm module to obtain fine code information of the sine-cosine encoder. The coarse code information of the sine-cosine encoder and the fine code information of the sine-cosine encoder are combined by a parameter determination module, and the motor rotor position information is calculated by a subdivision algorithm.

11. The parameter determination method of a drive apparatus according to claim 10, characterized by, Wherein, The edges of the sine-cosine square wave signal are counted by a QEP module to obtain coarse code information of the sine-cosine encoder, including: When the first signal generation module in the staggered trigger unit is composed of a first RC module, a first XOR module and a first inverter module, and the second signal generation module in the staggered trigger unit is composed of a second RC module, a second XOR module and a second inverter module, the edges of the sine-cosine square wave signal are counted and the set pulse number is compensated to obtain the coarse code information of the sine-cosine encoder. The coarse code information of the sine-cosine encoder and the fine code information of the sine-cosine encoder are combined by a parameter determination module, and the motor rotor position information is calculated by a subdivision algorithm, including: The coarse code information of the sine-cosine encoder and the fine code information of the sine-cosine encoder are combined, the subdivision algorithm is modified, and the motor rotor position information is calculated by the modified subdivision algorithm.

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